Prepare v2025.10-rc4

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Merge tag 'v2025.10-rc4' into next

Prepare v2025.10-rc4

Makefile

@@ -3,7 +3,7 @@
 VERSION = 2025
 PATCHLEVEL = 10
 SUBLEVEL =
-EXTRAVERSION = -rc3
+EXTRAVERSION = -rc4
 NAME =
 
 # *DOCUMENTATION*

arch/arm/dts/Makefile

@@ -124,6 +124,8 @@ dtb-$(CONFIG_ARCH_TEGRA) += \
 	tegra30-wexler-qc750.dtb \
 	tegra114-asus-tf701t.dtb \
 	tegra114-dalmore.dtb \
+	tegra114-microsoft-surface-2-0b.dtb \
+	tegra114-microsoft-surface-2-13.dtb \
 	tegra114-nvidia-tegratab.dtb \
 	tegra124-apalis.dtb \
 	tegra124-jetson-tk1.dtb \

arch/arm/dts/px30-u-boot.dtsi

@@ -27,6 +27,10 @@
 	};
 };
 
+&otp {
+	bootph-some-ram;
+};
+
 &uart2 {
 	clock-frequency = <24000000>;
 	bootph-all;

arch/arm/dts/rk3328-roc-cc-u-boot.dtsi

@@ -4,7 +4,7 @@
  */
 
 #include "rk3328-u-boot.dtsi"
-#include "rk3328-sdram-ddr4-666.dtsi"
+#include "rk3328-sdram-ddr4-1600.dtsi"
 
 / {
 	smbios {

arch/arm/dts/rk3328-sdram-ddr4-1600.dtsi

@@ -0,0 +1,226 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd.
+
+&dmc {
+	rockchip,sdram-params = <
+		0x1
+		0xA
+		0x2
+		0x1
+		0x0
+		0x0
+		0x11
+		0x0
+		0x11
+		0x0
+		0
+
+		0x94496354
+		0x00000000
+		0x0000002a
+		0x000004e2
+		0x00000015
+		0x0000034a
+		0x000000ff
+
+		800
+		0
+		1
+		0
+		0
+
+		0x00000000
+		0x43041010
+		0x00000064
+		0x0061008c
+		0x000000d0
+		0x000200c5
+		0x000000d4
+		0x00500000
+		0x000000d8
+		0x00000100
+		0x000000dc
+		0x03140401
+		0x000000e0
+		0x00000000
+		0x000000e4
+		0x00110000
+		0x000000e8
+		0x00000420
+		0x000000ec
+		0x00000400
+		0x000000f4
+		0x000f011f
+		0x00000100
+		0x0c0e1b0e
+		0x00000104
+		0x00030314
+		0x00000108
+		0x0506050b
+		0x0000010c
+		0x0040400c
+		0x00000110
+		0x06030307
+		0x00000114
+		0x04040302
+		0x00000120
+		0x06060b06
+		0x00000124
+		0x00020308
+		0x00000180
+		0x01000040
+		0x00000184
+		0x00000000
+		0x00000190
+		0x07040003
+		0x00000198
+		0x05001100
+		0x000001a0
+		0xc0400003
+		0x00000240
+		0x0600060c
+		0x00000244
+		0x00000201
+		0x00000250
+		0x00000f00
+		0x00000490
+		0x00000001
+		0xffffffff
+		0xffffffff
+		0xffffffff
+		0xffffffff
+		0xffffffff
+		0xffffffff
+		0xffffffff
+		0xffffffff
+		0xffffffff
+		0xffffffff
+		0xffffffff
+		0xffffffff
+		0xffffffff
+		0xffffffff
+
+		0x00000004
+		0x0000000c
+		0x00000028
+		0x0000000c
+		0x0000002c
+		0x00000000
+		0x00000030
+		0x00000009
+		0xffffffff
+		0xffffffff
+
+		0x77
+		0x88
+		0x79
+		0x79
+		0x87
+		0x97
+		0x87
+		0x78
+		0x77
+		0x78
+		0x87
+		0x88
+		0x87
+		0x87
+		0x77
+
+		0x78
+		0x78
+		0x78
+		0x78
+		0x78
+		0x78
+		0x78
+		0x78
+		0x78
+		0x69
+		0x9
+
+		0x77
+		0x78
+		0x77
+		0x78
+		0x77
+		0x78
+		0x77
+		0x78
+		0x77
+		0x79
+		0x9
+
+		0x78
+		0x78
+		0x78
+		0x78
+		0x78
+		0x78
+		0x78
+		0x78
+		0x78
+		0x69
+		0x9
+
+		0x77
+		0x78
+		0x77
+		0x77
+		0x77
+		0x77
+		0x77
+		0x77
+		0x77
+		0x79
+		0x9
+
+		0x78
+		0x78
+		0x78
+		0x78
+		0x78
+		0x78
+		0x78
+		0x78
+		0x78
+		0x69
+		0x9
+
+		0x77
+		0x78
+		0x77
+		0x78
+		0x77
+		0x78
+		0x77
+		0x78
+		0x77
+		0x79
+		0x9
+
+		0x78
+		0x78
+		0x78
+		0x78
+		0x78
+		0x78
+		0x78
+		0x78
+		0x78
+		0x69
+		0x9
+
+		0x77
+		0x78
+		0x77
+		0x77
+		0x77
+		0x77
+		0x77
+		0x77
+		0x77
+		0x79
+		0x9
+	>;
+};

arch/arm/dts/rk3528-generic-u-boot.dtsi

@@ -1,12 +1,3 @@
 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 
 #include "rk3528-u-boot.dtsi"
-
-&sdmmc {
-	bus-width = <4>;
-	cap-sd-highspeed;
-	disable-wp;
-	no-mmc;
-	no-sdio;
-	status = "okay";
-};

arch/arm/dts/rk3528-generic.dts

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
- * Minimal generic DT for RK3528 with eMMC enabled
+ * Minimal generic DT for RK3528 with eMMC and SD-card enabled
  */
 
 /dts-v1/;
@@ -10,6 +10,12 @@
 	model = "Generic RK3528";
 	compatible = "rockchip,rk3528";
 
+	aliases {
+		mmc0 = &sdhci;
+		mmc1 = &sdmmc;
+		serial0 = &uart0;
+	};
+
 	chosen {
 		stdout-path = "serial0:1500000n8";
 	};
@@ -25,6 +31,15 @@
 	status = "okay";
 };
 
+&sdmmc {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	disable-wp;
+	no-mmc;
+	no-sdio;
+	status = "okay";
+};
+
 &uart0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart0m0_xfer>;

arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi

@@ -6,11 +6,10 @@
 	mmc-hs200-1_8v;
 };
 
-&sdmmc {
+&vdd_arm {
-	bus-width = <4>;
+	regulator-init-microvolt = <953000>;
-	cap-mmc-highspeed;
+};
-	cap-sd-highspeed;
+
-	disable-wp;
+&vdd_logic {
-	vmmc-supply = <&vcc_3v3>;
+	regulator-init-microvolt = <900000>;
-	status = "okay";
 };

arch/arm/dts/rk3528-u-boot.dtsi

@@ -27,24 +27,6 @@
 			compatible = "rockchip,rk3528-otp";
 			reg = <0x0 0xffce0000 0x0 0x4000>;
 		};
-
-		sdmmc: mmc@ffc30000 {
-			compatible = "rockchip,rk3528-dw-mshc",
-				     "rockchip,rk3288-dw-mshc";
-			reg = <0x0 0xffc30000 0x0 0x4000>;
-			clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SRC_SDMMC0>;
-			clock-names = "biu", "ciu";
-			fifo-depth = <0x100>;
-			interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
-			max-frequency = <150000000>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&sdmmc_bus4>, <&sdmmc_clk>, <&sdmmc_cmd>,
-				    <&sdmmc_det>;
-			resets = <&cru SRST_H_SDMMC0>;
-			reset-names = "reset";
-			rockchip,default-sample-phase = <90>;
-			status = "disabled";
-		};
 	};
 };
 

arch/arm/dts/rk3576-armsom-sige5-u-boot.dtsi

@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3576-u-boot.dtsi"
+
+/ {
+	aliases {
+		mmc0 = &sdhci;
+		mmc1 = &sdmmc;
+	};
+};
+
+&red_led {
+	default-state = "on";
+};
+
+&sdhci {
+	cap-mmc-highspeed;
+};

arch/arm/dts/rk3576-generic-u-boot.dtsi

@@ -0,0 +1,3 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3576-u-boot.dtsi"

arch/arm/dts/rk3576-generic.dts

@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Minimal generic DT for RK3576 with eMMC, SD-card and USB OTG enabled
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include "rk3576.dtsi"
+
+/ {
+	model = "Generic RK3576";
+	compatible = "rockchip,rk3576";
+
+	aliases {
+		mmc0 = &sdhci;
+		mmc1 = &sdmmc;
+	};
+
+	chosen {
+		stdout-path = "serial0:1500000n8";
+	};
+};
+
+&sdhci {
+	bus-width = <8>;
+	cap-mmc-highspeed;
+	mmc-hs200-1_8v;
+	no-sd;
+	no-sdio;
+	non-removable;
+	status = "okay";
+};
+
+&sdmmc {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	disable-wp;
+	no-mmc;
+	no-sdio;
+	status = "okay";
+};
+
+&u2phy0 {
+	status = "okay";
+};
+
+&u2phy0_otg {
+	status = "okay";
+};
+
+&uart0 {
+	pinctrl-0 = <&uart0m0_xfer>;
+	status = "okay";
+};
+
+&usb_drd0_dwc3 {
+	dr_mode = "peripheral";
+	maximum-speed = "high-speed";
+	phys = <&u2phy0_otg>;
+	phy-names = "usb2-phy";
+	status = "okay";
+};

arch/arm/dts/rk3576-u-boot.dtsi

@@ -49,6 +49,10 @@
 	bootph-all;
 };
 
+&otp {
+	bootph-some-ram;
+};
+
 &pcfg_pull_none {
 	bootph-all;
 };

arch/arm/dts/rk3588-generic-u-boot.dtsi

@@ -1,21 +1,3 @@
 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 
 #include "rk3588s-u-boot.dtsi"
-
-&u2phy0 {
-	status = "okay";
-};
-
-&u2phy0_otg {
-	status = "okay";
-};
-
-&usbdp_phy0 {
-	status = "okay";
-};
-
-&usb_host0_xhci {
-	dr_mode = "peripheral";
-	maximum-speed = "high-speed";
-	status = "okay";
-};

arch/arm/dts/rk3588-generic.dts

@@ -39,7 +39,23 @@
 	status = "okay";
 };
 
+&u2phy0 {
+	status = "okay";
+};
+
+&u2phy0_otg {
+	status = "okay";
+};
+
 &uart2 {
 	pinctrl-0 = <&uart2m0_xfer>;
 	status = "okay";
 };
+
+&usb_host0_xhci {
+	dr_mode = "peripheral";
+	maximum-speed = "high-speed";
+	phys = <&u2phy0_otg>;
+	phy-names = "usb2-phy";
+	status = "okay";
+};

arch/arm/dts/rk3588-orangepi-5-ultra-u-boot.dtsi

@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3588-u-boot.dtsi"
+
+&fspim1_pins {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&sdhci {
+	cap-mmc-highspeed;
+	mmc-hs200-1_8v;
+};
+
+&sfc {
+	flash@0 {
+		bootph-pre-ram;
+		bootph-some-ram;
+	};
+};

arch/arm/dts/tegra114-microsoft-surface-2-0b.dts

@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "tegra114-microsoft-surface-2-common.dtsi"
+
+/ {
+	backlight: backlight {
+		enable-gpios = <&gpio TEGRA_GPIO(CC, 2) GPIO_ACTIVE_HIGH>;
+	};
+};

arch/arm/dts/tegra114-microsoft-surface-2-13.dts

@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "tegra114-microsoft-surface-2-common.dtsi"
+
+/ {
+	backlight: backlight {
+		enable-gpios = <&gpio TEGRA_GPIO(EE, 3) GPIO_ACTIVE_HIGH>;
+	};
+};

arch/arm/dts/tegra114-microsoft-surface-2-common.dtsi

@@ -0,0 +1,905 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/input/input.h>
+#include "tegra114.dtsi"
+
+/ {
+	model = "Microsoft Surface 2";
+	compatible = "microsoft,surface-2", "nvidia,tegra114";
+
+	chosen {
+		stdout-path = &uarta;
+	};
+
+	aliases {
+		i2c0 = &pwr_i2c;
+
+		mmc0 = &sdmmc4; /* eMMC */
+		mmc1 = &sdmmc3; /* uSD slot */
+
+		usb0 = &usb1;
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x80000000 0x80000000>;
+	};
+
+	host1x@50000000 {
+		dsia: dsi@54300000 {
+			status = "okay";
+
+			avdd-dsi-csi-supply = <&avdd_dsi_csi>;
+
+			panel@0 {
+				compatible = "samsung,ltl106hl02-001";
+				reg = <0>;
+
+				vdd-supply = <&tps65090_fet4>;
+
+				backlight = <&backlight>;
+			};
+		};
+	};
+
+	pinmux@70000868 {
+		pinctrl-names = "default";
+		pinctrl-0 = <&state_default>;
+
+		state_default: pinmux {
+			/* ULPI pinmux */
+			ulpi-data0 {
+				nvidia,pins = "ulpi_data0_po1",
+						"ulpi_data3_po4",
+						"ulpi_data4_po5";
+				nvidia,function = "ulpi";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			ulpi-data1 {
+				nvidia,pins = "ulpi_data1_po2";
+				nvidia,function = "ulpi";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			ulpi-data2 {
+				nvidia,pins = "ulpi_data2_po3";
+				nvidia,function = "ulpi";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			ulpi-data7 {
+				nvidia,pins = "ulpi_data7_po0",
+						"ulpi_data5_po6",
+						"ulpi_data6_po7";
+				nvidia,function = "ulpi";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			/* I2S pinmux */
+			dap1-din {
+				nvidia,pins = "dap1_fs_pn0",
+						"dap1_din_pn1",
+						"dap1_sclk_pn3";
+				nvidia,function = "i2s0";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			dap1-dout {
+				nvidia,pins = "dap1_dout_pn2";
+				nvidia,function = "i2s0";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			dap2-i2s1 {
+				nvidia,pins = "dap2_fs_pa2",
+						"dap2_sclk_pa3",
+						"dap2_din_pa4",
+						"dap2_dout_pa5";
+				nvidia,function = "i2s1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			dap3-i2s2 {
+				nvidia,pins = "dap3_fs_pp0",
+						"dap3_din_pp1",
+						"dap3_dout_pp2",
+						"dap3_sclk_pp3";
+				nvidia,function = "i2s2";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			dap4-din {
+				nvidia,pins = "dap4_fs_pp4",
+						"dap4_din_pp5",
+						"dap4_sclk_pp7";
+				nvidia,function = "i2s3";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			dap4-dout {
+				nvidia,pins = "dap4_dout_pp6";
+				nvidia,function = "i2s3";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			/* SDMMC1 pinmux */
+			sdmmc1-wp-clk {
+				nvidia,pins = "sdmmc1_wp_n_pv3",
+						"sdmmc1_clk_pz0";
+				nvidia,function = "sdmmc1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			sdmmc1-cmd {
+				nvidia,pins = "sdmmc1_cmd_pz1",
+						"sdmmc1_dat3_py4",
+						"sdmmc1_dat2_py5",
+						"sdmmc1_dat1_py6",
+						"sdmmc1_dat0_py7";
+				nvidia,function = "sdmmc1";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			/* SDMMC3 pinmux */
+			sdmmc3-clk {
+				nvidia,pins = "sdmmc3_clk_pa6";
+				nvidia,function = "sdmmc3";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			sdmmc3-cmd {
+				nvidia,pins = "sdmmc3_cmd_pa7",
+						"sdmmc3_dat3_pb4",
+						"sdmmc3_dat2_pb5",
+						"sdmmc3_dat1_pb6",
+						"sdmmc3_dat0_pb7",
+						"sdmmc3_cd_n_pv2",
+						"sdmmc3_clk_lb_in_pee5";
+				nvidia,function = "sdmmc3";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			sdmmc3-clk-lb-out {
+				nvidia,pins = "sdmmc3_clk_lb_out_pee4";
+				nvidia,function = "sdmmc3";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			/* SDMMC4 pinmux */
+			sdmmc4-clk {
+				nvidia,pins = "sdmmc4_clk_pcc4";
+				nvidia,function = "sdmmc4";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			sdmmc4-cmd {
+				nvidia,pins = "sdmmc4_cmd_pt7",
+						"sdmmc4_dat0_paa0",
+						"sdmmc4_dat1_paa1",
+						"sdmmc4_dat2_paa2",
+						"sdmmc4_dat3_paa3",
+						"sdmmc4_dat4_paa4",
+						"sdmmc4_dat5_paa5",
+						"sdmmc4_dat6_paa6",
+						"sdmmc4_dat7_paa7";
+				nvidia,function = "sdmmc4";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			/* HDMI pinmux */
+			hdmi-int {
+				nvidia,pins = "hdmi_int_pn7";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
+			};
+			hdmi-cec {
+				nvidia,pins = "hdmi_cec_pee3";
+				nvidia,function = "rsvd3";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+			};
+
+			/* I2C pinmux */
+			gen1-i2c {
+				nvidia,pins = "gen1_i2c_scl_pc4",
+						"gen1_i2c_sda_pc5";
+				nvidia,function = "i2c1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+			};
+			gen2-i2c {
+				nvidia,pins = "gen2_i2c_scl_pt5",
+						"gen2_i2c_sda_pt6";
+				nvidia,function = "i2c2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+			};
+			cam-i2c {
+				nvidia,pins = "cam_i2c_scl_pbb1",
+						"cam_i2c_sda_pbb2";
+				nvidia,function = "i2c3";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+			};
+			ddc-scl-pv4 {
+				nvidia,pins = "ddc_scl_pv4",
+						"ddc_sda_pv5";
+				nvidia,function = "i2c4";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
+			};
+			pwr-i2c {
+				nvidia,pins = "pwr_i2c_scl_pz6",
+						"pwr_i2c_sda_pz7";
+				nvidia,function = "i2cpwr";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+			};
+
+			/* UARTA pinmux */
+			uarta-out {
+				nvidia,pins = "pu0", "pu3";
+				nvidia,function = "uarta";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			uarta-in {
+				nvidia,pins = "pu1", "pu2";
+				nvidia,function = "uarta";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			/* UARTB pinmux */
+			uart2-txd-pc2 {
+				nvidia,pins = "uart2_txd_pc2";
+				nvidia,function = "irda";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			uart2-rxd-pc3 {
+				nvidia,pins = "uart2_rxd_pc3";
+				nvidia,function = "irda";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			uart2-cts-n-pj5 {
+				nvidia,pins = "uart2_cts_n_pj5",
+						"uart2_rts_n_pj6";
+				nvidia,function = "rsvd3";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			/* UARTC pinmux */
+			uart3-cts-rxd {
+				nvidia,pins = "uart3_cts_n_pa1",
+						"uart3_rxd_pw7";
+				nvidia,function = "uartc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			uart3-rts-txd {
+				nvidia,pins = "uart3_rts_n_pc0",
+						"uart3_txd_pw6";
+				nvidia,function = "uartc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			/* UARTD pinmux */
+			uartd-out {
+				nvidia,pins = "ulpi_clk_py0",
+						"ulpi_stp_py3";
+				nvidia,function = "uartd";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			uartd-in {
+				nvidia,pins = "ulpi_dir_py1",
+						"ulpi_nxt_py2";
+				nvidia,function = "uartd";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			/* GMI section */
+			gmi-a17 {
+				nvidia,pins = "gmi_a17_pb0",
+						"gmi_a18_pb1",
+						"gmi_iordy_pi5",
+						"kb_col1_pq1",
+						"kb_row8_ps0",
+						"pbb6";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			gmi-wp-n {
+				nvidia,pins = "gmi_wp_n_pc7",
+						"gmi_cs0_n_pj0",
+						"gpio_x7_aud_px7";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			gmi-ad0 {
+				nvidia,pins = "gmi_ad0_pg0",
+						"gmi_ad1_pg1",
+						"gmi_ad2_pg2",
+						"gmi_ad3_pg3",
+						"gmi_ad4_pg4",
+						"gmi_ad5_pg5",
+						"gmi_ad6_pg6",
+						"gmi_ad7_pg7",
+						"gmi_oe_n_pi1",
+						"pv1";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			gmi-ad8 {
+				nvidia,pins = "gmi_ad8_ph0";
+				nvidia,function = "pwm0";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			gmi-ad9 {
+				nvidia,pins = "gmi_ad9_ph1",
+						"gmi_ad10_ph2",
+						"gmi_ad11_ph3",
+						"gmi_ad15_ph7",
+						"gmi_cs4_n_pk2";
+				nvidia,function = "gmi";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			gmi-ad12 {
+				nvidia,pins = "gmi_ad12_ph4",
+						"gmi_ad13_ph5",
+						"gpio_x1_aud_px1",
+						"pcc1",
+						"clk3_req_pee1",
+						"clk1_req_pee2";
+				nvidia,function = "rsvd4";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			gmi-ad14 {
+				nvidia,pins = "gmi_ad14_ph6",
+						"gmi_a16_pj7",
+						"gmi_a19_pk7";
+				nvidia,function = "gmi";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			gmi-wr-n {
+				nvidia,pins = "gmi_wr_n_pi0";
+				nvidia,function = "spi4";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			gmi-cs6-n {
+				nvidia,pins = "gmi_cs6_n_pi3",
+						"gmi_cs7_n_pi6";
+				nvidia,function = "nand";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			gmi-rst-n {
+				nvidia,pins = "gmi_rst_n_pi4",
+						"spdif_out_pk5",
+						"spdif_in_pk6",
+						"clk2_out_pw5",
+						"dvfs_pwm_px0",
+						"dvfs_clk_px2",
+						"pbb7",
+						"pcc2",
+						"clk2_req_pcc5";
+				nvidia,function = "rsvd4";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			gmi-wait {
+				nvidia,pins = "gmi_wait_pi7";
+				nvidia,function = "nand";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			gmi-cs1-n {
+				nvidia,pins = "gmi_cs1_n_pj2";
+				nvidia,function = "soc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			gmi-dqs-p {
+				nvidia,pins = "gmi_dqs_p_pj3";
+				nvidia,function = "sdmmc2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			gmi-adv-n {
+				nvidia,pins = "gmi_adv_n_pk0";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			gmi-clk {
+				nvidia,pins = "gmi_clk_pk1",
+						"gmi_cs2_n_pk3",
+						"gmi_cs3_n_pk4";
+				nvidia,function = "gmi";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			jtag-rtck {
+				nvidia,pins = "jtag_rtck";
+				nvidia,function = "rtck";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			/* KBC pinmux */
+			kb-col0 {
+				nvidia,pins = "kb_col0_pq0",
+						"kb_col3_pq3",
+						"kb_col4_pq4",
+						"kb_row4_pr4";
+				nvidia,function = "kbc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			kb-col2 {
+				nvidia,pins = "kb_col2_pq2",
+						"kb_col6_pq6",
+						"kb_col7_pq7",
+						"kb_row0_pr0",
+						"kb_row2_pr2",
+						"pv0",
+						"sys_clk_req_pz5";
+				nvidia,function = "rsvd4";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			kb-col5 {
+				nvidia,pins = "kb_col5_pq5",
+						"kb_row5_pr5";
+				nvidia,function = "kbc";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			kb-row1 {
+				nvidia,pins = "kb_row1_pr1";
+				nvidia,function = "kbc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			kb-row3 {
+				nvidia,pins = "kb_row3_pr3",
+						"kb_row9_ps1";
+				nvidia,function = "rsvd3";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			kb-row6 {
+				nvidia,pins = "kb_row6_pr6";
+				nvidia,function = "kbc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			kb-row7 {
+				nvidia,pins = "kb_row7_pr7",
+						"pbb3",
+						"pbb4",
+						"pbb5";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			kb-row10 {
+				nvidia,pins = "kb_row10_ps2";
+				nvidia,function = "rsvd3";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			/* CORE pinmux */
+			clk-32k-out {
+				nvidia,pins = "clk_32k_out_pa0";
+				nvidia,function = "blink";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			clk-32k-in {
+				nvidia,pins = "clk_32k_in";
+				nvidia,function = "clk";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			core-pwr-req {
+				nvidia,pins = "core_pwr_req";
+				nvidia,function = "pwron";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			cpu-pwr-req {
+				nvidia,pins = "cpu_pwr_req";
+				nvidia,function = "cpu";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			pwr-int-n {
+				nvidia,pins = "pwr_int_n";
+				nvidia,function = "pmi";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			owr {
+				nvidia,pins = "owr";
+				nvidia,function = "rsvd4";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+				nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
+			};
+			reset-out-n {
+				nvidia,pins = "reset_out_n";
+				nvidia,function = "reset_out_n";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			/* AUD pinmux */
+			gpio-w2-aud {
+				nvidia,pins = "gpio_w2_aud_pw2";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			gpio-w3-aud {
+				nvidia,pins = "gpio_w3_aud_pw3";
+				nvidia,function = "spi6";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			gpio-x3-aud {
+				nvidia,pins = "gpio_x3_aud_px3";
+				nvidia,function = "rsvd4";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			gpio-x4-aud {
+				nvidia,pins = "gpio_x4_aud_px4";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			gpio-x5-aud {
+				nvidia,pins = "gpio_x5_aud_px5";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			gpio-x6-aud {
+				nvidia,pins = "gpio_x6_aud_px6";
+				nvidia,function = "spi6";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			pu4 {
+				nvidia,pins = "pu4";
+				nvidia,function = "pwm1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			pu5 {
+				nvidia,pins = "pu5";
+				nvidia,function = "pwm2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			pu6 {
+				nvidia,pins = "pu6";
+				nvidia,function = "pwm3";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			pbb0 {
+				nvidia,pins = "pbb0",
+						"cam_mclk_pcc0";
+				nvidia,function = "vi_alt1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			clk1-out {
+				nvidia,pins = "clk1_out_pw4";
+				nvidia,function = "extperiph1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			clk3-out {
+				nvidia,pins = "clk3_out_pee0";
+				nvidia,function = "extperiph3";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			/* USB pinmux */
+			usb-vbus-en0 {
+				nvidia,pins = "usb_vbus_en0_pn4";
+				nvidia,function = "rsvd4";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+			};
+			usb-vbus-en1 {
+				nvidia,pins = "usb_vbus_en1_pn5";
+				nvidia,function = "rsvd4";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+			};
+		};
+	};
+
+	uarta: serial@70006000 {
+		status = "okay";
+	};
+
+	pwm: pwm@7000a000 {
+		status = "okay";
+	};
+
+	pwr_i2c: i2c@7000d000 {
+		status = "okay";
+		clock-frequency = <400000>;
+
+		/* Texas Instruments TPS65090 PMIC */
+		tps65090@48 {
+			compatible = "ti,tps65090";
+			reg = <0x48>;
+
+			regulators {
+				tps65090_fet1: fet1 {
+					regulator-name = "vcd_led";
+					regulator-boot-on;
+				};
+
+				tps65090_fet4: fet4 {
+					regulator-name = "vdd_lcd";
+					regulator-boot-on;
+				};
+
+				tps65090_fet6: fet6 {
+					regulator-name = "vdd_usd";
+					regulator-boot-on;
+				};
+			};
+		};
+
+		/* Texas Instruments TPS65913 PMIC */
+		pmic: tps65913@58 {
+			compatible = "ti,tps65913";
+			reg = <0x58>;
+
+			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+
+			ti,system-power-controller;
+
+			pmic {
+				compatible = "ti,tps65913-pmic";
+
+				regulators {
+					vdd_1v8_vio: smps8 {
+						regulator-name = "vdd_1v8";
+						regulator-min-microvolt = <1800000>;
+						regulator-max-microvolt = <1800000>;
+						regulator-always-on;
+						regulator-boot-on;
+						regulator-ramp-delay = <5000>;
+					};
+
+					avdd_dsi_csi: ldo3 {
+						regulator-name = "avdd_dsi_csi";
+						regulator-min-microvolt = <1200000>;
+						regulator-max-microvolt = <1200000>;
+						regulator-boot-on;
+					};
+
+					vddio_usd: ldo9 {
+						regulator-name = "vddio_usd";
+						regulator-min-microvolt = <2900000>;
+						regulator-max-microvolt = <2900000>;
+						regulator-always-on;
+						regulator-boot-on;
+					};
+				};
+			};
+		};
+	};
+
+	sdmmc3: sdhci@78000400 {
+		status = "okay";
+		bus-width = <4>;
+
+		cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
+
+		nvidia,default-tap = <0x3>;
+		nvidia,default-trim = <0x3>;
+
+		vmmc-supply = <&tps65090_fet6>;
+		vqmmc-supply = <&vddio_usd>;
+	};
+
+	sdmmc4: sdhci@78000600 {
+		status = "okay";
+		bus-width = <8>;
+		non-removable;
+	};
+
+	usb1: usb@7d000000 {
+		status = "okay";
+		dr_mode = "otg";
+		nvidia,vbus-gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>;
+	};
+
+	usb-phy@7d000000 {
+		status = "okay";
+
+		nvidia,xcvr-setup = <7>;
+		nvidia,xcvr-lsfslew = <2>;
+		nvidia,xcvr-lsrslew = <2>;
+	};
+
+	backlight: backlight {
+		compatible = "pwm-backlight";
+
+		power-supply = <&tps65090_fet1>;
+		pwms = <&pwm 0 1000000>;
+
+		brightness-levels = <1 35 70 105 140 175 210 255>;
+		default-brightness-level = <5>;
+	};
+
+	/* PMIC has a built-in 32KHz oscillator which is used by PMC */
+	clk32k_in: clock-32k {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <32768>;
+		clock-output-names = "pmic-oscillator";
+	};
+
+	extcon-keys {
+		compatible = "gpio-keys";
+
+		switch-hall-sensor {
+			label = "Hall Sensor";
+			gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_HIGH>;
+			linux,code = <SW_LID>;
+		};
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		key-power {
+			label = "Power Button";
+			gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_HIGH>;
+			linux,code = <KEY_ENTER>;
+		};
+
+		key-volume-down {
+			label = "Volume Down";
+			gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_DOWN>;
+		};
+
+		key-volume-up {
+			label = "Volume Up";
+			gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_UP>;
+		};
+
+		key-windows {
+			label = "Windows Button";
+			gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_HIGH>;
+			linux,code = <KEY_ENTER>;
+		};
+	};
+};

arch/arm/dts/tegra20-asus-sl101.dts

@@ -6,4 +6,14 @@
 / {
 	model = "ASUS EeePad Slider SL101";
 	compatible = "asus,sl101", "nvidia,tegra20";
+
+	extcon-keys {
+		compatible = "gpio-keys";
+
+		switch-tablet-mode {
+			label = "Tablet Mode";
+			gpios = <&gpio TEGRA_GPIO(S, 4) GPIO_ACTIVE_LOW>;
+			linux,code = <SW_TABLET_MODE>;
+		};
+	};
 };

arch/arm/dts/tegra20-asus-tf101.dts

@@ -6,4 +6,14 @@
 / {
 	model = "ASUS EeePad Transformer TF101";
 	compatible = "asus,tf101", "nvidia,tegra20";
+
+	extcon-keys {
+		compatible = "gpio-keys";
+
+		switch-dock-hall-sensor {
+			label = "Lid sensor";
+			gpios = <&gpio TEGRA_GPIO(S, 4) GPIO_ACTIVE_LOW>;
+			linux,code = <SW_LID>;
+		};
+	};
 };

arch/arm/dts/tegra20-asus-tf101g.dts

@@ -6,4 +6,14 @@
 / {
 	model = "ASUS EeePad Transformer TF101G";
 	compatible = "asus,tf101g", "nvidia,tegra20";
+
+	extcon-keys {
+		compatible = "gpio-keys";
+
+		switch-dock-hall-sensor {
+			label = "Lid sensor";
+			gpios = <&gpio TEGRA_GPIO(S, 4) GPIO_ACTIVE_LOW>;
+			linux,code = <SW_LID>;
+		};
+	};
 };

arch/arm/dts/tegra20-asus-transformer.dtsi

@@ -497,12 +497,6 @@
 			gpios = <&gpio TEGRA_GPIO(Q, 5) GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_UP>;
 		};
-
-		switch-dock-hall-sensor {
-			label = "Lid sensor";
-			gpios = <&gpio TEGRA_GPIO(S, 4) GPIO_ACTIVE_LOW>;
-			linux,code = <SW_LID>;
-		};
 	};
 
 	panel: panel {

arch/arm/dts/tegra210-p3450-0000.dts

@@ -124,7 +124,14 @@
 
 	spi@70410000 {
 		status = "okay";
-		spi-max-frequency = <80000000>;
+
+		flash@0 {
+			compatible = "jedec,spi-nor";
+			reg = <0>;
+			spi-max-frequency = <104000000>;
+			spi-tx-bus-width = <2>;
+			spi-rx-bus-width = <2>;
+		};
 	};
 
 	usb@7d000000 {

arch/arm/dts/tegra210.dtsi

@@ -762,10 +762,10 @@
 		interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car TEGRA210_CLK_QSPI>;
+		clocks = <&tegra_car TEGRA210_CLK_QSPI>,
-		clock-names = "qspi";
+			 <&tegra_car TEGRA210_CLK_QSPI_PM>;
+		clock-names = "qspi", "qspi_out";
 		resets = <&tegra_car 211>;
-		reset-names = "qspi";
 		dmas = <&apbdma 5>, <&apbdma 5>;
 		dma-names = "rx", "tx";
 		status = "disabled";

arch/arm/lib/bootm.c

@@ -183,7 +183,7 @@ __weak void setup_board_tags(struct tag **in_params) {}
 static void do_nonsec_virt_switch(void)
 {
 	smp_kick_all_cpus();
-	dcache_disable();	/* flush cache before swtiching to EL2 */
+	dcache_disable();	/* flush cache before switching to EL2 */
 }
 #endif
 

arch/arm/mach-exynos/Kconfig

@@ -88,7 +88,7 @@ config TARGET_S5PC210_UNIVERSAL
 	select MISC_COMMON
 
 config TARGET_ORIGEN
-	bool "Exynos4412 Origen board"
+	bool "Exynos4210 Origen board"
 	select EXYNOS4210
 	select SUPPORT_SPL
 

arch/arm/mach-exynos/pinmux.c

@@ -32,7 +32,7 @@ static void exynos5_uart_config(int peripheral)
 		count = 2;
 		break;
 	default:
-		debug("%s: invalid peripheral %d", __func__, peripheral);
+		debug("%s: invalid peripheral %d\n", __func__, peripheral);
 		return;
 	}
 	for (i = start; i < start + count; i++) {
@@ -63,7 +63,7 @@ static void exynos5420_uart_config(int peripheral)
 		count = 2;
 		break;
 	default:
-		debug("%s: invalid peripheral %d", __func__, peripheral);
+		debug("%s: invalid peripheral %d\n", __func__, peripheral);
 		return;
 	}
 
@@ -97,12 +97,12 @@ static int exynos5_mmc_config(int peripheral, int flags)
 		start_ext = 0;
 		break;
 	default:
-		debug("%s: invalid peripheral %d", __func__, peripheral);
+		debug("%s: invalid peripheral %d\n", __func__, peripheral);
 		return -1;
 	}
 	if ((flags & PINMUX_FLAG_8BIT_MODE) && !start_ext) {
-		debug("SDMMC device %d does not support 8bit mode",
+		debug("SDMMC device %d does not support 8bit mode\n",
-				peripheral);
+		      peripheral);
 		return -1;
 	}
 	if (flags & PINMUX_FLAG_8BIT_MODE) {
@@ -145,12 +145,12 @@ static int exynos5420_mmc_config(int peripheral, int flags)
 		break;
 	default:
 		start = 0;
-		debug("%s: invalid peripheral %d", __func__, peripheral);
+		debug("%s: invalid peripheral %d\n", __func__, peripheral);
 		return -1;
 	}
 
 	if ((flags & PINMUX_FLAG_8BIT_MODE) && !start_ext) {
-		debug("SDMMC device %d does not support 8bit mode",
+		debug("SDMMC device %d does not support 8bit mode\n",
 		      peripheral);
 		return -1;
 	}
@@ -453,7 +453,7 @@ void exynos5420_spi_config(int peripheral)
 	default:
 		cfg = 0;
 		pin = 0;
-		debug("%s: invalid peripheral %d", __func__, peripheral);
+		debug("%s: invalid peripheral %d\n", __func__, peripheral);
 		return;
 	}
 
@@ -522,7 +522,7 @@ static int exynos5_pinmux_config(int peripheral, int flags)
 		gpio_cfg_pin(EXYNOS5_GPIO_B20, S5P_GPIO_FUNC(2));
 		break;
 	default:
-		debug("%s: invalid peripheral %d", __func__, peripheral);
+		debug("%s: invalid peripheral %d\n", __func__, peripheral);
 		return -1;
 	}
 
@@ -570,7 +570,7 @@ static int exynos5420_pinmux_config(int peripheral, int flags)
 		gpio_cfg_pin(EXYNOS5420_GPIO_B20, S5P_GPIO_FUNC(2));
 		break;
 	default:
-		debug("%s: invalid peripheral %d", __func__, peripheral);
+		debug("%s: invalid peripheral %d\n", __func__, peripheral);
 		return -1;
 	}
 
@@ -683,7 +683,7 @@ static void exynos4_uart_config(int peripheral)
 		count = 2;
 		break;
 	default:
-		debug("%s: invalid peripheral %d", __func__, peripheral);
+		debug("%s: invalid peripheral %d\n", __func__, peripheral);
 		return;
 	}
 	for (i = start; i < (start + count); i++) {
@@ -797,7 +797,7 @@ static void exynos4x12_uart_config(int peripheral)
 		count = 2;
 		break;
 	default:
-		debug("%s: invalid peripheral %d", __func__, peripheral);
+		debug("%s: invalid peripheral %d\n", __func__, peripheral);
 		return;
 	}
 	for (i = start; i < (start + count); i++) {
@@ -834,7 +834,7 @@ static int exynos4_pinmux_config(int peripheral, int flags)
 		debug("SDMMC device %d not implemented\n", peripheral);
 		return -1;
 	default:
-		debug("%s: invalid peripheral %d", __func__, peripheral);
+		debug("%s: invalid peripheral %d\n", __func__, peripheral);
 		return -1;
 	}
 
@@ -869,7 +869,7 @@ static int exynos4x12_pinmux_config(int peripheral, int flags)
 		debug("SDMMC device %d not implemented\n", peripheral);
 		return -1;
 	default:
-		debug("%s: invalid peripheral %d", __func__, peripheral);
+		debug("%s: invalid peripheral %d\n", __func__, peripheral);
 		return -1;
 	}
 
@@ -902,7 +902,7 @@ static int exynos4_pinmux_decode_periph_id(const void *blob, int node)
 	u32 cell[3];
 
 	err = fdtdec_get_int_array(blob, node, "interrupts", cell,
-					ARRAY_SIZE(cell));
+				   ARRAY_SIZE(cell));
 	if (err) {
 		debug(" invalid peripheral id\n");
 		return PERIPH_ID_NONE;
@@ -917,7 +917,7 @@ static int exynos5_pinmux_decode_periph_id(const void *blob, int node)
 	u32 cell[3];
 
 	err = fdtdec_get_int_array(blob, node, "interrupts", cell,
-					ARRAY_SIZE(cell));
+				   ARRAY_SIZE(cell));
 	if (err)
 		return PERIPH_ID_NONE;
 

arch/arm/mach-rockchip/px30/px30.c

@@ -2,10 +2,14 @@
 /*
  * Copyright (c) 2017 Rockchip Electronics Co., Ltd
  */
+
+#define LOG_CATEGORY LOGC_ARCH
+
 #include <clk.h>
 #include <dm.h>
 #include <fdt_support.h>
 #include <init.h>
+#include <misc.h>
 #include <spl.h>
 #include <asm/armv8/mmu.h>
 #include <asm/arch-rockchip/bootrom.h>
@@ -15,6 +19,7 @@
 #include <asm/arch-rockchip/clock.h>
 #include <asm/arch-rockchip/cru_px30.h>
 #include <dt-bindings/clock/px30-cru.h>
+#include <linux/bitfield.h>
 
 const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
 	[BROM_BOOTSOURCE_EMMC] = "/mmc@ff390000",
@@ -442,3 +447,59 @@ void board_debug_uart_init(void)
 #endif /* CONFIG_DEBUG_UART_BASE && CONFIG_DEBUG_UART_BASE == ... */
 }
 #endif /* CONFIG_DEBUG_UART_BOARD_INIT */
+
+#define PX30_OTP_SPECIFICATION_OFFSET		0x06
+
+#define DDR_GRF_BASE_ADDR               0xff630000
+#define DDR_GRF_CON(n)                  (0 + (n) * 4)
+
+int checkboard(void)
+{
+	struct udevice *dev;
+	u8 specification;
+	u32 base_soc;
+	int ret;
+
+	if (!IS_ENABLED(CONFIG_ROCKCHIP_OTP) || !CONFIG_IS_ENABLED(MISC))
+		return 0;
+
+	ret = uclass_get_device_by_driver(UCLASS_MISC,
+					  DM_DRIVER_GET(rockchip_otp), &dev);
+	if (ret) {
+		log_debug("Could not find otp device, ret=%d\n", ret);
+		return 0;
+	}
+
+	/* base SoC: 0x26334b52 for RK3326; 0x30335850 for PX30 */
+	ret = misc_read(dev, 0, &base_soc, 4);
+	if (ret < 0) {
+		log_debug("Could not read specification, ret=%d\n", ret);
+		return 0;
+	}
+
+	if (base_soc != 0x26334b52 && base_soc != 0x30335850) {
+		log_debug("Could not identify SoC, got 0x%04x in OTP\n", base_soc);
+		return 0;
+	}
+
+	/* SoC variant: 0x21 for PX30/PX30S/RK3326/RK3326S; 0x2b for PX30K */
+	ret = misc_read(dev, PX30_OTP_SPECIFICATION_OFFSET, &specification, 1);
+	if (ret < 0) {
+		log_debug("Could not read specification, ret=%d\n", ret);
+		return 0;
+	}
+
+	if (specification == 0x2b) {
+		printf("SoC:   PX30K\n");
+		return 0;
+	}
+
+	/* From vendor kernel: drivers/soc/rockchip/rockchip-cpuinfo.c */
+	specification = FIELD_GET(GENMASK(15, 14),
+				  readl(DDR_GRF_BASE_ADDR + DDR_GRF_CON(1)));
+	log_debug("DDR specification is %d\n", specification);
+	printf("SoC:   %s%s\n", base_soc == 0x26334b52 ? "RK3326" : "PX30",
+	       specification == 0x3 ? "S" : "");
+
+	return 0;
+}

arch/arm/mach-rockchip/rk3528/rk3528.c

@@ -9,6 +9,9 @@
 #include <asm/arch-rockchip/bootrom.h>
 #include <asm/arch-rockchip/hardware.h>
 
+#define VPU_GRF_BASE			0xff340000
+#define USB3OTG_CON1			0x44
+
 #define FIREWALL_DDR_BASE		0xff2e0000
 #define FW_DDR_MST6_REG			0x58
 #define FW_DDR_MST7_REG			0x5c
@@ -69,6 +72,9 @@ int arch_cpu_init(void)
 	val = readl(FIREWALL_DDR_BASE + FW_DDR_MST16_REG);
 	writel(val & 0xffff0000, FIREWALL_DDR_BASE + FW_DDR_MST16_REG);
 
+	/* Disable USB3OTG U3 port, later enabled in COMBPHY driver */
+	writel(0xffff0181, VPU_GRF_BASE + USB3OTG_CON1);
+
 	return 0;
 }
 

arch/arm/mach-rockchip/rk3576/MAINTAINERS

@@ -0,0 +1,11 @@
+GENERIC-RK3576
+M:	Jonas Karlman <jonas@kwiboo.se>
+S:	Maintained
+F:	arch/arm/dts/rk3576-generic*
+F:	configs/generic-rk3576_defconfig
+
+SIGE5-RK3576
+M:	Jonas Karlman <jonas@kwiboo.se>
+S:	Maintained
+F:	arch/arm/dts/rk3576-armsom-sige5*
+F:	configs/sige5-rk3576_defconfig

arch/arm/mach-rockchip/rk3576/rk3576.c

@@ -3,6 +3,10 @@
  * Copyright (c) 2024 Rockchip Electronics Co., Ltd
  */
 
+#define LOG_CATEGORY LOGC_ARCH
+
+#include <dm.h>
+#include <misc.h>
 #include <asm/armv8/mmu.h>
 #include <asm/arch-rockchip/bootrom.h>
 #include <asm/arch-rockchip/hardware.h>
@@ -29,6 +33,9 @@
 #define SGRF_DOMAIN_CON4	0x10
 #define SGRF_DOMAIN_CON5	0x14
 
+#define USB_GRF_BASE		0x2601E000
+#define USB3OTG0_CON1		0x0030
+
 const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
 	[BROM_BOOTSOURCE_EMMC] = "/soc/mmc@2a330000",
 	[BROM_BOOTSOURCE_SD] = "/soc/mmc@2a310000",
@@ -151,5 +158,52 @@ int arch_cpu_init(void)
 	 */
 	writel(0xffffff00, SYS_SGRF_BASE + SYS_SGRF_SOC_CON20);
 
+	/* Disable USB3OTG0 U3 port, later enabled by USBDP PHY driver */
+	writel(0xffff0188, USB_GRF_BASE + USB3OTG0_CON1);
+
+	return 0;
+}
+
+#define RK3576_OTP_CPU_CODE_OFFSET		0x02
+#define RK3576_OTP_SPECIFICATION_OFFSET		0x08
+
+int checkboard(void)
+{
+	u8 cpu_code[2], specification;
+	struct udevice *dev;
+	char suffix[2];
+	int ret;
+
+	if (!IS_ENABLED(CONFIG_ROCKCHIP_OTP) || !CONFIG_IS_ENABLED(MISC))
+		return 0;
+
+	ret = uclass_get_device_by_driver(UCLASS_MISC,
+					  DM_DRIVER_GET(rockchip_otp), &dev);
+	if (ret) {
+		log_debug("Could not find otp device, ret=%d\n", ret);
+		return 0;
+	}
+
+	/* cpu-code: SoC model, e.g. 0x35 0x76 */
+	ret = misc_read(dev, RK3576_OTP_CPU_CODE_OFFSET, cpu_code, 2);
+	if (ret < 0) {
+		log_debug("Could not read cpu-code, ret=%d\n", ret);
+		return 0;
+	}
+
+	/* specification: SoC variant, e.g. 0xA for RK3576J */
+	ret = misc_read(dev, RK3576_OTP_SPECIFICATION_OFFSET, &specification, 1);
+	if (ret < 0) {
+		log_debug("Could not read specification, ret=%d\n", ret);
+		return 0;
+	}
+	specification &= 0x1f;
+
+	/* for RK3576J i.e. '@' + 0xA = 'J' */
+	suffix[0] = specification > 1 ? '@' + specification : '\0';
+	suffix[1] = '\0';
+
+	printf("SoC:   RK%02x%02x%s\n", cpu_code[0], cpu_code[1], suffix);
+
 	return 0;
 }

arch/arm/mach-rockchip/rk3588/Kconfig

@@ -27,6 +27,23 @@ config TARGET_CM3588_NAS_RK3588
 	  - 3.5mm Headphone out, 2.0mm PH-2A Mic in
 	  - 5V Fan connector, PWM beeper, IR receiver, RTC battery connector
 
+config TARGET_GAMEFORCE_ACE_RK3588S
+	bool "GameForce Ace"
+	help
+	  The GameForce Ace is a handheld game console from GameForce with
+	  the Rockchip RK3588S SoC.
+
+	  Hardware features:
+	  - Rockchip RK3588S SoC
+	  - 12GB LPDDR4x RAM
+	  - 128GB eMMC
+	  - MicroSD card slot
+	  - 1x USB 3.0 Type-C with DP AltMode support
+	  - 1x HDMI 2.1 micro-HDMI out
+	  - 1920x1080 touchscreen MIPI-DSI panel
+	  - Analog joysticks and L/R triggers
+	  - 16 digital buttons
+
 config TARGET_GENBOOK_CM5_RK3588
 	bool "Cool Pi CM5 GenBook"
 	help
@@ -410,6 +427,7 @@ source "board/friendlyelec/cm3588-nas-rk3588/Kconfig"
 source "board/friendlyelec/nanopc-t6-rk3588/Kconfig"
 source "board/friendlyelec/nanopi-r6c-rk3588s/Kconfig"
 source "board/friendlyelec/nanopi-r6s-rk3588s/Kconfig"
+source "board/gameforce/ace-rk3588s/Kconfig"
 source "board/hardkernel/odroid_m2/Kconfig"
 source "board/indiedroid/nova/Kconfig"
 source "board/khadas/khadas-edge2-rk3588s/Kconfig"

arch/arm/mach-rockchip/rk3588/rk3588.c

@@ -15,6 +15,10 @@
 #include <asm/arch-rockchip/hardware.h>
 #include <asm/arch-rockchip/ioc_rk3588.h>
 
+#define USB_GRF_BASE			0xfd5ac000
+#define USB3OTG0_CON1			0x001c
+#define USB3OTG1_CON1			0x0034
+
 #define FIREWALL_DDR_BASE		0xfe030000
 #define FW_DDR_MST5_REG			0x54
 #define FW_DDR_MST13_REG		0x74
@@ -184,6 +188,10 @@ int arch_cpu_init(void)
 	/* Disable JTAG exposed on SDMMC */
 	rk_clrreg(&sys_grf->soc_con[6], SYS_GRF_FORCE_JTAG);
 #endif
+
+	/* Disable USB3OTG U3 ports, later enabled by USBDP PHY driver */
+	writel(0xffff0188, USB_GRF_BASE + USB3OTG0_CON1);
+	writel(0xffff0188, USB_GRF_BASE + USB3OTG1_CON1);
 #endif
 
 	return 0;

arch/arm/mach-tegra/tegra114/Kconfig

@@ -8,6 +8,10 @@ config TARGET_DALMORE
 	bool "NVIDIA Tegra114 Dalmore evaluation board"
 	select BOARD_LATE_INIT
 
+config TARGET_SURFACE_2
+	bool "Microsoft Surface 2"
+	select BOARD_LATE_INIT
+
 config TARGET_TEGRATAB
 	bool "NVIDIA Tegra114 TegraTab evaluation board"
 	select BOARD_LATE_INIT
@@ -22,6 +26,7 @@ config SYS_SOC
 	default "tegra114"
 
 source "board/nvidia/dalmore/Kconfig"
+source "board/microsoft/surface-2/Kconfig"
 source "board/nvidia/tegratab/Kconfig"
 source "board/asus/transformer-t114/Kconfig"
 

board/asus/transformer-t20/configs/sl101.config

@@ -1 +1,2 @@
+CONFIG_ENV_SOURCE_FILE="sl101"
 CONFIG_DEFAULT_DEVICE_TREE="tegra20-asus-sl101"

board/asus/transformer-t20/sl101.env

@@ -0,0 +1,15 @@
+#include <env/nvidia/prod_upd.env>
+
+button_cmd_0_name=Volume Down
+button_cmd_0=bootmenu
+partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs}
+boot_dev=1
+
+bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu
+bootmenu_1=mount external storage=usb start && ums 0 mmc 1; bootmenu
+bootmenu_2=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu
+bootmenu_3=update bootloader=run flash_uboot
+bootmenu_4=reboot RCM=enterrcm
+bootmenu_5=reboot=reset
+bootmenu_6=power off=poweroff
+bootmenu_delay=-1

board/gameforce/ace-rk3588s/Kconfig

@@ -0,0 +1,9 @@
+if TARGET_GAMEFORCE_ACE_RK3588S
+
+config SYS_BOARD
+	default "gameforce-ace-rk3588s"
+
+config SYS_VENDOR
+	default "GameForce"
+
+endif

board/gameforce/ace-rk3588s/MAINTAINERS

@@ -0,0 +1,5 @@
+GAMEFORCE-ACE-RK3588S
+M:	Chris Morgan <macromorgan@hotmail.com>
+S:	Maintained
+F:	board/gameforce/ace-rk3588s/
+F:	configs/gameforce-ace-rk3588s_defconfig

board/microsoft/surface-2/Kconfig

@@ -0,0 +1,13 @@
+if TARGET_SURFACE_2
+
+config SYS_BOARD
+	default "surface-2"
+
+config SYS_VENDOR
+	default "microsoft"
+
+config TEGRA_BOARD_STRING
+	string "Default Tegra board name"
+	default "Microsoft Surface 2"
+
+endif

board/microsoft/surface-2/MAINTAINERS

@@ -0,0 +1,7 @@
+SURFACE_2 BOARD
+M:	Jonas Schwöbel <jonasschwoebel@yahoo.de>
+S:	Maintained
+F:	arch/arm/dts/tegra114-microsoft-surface-2*
+F:	board/microsoft/surface-2/
+F:	configs/surface-2_defconfig
+F:	doc/board/microsoft/surface-2.rst

board/microsoft/surface-2/Makefile

@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+
+obj-$(CONFIG_XPL_BUILD) += surface-2-spl.o
+obj-$(CONFIG_MULTI_DTB_FIT) += board-info.o

board/microsoft/surface-2/board-info.c

@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  (C) Copyright 2025
+ *  Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <stdio.h>
+#include <env.h>
+#include <spl_gpio.h>
+
+#include <asm/gpio.h>
+#include <asm/arch/pinmux.h>
+#include <linux/string.h>
+
+static int id_gpio_get_value(u32 pingrp, u32 pin)
+{
+	/* Configure pinmux */
+	pinmux_set_func(pingrp, PMUX_FUNC_KBC);
+	pinmux_set_pullupdown(pingrp, PMUX_PULL_DOWN);
+	pinmux_tristate_enable(pingrp);
+	pinmux_set_io(pingrp, PMUX_PIN_INPUT);
+
+	/*
+	 * Since this function may be called
+	 * during DM reload we should use SPL
+	 * GPIO functions which do not depend
+	 * on DM.
+	 */
+	spl_gpio_input(NULL, pin);
+	return spl_gpio_get_value(NULL, pin);
+}
+
+static int get_board_id(void)
+{
+	u32 pcb_id0, pcb_id1, pcb_id2, pcb_id3, pcb_id4, board_id;
+
+	pcb_id0 = id_gpio_get_value(PMUX_PINGRP_KB_COL0_PQ0, TEGRA_GPIO(Q, 0));
+	pcb_id1 = id_gpio_get_value(PMUX_PINGRP_KB_COL1_PQ1, TEGRA_GPIO(Q, 1));
+	pcb_id2 = id_gpio_get_value(PMUX_PINGRP_KB_COL2_PQ2, TEGRA_GPIO(Q, 2));
+	pcb_id3 = id_gpio_get_value(PMUX_PINGRP_KB_COL3_PQ3, TEGRA_GPIO(Q, 3));
+	pcb_id4 = id_gpio_get_value(PMUX_PINGRP_KB_COL4_PQ4, TEGRA_GPIO(Q, 4));
+
+	/* Construct board ID */
+	board_id = pcb_id4 << 4 | pcb_id3 << 3 | pcb_id2 << 2 | pcb_id1 << 1 | pcb_id0;
+
+	log_debug("[SURFACE-2]: Board ID %02x\n", board_id);
+
+	return board_id & 0x1f;
+}
+
+int board_fit_config_name_match(const char *name)
+{
+	char dt_name[64] = { 0 };
+
+	snprintf(dt_name, sizeof(dt_name), "tegra114-microsoft-surface-2-%02x.dtb",
+		 get_board_id());
+
+	if (!strcmp(name, dt_name))
+		return 0;
+
+	return -1;
+}
+
+void nvidia_board_late_init(void)
+{
+	char dt_path[64] = { 0 };
+
+	snprintf(dt_path, sizeof(dt_path), "tegra114-microsoft-surface-2-%02x.dtb",
+		 get_board_id());
+	env_set("fdtfile", dt_path);
+}

board/microsoft/surface-2/surface-2-spl.c

@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ *  Surface 2 SPL stage configuration
+ *
+ *  (C) Copyright 2010-2013
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ *  (C) Copyright 2023
+ *  Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/tegra_i2c.h>
+#include <linux/delay.h>
+
+#define TPS65913_I2C_ADDR		(0x58 << 1)
+
+#define TPS65913_SMPS12_CTRL		0x20
+#define TPS65913_SMPS12_VOLTAGE		0x23
+#define TPS65913_SMPS45_CTRL		0x28
+#define TPS65913_SMPS45_VOLTAGE		0x2B
+
+#define TPS65913_SMPS12_CTRL_DATA	(0x5100 | TPS65913_SMPS12_CTRL)
+#define TPS65913_SMPS12_VOLTAGE_DATA	(0x3900 | TPS65913_SMPS12_VOLTAGE)
+#define TPS65913_SMPS45_CTRL_DATA	(0x5100 | TPS65913_SMPS45_CTRL)
+#define TPS65913_SMPS45_VOLTAGE_DATA	(0x4c00 | TPS65913_SMPS45_VOLTAGE)
+
+void pmic_enable_cpu_vdd(void)
+{
+	/* Set CORE VDD to 1.200V. */
+	tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS45_VOLTAGE_DATA);
+	udelay(1000);
+	tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS45_CTRL_DATA);
+
+	udelay(1000);
+
+	/* Set CPU VDD to 1.0125V. */
+	tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS12_VOLTAGE_DATA);
+	udelay(1000);
+	tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS12_CTRL_DATA);
+	udelay(10 * 1000);
+}

board/microsoft/surface-2/surface-2.env

@@ -0,0 +1,8 @@
+button_cmd_0_name=Volume Down
+button_cmd_0=bootmenu
+
+bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu
+bootmenu_1=mount external storage=usb start && ums 0 mmc 1; bootmenu
+bootmenu_2=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu
+bootmenu_4=power off=reset
+bootmenu_delay=-1

board/rockchip/evb_rk3588/MAINTAINERS

@@ -48,3 +48,9 @@ S:	Maintained
 F:	configs/orangepi-5-plus-rk3588_defconfig
 F:	arch/arm/dts/rk3588-orangepi-5-plus.dts
 F:	arch/arm/dts/rk3588-orangepi-5-plus-u-boot.dtsi
+
+ORANGEPI-5-RK3588-ULTRA
+M:	Niu Zhihong <zhihong@nzhnb.com>
+S:	Maintained
+F:	configs/orangepi-5-ultra-rk3588_defconfig
+F:	arch/arm/dts/rk3588-orangepi-5-ultra-u-boot.dtsi

board/samsung/e850-96/Makefile

@@ -3,4 +3,4 @@
 # Copyright (C) 2024, Linaro Limited
 # Sam Protsenko <semen.protsenko@linaro.org>
 
-obj-y	:= e850-96.o fw.o
+obj-y := e850-96.o fw.o acpm.o pmic.o

board/samsung/e850-96/acpm.c

@@ -0,0 +1,169 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2025 Linaro Ltd.
+ * Author: Sam Protsenko <semen.protsenko@linaro.org>
+ *
+ * ACPM (Active Clock and Power Management) is an IPC protocol for communicating
+ * with APM (Active Power Management) core. The message exchange between AP
+ * (Application Processor) and APM is happening by using shared memory in SRAM
+ * (iRAM) and generating interrupts using Mailbox block. By using this IPC
+ * interface it's possible to offload power management tasks to APM core, which
+ * acts as a supervisor for CPU. One of the main tasks of APM is controlling
+ * PMIC chip over I3C bus. So in order to access PMIC chip registers it's
+ * recommended to do so by sending corresponding commands to APM via ACPM IPC
+ * protocol. The IPC interaction sequence looks like this:
+ *
+ *     AP (CPU) <-> ACPM IPC (Mailbox + SRAM) <-> APM <-> I3C <-> PMIC
+ *
+ * This file contains functions for accessing I3C bus via APM block using
+ * ACPM IPC.
+ */
+
+#include <linux/iopoll.h>
+#include <linux/time.h>
+#include <asm/io.h>
+#include "acpm.h"
+
+/* Mailbox registers */
+#define MBOX_INTGR0			0x8	/* Interrupt Generation */
+#define MBOX_INTCR1			0x20	/* Interrupt Clear */
+#define MBOX_INTSR1			0x28	/* Interrupt Status */
+#define MBOX_INTGR_OFFSET		16
+#define MBOX_TIMEOUT			(1 * USEC_PER_SEC)
+
+/* APM shared memory registers */
+#define SHMEM_SR0			0x0
+#define SHMEM_SR1			0x4
+#define SHMEM_SR2			0x8
+#define SHMEM_SR3			0xc
+
+/* IPC functions */
+#define IPC_FUNC_READ			0x0
+#define IPC_FUNC_WRITE			0x1
+/* Command 0 shifts and masks */
+#define IPC_REG_SHIFT			0
+#define IPC_REG_MASK			0xff
+#define IPC_TYPE_SHIFT			8
+#define IPC_TYPE_MASK			0xf
+#define IPC_CHANNEL_SHIFT		12
+#define IPC_CHANNEL_MASK		0xf
+/* Command 1 shifts and masks */
+#define IPC_FUNC_SHIFT			0
+#define IPC_FUNC_MASK			0xff
+#define IPC_WRITE_VAL_SHIFT		8
+#define IPC_WRITE_VAL_MASK		0xff
+/* Command 3 shifts and masks */
+#define IPC_DEST_SHIFT			8
+#define IPC_DEST_MASK			0xff
+#define IPC_RETURN_SHIFT		24
+#define IPC_RETURN_MASK			0xff
+
+/**
+ * acpm_ipc_send_data_async() - Send data to I3C block over ACPM IPC
+ * @acpm: ACPM data
+ * @cmd0: Command 0 value to send
+ * @cmd1: Command 1 value to send
+ */
+static void acpm_ipc_send_data_async(struct acpm *acpm, u32 cmd0, u32 cmd1)
+{
+	u32 irq_bit = 1 << acpm->ipc_ch;
+	u32 intgr = irq_bit << MBOX_INTGR_OFFSET;
+
+	/* Write data to the shared memory */
+	writel(cmd0, acpm->sram_base + SHMEM_SR0);
+	writel(cmd1, acpm->sram_base + SHMEM_SR1);
+	dsb();
+
+	/* Generate interrupt for I3C block */
+	writel(intgr, acpm->mbox_base + MBOX_INTGR0);
+}
+
+/**
+ * acpm_ipc_wait_resp() - Read response data from I3C block over ACPM IPC
+ * @acpm: ACPM data
+ * @cmd2: Will contain read value for command 2
+ * @cmd3: Will contain read value for command 3
+ *
+ * Return: 0 on success or negative value on error.
+ */
+static int acpm_ipc_wait_resp(struct acpm *acpm, u32 *cmd2, u32 *cmd3)
+{
+	u32 irq_bit = 1 << acpm->ipc_ch;
+	u32 reg;
+	int ret;
+
+	/* Wait for the interrupt from I3C block */
+	ret = readl_poll_timeout(acpm->mbox_base + MBOX_INTSR1, reg,
+				 reg & irq_bit, MBOX_TIMEOUT);
+	if (ret < 0)
+		return ret;
+
+	/* Clear the interrupt */
+	writel(irq_bit, acpm->mbox_base + MBOX_INTCR1);
+
+	/* Read data from the shared memory */
+	*cmd2 = readl(acpm->sram_base + SHMEM_SR2);
+	*cmd3 = readl(acpm->sram_base + SHMEM_SR3);
+
+	return 0;
+}
+
+/**
+ * acpm_i3c_read() - Read an I3C register of some I3C slave device
+ * @acpm: ACPM data
+ * @ch: I3C channel (bus) number (0-15)
+ * @addr: I3C address of slave device (0-15)
+ * @reg: Address of I3C register in the slave device to read from
+ * @val: Will contain the read value
+ *
+ * Return: 0 on success or non-zero code on error (may be positive).
+ */
+int acpm_i3c_read(struct acpm *acpm, u8 ch, u8 addr, u8 reg, u8 *val)
+{
+	u32 cmd[4] = { 0 };
+	u8 ret;
+
+	cmd[0] = (ch & IPC_CHANNEL_MASK) << IPC_CHANNEL_SHIFT |
+		 (addr & IPC_TYPE_MASK) << IPC_TYPE_SHIFT |
+		 (reg & IPC_REG_MASK) << IPC_REG_SHIFT;
+	cmd[1] = IPC_FUNC_READ << IPC_FUNC_SHIFT;
+
+	acpm_ipc_send_data_async(acpm, cmd[0], cmd[1]);
+	ret = acpm_ipc_wait_resp(acpm, &cmd[2], &cmd[3]);
+	if (ret)
+		return ret;
+
+	*val = (cmd[3] >> IPC_DEST_SHIFT) & IPC_DEST_MASK;
+	ret = (cmd[3] >> IPC_RETURN_SHIFT) & IPC_RETURN_MASK;
+	return ret;
+}
+
+/**
+ * acpm_i3c_write() - Write an I3C register of some I3C slave device
+ * @acpm: ACPM data
+ * @ch: I3C channel (bus) number (0-15)
+ * @addr: I3C address of slave device (0-15)
+ * @reg: Address of I3C register in the slave device to write into
+ * @val: Value to write
+ *
+ * Return: 0 on success or non-zero code on error (may be positive).
+ */
+int acpm_i3c_write(struct acpm *acpm, u8 ch, u8 addr, u8 reg, u8 val)
+{
+	u32 cmd[4] = { 0 };
+	u8 ret;
+
+	cmd[0] = (ch & IPC_CHANNEL_MASK) << IPC_CHANNEL_SHIFT |
+		 (addr & IPC_TYPE_MASK) << IPC_TYPE_SHIFT |
+		 (reg & IPC_REG_MASK) << IPC_REG_SHIFT;
+	cmd[1] = IPC_FUNC_WRITE << IPC_FUNC_SHIFT |
+		 (val & IPC_WRITE_VAL_MASK) << IPC_WRITE_VAL_SHIFT;
+
+	acpm_ipc_send_data_async(acpm, cmd[0], cmd[1]);
+	ret = acpm_ipc_wait_resp(acpm, &cmd[2], &cmd[3]);
+	if (ret)
+		return ret;
+
+	ret = (cmd[3] >> IPC_RETURN_SHIFT) & IPC_RETURN_MASK;
+	return ret;
+}

board/samsung/e850-96/acpm.h

@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2025 Linaro Ltd.
+ * Sam Protsenko <semen.protsenko@linaro.org>
+ */
+
+#ifndef __E850_96_ACPM_H
+#define __E850_96_ACPM_H
+
+#include <linux/types.h>
+
+/**
+ * struct acpm - Data for I3C communication over ACPM IPC protocol
+ * @mbox_base: Base address of APM mailbox block
+ * @sram_base: Base address of shared memory used for APM messages
+ * @ipc_ch: Mailbox channel number used for communication with I3C block (0-15)
+ */
+struct acpm {
+	void __iomem *mbox_base;
+	void __iomem *sram_base;
+	u8 ipc_ch;
+};
+
+int acpm_i3c_read(struct acpm *acpm, u8 ch, u8 addr, u8 reg, u8 *val);
+int acpm_i3c_write(struct acpm *acpm, u8 ch, u8 addr, u8 reg, u8 val);
+
+#endif /* __E850_96_ACPM_H */

board/samsung/e850-96/e850-96.c

@@ -8,13 +8,28 @@
 #include <env.h>
 #include <init.h>
 #include <mapmem.h>
+#include <net.h>
+#include <usb.h>
 #include <asm/io.h>
 #include "fw.h"
+#include "pmic.h"
 
 /* OTP Controller base address and register offsets */
-#define EXYNOS850_OTP_BASE	0x10000000
+#define EXYNOS850_OTP_BASE		0x10000000
-#define OTP_CHIPID0		0x4
+#define OTP_CHIPID0			0x4
-#define OTP_CHIPID1		0x8
+#define OTP_CHIPID1			0x8
+
+/* ACPM and PMIC definitions */
+#define EXYNOS850_MBOX_APM2AP_BASE	0x11900000
+#define EXYNOS850_APM_SRAM_BASE		0x02039000	/* in iRAM */
+#define EXYNOS850_APM_SHMEM_OFFSET	0x3200
+#define EXYNOS850_IPC_AP_I3C		10
+
+/* LDFW firmware definitions */
+#define LDFW_NWD_ADDR			0x88000000
+#define EMMC_IFNAME			"mmc"
+#define EMMC_DEV_NUM			0
+#define EMMC_ESP_PART			1
 
 struct efi_fw_image fw_images[] = {
 	{
@@ -55,6 +70,13 @@ struct efi_capsule_update_info update_info = {
 	.images = fw_images,
 };
 
+static struct acpm acpm = {
+	.mbox_base	= (void __iomem *)EXYNOS850_MBOX_APM2AP_BASE,
+	.sram_base	= (void __iomem *)(EXYNOS850_APM_SRAM_BASE +
+					   EXYNOS850_APM_SHMEM_OFFSET),
+	.ipc_ch		= EXYNOS850_IPC_AP_I3C,
+};
+
 int dram_init(void)
 {
 	return fdtdec_setup_mem_size_base();
@@ -92,19 +114,74 @@ static void setup_serial(void)
 	env_set("serial#", serial_str);
 }
 
-int board_late_init(void)
+static void setup_ethaddr(void)
 {
+	u64 serial_num;
+	u32 mac_hi, mac_lo;
+	u8 mac_addr[6];
+
+	if (env_get("ethaddr"))
+		return;
+
+	serial_num = get_chip_id();
+	mac_lo = (u32)serial_num;		/* OTP_CHIPID0 */
+	mac_hi = (u32)(serial_num >> 32UL);	/* OTP_CHIPID1 */
+	mac_addr[0] = (mac_hi >> 8) & 0xff;
+	mac_addr[1] = mac_hi & 0xff;
+	mac_addr[2] = (mac_lo >> 24) & 0xff;
+	mac_addr[3] = (mac_lo >> 16) & 0xff;
+	mac_addr[4] = (mac_lo >> 8) & 0xff;
+	mac_addr[5] = mac_lo & 0xff;
+	mac_addr[0] &= ~0x1; /* make sure it's not a multicast address */
+	if (is_valid_ethaddr(mac_addr))
+		eth_env_set_enetaddr("ethaddr", mac_addr);
+}
+
+/*
+ * Call this in board_late_init() to avoid probing block devices before
+ * efi_init_early().
+ */
+void load_firmware(void)
+{
+	const char *ifname;
+	ulong dev, part;
 	int err;
 
-	setup_serial();
+	ifname = env_get("bootdev");
+	if (!ifname)
+		ifname = EMMC_IFNAME;
+	dev = env_get_ulong("bootdevnum", 10, EMMC_DEV_NUM);
+	part = env_get_ulong("bootdevpart", 10, EMMC_ESP_PART);
 
-	/*
+	if (!strcmp(ifname, "usb")) {
-	 * Do this in board_late_init() to make sure MMC is not probed before
+		printf("Starting USB (bootdev=usb)...\n");
-	 * efi_init_early().
+		err = usb_init();
-	 */
+		if (err)
-	err = load_ldfw();
+			return;
+	}
+
+	printf("Loading LDFW firmware (from %s %ld)...\n", ifname, dev);
+	err = load_ldfw(ifname, dev, part, LDFW_NWD_ADDR);
 	if (err)
 		printf("ERROR: LDFW loading failed (%d)\n", err);
+}
+
+int board_late_init(void)
+{
+	setup_serial();
+	setup_ethaddr();
+	load_firmware();
+
+	return 0;
+}
+
+int power_init_board(void)
+{
+	int err;
+
+	err = pmic_init(&acpm);
+	if (err)
+		printf("ERROR: Failed to configure PMIC (%d)\n", err);
 
 	return 0;
 }

board/samsung/e850-96/e850-96.env

@@ -5,7 +5,7 @@ fdt_addr_r=0x8c000000
 scriptaddr=0x8c100000
 pxefile_addr_r=0x8c200000
 ramdisk_addr_r=0x8c300000
-fdtfile=CONFIG_DEFAULT_FDT_FILE
+fdtfile=exynos/exynos850-e850-96.dtb
 
 dfu_alt_info=
 	rawemmc raw 0 0x747c000 mmcpart 1;

board/samsung/e850-96/fw.c

@@ -11,13 +11,9 @@
 #include <linux/arm-smccc.h>
 #include "fw.h"
 
-#define EMMC_IFACE		"mmc"
-#define EMMC_DEV_NUM		0
 #define LDFW_RAW_PART		"ldfw"
-#define LDFW_FAT_PART		"esp"
 #define LDFW_FAT_PATH		"/EFI/firmware/ldfw.bin"
 
-#define LDFW_NWD_ADDR		0x88000000
 #define LDFW_MAGIC		0x10adab1e
 #define SMC_CMD_LOAD_LDFW	-0x500
 #define SDM_HW_RESET_STATUS	0x1230
@@ -39,21 +35,25 @@ struct ldfw_header {
 };
 
 /* Load LDFW binary as a file from FAT partition */
-static int read_fw_from_fat(const char *part_name, const char *path, void *buf)
+static int read_fw_from_fat(const char *ifname, int dev, int part,
+			    const char *path, void *buf)
 {
-	char dev_part_str[8];
+	struct blk_desc *blk_desc;
 	loff_t len_read;
 	int err;
 
-	snprintf(dev_part_str, sizeof(dev_part_str), "%d#%s", EMMC_DEV_NUM,
+	blk_desc = blk_get_dev(ifname, dev);
-		 LDFW_FAT_PART);
+	if (!blk_desc) {
-
+		debug("%s: Can't get block device\n", __func__);
-	err = fs_set_blk_dev(EMMC_IFACE, dev_part_str, FS_TYPE_FAT);
-	if (err) {
-		debug("%s: Can't set block device\n", __func__);
 		return -ENODEV;
 	}
 
+	err = fs_set_blk_dev_with_part(blk_desc, part);
+	if (err) {
+		debug("%s: Can't set partition\n", __func__);
+		return -ENOENT;
+	}
+
 	err = fs_read(path, (ulong)buf, 0, 0, &len_read);
 	if (err) {
 		debug("%s: Can't read LDFW file\n", __func__);
@@ -64,16 +64,17 @@ static int read_fw_from_fat(const char *part_name, const char *path, void *buf)
 }
 
 /* Load LDFW binary from raw partition on block device into RAM buffer */
-static int read_fw_from_raw(const char *part_name, void *buf)
+static int read_fw_from_raw(const char *ifname, int dev, const char *part_name,
+			    void *buf)
 {
 	struct blk_desc *blk_desc;
 	struct disk_partition part;
 	unsigned long cnt;
 	int part_num;
 
-	blk_desc = blk_get_dev(EMMC_IFACE, EMMC_DEV_NUM);
+	blk_desc = blk_get_dev(ifname, dev);
 	if (!blk_desc) {
-		debug("%s: Can't get eMMC device\n", __func__);
+		debug("%s: Can't get block device\n", __func__);
 		return -ENODEV;
 	}
 
@@ -92,9 +93,17 @@ static int read_fw_from_raw(const char *part_name, void *buf)
 	return 0;
 }
 
-int load_ldfw(void)
+/**
+ * load_ldfw - Load the loadable firmware (LDFW)
+ * @ifname: Interface name of the block device to load the firmware from
+ * @dev: Device number
+ * @part: Partition number
+ * @addr: Temporary memory (Normal World) to use for loading the firmware
+ *
+ * Return: 0 on success or a negative value on error.
+ */
+int load_ldfw(const char *ifname, int dev, int part, phys_addr_t addr)
 {
-	const phys_addr_t addr = (phys_addr_t)LDFW_NWD_ADDR;
 	struct ldfw_header *hdr;
 	struct arm_smccc_res res;
 	void *buf = (void *)addr;
@@ -102,9 +111,9 @@ int load_ldfw(void)
 	int err, i;
 
 	/* First try to read LDFW from EFI partition, then from the raw one */
-	err = read_fw_from_fat(LDFW_FAT_PART, LDFW_FAT_PATH, buf);
+	err = read_fw_from_fat(ifname, dev, part, LDFW_FAT_PATH, buf);
 	if (err) {
-		err = read_fw_from_raw(LDFW_RAW_PART, buf);
+		err = read_fw_from_raw(ifname, dev, LDFW_RAW_PART, buf);
 		if (err)
 			return err;
 	}

board/samsung/e850-96/fw.h

@@ -7,6 +7,8 @@
 #ifndef __E850_96_FW_H
 #define __E850_96_FW_H
 
-int load_ldfw(void);
+#include <asm/types.h>
+
+int load_ldfw(const char *ifname, int dev, int part, phys_addr_t addr);
 
 #endif /* __E850_96_FW_H */

board/samsung/e850-96/pmic.c

@@ -0,0 +1,144 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2025 Linaro Ltd.
+ * Author: Sam Protsenko <semen.protsenko@linaro.org>
+ *
+ * This file contains functions for S2MPU12 PMIC regulators configuration.
+ *
+ * Example of voltage calculation for LDO24 and LDO32:
+ *   - V_min = 1800 mV
+ *   - V_step = 25 mV
+ *   - V_wanted = 3300 mV
+ *   - register value: (V_wanted - V_min) / V_step = 60 = 0x3c
+ *
+ * NOTE: 0x3c value might mean different voltage for other LDOs.
+ */
+
+#include <linux/errno.h>
+#include <linux/kernel.h>
+#include "pmic.h"
+
+/* PMIC definitions */
+#define S2MPU12_CHANNEL			0	/* I3C bus number of PMIC */
+#define S2MPU12_PM_ADDR			0x1	/* I3C slave addr of PM part */
+
+/* PMIC I3C registers */
+#define S2MPU12_PM_LDO1_CTRL		0x2b
+#define S2MPU12_PM_LDO_CTRL(n)		(S2MPU12_PM_LDO1_CTRL + (n) - 1)
+
+/* LDOx_CTRL values */
+#define S2MPU12_LDO_CTRL_OUT_MASK	(0x3 << 6)
+#define S2MPU12_LDO_CTRL_OUT_ALWAYS_ON	(0x3 << 6)
+
+struct pmic_ldo {
+	u8 num;	/* LDO number */
+	u8 en;	/* "enable" bits value in LDOx_CTRL register */
+	u8 out;	/* "output voltage" bits value in LDOx_CTRL register */
+};
+
+/* List of LDOs to enable only */
+static u8 pmic_ldos_en[] = {
+	2,	/* 1.8V/450mA:	multiple lines */
+	11,	/* 3.0V/150mA:	AVDD33_USB20 */
+	23,	/* 2.85V/800mA:	VDD_EMMC_2P85 */
+	27,	/* 3.0V/150mA:	MIPI_SWITCH_3V3 */
+	28,	/* 1.8V/150mA:	HDMI_CONV_1V8 */
+	30,	/* 1.8V/150mA:	NPU_VDD18 */
+};
+
+/* List of LDOs to enable and set output voltage */
+static struct pmic_ldo pmic_ldos_en_out[] = {
+	{
+		.num	= 24, /* 3.0V/800mA:	VDD_LAN (LAN9514) */
+		.en	= S2MPU12_LDO_CTRL_OUT_ALWAYS_ON,
+		.out	= 0x3c, /* means 3.3V for LDO24 */
+	}, {
+		.num	= 32, /* 3.3V/300mA:	CAM_VDD (RPi camera module) */
+		.en	= S2MPU12_LDO_CTRL_OUT_ALWAYS_ON,
+		.out	= 0x3c, /* means 3.3V for LDO32 */
+	},
+};
+
+/* Enable specified LDO */
+static int pmic_ldo_set_en(struct acpm *acpm, u8 ldo)
+{
+	const u8 reg = S2MPU12_PM_LDO_CTRL(ldo);
+	u8 val;
+	int err;
+
+	err = acpm_i3c_read(acpm, S2MPU12_CHANNEL, S2MPU12_PM_ADDR, reg, &val);
+	if (err)
+		return err;
+
+	val &= ~S2MPU12_LDO_CTRL_OUT_MASK;
+	val |= S2MPU12_LDO_CTRL_OUT_ALWAYS_ON;
+
+	return acpm_i3c_write(acpm, S2MPU12_CHANNEL, S2MPU12_PM_ADDR, reg, val);
+}
+
+/* Enable specified LDO and set its voltage to 0xc0 value */
+static int pmic_ldo_set_en_out(struct acpm *acpm, struct pmic_ldo *ldo)
+{
+	const u8 reg = S2MPU12_PM_LDO_CTRL(ldo->num);
+	const u8 val = ldo->en | ldo->out;
+
+	return acpm_i3c_write(acpm, S2MPU12_CHANNEL, S2MPU12_PM_ADDR, reg, val);
+}
+
+#ifdef DEBUG
+static void pmic_trace_ldo(struct acpm *acpm, u8 ldo)
+{
+	const u8 reg = S2MPU12_PM_LDO_CTRL(ldo);
+	u8 val;
+	int err;
+
+	err = acpm_i3c_read(acpm, S2MPU12_CHANNEL, S2MPU12_PM_ADDR, reg, &val);
+	if (err)
+		printf("  S2MPU12_PM_LDO%u_CTRL: Read error!\n", ldo);
+	else
+		printf("  S2MPU12_PM_LDO%u_CTRL: 0x%x\n", ldo, val);
+}
+
+static void pmic_trace_ldos(struct acpm *acpm)
+{
+	size_t i;
+
+	printf("Tracing LDOs...\n");
+	for (i = 0; i < ARRAY_SIZE(pmic_ldos_en); ++i)
+		pmic_trace_ldo(acpm, pmic_ldos_en[i]);
+	for (i = 0; i < ARRAY_SIZE(pmic_ldos_en_out); ++i)
+		pmic_trace_ldo(acpm, pmic_ldos_en_out[i].num);
+}
+#endif
+
+/**
+ * pmic_init() - Enable power regulators in S2MPU12 PMIC.
+ * @acpm: Data for I3C communication with PMIC over ACPM protocol
+ *
+ * Enable LDOs needed for devices used in the bootloader and kernel.
+ *
+ * Return: 0 on success or non-zero code on error.
+ */
+int pmic_init(struct acpm *acpm)
+{
+	size_t i;
+	int err;
+
+	for (i = 0; i < ARRAY_SIZE(pmic_ldos_en); ++i) {
+		err = pmic_ldo_set_en(acpm, pmic_ldos_en[i]);
+		if (err)
+			return -EIO;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(pmic_ldos_en_out); ++i) {
+		err = pmic_ldo_set_en_out(acpm, &pmic_ldos_en_out[i]);
+		if (err)
+			return -EIO;
+	}
+
+#ifdef DEBUG
+	pmic_trace_ldos(acpm);
+#endif
+
+	return 0;
+}

board/samsung/e850-96/pmic.h

@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2025 Linaro Ltd.
+ * Sam Protsenko <semen.protsenko@linaro.org>
+ */
+
+#ifndef __E850_96_PMIC_H
+#define __E850_96_PMIC_H
+
+#include "acpm.h"
+
+int pmic_init(struct acpm *acpm);
+
+#endif /* __E850_96_PMIC_H */

board/theobroma-systems/jaguar_rk3588/jaguar_rk3588.c

@@ -51,3 +51,22 @@ int rockchip_early_misc_init_r(void)
 
 	return 0;
 }
+
+#define GPIO0B7_PU_EN BIT(15)
+
+void spl_board_init(void)
+{
+	/*
+	 * GPIO0_B7 is routed to CAN TX. This SoC pin has a pull-down per default.
+	 * So on power-up, we block the CAN bus with a dominant zero. We want to keep
+	 * this blocking time to a minimum, so we want to get this pin high in SPL.
+	 *
+	 * The CAN driver in Linux disables the pull-down and sets the pin to
+	 * output high. We don't have a CAN driver in U-Boot and don't need one,
+	 * so we just use the easiest way to get the pin high, which is setting a
+	 * pull-up.
+	 */
+	struct rk3588_pmu2_ioc * const ioc = (void *)PMU2_IOC_BASE;
+
+	rk_setreg(&ioc->gpio0b_p, GPIO0B7_PU_EN);
+}

board/ti/am57xx/Kconfig

@@ -9,6 +9,18 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "am57xx_evm"
 
+config ENV_SOURCE_FILE
+	default "am57xx"
+
+source "board/ti/common/Kconfig"
+
+endif
+
+if TARGET_DRA7XX_EVM
+
+config ENV_SOURCE_FILE
+	default "am57xx"
+
 source "board/ti/common/Kconfig"
 
 endif

board/ti/am57xx/am57xx.env

@@ -0,0 +1,162 @@
+#include <env/ti/ti_common.env>
+#include <env/ti/mmc.env>
+#include <env/ti/dfu.env>
+
+bootpart=0:2
+bootdir=/boot
+get_name_kern=
+	if test $boot_fit -eq 1; then
+		setenv bootfile fitImage;
+	else
+		setenv bootfile zImage;
+	fi
+get_fit_config=setenv name_fit_config ${fdtfile}
+console=ttyS2,115200n8
+fdtfile=undefined
+finduuid=part uuid mmc 0:2 uuid
+usbtty=cdc_acm
+vram=16M
+
+#if CONFIG_CMD_AVB
+avb_verify=avb init 1; avb verify $slot_suffix;
+#endif
+
+partitions=uuid_disk=${uuid_gpt_disk};
+	name=bootloader,start=384K,size=1792K,uuid=${uuid_gpt_bootloader};
+	name=rootfs,start=2688K,size=-,uuid=${uuid_gpt_rootfs}
+	partitions_android=
+	uuid_disk=${uuid_gpt_disk};
+	name=xloader,start=128K,size=256K,uuid=${uuid_gpt_xloader};
+	name=bootloader,size=2048K,uuid=${uuid_gpt_bootloader};
+	name=uboot-env,start=2432K,size=256K,uuid=${uuid_gpt_reserved};
+	name=misc,size=128K,uuid=${uuid_gpt_misc};
+	name=boot_a,size=20M,uuid=${uuid_gpt_boot_a};
+	name=boot_b,size=20M,uuid=${uuid_gpt_boot_b};
+	name=dtbo_a,size=8M,uuid=${uuid_gpt_dtbo_a};
+	name=dtbo_b,size=8M,uuid=${uuid_gpt_dtbo_b};
+	name=vbmeta_a,size=64K,uuid=${uuid_gpt_vbmeta_a};
+	name=vbmeta_b,size=64K,uuid=${uuid_gpt_vbmeta_b};
+	name=recovery,size=64M,uuid=${uuid_gpt_recovery};
+	name=super,size=2560M,uuid=${uuid_gpt_super};
+	name=metadata,size=16M,uuid=${uuid_gpt_metadata};
+	name=userdata,size=-,uuid=${uuid_gpt_userdata}
+optargs=
+dofastboot=0
+emmc_android_boot=
+	setenv mmcdev 1;
+	mmc dev $mmcdev;
+	mmc rescan;
+#if CONFIG_CMD_BCB
+#if CONFIG_ANDROID_AB
+	if part number mmc 1 misc control_part_number; then
+		echo "misc partition number:${control_part_number};"
+		bcb ab_select slot_name mmc ${mmcdev}:${control_part_number};
+	else
+		echo "misc partition not found;"
+		exit;
+	fi;
+	setenv slot_suffix _${slot_name};
+#endif
+#endif
+if bcb load CONFIG_FASTBOOT_FLASH_MMC_DEV misc; then
+	setenv ardaddr -;
+	if bcb test command = bootonce-bootloader; then
+		echo "Android: Bootloader boot...";
+		bcb clear command; bcb store;
+		fastboot 1;
+		exit;
+	elif bcb test command = boot-recovery; then
+		echo "Android: Recovery boot...";
+		setenv ardaddr $loadaddr;
+		setenv apart recovery;
+	else
+		echo "Android: Normal boot...";
+		setenv ardaddr $loadaddr;
+		setenv apart boot${slot_suffix};
+	fi;
+else
+	echo "Warning: BCB is corrupted or does not exist";
+	echo "Android: Normal boot...";
+fi;
+setenv eval_bootargs setenv bootargs $bootargs;
+run eval_bootargs;
+setenv machid fe6;
+#if CONFIG_CMD_AVB
+if run avb_verify; then
+	echo "AVB verification OK.";
+	set bootargs $bootargs $avb_bootargs;
+else
+	echo "AVB verification failed.";
+	exit;
+fi;
+#endif
+#if CONFIG_CMD_BCB
+#if CONFIG_ANDROID_AB
+setenv bootargs_ab androidboot.slot_suffix=${slot_suffix};
+echo "A/B cmdline addition: ${bootargs_ab}";
+setenv bootargs ${bootargs} ${bootargs_ab};
+#endif
+#endif
+if part start mmc $mmcdev $apart boot_start; then
+	part size mmc $mmcdev $apart boot_size;
+	mmc read $loadaddr $boot_start $boot_size;
+	echo "Preparing FDT...";
+	if test $board_name = am57xx_evm_reva3; then
+		echo "  Reading DTBO partition...";
+		part start mmc ${mmcdev} dtbo${slot_suffix} p_dtbo_start;
+		part size mmc ${mmcdev} dtbo${slot_suffix} p_dtbo_size;
+		mmc read ${dtboaddr} ${p_dtbo_start} ${p_dtbo_size};
+		echo "  Reading DTB for AM57x EVM RevA3...";
+		abootimg get dtb --index=0 dtb_start dtb_size;
+		cp.b $dtb_start $fdtaddr $dtb_size;
+		fdt addr $fdtaddr 0x80000;
+		echo "  Applying DTBOs for AM57x EVM RevA3...";
+		adtimg addr $dtboaddr;
+		adtimg get dt --index=0 dtbo0_addr dtbo0_size;
+		fdt apply $dtbo0_addr;
+		adtimg get dt --index=1 dtbo1_addr dtbo1_size;
+		fdt apply $dtbo1_addr;
+	elif test $board_name = beagle_x15_revc; then
+		echo "  Reading DTB for Beagle X15 RevC...";
+		abootimg get dtb --index=0 dtb_start dtb_size;
+		cp.b $dtb_start $fdtaddr $dtb_size;
+		fdt addr $fdtaddr 0x80000;
+	else
+		echo "Error: Android boot is not supported for $board_name";
+		exit;
+	fi;
+	bootm $loadaddr $ardaddr $fdtaddr;
+else
+	echo "$apart partition not found";
+	exit;
+fi;
+get_overlay_mmc=
+	fdt address ${fdtaddr};
+	fdt resize 0x100000;
+	for overlay in $name_overlays;
+	do;
+		load mmc ${bootpart} ${dtboaddr} ${bootdir}/dtb/${overlay};
+		fdt apply ${dtboaddr};
+	done;
+#if CONFIG_CMD_NET
+static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off
+nfsopts=nolock
+rootpath=/export/rootfs
+netloadimage=tftp ${loadaddr} ${bootfile}
+netloadfdt=tftp ${fdtaddr} ${fdtfile}
+netargs=setenv bootargs console=${console} ${optargs}
+	root=/dev/nfs
+	nfsroot=${serverip}:${rootpath},${nfsopts} rw
+	ip=dhcp
+netboot=echo Booting from network ...;
+	setenv autoload no;
+	dhcp;
+	run netloadimage;
+	run netloadfdt;
+	run netargs;
+	bootz ${loadaddr} - ${fdtaddr}
+#endif
+#if CONFIG_MTD_RAW_NAND
+#include <env/ti/nand.env>
+#endif
+dfu_bufsiz=0x10000

board/ti/am57xx/board.c

@@ -42,6 +42,7 @@
 
 #include "../common/board_detect.h"
 #include "../common/cape_detect.h"
+#include "../common/fdt_ops.h"
 #include "mux_data.h"
 
 #ifdef CONFIG_SUPPORT_EMMC_BOOT
@@ -577,6 +578,18 @@ void do_board_detect(void)
 			 "Board: %s REV %s\n", bname, board_ti_get_rev());
 }
 
+static struct ti_fdt_map ti_omap_am57_evm_fdt_map[] = {
+	{"beagle_x15", "ti/omap/am57xx-beagle-x15.dtb"},
+	{"beagle_x15_revb1", "ti/omap/am57xx-beagle-x15-revb1.dtb"},
+	{"beagle_x15_revc", "ti/omap/am57xx-beagle-x15-revc.dtb"},
+	{"am5729_beagleboneai", "ti/omap/am5729-beagleboneai.dtb"},
+	{"am572x_idk", "ti/omap/am572x-idk.dtb"},
+	{"am574x_idk", "ti/omap/am574x-idk.dtb"},
+	{"am57xx_evm", "ti/omap/am57xx-beagle-x15.dtb"},
+	{"am57xx_evm_reva3", "ti/omap/am57xx-beagle-x15.dtb"},
+	{"am571x_idk", "ti/omap/am571x-idk.dtb"},
+};
+
 static void setup_board_eeprom_env(void)
 {
 	char *name = "beagle_x15";
@@ -614,6 +627,7 @@ static void setup_board_eeprom_env(void)
 
 invalid_eeprom:
 	set_board_info_env(name);
+	ti_set_fdt_env(name, ti_omap_am57_evm_fdt_map);
 }
 
 #endif	/* CONFIG_XPL_BUILD */

board/ti/dra7xx/evm.c

@@ -38,6 +38,7 @@
 
 #include "mux_data.h"
 #include "../common/board_detect.h"
+#include "../common/fdt_ops.h"
 
 #define board_is_dra76x_evm()		board_ti_is("DRA76/7x")
 #define board_is_dra74x_evm()		board_ti_is("5777xCPU")
@@ -665,6 +666,15 @@ static int device_okay(const char *path)
 }
 #endif
 
+static struct ti_fdt_map ti_omap_dra7_evm_fdt_map[] = {
+	{"omap5_uevm", "ti/omap/omap5-uevm.dtb"},
+	{"dra7xx", "ti/omap/dra7-evm.dtb"},
+	{"dra72x-revc", "ti/omap/dra72-evm-revc.dtb"},
+	{"dra72x", "ti/omap/dra72-evm.dtb"},
+	{"dra71x", "ti/omap/dra71-evm.dtb"},
+	{"dra76x_acd", "ti/omap/dra76-evm.dtb"},
+};
+
 int board_late_init(void)
 {
 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
@@ -686,6 +696,7 @@ int board_late_init(void)
 	}
 
 	set_board_info_env(name);
+	ti_set_fdt_env(name, ti_omap_dra7_evm_fdt_map);
 
 	/*
 	 * Default FIT boot on HS devices. Non FIT images are not allowed

board/xunlong/orangepi-5-ultra-rk3588/Kconfig

@@ -0,0 +1,12 @@
+if TARGET_ORANGEPI_5_ULTRA_RK3588
+
+config SYS_BOARD
+	default "orangepi-5-ultra-rk3588"
+
+config SYS_VENDOR
+	default "xunlong"
+
+config SYS_CONFIG_NAME
+	default "evb_rk3588"
+
+endif

board/xunlong/orangepi-5-ultra-rk3588/MAINTAINERS

@@ -0,0 +1,6 @@
+ORANGEPI-5-RK3588-ULTRA
+M:	Niu Zhihong <zhihong@nzhnb.com>
+S:	Maintained
+F:	board/xunlong/orangepi-5-rk3588-ultra
+F:	configs/orangepi-5-ultra-rk3588_defconfig
+F:	arch/arm/dts/rk3588-orangepi-5-ultra.dts

configs/e850-96_defconfig

@@ -19,7 +19,6 @@ CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
 CONFIG_EFI_CAPSULE_ON_DISK=y
 CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
 CONFIG_BOOTSTD_FULL=y
-CONFIG_DEFAULT_FDT_FILE="exynos850-e850-96.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 # CONFIG_BOARD_INIT is not set
 CONFIG_BOARD_LATE_INIT=y
@@ -30,6 +29,8 @@ CONFIG_CMD_CLK=y
 CONFIG_CMD_DFU=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_EFIDEBUG=y
 # CONFIG_CMD_DATE is not set
 CONFIG_CMD_RTC=y
@@ -41,7 +42,7 @@ CONFIG_ENV_IS_IN_MMC=y
 CONFIG_ENV_REDUNDANT=y
 CONFIG_ENV_RELOC_GD_ENV_ADDR=y
 CONFIG_ENV_MMC_EMMC_HW_PARTITION=2
-CONFIG_NO_NET=y
+CONFIG_NET_LWIP=y
 CONFIG_CLK_EXYNOS850=y
 CONFIG_DFU_MMC=y
 CONFIG_USB_FUNCTION_FASTBOOT=y
@@ -64,8 +65,13 @@ CONFIG_SYSRESET=y
 CONFIG_SYSRESET_SYSCON=y
 CONFIG_USB=y
 CONFIG_DM_USB_GADGET=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_SMSC95XX=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="Samsung"
 CONFIG_USB_GADGET_VENDOR_NUM=0x18d1

configs/gameforce-ace-rk3588s_defconfig

@@ -0,0 +1,67 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588s-gameforce-ace"
+CONFIG_ROCKCHIP_RK3588=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_DEBUG_UART_BASE=0xFEB50000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-gameforce-ace.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x40000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_ATF=y
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_NO_NET=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_BUTTON=y
+CONFIG_BUTTON_ADC=y
+CONFIG_BUTTON_GPIO=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MISC=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_PHY_ROCKCHIP_USBDP=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+# CONFIG_RAM_ROCKCHIP_DEBUG is not set
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_ERRNO_STR=y

configs/generic-rk3576_defconfig

@@ -0,0 +1,50 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3576-generic"
+CONFIG_ROCKCHIP_RK3576=y
+CONFIG_SYS_LOAD_ADDR=0x40c00800
+CONFIG_DEBUG_UART_BASE=0x2AD40000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+# CONFIG_BOOTMETH_VBE is not set
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3576-generic.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_MAX_SIZE=0x40000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEMINFO_MAP=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MISC=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_ROCKUSB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_RNG=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_OF_UPSTREAM is not set
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_NO_NET=y
+# CONFIG_ADC is not set
+# CONFIG_USB_FUNCTION_FASTBOOT is not set
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
+CONFIG_ERRNO_STR=y

configs/generic-rk3588_defconfig

@@ -53,7 +53,6 @@ CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_MMC_SDHCI_ROCKCHIP=y
 CONFIG_PHY_ROCKCHIP_INNO_USB2=y
-CONFIG_PHY_ROCKCHIP_USBDP=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_SPL_RAM=y
 CONFIG_BAUDRATE=1500000

configs/jaguar-rk3588_defconfig

@@ -27,6 +27,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-jaguar.dtb"
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_CYCLIC=y
 CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_BOARD_INIT=y
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 CONFIG_SPL_ATF=y
 # CONFIG_BOOTM_NETBSD is not set
@@ -34,6 +35,7 @@ CONFIG_SPL_ATF=y
 # CONFIG_BOOTM_RTEMS is not set
 # CONFIG_BOOTM_VXWORKS is not set
 # CONFIG_CMD_ELF is not set
+CONFIG_CMD_ERASEENV=y
 CONFIG_CMD_ADC=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y

configs/nanopi-r5s-rk3568_defconfig

@@ -28,6 +28,8 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_PCI=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_ROCKUSB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_PMIC=y
 CONFIG_CMD_REGULATOR=y
 # CONFIG_SPL_DOS_PARTITION is not set
@@ -38,6 +40,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_SPL_REGMAP=y
 CONFIG_SPL_SYSCON=y
 CONFIG_SPL_CLK=y
+# CONFIG_USB_FUNCTION_FASTBOOT is not set
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
 CONFIG_MISC=y
@@ -73,4 +76,8 @@ CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_OHCI_GENERIC=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GENERIC=y
+CONFIG_SPL_USB_DWC3_GENERIC=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
 CONFIG_ERRNO_STR=y

configs/orangepi-5-ultra-rk3588_defconfig

@@ -0,0 +1,88 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SF_DEFAULT_SPEED=80000000
+CONFIG_SF_DEFAULT_MODE=0x2000
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588-orangepi-5-ultra"
+CONFIG_ROCKCHIP_RK3588=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
+CONFIG_SPL_SERIAL=y
+CONFIG_TARGET_EVB_RK3588=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_SF_DEFAULT_BUS=5
+CONFIG_DEBUG_UART_BASE=0xFEB50000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_PCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-orangepi-5-ultra.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x40000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
+CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_AHCI_PCI=y
+CONFIG_DWC_AHCI=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_XMC=y
+CONFIG_PHYLIB=y
+CONFIG_RTL8169=y
+CONFIG_NVME_PCI=y
+CONFIG_PCIE_DW_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_PHY_ROCKCHIP_USBDP=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_SCSI=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SFC=y
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_ERRNO_STR=y

configs/p3450-0000_defconfig

@@ -18,13 +18,21 @@ CONFIG_TEGRA210=y
 CONFIG_TARGET_P3450_0000=y
 CONFIG_TEGRA_GPU=y
 CONFIG_PCI=y
+CONFIG_HAS_BOARD_SIZE_LIMIT=y
+CONFIG_BOARD_SIZE_LIMIT=753664
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_SYS_PBSIZE=2089
 CONFIG_CONSOLE_MUX=y
 CONFIG_SYS_STDIO_DEREGISTER=y
 CONFIG_SYS_PROMPT="Tegra210 (P3450-0000) # "
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_BOOTM_VXWORKS is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_GO is not set
 # CONFIG_CMD_IMI is not set
+# CONFIG_CRC32_VERIFY is not set
 CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
@@ -53,7 +61,6 @@ CONFIG_RTL8169=y
 CONFIG_NVME_PCI=y
 CONFIG_PCI_TEGRA=y
 CONFIG_SYS_NS16550=y
-CONFIG_TEGRA114_SPI=y
 CONFIG_TEGRA210_QSPI=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y

configs/puma-rk3399_defconfig

@@ -36,6 +36,7 @@ CONFIG_TPL_GPIO=y
 # CONFIG_BOOTM_RTEMS is not set
 # CONFIG_CMD_VBE is not set
 # CONFIG_BOOTM_VXWORKS is not set
+CONFIG_CMD_ERASEENV=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y

configs/r8a779g3_sparrowhawk_defconfig

@@ -18,7 +18,7 @@ CONFIG_SYS_BARGSIZE=2048
 CONFIG_SYS_CBSIZE=2048
 CONFIG_BAUDRATE=921600
 CONFIG_BINMAN=y
-CONFIG_BOOTCOMMAND="tftp 0x50000000 fitImage && bootm 0x50000000"
+CONFIG_BOOTCOMMAND="tftp ${loadaddr} fitImage && bootm ${loadaddr}"
 CONFIG_DEFAULT_FDT_FILE="r8a779g3-sparrow-hawk.dtb"
 CONFIG_CMD_REMOTEPROC=y
 CONFIG_GPIO_HOG=y

configs/radxa-e20c-rk3528_defconfig

@@ -20,6 +20,8 @@ CONFIG_CMD_GPT=y
 CONFIG_CMD_MISC=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_ROCKUSB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_RNG=y
 CONFIG_CMD_REGULATOR=y
@@ -28,6 +30,7 @@ CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigne
 CONFIG_BUTTON=y
 CONFIG_BUTTON_ADC=y
 CONFIG_BUTTON_GPIO=y
+# CONFIG_USB_FUNCTION_FASTBOOT is not set
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_LED=y
 CONFIG_LED_GPIO=y
@@ -43,6 +46,7 @@ CONFIG_DM_MDIO=y
 CONFIG_DWC_ETH_QOS=y
 CONFIG_DWC_ETH_QOS_ROCKCHIP=y
 CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
 CONFIG_REGULATOR_PWM=y
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_PWM_ROCKCHIP=y
@@ -50,6 +54,12 @@ CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYS_NS16550_MEM32=y
 CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
 CONFIG_ERRNO_STR=y

configs/renesas_rcar.config

@@ -18,6 +18,7 @@ CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_DM_SPI=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
 CONFIG_FIT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_MTD=y

configs/ringneck-px30_defconfig

@@ -40,6 +40,7 @@ CONFIG_SPL_ATF=y
 # CONFIG_CMD_VBE is not set
 # CONFIG_BOOTM_VXWORKS is not set
 # CONFIG_CMD_ELF is not set
+CONFIG_CMD_ERASEENV=y
 # CONFIG_CMD_LZMADEC is not set
 # CONFIG_CMD_UNZIP is not set
 CONFIG_CMD_BIND=y

configs/sige5-rk3576_defconfig

@@ -0,0 +1,66 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3576-armsom-sige5"
+CONFIG_ROCKCHIP_RK3576=y
+CONFIG_SYS_LOAD_ADDR=0x40c00800
+CONFIG_DEBUG_UART_BASE=0x2AD40000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_PCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3576-armsom-sige5.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_MAX_SIZE=0x40000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEMINFO_MAP=y
+CONFIG_CMD_ADC=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MISC=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_ROCKUSB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_RNG=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+# CONFIG_USB_FUNCTION_FASTBOOT is not set
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_ROCKCHIP=y
+CONFIG_NVME_PCI=y
+CONFIG_PCIE_DW_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_PHY_ROCKCHIP_USBDP=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
+CONFIG_ERRNO_STR=y

configs/stm32mp25_defconfig

@@ -41,6 +41,8 @@ CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_LOG=y
 CONFIG_CMD_UBI=y
 CONFIG_OF_LIVE=y
+CONFIG_OF_UPSTREAM_BUILD_VENDOR=y
+CONFIG_OF_UPSTREAM_VENDOR="st"
 CONFIG_ENV_IS_NOWHERE=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y

configs/surface-2_defconfig

@@ -0,0 +1,80 @@
+CONFIG_ARM=y
+CONFIG_ARCH_TEGRA=y
+CONFIG_SUPPORT_PASSING_ATAGS=y
+CONFIG_CMDLINE_TAG=y
+CONFIG_INITRD_TAG=y
+CONFIG_TEXT_BASE=0x80110000
+CONFIG_SYS_MALLOC_LEN=0x2500000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SOURCE_FILE="surface-2"
+CONFIG_ENV_SIZE=0x3000
+CONFIG_ENV_OFFSET=0xFFFFD000
+CONFIG_DEFAULT_DEVICE_TREE="tegra114-microsoft-surface-2-0b"
+CONFIG_SPL_STACK=0x800ffffc
+CONFIG_SPL_TEXT_BASE=0x80108000
+CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_TEGRA114=y
+CONFIG_TARGET_SURFACE_2=y
+CONFIG_BUTTON_CMD=y
+CONFIG_BOOTDELAY=0
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_KEYED_CTRLC=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SYS_PBSIZE=2086
+CONFIG_SPL_FOOTPRINT_LIMIT=y
+CONFIG_SPL_MAX_FOOTPRINT=0x8000
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80090000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x10000
+CONFIG_SYS_PROMPT="Tegra114 (Surface 2) # "
+# CONFIG_CMD_BOOTEFI_BOOTMGR is not set
+CONFIG_CMD_BOOTMENU=y
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_UMS_ABORT_KEYED=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PAUSE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_OF_LIST="tegra114-microsoft-surface-2-0b tegra114-microsoft-surface-2-13"
+CONFIG_DTB_RESELECT=y
+CONFIG_MULTI_DTB_FIT=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_BUTTON=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x91000000
+CONFIG_FASTBOOT_BUF_SIZE=0x10000000
+CONFIG_SYS_I2C_TEGRA=y
+CONFIG_BUTTON_KEYBOARD=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_TPS65090=y
+CONFIG_PMIC_PALMAS=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_REGULATOR_TPS65090=y
+CONFIG_DM_REGULATOR_PALMAS=y
+CONFIG_PWM_TEGRA=y
+CONFIG_SYS_NS16550=y
+CONFIG_SYSRESET_PALMAS=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_TEGRA=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_VIDEO=y
+# CONFIG_VIDEO_LOGO is not set
+CONFIG_VIDEO_LCD_SAMSUNG_LTL106HL02=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_VIDEO_DSI_TEGRA=y

configs/tiger-rk3588_defconfig

@@ -35,6 +35,7 @@ CONFIG_SPL_ATF=y
 # CONFIG_BOOTM_RTEMS is not set
 # CONFIG_BOOTM_VXWORKS is not set
 # CONFIG_CMD_ELF is not set
+CONFIG_CMD_ERASEENV=y
 CONFIG_CMD_ADC=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y

doc/board/microsoft/index.rst

@@ -6,4 +6,5 @@ Microsoft
 .. toctree::
    :maxdepth: 2
 
+   surface-2
    surface-rt

doc/board/microsoft/surface-2.rst

@@ -0,0 +1,41 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for the Microsoft Surface 2 tablet
+=========================================
+
+Quick Start
+-----------
+
+- Build U-Boot
+- Boot
+
+Build U-Boot
+------------
+
+.. code-block:: bash
+
+    $ export CROSS_COMPILE=arm-none-eabi-
+    $ make surface-2_defconfig
+    $ make
+
+After the build succeeds, you will obtain the final ``u-boot-dtb-tegra.bin``
+image, ready for loading.
+
+Boot
+----
+
+Currently, U-Boot can be preloaded into RAM via the Fusée Gelée. To enter
+RCM protocol use ``power`` and ``volume up`` key combination from powered
+off device. The host PC should recognize an APX device.
+
+Built U-Boot ``u-boot-dtb-tegra.bin`` can be loaded from fusee-tools
+directory with
+
+.. code-block:: bash
+
+    $ ./run_bootloader.sh -s T30 -t ./bct/surface-2.bct
+
+To boot Linux, U-Boot will look for an ``extlinux.conf`` on MicroSD and then on
+eMMC. Additionally, if the Volume Down button is pressed while loading, the
+device will enter bootmenu. Bootmenu contains entries to mount MicroSD and eMMC
+as mass storage, fastboot, poweroff and enter U-Boot console.

doc/board/rockchip/rockchip.rst

@@ -134,7 +134,9 @@ List of mainline supported Rockchip boards:
      - Radxa ROCK 3B (rock-3b-rk3568)
 
 * rk3576
+     - ArmSoM Sige5 (sige5-rk3576)
      - Firefly ROC-RK3576-PC (roc-pc-rk3576)
+     - Generic RK3576 (generic-rk3576)
 
 * rk3588
      - ArmSoM Sige7 (sige7-rk3588)
@@ -145,6 +147,7 @@ List of mainline supported Rockchip boards:
      - FriendlyElec NanoPC-T6 (nanopc-t6-rk3588)
      - FriendlyElec NanoPi R6C (nanopi-r6c-rk3588s)
      - FriendlyElec NanoPi R6S (nanopi-r6s-rk3588s)
+     - GameForce Ace (gameforce-ace-rk3588s)
      - Generic RK3588S/RK3588 (generic-rk3588)
      - Hardkernel ODROID-M2 (odroid-m2-rk3588s)
      - Indiedroid Nova (nova-rk3588s)
@@ -161,6 +164,7 @@ List of mainline supported Rockchip boards:
      - Xunlong Orange Pi 5 (orangepi-5-rk3588s)
      - Xunlong Orange Pi 5 Max (orangepi-5-max-rk3588)
      - Xunlong Orange Pi 5 Plus (orangepi-5-plus-rk3588)
+     - Xunlong Orange Pi 5 Ultra (orangepi-5-ultra-rk3588)
      - Yanyi Tech CoolPi 4 Model B (coolpi-4b-rk3588s)
      - Yanyi Tech CoolPi CM5 EVB (coolpi-cm5-evb-rk3588)
      - Yanyi Tech CoolPi CM5 GenBook (coolpi-cm5-genbook-rk3588)

doc/build/clang.rst

@@ -46,9 +46,9 @@ It can also be used to compile sandbox:
 FreeBSD 11
 ----------
 
-Since llvm 3.4 is currently in the base system, the integrated assembler as
+Since LLVM 3.4 is currently in the base system, the integrated assembler is
-is incapable of building U-Boot. Therefore gas from devel/arm-gnueabi-binutils
+incapable of building U-Boot. Therefore gas from devel/arm-gnueabi-binutils is
-is used instead. It needs a symlink to be picked up correctly though:
+used instead. It needs a symbolic link to be picked up correctly though:
 
 .. code-block:: bash
 
@@ -64,7 +64,7 @@ The following commands compile U-Boot using the Clang xdev toolchain.
     gmake rpi_2_defconfig
     gmake CC="clang -target arm-freebsd-eabi --sysroot /usr/arm-freebsd" -j8
 
-Given that U-Boot will default to gcc, above commands can be
+Given that U-Boot will default to gcc, the commands above can be
 simplified with a simple wrapper script - saved as
 /usr/local/bin/arm-gnueabi-freebsd-gcc - listed below:
 

doc/build/gen_compile_commands.rst

@@ -39,7 +39,7 @@ course) to have an up-to-date database.
 
 The database will be in the root of the repository. No further modifications are
 needed for it to be usable by the LSP, unless you set a name for the database
-other than it's default one (compile_commands.json).
+other than the default one (compile_commands.json).
 
 Compatible IDEs
 ---------------

doc/build/reproducible.rst

@@ -24,4 +24,4 @@ This date is shown when we launch U-Boot:
     ./u-boot -T
     U-Boot 2023.01 (Jan 01 2023 - 00:00:00 +0000)
 
-The same effect can be obtained with buildman using the `-r` flag.
+The same effect can be obtained with Buildman using the `-r` flag.

doc/build/tools.rst

@@ -8,7 +8,7 @@ Building tools for Linux
 ------------------------
 
 To allow distributions to distribute all possible tools in a generic way,
-avoiding the need of specific tools building for each machine, a tools only
+avoiding the need of specific building tools for each machine, a tools-only
 defconfig file is provided.
 
 Using this, we can build the tools by doing::
@@ -30,9 +30,8 @@ installed all required packages below in order to build these host tools::
    * diffutils (3.7)
    * openssl-devel (1.1.1.d)
 
-Note the version numbers in these parentheses above are the package versions
+Note that the version numbers in parentheses above are the package versions at
-at the time being when writing this document. The MSYS2 installer tested is
+the time of writing this document.
-http://repo.msys2.org/distrib/x86_64/msys2-x86_64-20190524.exe.
 
 There are 3 MSYS subsystems installed: MSYS2, MinGW32 and MinGW64. Each
 subsystem provides an environment to build Windows applications. The MSYS2
@@ -50,7 +49,7 @@ Launch the MSYS2 shell of the MSYS2 environment, and do the following::
 Building without Python
 -----------------------
 
-The tools-only builds bytes pylibfdt by default. To disable this, use the
+The tools-only builds pylibfdt by default. To disable this, use the
 NO_PYTHON variable::
 
    NO_PYTHON=1 make tools-only_defconfig tools-only

doc/develop/release_cycle.rst

@@ -77,7 +77,7 @@ For the next scheduled release, release candidates were made on::
 
 * U-Boot |next_ver|-rc3 was released on Mon 25 August 2025.
 
-.. * U-Boot |next_ver|-rc4 was released on Mon 08 September 2025.
+* U-Boot |next_ver|-rc4 was released on Mon 08 September 2025.
 
 .. * U-Boot |next_ver|-rc5 was released on Mon 22 September 2025.
 

drivers/clk/at91/clk-main.c

@@ -315,7 +315,8 @@ static int clk_sam9x5_main_set_parent(struct clk *clk, struct clk *parent)
 {
 	struct clk_main *main = to_clk_main(clk);
 	void __iomem *reg = main->reg;
-	unsigned int tmp, index;
+	unsigned int tmp;
+	int index;
 
 	index = at91_clk_mux_val_to_index(main->clk_mux_table,
 			main->num_parents, AT91_CLK_ID_TO_DID(parent->id));

drivers/clk/at91/clk-master.c

@@ -335,8 +335,8 @@ struct clk *at91_clk_sama7g5_register_master(void __iomem *base,
 {
 	struct clk_master *master;
 	struct clk *clk;
-	u32 val, index;
+	u32 val;
-	int ret;
+	int ret, index;
 
 	if (!base || !name || !num_parents || !parent_names ||
 	    !mux_table || !clk_mux_table || id > MASTER_MAX_ID)

drivers/clk/at91/sckc.c

@@ -74,8 +74,8 @@ static struct clk *at91_sam9x60_clk_register_td_slck(struct sam9x60_sckc *sckc,
 		int num_parents)
 {
 	struct clk *clk;
-	int ret = -ENOMEM;
+	int ret = -ENOMEM, i;
-	u32 val, i;
+	u32 val;
 
 	if (!sckc || !name || !parent_names || num_parents != 2)
 		return ERR_PTR(-EINVAL);
@@ -99,8 +99,10 @@ static struct clk *at91_sam9x60_clk_register_td_slck(struct sam9x60_sckc *sckc,
 	clk = &sckc->clk;
 	ret = clk_register(clk, UBOOT_DM_CLK_AT91_SAM9X60_TD_SLCK, name,
 			   parent_names[val]);
-	if (ret)
+	if (ret) {
+		i--;
 		goto free;
+	}
 
 	return clk;
 

drivers/clk/exynos/clk-exynos7420.c

@@ -192,7 +192,7 @@ static int exynos7420_clk_top0_probe(struct udevice *dev)
 static ulong exynos7420_peric1_get_rate(struct clk *clk)
 {
 	struct clk in_clk;
-	unsigned int ret;
+	int ret;
 	unsigned long freq = 0;
 
 	switch (clk->id) {

drivers/clk/rockchip/clk_rk3528.c

@@ -1535,6 +1535,7 @@ static ulong rk3528_clk_set_rate(struct clk *clk, ulong rate)
 	/* Might occur in cru assigned-clocks, can be ignored here */
 	case ACLK_BUS_VOPGL_ROOT:
 	case BCLK_EMMC:
+	case CLK_REF_PCIE_INNER_PHY:
 	case XIN_OSC0_DIV:
 		ret = 0;
 		break;

drivers/clk/rockchip/clk_rk3576.c

@@ -2168,6 +2168,8 @@ static ulong rk3576_clk_set_rate(struct clk *clk, ulong rate)
 	case CLK_CPLL_DIV10:
 	case FCLK_DDR_CM0_CORE:
 	case ACLK_PHP_ROOT:
+	case CLK_REF_PCIE0_PHY:
+	case CLK_REF_PCIE1_PHY:
 		ret = 0;
 		break;
 #ifndef CONFIG_SPL_BUILD

drivers/mfd/atmel-smc.c

@@ -347,7 +347,7 @@ const struct atmel_hsmc_reg_layout *
 atmel_hsmc_get_reg_layout(ofnode np)
 {
 	int i;
-	const struct udevice_id *match;
+	const struct udevice_id *match = NULL;
 	const char *name;
 	int len;
 

drivers/mmc/gen_atmel_mci.c

@@ -206,10 +206,9 @@ static u32 mci_data_read(atmel_mci_t *mci, u32* data, u32 error_flags)
 			goto io_fail;
 	} while (!(status & MMCI_BIT(RXRDY)));
 
-	if (status & MMCI_BIT(RXRDY)) {
+	*data = readl(&mci->rdr);
-		*data = readl(&mci->rdr);
+	status = 0;
-		status = 0;
+
-	}
 io_fail:
 	return status;
 }
@@ -225,10 +224,9 @@ static u32 mci_data_write(atmel_mci_t *mci, u32* data, u32 error_flags)
 			goto io_fail;
 	} while (!(status & MMCI_BIT(TXRDY)));
 
-	if (status & MMCI_BIT(TXRDY)) {
+	writel(*data, &mci->tdr);
-		writel(*data, &mci->tdr);
+	status = 0;
-		status = 0;
+
-	}
 io_fail:
 	return status;
 }
@@ -265,13 +263,15 @@ mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 	/* Figure out the transfer arguments */
 	cmdr = mci_encode_cmd(cmd, data, &error_flags);
 
-	mci_set_blklen(mci, data->blocksize);
+	if (data) {
+		mci_set_blklen(mci, data->blocksize);
 
-	/* For multi blocks read/write, set the block register */
+		/* For multi blocks read/write, set the block register */
-	if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK)
+		if (cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK ||
-			|| (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK))
+		    cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)
-		writel(data->blocks | MMCI_BF(BLKLEN, data->blocksize),
+			writel(data->blocks | MMCI_BF(BLKLEN, data->blocksize),
-		       &mci->blkr);
+			       &mci->blkr);
+	}
 
 	/* Send the command */
 	writel(cmd->cmdarg, &mci->argr);

drivers/mmc/rockchip_sdhci.c

@@ -500,7 +500,7 @@ static int rockchip_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
 {
 	struct rockchip_sdhc *priv = dev_get_priv(mmc->dev);
 	struct sdhci_host *host = &priv->host;
-	char tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT;
+	s8 tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT;
 	struct mmc_cmd cmd;
 	u32 ctrl, blk_size;
 	int ret;

drivers/mmc/stm32_sdmmc2.c

@@ -385,15 +385,29 @@ static int stm32_sdmmc2_end_data(struct udevice *dev,
 	u32 mask = SDMMC_STA_DCRCFAIL | SDMMC_STA_DTIMEOUT |
 		   SDMMC_STA_IDMATE | SDMMC_STA_DATAEND;
 	u32 status;
+	unsigned long timeout_msecs = ctx->data_length >> 8;
+	unsigned long start_timeout;
+
+	/* At least, a timeout of 2 seconds is set */
+	if (timeout_msecs < 2000)
+		timeout_msecs = 2000;
 
 	if (data->flags & MMC_DATA_READ)
 		mask |= SDMMC_STA_RXOVERR;
 	else
 		mask |= SDMMC_STA_TXUNDERR;
 
+	start_timeout = get_timer(0);
 	status = readl(plat->base + SDMMC_STA);
-	while (!(status & mask))
+	while (!(status & mask)) {
+		if (get_timer(start_timeout) > timeout_msecs) {
+			ctx->dpsm_abort = true;
+			return -ETIMEDOUT;
+		}
+
+		schedule();
 		status = readl(plat->base + SDMMC_STA);
+	}
 
 	/*
 	 * Need invalidate the dcache again to avoid any

drivers/mtd/nand/raw/stm32_fmc2_nand.c

@@ -1034,6 +1034,7 @@ static int stm32_fmc2_nfc_probe(struct udevice *dev)
 		ecclayout->eccpos[i] = oob_index;
 	ecclayout->oobfree->offset = oob_index;
 	ecclayout->oobfree->length = mtd->oobsize - ecclayout->oobfree->offset;
+	ecclayout->oobavail = ecclayout->oobfree->length;
 	chip->ecc.layout = ecclayout;
 
 	if (chip->options & NAND_BUSWIDTH_16)

drivers/net/MAINTAINERS

@@ -0,0 +1,6 @@
+NETWORK DW XGMAC
+M:	Boon Khai Ng <boon.khai.ng@altera.com>
+S:	Supported
+F:	drivers/net/dwc_eth_xgmac.c
+F:	drivers/net/dwc_eth_xgmac.h
+F:	drivers/net/dwc_eth_xgmac_socfpga.c

drivers/phy/rockchip/phy-rockchip-inno-usb2.c

@@ -167,20 +167,27 @@ static struct phy_ops rockchip_usb2phy_ops = {
 	.of_xlate = rockchip_usb2phy_of_xlate,
 };
 
-static void rockchip_usb2phy_clkout_ctl(struct clk *clk, struct regmap **base,
+static int rockchip_usb2phy_clkout_ctl(struct clk *clk, struct regmap **base,
-					const struct usb2phy_reg **clkout_ctl)
+				       const struct usb2phy_reg **clkout_ctl)
 {
 	struct udevice *parent = dev_get_parent(clk->dev);
 	struct rockchip_usb2phy *priv = dev_get_priv(parent);
 	const struct rockchip_usb2phy_cfg *phy_cfg = priv->phy_cfg;
 
-	if (priv->phy_cfg->clkout_ctl_phy.enable) {
+	// phy_cfg can be NULL if this function called before probe (when parent
+	// clocks are enabled)
+	if (!phy_cfg)
+		return -EINVAL;
+
+	if (phy_cfg->clkout_ctl_phy.enable) {
 		*base = priv->phy_base;
 		*clkout_ctl = &phy_cfg->clkout_ctl_phy;
 	} else {
 		*base = priv->reg_base;
 		*clkout_ctl = &phy_cfg->clkout_ctl;
 	}
+
+	return 0;
 }
 
 /**
@@ -206,7 +213,8 @@ int rockchip_usb2phy_clk_enable(struct clk *clk)
 	const struct usb2phy_reg *clkout_ctl;
 	struct regmap *base;
 
-	rockchip_usb2phy_clkout_ctl(clk, &base, &clkout_ctl);
+	if (rockchip_usb2phy_clkout_ctl(clk, &base, &clkout_ctl))
+		return -ENOSYS;
 
 	/* turn on 480m clk output if it is off */
 	if (!property_enabled(base, clkout_ctl)) {
@@ -230,7 +238,8 @@ int rockchip_usb2phy_clk_disable(struct clk *clk)
 	const struct usb2phy_reg *clkout_ctl;
 	struct regmap *base;
 
-	rockchip_usb2phy_clkout_ctl(clk, &base, &clkout_ctl);
+	if (rockchip_usb2phy_clkout_ctl(clk, &base, &clkout_ctl))
+		return -ENOSYS;
 
 	/* turn off 480m clk output */
 	property_enable(base, clkout_ctl, false);
@@ -456,6 +465,28 @@ static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = {
 	{ /* sentinel */ }
 };
 
+static const struct rockchip_usb2phy_cfg rk3576_phy_cfgs[] = {
+	{
+		.reg		= 0x0000,
+		.clkout_ctl	= { 0x0008, 0, 0, 1, 0 },
+		.port_cfgs	= {
+			[USB2PHY_PORT_OTG] = {
+				.phy_sus	= { 0x0000, 1, 0, 2, 1 },
+			}
+		},
+	},
+	{
+		.reg		= 0x2000,
+		.clkout_ctl	= { 0x2008, 0, 0, 1, 0 },
+		.port_cfgs	= {
+			[USB2PHY_PORT_OTG] = {
+				.phy_sus	= { 0x2000, 1, 0, 2, 1 },
+			}
+		},
+	},
+	{ /* sentinel */ }
+};
+
 static const struct rockchip_usb2phy_cfg rk3588_phy_cfgs[] = {
 	{
 		.reg		= 0x0000,
@@ -517,6 +548,10 @@ static const struct udevice_id rockchip_usb2phy_ids[] = {
 		.compatible = "rockchip,rk3568-usb2phy",
 		.data = (ulong)&rk3568_phy_cfgs,
 	},
+	{
+		.compatible = "rockchip,rk3576-usb2phy",
+		.data = (ulong)&rk3576_phy_cfgs,
+	},
 	{
 		.compatible = "rockchip,rk3588-usb2phy",
 		.data = (ulong)&rk3588_phy_cfgs,
@@ -538,7 +573,7 @@ U_BOOT_DRIVER(rockchip_usb2phy_clock) = {
 
 U_BOOT_DRIVER(rockchip_usb2phy) = {
 	.name	= "rockchip_usb2phy",
-	.id	= UCLASS_PHY,
+	.id	= UCLASS_NOP,
 	.of_match = rockchip_usb2phy_ids,
 	.probe = rockchip_usb2phy_probe,
 	.bind = rockchip_usb2phy_bind,