From 709b5be0a48d4e5bb95ef0b107c56045a8fe67c6 Mon Sep 17 00:00:00 2001 From: Ramin Moussavi Date: Tue, 22 Jul 2025 20:27:09 +0200 Subject: [PATCH 001/103] spi: atmel_qspi: fix race condition in transfer completion check In atmel_qspi_transfer(), the status register is polled with: imr = QSPI_SR_INSTRE | QSPI_SR_CSR; return readl_poll_timeout(aq->regs + QSPI_SR, sr, (sr & imr) == imr, ATMEL_QSPI_TIMEOUT); However, this is racy: QSPI_SR_INSTRE can be set before QSPI_SR_CSR, and will then be cleared by the read. If that happens, the condition "(sr & imr) == imr" can never be true, and the function times out. This race condition is avoided in at91bootstrap by accumulating the status bits across reads until both bits have been observed: /* Poll INSTruction End and Chip Select Rise flags. */ imr = (QSPI_SR_INSTRE | QSPI_SR_CSR); sr = 0; do { udelay(1); sr |= qspi_readl(qspi, QSPI_SR) & imr; } while ((--timeout) && (sr != imr)); Update U-Boot's atmel_qspi_transfer() to use the same pattern, ensuring that both flags are observed even if they are not set simultaneously. Signed-off-by: Ramin Moussavi [eugen.hristev@linaro.org: remove 'sr' and fix commit msg] Signed-off-by: Eugen Hristev --- drivers/spi/atmel-quadspi.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c index 8aa7a83aef4..b2b96e1c4b9 100644 --- a/drivers/spi/atmel-quadspi.c +++ b/drivers/spi/atmel-quadspi.c @@ -615,7 +615,8 @@ static int atmel_qspi_set_cfg(struct atmel_qspi *aq, static int atmel_qspi_transfer(struct atmel_qspi *aq, const struct spi_mem_op *op, u32 offset) { - u32 sr, imr; + u32 imr, val = 0; + unsigned long timeout; /* Skip to the final steps if there is no data */ if (op->data.nbytes) { @@ -636,8 +637,16 @@ static int atmel_qspi_transfer(struct atmel_qspi *aq, /* Poll INSTruction End and Chip Select Rise flags. */ imr = QSPI_SR_INSTRE | QSPI_SR_CSR; - return readl_poll_timeout(aq->regs + QSPI_SR, sr, (sr & imr) == imr, - ATMEL_QSPI_TIMEOUT); + + timeout = timer_get_us() + ATMEL_QSPI_TIMEOUT; + while (1) { + val |= readl(aq->regs + QSPI_SR) & imr; + if ((val & imr) == imr) + return 0; + + if (time_after(timer_get_us(), timeout)) + return -ETIMEDOUT; + } } static int atmel_qspi_sama7g5_set_cfg(struct atmel_qspi *aq, From 29ea990a1c4a2455f432d5e71b217e93b406fc12 Mon Sep 17 00:00:00 2001 From: Andrew Goodbody Date: Wed, 23 Jul 2025 15:13:48 +0100 Subject: [PATCH 002/103] clk: at91: Fix testing of unsigned variable to be negative The variable 'index' is declared as unsigned but used to receive the return value of a function returning 'int'. This value is then tested for being less than zero to detect an error condition but as index is unsigned this can never be true. Change the variable 'index' to be an int so that the error condition can be detected. This issue was found by Smatch. Signed-off-by: Andrew Goodbody --- drivers/clk/at91/clk-main.c | 3 ++- drivers/clk/at91/clk-master.c | 4 ++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/clk/at91/clk-main.c b/drivers/clk/at91/clk-main.c index a5186f885f0..0542b066788 100644 --- a/drivers/clk/at91/clk-main.c +++ b/drivers/clk/at91/clk-main.c @@ -315,7 +315,8 @@ static int clk_sam9x5_main_set_parent(struct clk *clk, struct clk *parent) { struct clk_main *main = to_clk_main(clk); void __iomem *reg = main->reg; - unsigned int tmp, index; + unsigned int tmp; + int index; index = at91_clk_mux_val_to_index(main->clk_mux_table, main->num_parents, AT91_CLK_ID_TO_DID(parent->id)); diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c index cdc5271fa83..530205b8c6b 100644 --- a/drivers/clk/at91/clk-master.c +++ b/drivers/clk/at91/clk-master.c @@ -335,8 +335,8 @@ struct clk *at91_clk_sama7g5_register_master(void __iomem *base, { struct clk_master *master; struct clk *clk; - u32 val, index; - int ret; + u32 val; + int ret, index; if (!base || !name || !num_parents || !parent_names || !mux_table || !clk_mux_table || id > MASTER_MAX_ID) From da13ce8a6b1a37c49d2215ef78ee7984bae1c068 Mon Sep 17 00:00:00 2001 From: Andrew Goodbody Date: Wed, 23 Jul 2025 15:13:49 +0100 Subject: [PATCH 003/103] clk: at91: Fix use of unsigned loop index The use of the unsigned variable 'i' as a loop index leads to the test for i being non-negative always being true. Instead declare 'i' as an int so that the for loop will terminate as expected. If the original for loop completes 'i' will be 1 past the end of the array so decrement it in the subsequent error path to prevent an out of bounds access occurring. This issue was found by Smatch. Signed-off-by: Andrew Goodbody --- drivers/clk/at91/sckc.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at91/sckc.c index 6d6f12578db..3fde8ea7138 100644 --- a/drivers/clk/at91/sckc.c +++ b/drivers/clk/at91/sckc.c @@ -74,8 +74,8 @@ static struct clk *at91_sam9x60_clk_register_td_slck(struct sam9x60_sckc *sckc, int num_parents) { struct clk *clk; - int ret = -ENOMEM; - u32 val, i; + int ret = -ENOMEM, i; + u32 val; if (!sckc || !name || !parent_names || num_parents != 2) return ERR_PTR(-EINVAL); @@ -99,8 +99,10 @@ static struct clk *at91_sam9x60_clk_register_td_slck(struct sam9x60_sckc *sckc, clk = &sckc->clk; ret = clk_register(clk, UBOOT_DM_CLK_AT91_SAM9X60_TD_SLCK, name, parent_names[val]); - if (ret) + if (ret) { + i--; goto free; + } return clk; From b824136ab4f743e09c81af531d430dbe6a2d92bf Mon Sep 17 00:00:00 2001 From: Andrew Goodbody Date: Mon, 28 Jul 2025 17:12:13 +0100 Subject: [PATCH 004/103] mfd: atmel-smc: Ensure match is initialised If the test in the for loop is never matched then the variable 'match' will never be assigned to. Provide an initial value so this cannot be a problem. This issue was found by Smatch. Signed-off-by: Andrew Goodbody --- drivers/mfd/atmel-smc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mfd/atmel-smc.c b/drivers/mfd/atmel-smc.c index 15296f71a16..94e5e7b67a0 100644 --- a/drivers/mfd/atmel-smc.c +++ b/drivers/mfd/atmel-smc.c @@ -347,7 +347,7 @@ const struct atmel_hsmc_reg_layout * atmel_hsmc_get_reg_layout(ofnode np) { int i; - const struct udevice_id *match; + const struct udevice_id *match = NULL; const char *name; int len; From 4fb189a58eacd8bac267f2f330b41e7700bcfa12 Mon Sep 17 00:00:00 2001 From: Andrew Goodbody Date: Tue, 29 Jul 2025 17:16:16 +0100 Subject: [PATCH 005/103] mmc: gen_atmel_mci: Remove duplicate checks Remove duplicate checks on status from mci_data_read and mci_data_write which are guaranteed to be true as exiting the above do..while loop above requires that to be so. This issue was found by Smatch. Signed-off-by: Andrew Goodbody Reviewed-by: Peng Fan --- drivers/mmc/gen_atmel_mci.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/drivers/mmc/gen_atmel_mci.c b/drivers/mmc/gen_atmel_mci.c index 6a531fa0961..62aa6b3cb0b 100644 --- a/drivers/mmc/gen_atmel_mci.c +++ b/drivers/mmc/gen_atmel_mci.c @@ -206,10 +206,9 @@ static u32 mci_data_read(atmel_mci_t *mci, u32* data, u32 error_flags) goto io_fail; } while (!(status & MMCI_BIT(RXRDY))); - if (status & MMCI_BIT(RXRDY)) { - *data = readl(&mci->rdr); - status = 0; - } + *data = readl(&mci->rdr); + status = 0; + io_fail: return status; } @@ -225,10 +224,9 @@ static u32 mci_data_write(atmel_mci_t *mci, u32* data, u32 error_flags) goto io_fail; } while (!(status & MMCI_BIT(TXRDY))); - if (status & MMCI_BIT(TXRDY)) { - writel(*data, &mci->tdr); - status = 0; - } + writel(*data, &mci->tdr); + status = 0; + io_fail: return status; } From c1168f99387b40f5e3323ff16c670427c2c8a66e Mon Sep 17 00:00:00 2001 From: Andrew Goodbody Date: Tue, 29 Jul 2025 17:16:17 +0100 Subject: [PATCH 006/103] mmc: gen_atmel_mci: NULL check variable before use In mci_send_cmd the pointer 'data' is optional so guard its use with a NULL check to prevent any attempt to dereference it when not provided. This issue was found by Smatch. Signed-off-by: Andrew Goodbody Reviewed-by: Peng Fan --- drivers/mmc/gen_atmel_mci.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/mmc/gen_atmel_mci.c b/drivers/mmc/gen_atmel_mci.c index 62aa6b3cb0b..838b4f4a65a 100644 --- a/drivers/mmc/gen_atmel_mci.c +++ b/drivers/mmc/gen_atmel_mci.c @@ -263,13 +263,15 @@ mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) /* Figure out the transfer arguments */ cmdr = mci_encode_cmd(cmd, data, &error_flags); - mci_set_blklen(mci, data->blocksize); + if (data) { + mci_set_blklen(mci, data->blocksize); - /* For multi blocks read/write, set the block register */ - if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) - || (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) - writel(data->blocks | MMCI_BF(BLKLEN, data->blocksize), - &mci->blkr); + /* For multi blocks read/write, set the block register */ + if (cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK || + cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK) + writel(data->blocks | MMCI_BF(BLKLEN, data->blocksize), + &mci->blkr); + } /* Send the command */ writel(cmd->cmdarg, &mci->argr); From e69e2dc7f5559cb5fe31dddf4b3f5336c25fa0ac Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jonas=20Schw=C3=B6bel?= Date: Sat, 2 Dec 2023 08:19:41 +0100 Subject: [PATCH 007/103] board: microsoft: add Microsoft Surface 2 support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Surface 2 is a Surface-series Windows RT hybrid tablet computer created by Microsoft. Surface 2 uses a 1.7 GHz quad-core Nvidia Tegra 4 chipset with 2 GB of RAM, features 10.6 inch FullHD ClearType HD screen with 16:9 aspect ratio and 32/64 GB of internal memory that can be supplemented with a microSDXC card giving up to 64 GB of additional storage. Signed-off-by: Jonas Schwöbel Signed-off-by: Svyatoslav Ryhel --- arch/arm/dts/Makefile | 2 + .../dts/tegra114-microsoft-surface-2-0b.dts | 10 + .../dts/tegra114-microsoft-surface-2-13.dts | 10 + .../tegra114-microsoft-surface-2-common.dtsi | 905 ++++++++++++++++++ arch/arm/mach-tegra/tegra114/Kconfig | 5 + board/microsoft/surface-2/Kconfig | 13 + board/microsoft/surface-2/MAINTAINERS | 7 + board/microsoft/surface-2/Makefile | 6 + board/microsoft/surface-2/board-info.c | 71 ++ board/microsoft/surface-2/surface-2-spl.c | 42 + board/microsoft/surface-2/surface-2.env | 8 + configs/surface-2_defconfig | 82 ++ doc/board/microsoft/index.rst | 1 + doc/board/microsoft/surface-2.rst | 41 + 14 files changed, 1203 insertions(+) create mode 100644 arch/arm/dts/tegra114-microsoft-surface-2-0b.dts create mode 100644 arch/arm/dts/tegra114-microsoft-surface-2-13.dts create mode 100644 arch/arm/dts/tegra114-microsoft-surface-2-common.dtsi create mode 100644 board/microsoft/surface-2/Kconfig create mode 100644 board/microsoft/surface-2/MAINTAINERS create mode 100644 board/microsoft/surface-2/Makefile create mode 100644 board/microsoft/surface-2/board-info.c create mode 100644 board/microsoft/surface-2/surface-2-spl.c create mode 100644 board/microsoft/surface-2/surface-2.env create mode 100644 configs/surface-2_defconfig create mode 100644 doc/board/microsoft/surface-2.rst diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index ff8f1ed1ac0..7c8cf3a5a1d 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -124,6 +124,8 @@ dtb-$(CONFIG_ARCH_TEGRA) += \ tegra30-wexler-qc750.dtb \ tegra114-asus-tf701t.dtb \ tegra114-dalmore.dtb \ + tegra114-microsoft-surface-2-0b.dtb \ + tegra114-microsoft-surface-2-13.dtb \ tegra114-nvidia-tegratab.dtb \ tegra124-apalis.dtb \ tegra124-jetson-tk1.dtb \ diff --git a/arch/arm/dts/tegra114-microsoft-surface-2-0b.dts b/arch/arm/dts/tegra114-microsoft-surface-2-0b.dts new file mode 100644 index 00000000000..2007aae8737 --- /dev/null +++ b/arch/arm/dts/tegra114-microsoft-surface-2-0b.dts @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra114-microsoft-surface-2-common.dtsi" + +/ { + backlight: backlight { + enable-gpios = <&gpio TEGRA_GPIO(CC, 2) GPIO_ACTIVE_HIGH>; + }; +}; diff --git a/arch/arm/dts/tegra114-microsoft-surface-2-13.dts b/arch/arm/dts/tegra114-microsoft-surface-2-13.dts new file mode 100644 index 00000000000..da121d5a101 --- /dev/null +++ b/arch/arm/dts/tegra114-microsoft-surface-2-13.dts @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra114-microsoft-surface-2-common.dtsi" + +/ { + backlight: backlight { + enable-gpios = <&gpio TEGRA_GPIO(EE, 3) GPIO_ACTIVE_HIGH>; + }; +}; diff --git a/arch/arm/dts/tegra114-microsoft-surface-2-common.dtsi b/arch/arm/dts/tegra114-microsoft-surface-2-common.dtsi new file mode 100644 index 00000000000..f8f71262538 --- /dev/null +++ b/arch/arm/dts/tegra114-microsoft-surface-2-common.dtsi @@ -0,0 +1,905 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +#include "tegra114.dtsi" + +/ { + model = "Microsoft Surface 2"; + compatible = "microsoft,surface-2", "nvidia,tegra114"; + + chosen { + stdout-path = &uarta; + }; + + aliases { + i2c0 = &pwr_i2c; + + mmc0 = &sdmmc4; /* eMMC */ + mmc1 = &sdmmc3; /* uSD slot */ + + usb0 = &usb1; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + host1x@50000000 { + dsia: dsi@54300000 { + status = "okay"; + + avdd-dsi-csi-supply = <&avdd_dsi_csi>; + + panel@0 { + compatible = "samsung,ltl106hl02-001"; + reg = <0>; + + vdd-supply = <&tps65090_fet4>; + + backlight = <&backlight>; + }; + }; + }; + + pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + /* ULPI pinmux */ + ulpi-data0 { + nvidia,pins = "ulpi_data0_po1", + "ulpi_data3_po4", + "ulpi_data4_po5"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi-data1 { + nvidia,pins = "ulpi_data1_po2"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi-data2 { + nvidia,pins = "ulpi_data2_po3"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi-data7 { + nvidia,pins = "ulpi_data7_po0", + "ulpi_data5_po6", + "ulpi_data6_po7"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* I2S pinmux */ + dap1-din { + nvidia,pins = "dap1_fs_pn0", + "dap1_din_pn1", + "dap1_sclk_pn3"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1-dout { + nvidia,pins = "dap1_dout_pn2"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2-i2s1 { + nvidia,pins = "dap2_fs_pa2", + "dap2_sclk_pa3", + "dap2_din_pa4", + "dap2_dout_pa5"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3-i2s2 { + nvidia,pins = "dap3_fs_pp0", + "dap3_din_pp1", + "dap3_dout_pp2", + "dap3_sclk_pp3"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4-din { + nvidia,pins = "dap4_fs_pp4", + "dap4_din_pp5", + "dap4_sclk_pp7"; + nvidia,function = "i2s3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4-dout { + nvidia,pins = "dap4_dout_pp6"; + nvidia,function = "i2s3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* SDMMC1 pinmux */ + sdmmc1-wp-clk { + nvidia,pins = "sdmmc1_wp_n_pv3", + "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1-cmd { + nvidia,pins = "sdmmc1_cmd_pz1", + "sdmmc1_dat3_py4", + "sdmmc1_dat2_py5", + "sdmmc1_dat1_py6", + "sdmmc1_dat0_py7"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* SDMMC3 pinmux */ + sdmmc3-clk { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3-cmd { + nvidia,pins = "sdmmc3_cmd_pa7", + "sdmmc3_dat3_pb4", + "sdmmc3_dat2_pb5", + "sdmmc3_dat1_pb6", + "sdmmc3_dat0_pb7", + "sdmmc3_cd_n_pv2", + "sdmmc3_clk_lb_in_pee5"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3-clk-lb-out { + nvidia,pins = "sdmmc3_clk_lb_out_pee4"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* SDMMC4 pinmux */ + sdmmc4-clk { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4-cmd { + nvidia,pins = "sdmmc4_cmd_pt7", + "sdmmc4_dat0_paa0", + "sdmmc4_dat1_paa1", + "sdmmc4_dat2_paa2", + "sdmmc4_dat3_paa3", + "sdmmc4_dat4_paa4", + "sdmmc4_dat5_paa5", + "sdmmc4_dat6_paa6", + "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* HDMI pinmux */ + hdmi-int { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,rcv-sel = ; + }; + hdmi-cec { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + /* I2C pinmux */ + gen1-i2c { + nvidia,pins = "gen1_i2c_scl_pc4", + "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + gen2-i2c { + nvidia,pins = "gen2_i2c_scl_pt5", + "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + cam-i2c { + nvidia,pins = "cam_i2c_scl_pbb1", + "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + ddc-scl-pv4 { + nvidia,pins = "ddc_scl_pv4", + "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,rcv-sel = ; + }; + pwr-i2c { + nvidia,pins = "pwr_i2c_scl_pz6", + "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + /* UARTA pinmux */ + uarta-out { + nvidia,pins = "pu0", "pu3"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uarta-in { + nvidia,pins = "pu1", "pu2"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* UARTB pinmux */ + uart2-txd-pc2 { + nvidia,pins = "uart2_txd_pc2"; + nvidia,function = "irda"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2-rxd-pc3 { + nvidia,pins = "uart2_rxd_pc3"; + nvidia,function = "irda"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2-cts-n-pj5 { + nvidia,pins = "uart2_cts_n_pj5", + "uart2_rts_n_pj6"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* UARTC pinmux */ + uart3-cts-rxd { + nvidia,pins = "uart3_cts_n_pa1", + "uart3_rxd_pw7"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3-rts-txd { + nvidia,pins = "uart3_rts_n_pc0", + "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* UARTD pinmux */ + uartd-out { + nvidia,pins = "ulpi_clk_py0", + "ulpi_stp_py3"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uartd-in { + nvidia,pins = "ulpi_dir_py1", + "ulpi_nxt_py2"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* GMI section */ + gmi-a17 { + nvidia,pins = "gmi_a17_pb0", + "gmi_a18_pb1", + "gmi_iordy_pi5", + "kb_col1_pq1", + "kb_row8_ps0", + "pbb6"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-wp-n { + nvidia,pins = "gmi_wp_n_pc7", + "gmi_cs0_n_pj0", + "gpio_x7_aud_px7"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-ad0 { + nvidia,pins = "gmi_ad0_pg0", + "gmi_ad1_pg1", + "gmi_ad2_pg2", + "gmi_ad3_pg3", + "gmi_ad4_pg4", + "gmi_ad5_pg5", + "gmi_ad6_pg6", + "gmi_ad7_pg7", + "gmi_oe_n_pi1", + "pv1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-ad8 { + nvidia,pins = "gmi_ad8_ph0"; + nvidia,function = "pwm0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-ad9 { + nvidia,pins = "gmi_ad9_ph1", + "gmi_ad10_ph2", + "gmi_ad11_ph3", + "gmi_ad15_ph7", + "gmi_cs4_n_pk2"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-ad12 { + nvidia,pins = "gmi_ad12_ph4", + "gmi_ad13_ph5", + "gpio_x1_aud_px1", + "pcc1", + "clk3_req_pee1", + "clk1_req_pee2"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-ad14 { + nvidia,pins = "gmi_ad14_ph6", + "gmi_a16_pj7", + "gmi_a19_pk7"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-wr-n { + nvidia,pins = "gmi_wr_n_pi0"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-cs6-n { + nvidia,pins = "gmi_cs6_n_pi3", + "gmi_cs7_n_pi6"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-rst-n { + nvidia,pins = "gmi_rst_n_pi4", + "spdif_out_pk5", + "spdif_in_pk6", + "clk2_out_pw5", + "dvfs_pwm_px0", + "dvfs_clk_px2", + "pbb7", + "pcc2", + "clk2_req_pcc5"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-wait { + nvidia,pins = "gmi_wait_pi7"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-cs1-n { + nvidia,pins = "gmi_cs1_n_pj2"; + nvidia,function = "soc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-dqs-p { + nvidia,pins = "gmi_dqs_p_pj3"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-adv-n { + nvidia,pins = "gmi_adv_n_pk0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-clk { + nvidia,pins = "gmi_clk_pk1", + "gmi_cs2_n_pk3", + "gmi_cs3_n_pk4"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + jtag-rtck { + nvidia,pins = "jtag_rtck"; + nvidia,function = "rtck"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* KBC pinmux */ + kb-col0 { + nvidia,pins = "kb_col0_pq0", + "kb_col3_pq3", + "kb_col4_pq4", + "kb_row4_pr4"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-col2 { + nvidia,pins = "kb_col2_pq2", + "kb_col6_pq6", + "kb_col7_pq7", + "kb_row0_pr0", + "kb_row2_pr2", + "pv0", + "sys_clk_req_pz5"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-col5 { + nvidia,pins = "kb_col5_pq5", + "kb_row5_pr5"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-row1 { + nvidia,pins = "kb_row1_pr1"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-row3 { + nvidia,pins = "kb_row3_pr3", + "kb_row9_ps1"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-row6 { + nvidia,pins = "kb_row6_pr6"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-row7 { + nvidia,pins = "kb_row7_pr7", + "pbb3", + "pbb4", + "pbb5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-row10 { + nvidia,pins = "kb_row10_ps2"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* CORE pinmux */ + clk-32k-out { + nvidia,pins = "clk_32k_out_pa0"; + nvidia,function = "blink"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk-32k-in { + nvidia,pins = "clk_32k_in"; + nvidia,function = "clk"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + core-pwr-req { + nvidia,pins = "core_pwr_req"; + nvidia,function = "pwron"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + cpu-pwr-req { + nvidia,pins = "cpu_pwr_req"; + nvidia,function = "cpu"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pwr-int-n { + nvidia,pins = "pwr_int_n"; + nvidia,function = "pmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + owr { + nvidia,pins = "owr"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,rcv-sel = ; + }; + reset-out-n { + nvidia,pins = "reset_out_n"; + nvidia,function = "reset_out_n"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* AUD pinmux */ + gpio-w2-aud { + nvidia,pins = "gpio_w2_aud_pw2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio-w3-aud { + nvidia,pins = "gpio_w3_aud_pw3"; + nvidia,function = "spi6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio-x3-aud { + nvidia,pins = "gpio_x3_aud_px3"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio-x4-aud { + nvidia,pins = "gpio_x4_aud_px4"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio-x5-aud { + nvidia,pins = "gpio_x5_aud_px5"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio-x6-aud { + nvidia,pins = "gpio_x6_aud_px6"; + nvidia,function = "spi6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu4 { + nvidia,pins = "pu4"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu5 { + nvidia,pins = "pu5"; + nvidia,function = "pwm2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu6 { + nvidia,pins = "pu6"; + nvidia,function = "pwm3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb0 { + nvidia,pins = "pbb0", + "cam_mclk_pcc0"; + nvidia,function = "vi_alt1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk1-out { + nvidia,pins = "clk1_out_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk3-out { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* USB pinmux */ + usb-vbus-en0 { + nvidia,pins = "usb_vbus_en0_pn4"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + usb-vbus-en1 { + nvidia,pins = "usb_vbus_en1_pn5"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + }; + }; + + uarta: serial@70006000 { + status = "okay"; + }; + + pwm: pwm@7000a000 { + status = "okay"; + }; + + pwr_i2c: i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + /* Texas Instruments TPS65090 PMIC */ + tps65090@48 { + compatible = "ti,tps65090"; + reg = <0x48>; + + regulators { + tps65090_fet1: fet1 { + regulator-name = "vcd_led"; + regulator-boot-on; + }; + + tps65090_fet4: fet4 { + regulator-name = "vdd_lcd"; + regulator-boot-on; + }; + + tps65090_fet6: fet6 { + regulator-name = "vdd_usd"; + regulator-boot-on; + }; + }; + }; + + /* Texas Instruments TPS65913 PMIC */ + pmic: tps65913@58 { + compatible = "ti,tps65913"; + reg = <0x58>; + + interrupts = ; + #interrupt-cells = <2>; + interrupt-controller; + + ti,system-power-controller; + + pmic { + compatible = "ti,tps65913-pmic"; + + regulators { + vdd_1v8_vio: smps8 { + regulator-name = "vdd_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-ramp-delay = <5000>; + }; + + avdd_dsi_csi: ldo3 { + regulator-name = "avdd_dsi_csi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + }; + + vddio_usd: ldo9 { + regulator-name = "vddio_usd"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; + }; + }; + + sdmmc3: sdhci@78000400 { + status = "okay"; + bus-width = <4>; + + cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; + + nvidia,default-tap = <0x3>; + nvidia,default-trim = <0x3>; + + vmmc-supply = <&tps65090_fet6>; + vqmmc-supply = <&vddio_usd>; + }; + + sdmmc4: sdhci@78000600 { + status = "okay"; + bus-width = <8>; + non-removable; + }; + + usb1: usb@7d000000 { + status = "okay"; + dr_mode = "otg"; + nvidia,vbus-gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; + }; + + usb-phy@7d000000 { + status = "okay"; + + nvidia,xcvr-setup = <7>; + nvidia,xcvr-lsfslew = <2>; + nvidia,xcvr-lsrslew = <2>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + + power-supply = <&tps65090_fet1>; + pwms = <&pwm 0 1000000>; + + brightness-levels = <1 35 70 105 140 175 210 255>; + default-brightness-level = <5>; + }; + + /* PMIC has a built-in 32KHz oscillator which is used by PMC */ + clk32k_in: clock-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "pmic-oscillator"; + }; + + extcon-keys { + compatible = "gpio-keys"; + + switch-hall-sensor { + label = "Hall Sensor"; + gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_HIGH>; + linux,code = ; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-power { + label = "Power Button"; + gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_HIGH>; + linux,code = ; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + key-windows { + label = "Windows Button"; + gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_HIGH>; + linux,code = ; + }; + }; +}; diff --git a/arch/arm/mach-tegra/tegra114/Kconfig b/arch/arm/mach-tegra/tegra114/Kconfig index 98f1d0e71c1..43dd59fb113 100644 --- a/arch/arm/mach-tegra/tegra114/Kconfig +++ b/arch/arm/mach-tegra/tegra114/Kconfig @@ -8,6 +8,10 @@ config TARGET_DALMORE bool "NVIDIA Tegra114 Dalmore evaluation board" select BOARD_LATE_INIT +config TARGET_SURFACE_2 + bool "Microsoft Surface 2" + select BOARD_LATE_INIT + config TARGET_TEGRATAB bool "NVIDIA Tegra114 TegraTab evaluation board" select BOARD_LATE_INIT @@ -22,6 +26,7 @@ config SYS_SOC default "tegra114" source "board/nvidia/dalmore/Kconfig" +source "board/microsoft/surface-2/Kconfig" source "board/nvidia/tegratab/Kconfig" source "board/asus/transformer-t114/Kconfig" diff --git a/board/microsoft/surface-2/Kconfig b/board/microsoft/surface-2/Kconfig new file mode 100644 index 00000000000..8573666dc92 --- /dev/null +++ b/board/microsoft/surface-2/Kconfig @@ -0,0 +1,13 @@ +if TARGET_SURFACE_2 + +config SYS_BOARD + default "surface-2" + +config SYS_VENDOR + default "microsoft" + +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "Microsoft Surface 2" + +endif diff --git a/board/microsoft/surface-2/MAINTAINERS b/board/microsoft/surface-2/MAINTAINERS new file mode 100644 index 00000000000..57747d304cd --- /dev/null +++ b/board/microsoft/surface-2/MAINTAINERS @@ -0,0 +1,7 @@ +SURFACE_2 BOARD +M: Jonas Schwöbel +S: Maintained +F: arch/arm/dts/tegra114-microsoft-surface-2* +F: board/microsoft/surface-2/ +F: configs/surface-2_defconfig +F: doc/board/microsoft/surface-2.rst diff --git a/board/microsoft/surface-2/Makefile b/board/microsoft/surface-2/Makefile new file mode 100644 index 00000000000..43bf6c66db2 --- /dev/null +++ b/board/microsoft/surface-2/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + +obj-$(CONFIG_XPL_BUILD) += surface-2-spl.o +obj-$(CONFIG_MULTI_DTB_FIT) += board-info.o diff --git a/board/microsoft/surface-2/board-info.c b/board/microsoft/surface-2/board-info.c new file mode 100644 index 00000000000..95a4accdc90 --- /dev/null +++ b/board/microsoft/surface-2/board-info.c @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2025 + * Svyatoslav Ryhel + */ + +#include +#include +#include + +#include +#include +#include + +static int id_gpio_get_value(u32 pingrp, u32 pin) +{ + /* Configure pinmux */ + pinmux_set_func(pingrp, PMUX_FUNC_KBC); + pinmux_set_pullupdown(pingrp, PMUX_PULL_DOWN); + pinmux_tristate_enable(pingrp); + pinmux_set_io(pingrp, PMUX_PIN_INPUT); + + /* + * Since this function may be called + * during DM reload we should use SPL + * GPIO functions which do not depend + * on DM. + */ + spl_gpio_input(NULL, pin); + return spl_gpio_get_value(NULL, pin); +} + +static int get_board_id(void) +{ + u32 pcb_id0, pcb_id1, pcb_id2, pcb_id3, pcb_id4, board_id; + + pcb_id0 = id_gpio_get_value(PMUX_PINGRP_KB_COL0_PQ0, TEGRA_GPIO(Q, 0)); + pcb_id1 = id_gpio_get_value(PMUX_PINGRP_KB_COL1_PQ1, TEGRA_GPIO(Q, 1)); + pcb_id2 = id_gpio_get_value(PMUX_PINGRP_KB_COL2_PQ2, TEGRA_GPIO(Q, 2)); + pcb_id3 = id_gpio_get_value(PMUX_PINGRP_KB_COL3_PQ3, TEGRA_GPIO(Q, 3)); + pcb_id4 = id_gpio_get_value(PMUX_PINGRP_KB_COL4_PQ4, TEGRA_GPIO(Q, 4)); + + /* Construct board ID */ + board_id = pcb_id4 << 4 | pcb_id3 << 3 | pcb_id2 << 2 | pcb_id1 << 1 | pcb_id0; + + log_debug("[SURFACE-2]: Board ID %02x\n", board_id); + + return board_id & 0x1f; +} + +int board_fit_config_name_match(const char *name) +{ + char dt_name[64] = { 0 }; + + snprintf(dt_name, sizeof(dt_name), "tegra114-microsoft-surface-2-%02x.dtb", + get_board_id()); + + if (!strcmp(name, dt_name)) + return 0; + + return -1; +} + +void nvidia_board_late_init(void) +{ + char dt_path[64] = { 0 }; + + snprintf(dt_path, sizeof(dt_path), "tegra114-microsoft-surface-2-%02x.dtb", + get_board_id()); + env_set("fdtfile", dt_path); +} diff --git a/board/microsoft/surface-2/surface-2-spl.c b/board/microsoft/surface-2/surface-2-spl.c new file mode 100644 index 00000000000..16f4373c7f0 --- /dev/null +++ b/board/microsoft/surface-2/surface-2-spl.c @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Surface 2 SPL stage configuration + * + * (C) Copyright 2010-2013 + * NVIDIA Corporation + * + * (C) Copyright 2023 + * Svyatoslav Ryhel + */ + +#include +#include +#include + +#define TPS65913_I2C_ADDR (0x58 << 1) + +#define TPS65913_SMPS12_CTRL 0x20 +#define TPS65913_SMPS12_VOLTAGE 0x23 +#define TPS65913_SMPS45_CTRL 0x28 +#define TPS65913_SMPS45_VOLTAGE 0x2B + +#define TPS65913_SMPS12_CTRL_DATA (0x5100 | TPS65913_SMPS12_CTRL) +#define TPS65913_SMPS12_VOLTAGE_DATA (0x3900 | TPS65913_SMPS12_VOLTAGE) +#define TPS65913_SMPS45_CTRL_DATA (0x5100 | TPS65913_SMPS45_CTRL) +#define TPS65913_SMPS45_VOLTAGE_DATA (0x4c00 | TPS65913_SMPS45_VOLTAGE) + +void pmic_enable_cpu_vdd(void) +{ + /* Set CORE VDD to 1.200V. */ + tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS45_VOLTAGE_DATA); + udelay(1000); + tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS45_CTRL_DATA); + + udelay(1000); + + /* Set CPU VDD to 1.0125V. */ + tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS12_VOLTAGE_DATA); + udelay(1000); + tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS12_CTRL_DATA); + udelay(10 * 1000); +} diff --git a/board/microsoft/surface-2/surface-2.env b/board/microsoft/surface-2/surface-2.env new file mode 100644 index 00000000000..a77885a7c6d --- /dev/null +++ b/board/microsoft/surface-2/surface-2.env @@ -0,0 +1,8 @@ +button_cmd_0_name=Volume Down +button_cmd_0=bootmenu + +bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu +bootmenu_1=mount external storage=usb start && ums 0 mmc 1; bootmenu +bootmenu_2=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu +bootmenu_4=power off=reset +bootmenu_delay=-1 diff --git a/configs/surface-2_defconfig b/configs/surface-2_defconfig new file mode 100644 index 00000000000..7b71fa2b4ea --- /dev/null +++ b/configs/surface-2_defconfig @@ -0,0 +1,82 @@ +CONFIG_ARM=y +CONFIG_ARCH_TEGRA=y +CONFIG_SUPPORT_PASSING_ATAGS=y +CONFIG_CMDLINE_TAG=y +CONFIG_INITRD_TAG=y +CONFIG_TEXT_BASE=0x80110000 +CONFIG_SYS_MALLOC_LEN=0x2500000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SOURCE_FILE="surface-2" +CONFIG_ENV_SIZE=0x3000 +CONFIG_ENV_OFFSET=0xFFFFD000 +CONFIG_DEFAULT_DEVICE_TREE="tegra114-microsoft-surface-2-0b" +CONFIG_SPL_STACK=0x800ffffc +CONFIG_SPL_TEXT_BASE=0x80108000 +CONFIG_SYS_LOAD_ADDR=0x82000000 +CONFIG_TEGRA114=y +CONFIG_TARGET_SURFACE_2=y +CONFIG_BUTTON_CMD=y +CONFIG_BOOTDELAY=0 +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_KEYED_CTRLC=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_PBSIZE=2086 +CONFIG_SPL_FOOTPRINT_LIMIT=y +CONFIG_SPL_MAX_FOOTPRINT=0x8000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_HAVE_INIT_STACK=y +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80090000 +CONFIG_SPL_SYS_MALLOC_SIZE=0x10000 +CONFIG_SYS_PROMPT="Tegra114 (Surface 2) # " +# CONFIG_CMD_BOOTEFI_BOOTMGR is not set +CONFIG_CMD_BOOTMENU=y +# CONFIG_CMD_IMI is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_UMS_ABORT_KEYED=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_PAUSE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT4_WRITE=y +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_OF_LIST="tegra114-microsoft-surface-2-0b tegra114-microsoft-surface-2-13" +CONFIG_DTB_RESELECT=y +CONFIG_MULTI_DTB_FIT=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_BUTTON=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x91000000 +CONFIG_FASTBOOT_BUF_SIZE=0x10000000 +CONFIG_SYS_I2C_TEGRA=y +CONFIG_BUTTON_KEYBOARD=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_TPS65090=y +CONFIG_PMIC_PALMAS=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_TPS65090=y +CONFIG_DM_REGULATOR_PALMAS=y +CONFIG_PWM_TEGRA=y +CONFIG_SYS_NS16550=y +CONFIG_SYSRESET_PALMAS=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_TEGRA=y +CONFIG_USB_KEYBOARD=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_VIDEO=y +# CONFIG_VIDEO_LOGO is not set +CONFIG_VIDEO_LCD_SAMSUNG_LTL106HL02=y +CONFIG_VIDEO_BRIDGE=y +CONFIG_VIDEO_DSI_TEGRA=y diff --git a/doc/board/microsoft/index.rst b/doc/board/microsoft/index.rst index 107f3527852..8318449a9a2 100644 --- a/doc/board/microsoft/index.rst +++ b/doc/board/microsoft/index.rst @@ -6,4 +6,5 @@ Microsoft .. toctree:: :maxdepth: 2 + surface-2 surface-rt diff --git a/doc/board/microsoft/surface-2.rst b/doc/board/microsoft/surface-2.rst new file mode 100644 index 00000000000..8185c6f5ae4 --- /dev/null +++ b/doc/board/microsoft/surface-2.rst @@ -0,0 +1,41 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +U-Boot for the Microsoft Surface 2 tablet +========================================= + +Quick Start +----------- + +- Build U-Boot +- Boot + +Build U-Boot +------------ + +.. code-block:: bash + + $ export CROSS_COMPILE=arm-none-eabi- + $ make surface-2_defconfig + $ make + +After the build succeeds, you will obtain the final ``u-boot-dtb-tegra.bin`` +image, ready for loading. + +Boot +---- + +Currently, U-Boot can be preloaded into RAM via the Fusée Gelée. To enter +RCM protocol use ``power`` and ``volume up`` key combination from powered +off device. The host PC should recognize an APX device. + +Built U-Boot ``u-boot-dtb-tegra.bin`` can be loaded from fusee-tools +directory with + +.. code-block:: bash + + $ ./run_bootloader.sh -s T30 -t ./bct/surface-2.bct + +To boot Linux, U-Boot will look for an ``extlinux.conf`` on MicroSD and then on +eMMC. Additionally, if the Volume Down button is pressed while loading, the +device will enter bootmenu. Bootmenu contains entries to mount MicroSD and eMMC +as mass storage, fastboot, poweroff and enter U-Boot console. From 9999821e7516ad5c70f17319d0d33b99ef702e09 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Tue, 19 Aug 2025 16:40:13 +0100 Subject: [PATCH 008/103] configs: p3450: reduce size of Jetson Nano u-boot.bin The Jetson Nano contains all it's firmware on a 4Mb SPI flash, the allocated size in that flash for U-Boot is 753664 bytes so we need to ensure the u-boot.bin doesn't exceed that else it will fail. Add a BOARD_SIZE_LIMIT and drop a few large, and somewhat esoteric, options to bring us back under that limit. Signed-off-by: Peter Robinson Acked-by: Thierry Reding Reviewed-by: Svyatoslav Ryhel Signed-off-by: Svyatoslav Ryhel --- configs/p3450-0000_defconfig | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/configs/p3450-0000_defconfig b/configs/p3450-0000_defconfig index a002178b7fb..518ed6b37a2 100644 --- a/configs/p3450-0000_defconfig +++ b/configs/p3450-0000_defconfig @@ -14,6 +14,8 @@ CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="tegra210-p3450-0000" CONFIG_SYS_BOOTM_LEN=0x800000 CONFIG_SYS_LOAD_ADDR=0x80080000 +CONFIG_HAS_BOARD_SIZE_LIMIT=y +CONFIG_BOARD_SIZE_LIMIT=753664 CONFIG_TEGRA210=y CONFIG_TARGET_P3450_0000=y CONFIG_TEGRA_GPU=y @@ -24,8 +26,14 @@ CONFIG_SYS_PBSIZE=2089 CONFIG_CONSOLE_MUX=y CONFIG_SYS_STDIO_DEREGISTER=y CONFIG_SYS_PROMPT="Tegra210 (P3450-0000) # " +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +# CONFIG_BOOTM_PLAN9 is not set # CONFIG_CMD_IMI is not set +# CONFIG_CRC32_VERIFY is not set CONFIG_CMD_DFU=y +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_GO is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y From a353211288464543e67b3ec4a421a751fcae98ce Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Tue, 19 Aug 2025 16:40:14 +0100 Subject: [PATCH 009/103] ARM: tegra210: p3450: fix Jetson Nano SPI flash The Nano's SPI flash stopped working in U-Boot, as the prior stage loaded U-Boot, the only thing it was used for was save/loading env vars so update the DT so it can now initialise it. It also drops enabling the old TEGRA114_SPI driver, as the flash hangs off the faster TEGRA210_QSPI interface, nothing on the Nano uses the old interface by default so it's surplus. Signed-off-by: Peter Robinson Acked-by: Thierry Reding Reviewed-by: Svyatoslav Ryhel Signed-off-by: Svyatoslav Ryhel --- arch/arm/dts/tegra210-p3450-0000.dts | 9 ++++++++- arch/arm/dts/tegra210.dtsi | 6 +++--- configs/p3450-0000_defconfig | 1 - 3 files changed, 11 insertions(+), 5 deletions(-) diff --git a/arch/arm/dts/tegra210-p3450-0000.dts b/arch/arm/dts/tegra210-p3450-0000.dts index 9ef744ac8b0..ddeeb232de2 100644 --- a/arch/arm/dts/tegra210-p3450-0000.dts +++ b/arch/arm/dts/tegra210-p3450-0000.dts @@ -124,7 +124,14 @@ spi@70410000 { status = "okay"; - spi-max-frequency = <80000000>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <104000000>; + spi-tx-bus-width = <2>; + spi-rx-bus-width = <2>; + }; }; usb@7d000000 { diff --git a/arch/arm/dts/tegra210.dtsi b/arch/arm/dts/tegra210.dtsi index 28ecd2b467a..92eb4f67bf5 100644 --- a/arch/arm/dts/tegra210.dtsi +++ b/arch/arm/dts/tegra210.dtsi @@ -762,10 +762,10 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; - clocks = <&tegra_car TEGRA210_CLK_QSPI>; - clock-names = "qspi"; + clocks = <&tegra_car TEGRA210_CLK_QSPI>, + <&tegra_car TEGRA210_CLK_QSPI_PM>; + clock-names = "qspi", "qspi_out"; resets = <&tegra_car 211>; - reset-names = "qspi"; dmas = <&apbdma 5>, <&apbdma 5>; dma-names = "rx", "tx"; status = "disabled"; diff --git a/configs/p3450-0000_defconfig b/configs/p3450-0000_defconfig index 518ed6b37a2..3b4b863100f 100644 --- a/configs/p3450-0000_defconfig +++ b/configs/p3450-0000_defconfig @@ -61,7 +61,6 @@ CONFIG_RTL8169=y CONFIG_NVME_PCI=y CONFIG_PCI_TEGRA=y CONFIG_SYS_NS16550=y -CONFIG_TEGRA114_SPI=y CONFIG_TEGRA210_QSPI=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y From 4c28c4d9a3a814cebb93e20842ed2c1c90f703d3 Mon Sep 17 00:00:00 2001 From: Christophe Kerello Date: Tue, 12 Aug 2025 14:35:11 +0200 Subject: [PATCH 010/103] mtd: rawnand: stm32_fmc2: set available OOB bytes per page File system such as YAFFS2 need to know the number of available OOB bytes per page to be able to choose if they should locate their metadata in the data area or in the spare area. Signed-off-by: Christophe Kerello Reviewed-by: Patrice Chotard --- drivers/mtd/nand/raw/stm32_fmc2_nand.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/nand/raw/stm32_fmc2_nand.c b/drivers/mtd/nand/raw/stm32_fmc2_nand.c index d1c88643c98..21e3c88a55a 100644 --- a/drivers/mtd/nand/raw/stm32_fmc2_nand.c +++ b/drivers/mtd/nand/raw/stm32_fmc2_nand.c @@ -1034,6 +1034,7 @@ static int stm32_fmc2_nfc_probe(struct udevice *dev) ecclayout->eccpos[i] = oob_index; ecclayout->oobfree->offset = oob_index; ecclayout->oobfree->length = mtd->oobsize - ecclayout->oobfree->offset; + ecclayout->oobavail = ecclayout->oobfree->length; chip->ecc.layout = ecclayout; if (chip->options & NAND_BUSWIDTH_16) From 1067d2060ff017fb58758c0c21ae35504d144ea7 Mon Sep 17 00:00:00 2001 From: Christophe Kerello Date: Tue, 12 Aug 2025 15:55:26 +0200 Subject: [PATCH 011/103] mmc: stm32_sdmmc2: avoid infinite while loop Avoid unlimited while loop by adding a timeout. The timeout is calculated based on a minimal throughput of 256 KB/s. The timeout is set at least to 2 seconds. Signed-off-by: Christophe Kerello Reviewed-by: Patrice Chotard --- drivers/mmc/stm32_sdmmc2.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/stm32_sdmmc2.c b/drivers/mmc/stm32_sdmmc2.c index 9483fb57daf..122690aef3e 100644 --- a/drivers/mmc/stm32_sdmmc2.c +++ b/drivers/mmc/stm32_sdmmc2.c @@ -385,15 +385,29 @@ static int stm32_sdmmc2_end_data(struct udevice *dev, u32 mask = SDMMC_STA_DCRCFAIL | SDMMC_STA_DTIMEOUT | SDMMC_STA_IDMATE | SDMMC_STA_DATAEND; u32 status; + unsigned long timeout_msecs = ctx->data_length >> 8; + unsigned long start_timeout; + + /* At least, a timeout of 2 seconds is set */ + if (timeout_msecs < 2000) + timeout_msecs = 2000; if (data->flags & MMC_DATA_READ) mask |= SDMMC_STA_RXOVERR; else mask |= SDMMC_STA_TXUNDERR; + start_timeout = get_timer(0); status = readl(plat->base + SDMMC_STA); - while (!(status & mask)) + while (!(status & mask)) { + if (get_timer(start_timeout) > timeout_msecs) { + ctx->dpsm_abort = true; + return -ETIMEDOUT; + } + + schedule(); status = readl(plat->base + SDMMC_STA); + } /* * Need invalidate the dcache again to avoid any From 198c48f2657e67ded7fc7679c2ed1c26227f9fdc Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Thu, 14 Aug 2025 14:09:38 +0200 Subject: [PATCH 012/103] configs: stm32mp25: Enable OF_UPSTREAM_BUILD_VENDOR Initially, only one STM32MP25 based board was available, the stm32mp257f-ev1 board which was set by default in stm32mp25_defconfig. Since commit 79f3e77133bd ("Subtree merge tag 'v6.16-dts' of dts repo [1] into dts/upstream") we inherited of a second MP25 based board which is the stm32mp257f-dk board. Enable OF_UPSTREAM_BUILD_VENDOR and set OF_UPSTREAM_VENDOR to allow all STMicroelectronics DT compilation. Signed-off-by: Patrice Chotard --- configs/stm32mp25_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/stm32mp25_defconfig b/configs/stm32mp25_defconfig index 14619ffd96c..2b02cd86d61 100644 --- a/configs/stm32mp25_defconfig +++ b/configs/stm32mp25_defconfig @@ -41,6 +41,8 @@ CONFIG_CMD_REGULATOR=y CONFIG_CMD_LOG=y CONFIG_CMD_UBI=y CONFIG_OF_LIVE=y +CONFIG_OF_UPSTREAM_BUILD_VENDOR=y +CONFIG_OF_UPSTREAM_VENDOR="st" CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y From ae2cd1b52d4ded22ac2359964c5682b5a5c1cc28 Mon Sep 17 00:00:00 2001 From: Andrew Goodbody Date: Wed, 13 Aug 2025 17:30:12 +0100 Subject: [PATCH 013/103] usb: cdns3: Do not access memory after free The call to cdns3_gadget_ep_free_request will free priv_req so do the call to list_del_init which accesses the memory pointed to by priv_req before the free. This issue was found by Smatch. Signed-off-by: Andrew Goodbody Reviewed-by: Siddharth Vadapalli --- drivers/usb/cdns3/gadget.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/usb/cdns3/gadget.c b/drivers/usb/cdns3/gadget.c index a30c40ef80e..9eaf7e40ab6 100644 --- a/drivers/usb/cdns3/gadget.c +++ b/drivers/usb/cdns3/gadget.c @@ -557,10 +557,10 @@ static void cdns3_wa2_remove_old_request(struct cdns3_endpoint *priv_ep) trace_cdns3_wa2(priv_ep, "removes eldest request"); + list_del_init(&priv_req->list); kfree(priv_req->request.buf); cdns3_gadget_ep_free_request(&priv_ep->endpoint, &priv_req->request); - list_del_init(&priv_req->list); --priv_ep->wa2_counter; if (!chain) @@ -1959,10 +1959,10 @@ static int cdns3_gadget_ep_disable(struct usb_ep *ep) while (!list_empty(&priv_ep->wa2_descmiss_req_list)) { priv_req = cdns3_next_priv_request(&priv_ep->wa2_descmiss_req_list); + list_del_init(&priv_req->list); kfree(priv_req->request.buf); cdns3_gadget_ep_free_request(&priv_ep->endpoint, &priv_req->request); - list_del_init(&priv_req->list); --priv_ep->wa2_counter; } From 1848a504379531eb726d29b355f9038d194e8430 Mon Sep 17 00:00:00 2001 From: Alex Shumsky Date: Thu, 3 Jul 2025 09:04:48 +0300 Subject: [PATCH 014/103] rockchip: rockchip-inno-usb2: Fix Synchronous Abort on usb start Fix NULL pointer dereference that happen when rockchip-inno-usb2 clock enabled before device probe. This early clock enable call happen in process of parent clock activation added in ac30d90f3367. Fixes: 229218373c22 ("phy: rockchip-inno-usb2: Add support for clkout_ctl_phy"). Fixes: ac30d90f3367 ("clk: Ensure the parent clocks are enabled while reparenting") Co-authored-by: Jonas Karlman Signed-off-by: Alex Shumsky Reviewed-by: Jonas Karlman Reviewed-by: Kever Yang --- drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c index 88b33de1b2a..3cc5956aed5 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c @@ -167,20 +167,27 @@ static struct phy_ops rockchip_usb2phy_ops = { .of_xlate = rockchip_usb2phy_of_xlate, }; -static void rockchip_usb2phy_clkout_ctl(struct clk *clk, struct regmap **base, - const struct usb2phy_reg **clkout_ctl) +static int rockchip_usb2phy_clkout_ctl(struct clk *clk, struct regmap **base, + const struct usb2phy_reg **clkout_ctl) { struct udevice *parent = dev_get_parent(clk->dev); struct rockchip_usb2phy *priv = dev_get_priv(parent); const struct rockchip_usb2phy_cfg *phy_cfg = priv->phy_cfg; - if (priv->phy_cfg->clkout_ctl_phy.enable) { + // phy_cfg can be NULL if this function called before probe (when parent + // clocks are enabled) + if (!phy_cfg) + return -EINVAL; + + if (phy_cfg->clkout_ctl_phy.enable) { *base = priv->phy_base; *clkout_ctl = &phy_cfg->clkout_ctl_phy; } else { *base = priv->reg_base; *clkout_ctl = &phy_cfg->clkout_ctl; } + + return 0; } /** @@ -206,7 +213,8 @@ int rockchip_usb2phy_clk_enable(struct clk *clk) const struct usb2phy_reg *clkout_ctl; struct regmap *base; - rockchip_usb2phy_clkout_ctl(clk, &base, &clkout_ctl); + if (rockchip_usb2phy_clkout_ctl(clk, &base, &clkout_ctl)) + return -ENOSYS; /* turn on 480m clk output if it is off */ if (!property_enabled(base, clkout_ctl)) { @@ -230,7 +238,8 @@ int rockchip_usb2phy_clk_disable(struct clk *clk) const struct usb2phy_reg *clkout_ctl; struct regmap *base; - rockchip_usb2phy_clkout_ctl(clk, &base, &clkout_ctl); + if (rockchip_usb2phy_clkout_ctl(clk, &base, &clkout_ctl)) + return -ENOSYS; /* turn off 480m clk output */ property_enable(base, clkout_ctl, false); From 2390eb8b614e4dc038bc41706821b275c367d55d Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Tue, 10 Jun 2025 11:42:50 +0200 Subject: [PATCH 015/103] rockchip: px30/rk3326: Implement checkboard() to print SoC variant This implements checkboard() to print the current SoC model used by a board, e.g. one of: SoC: PX30 SoC: PX30S SoC: PX30K SoC: RK3326 SoC: RK3326S when U-Boot proper is running. The information is read from the OTP and also the DDR_GRF. There's no public information as far as I know about the layout and stored information on OTP but this was provided by Rockchip themselves through their support channel. The OTP stores the information of whether the SoC is PX30K or something else. To differentiate between PX30/RK3326 and PX30S/RK3326S, one needs to read some undocumented bitfield in a DDR_GRF register as done in vendor kernel, c.f. https://github.com/armbian/linux-rockchip/blob/rk-6.1-rkr5.1/drivers/soc/rockchip/rockchip-cpuinfo.c#L118-L133. I do not own a PX30S, nor RK3326/RK3326S so cannot test it works properly. Also add the OTP node to the pre-relocation phase of U-Boot proper so that the SoC variant can be printed when DISPLAY_BOARDINFO is enabled. This is not required if DISPLAY_BOARDINFO_LATE is enabled because this happens after relocation. If both are enabled, then the SoC variant will be printed twice in the boot log, e.g.: U-Boot 2025.07-rc3-00014-g7cb731574ae6-dirty (May 28 2025 - 13:52:47 +0200) Model: Theobroma Systems PX30-uQ7 SoM on Haikou devkit SoC: PX30 <---- due to DISPLAY_BOARDINFO DRAM: 2 GiB PMIC: RK809 (on=0x40, off=0x00) Core: 293 devices, 27 uclasses, devicetree: separate MMC: mmc@ff370000: 1, mmc@ff390000: 0 Loading Environment from MMC... Reading from MMC(1)... OK In: serial@ff030000 Out: serial@ff030000 Err: serial@ff030000 Model: Theobroma Systems PX30-uQ7 SoM on Haikou devkit SoC: PX30 <----- due to DISPLAY_BOARDINFO_LATE Net: eth0: ethernet@ff360000 Signed-off-by: Quentin Schulz Reviewed-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/px30-u-boot.dtsi | 4 ++ arch/arm/mach-rockchip/px30/px30.c | 61 ++++++++++++++++++++++++++++++ 2 files changed, 65 insertions(+) diff --git a/arch/arm/dts/px30-u-boot.dtsi b/arch/arm/dts/px30-u-boot.dtsi index 157d0ea6930..2f726b0aaba 100644 --- a/arch/arm/dts/px30-u-boot.dtsi +++ b/arch/arm/dts/px30-u-boot.dtsi @@ -27,6 +27,10 @@ }; }; +&otp { + bootph-some-ram; +}; + &uart2 { clock-frequency = <24000000>; bootph-all; diff --git a/arch/arm/mach-rockchip/px30/px30.c b/arch/arm/mach-rockchip/px30/px30.c index 8ce9ac561f0..5a5c119328f 100644 --- a/arch/arm/mach-rockchip/px30/px30.c +++ b/arch/arm/mach-rockchip/px30/px30.c @@ -2,10 +2,14 @@ /* * Copyright (c) 2017 Rockchip Electronics Co., Ltd */ + +#define LOG_CATEGORY LOGC_ARCH + #include #include #include #include +#include #include #include #include @@ -15,6 +19,7 @@ #include #include #include +#include const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { [BROM_BOOTSOURCE_EMMC] = "/mmc@ff390000", @@ -442,3 +447,59 @@ void board_debug_uart_init(void) #endif /* CONFIG_DEBUG_UART_BASE && CONFIG_DEBUG_UART_BASE == ... */ } #endif /* CONFIG_DEBUG_UART_BOARD_INIT */ + +#define PX30_OTP_SPECIFICATION_OFFSET 0x06 + +#define DDR_GRF_BASE_ADDR 0xff630000 +#define DDR_GRF_CON(n) (0 + (n) * 4) + +int checkboard(void) +{ + struct udevice *dev; + u8 specification; + u32 base_soc; + int ret; + + if (!IS_ENABLED(CONFIG_ROCKCHIP_OTP) || !CONFIG_IS_ENABLED(MISC)) + return 0; + + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_DRIVER_GET(rockchip_otp), &dev); + if (ret) { + log_debug("Could not find otp device, ret=%d\n", ret); + return 0; + } + + /* base SoC: 0x26334b52 for RK3326; 0x30335850 for PX30 */ + ret = misc_read(dev, 0, &base_soc, 4); + if (ret < 0) { + log_debug("Could not read specification, ret=%d\n", ret); + return 0; + } + + if (base_soc != 0x26334b52 && base_soc != 0x30335850) { + log_debug("Could not identify SoC, got 0x%04x in OTP\n", base_soc); + return 0; + } + + /* SoC variant: 0x21 for PX30/PX30S/RK3326/RK3326S; 0x2b for PX30K */ + ret = misc_read(dev, PX30_OTP_SPECIFICATION_OFFSET, &specification, 1); + if (ret < 0) { + log_debug("Could not read specification, ret=%d\n", ret); + return 0; + } + + if (specification == 0x2b) { + printf("SoC: PX30K\n"); + return 0; + } + + /* From vendor kernel: drivers/soc/rockchip/rockchip-cpuinfo.c */ + specification = FIELD_GET(GENMASK(15, 14), + readl(DDR_GRF_BASE_ADDR + DDR_GRF_CON(1))); + log_debug("DDR specification is %d\n", specification); + printf("SoC: %s%s\n", base_soc == 0x26334b52 ? "RK3326" : "PX30", + specification == 0x3 ? "S" : ""); + + return 0; +} From 9d98a6b9803d9989528d320ad71d607914378d9e Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Mon, 9 Jun 2025 22:06:16 -0500 Subject: [PATCH 016/103] rockchip: Add support for GameForce Ace The GameForce Ace is an RK3588S based handheld gaming device. Signed-off-by: Chris Morgan Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/rk3588/Kconfig | 18 +++++++ board/gameforce/ace-rk3588s/Kconfig | 9 ++++ board/gameforce/ace-rk3588s/MAINTAINERS | 5 ++ configs/gameforce-ace-rk3588s_defconfig | 67 +++++++++++++++++++++++++ doc/board/rockchip/rockchip.rst | 1 + 5 files changed, 100 insertions(+) create mode 100644 board/gameforce/ace-rk3588s/Kconfig create mode 100644 board/gameforce/ace-rk3588s/MAINTAINERS create mode 100644 configs/gameforce-ace-rk3588s_defconfig diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig index 4e7942ada87..9fbe3f225aa 100644 --- a/arch/arm/mach-rockchip/rk3588/Kconfig +++ b/arch/arm/mach-rockchip/rk3588/Kconfig @@ -27,6 +27,23 @@ config TARGET_CM3588_NAS_RK3588 - 3.5mm Headphone out, 2.0mm PH-2A Mic in - 5V Fan connector, PWM beeper, IR receiver, RTC battery connector +config TARGET_GAMEFORCE_ACE_RK3588S + bool "GameForce Ace" + help + The GameForce Ace is a handheld game console from GameForce with + the Rockchip RK3588S SoC. + + Hardware features: + - Rockchip RK3588S SoC + - 12GB LPDDR4x RAM + - 128GB eMMC + - MicroSD card slot + - 1x USB 3.0 Type-C with DP AltMode support + - 1x HDMI 2.1 micro-HDMI out + - 1920x1080 touchscreen MIPI-DSI panel + - Analog joysticks and L/R triggers + - 16 digital buttons + config TARGET_GENBOOK_CM5_RK3588 bool "Cool Pi CM5 GenBook" help @@ -410,6 +427,7 @@ source "board/friendlyelec/cm3588-nas-rk3588/Kconfig" source "board/friendlyelec/nanopc-t6-rk3588/Kconfig" source "board/friendlyelec/nanopi-r6c-rk3588s/Kconfig" source "board/friendlyelec/nanopi-r6s-rk3588s/Kconfig" +source "board/gameforce/ace-rk3588s/Kconfig" source "board/hardkernel/odroid_m2/Kconfig" source "board/indiedroid/nova/Kconfig" source "board/khadas/khadas-edge2-rk3588s/Kconfig" diff --git a/board/gameforce/ace-rk3588s/Kconfig b/board/gameforce/ace-rk3588s/Kconfig new file mode 100644 index 00000000000..52f98ccf897 --- /dev/null +++ b/board/gameforce/ace-rk3588s/Kconfig @@ -0,0 +1,9 @@ +if TARGET_GAMEFORCE_ACE_RK3588S + +config SYS_BOARD + default "gameforce-ace-rk3588s" + +config SYS_VENDOR + default "GameForce" + +endif diff --git a/board/gameforce/ace-rk3588s/MAINTAINERS b/board/gameforce/ace-rk3588s/MAINTAINERS new file mode 100644 index 00000000000..dc18e7c8849 --- /dev/null +++ b/board/gameforce/ace-rk3588s/MAINTAINERS @@ -0,0 +1,5 @@ +GAMEFORCE-ACE-RK3588S +M: Chris Morgan +S: Maintained +F: board/gameforce/ace-rk3588s/ +F: configs/gameforce-ace-rk3588s_defconfig diff --git a/configs/gameforce-ace-rk3588s_defconfig b/configs/gameforce-ace-rk3588s_defconfig new file mode 100644 index 00000000000..ec725a8df40 --- /dev/null +++ b/configs/gameforce-ace-rk3588s_defconfig @@ -0,0 +1,67 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588s-gameforce-ace" +CONFIG_ROCKCHIP_RK3588=y +CONFIG_SPL_SERIAL=y +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_DEBUG_UART_BASE=0xFEB50000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-gameforce-ace.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_ATF=y +CONFIG_CMD_MMC=y +# CONFIG_CMD_SETEXPR is not set +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_NO_NET=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_BUTTON=y +CONFIG_BUTTON_ADC=y +CONFIG_BUTTON_GPIO=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MISC=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_PHY_ROCKCHIP_USBDP=y +CONFIG_SPL_PINCTRL=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +# CONFIG_RAM_ROCKCHIP_DEBUG is not set +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SPI=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_ERRNO_STR=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index b88299cbba2..a2d8a715a4b 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -145,6 +145,7 @@ List of mainline supported Rockchip boards: - FriendlyElec NanoPC-T6 (nanopc-t6-rk3588) - FriendlyElec NanoPi R6C (nanopi-r6c-rk3588s) - FriendlyElec NanoPi R6S (nanopi-r6s-rk3588s) + - GameForce Ace (gameforce-ace-rk3588s) - Generic RK3588S/RK3588 (generic-rk3588) - Hardkernel ODROID-M2 (odroid-m2-rk3588s) - Indiedroid Nova (nova-rk3588s) From d48f063a5385a1bd79f048810826c823d09be8ec Mon Sep 17 00:00:00 2001 From: Da Xue Date: Tue, 10 Jun 2025 19:08:19 +0000 Subject: [PATCH 017/103] ram: rk3328: add ddr4-1600 sdram timing Add DDR4 1600MHz SDRAM timing data from LibreComputer u-boot sources for the ROC-3328-CC board. Signed-off-by: Da Xue Signed-off-by: Christian Hewitt Reviewed-by: Kever Yang --- arch/arm/dts/rk3328-sdram-ddr4-1600.dtsi | 226 +++++++++++++++++++++++ 1 file changed, 226 insertions(+) create mode 100644 arch/arm/dts/rk3328-sdram-ddr4-1600.dtsi diff --git a/arch/arm/dts/rk3328-sdram-ddr4-1600.dtsi b/arch/arm/dts/rk3328-sdram-ddr4-1600.dtsi new file mode 100644 index 00000000000..9594bb42839 --- /dev/null +++ b/arch/arm/dts/rk3328-sdram-ddr4-1600.dtsi @@ -0,0 +1,226 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd. + +&dmc { + rockchip,sdram-params = < + 0x1 + 0xA + 0x2 + 0x1 + 0x0 + 0x0 + 0x11 + 0x0 + 0x11 + 0x0 + 0 + + 0x94496354 + 0x00000000 + 0x0000002a + 0x000004e2 + 0x00000015 + 0x0000034a + 0x000000ff + + 800 + 0 + 1 + 0 + 0 + + 0x00000000 + 0x43041010 + 0x00000064 + 0x0061008c + 0x000000d0 + 0x000200c5 + 0x000000d4 + 0x00500000 + 0x000000d8 + 0x00000100 + 0x000000dc + 0x03140401 + 0x000000e0 + 0x00000000 + 0x000000e4 + 0x00110000 + 0x000000e8 + 0x00000420 + 0x000000ec + 0x00000400 + 0x000000f4 + 0x000f011f + 0x00000100 + 0x0c0e1b0e + 0x00000104 + 0x00030314 + 0x00000108 + 0x0506050b + 0x0000010c + 0x0040400c + 0x00000110 + 0x06030307 + 0x00000114 + 0x04040302 + 0x00000120 + 0x06060b06 + 0x00000124 + 0x00020308 + 0x00000180 + 0x01000040 + 0x00000184 + 0x00000000 + 0x00000190 + 0x07040003 + 0x00000198 + 0x05001100 + 0x000001a0 + 0xc0400003 + 0x00000240 + 0x0600060c + 0x00000244 + 0x00000201 + 0x00000250 + 0x00000f00 + 0x00000490 + 0x00000001 + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + + 0x00000004 + 0x0000000c + 0x00000028 + 0x0000000c + 0x0000002c + 0x00000000 + 0x00000030 + 0x00000009 + 0xffffffff + 0xffffffff + + 0x77 + 0x88 + 0x79 + 0x79 + 0x87 + 0x97 + 0x87 + 0x78 + 0x77 + 0x78 + 0x87 + 0x88 + 0x87 + 0x87 + 0x77 + + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x69 + 0x9 + + 0x77 + 0x78 + 0x77 + 0x78 + 0x77 + 0x78 + 0x77 + 0x78 + 0x77 + 0x79 + 0x9 + + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x69 + 0x9 + + 0x77 + 0x78 + 0x77 + 0x77 + 0x77 + 0x77 + 0x77 + 0x77 + 0x77 + 0x79 + 0x9 + + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x69 + 0x9 + + 0x77 + 0x78 + 0x77 + 0x78 + 0x77 + 0x78 + 0x77 + 0x78 + 0x77 + 0x79 + 0x9 + + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x69 + 0x9 + + 0x77 + 0x78 + 0x77 + 0x77 + 0x77 + 0x77 + 0x77 + 0x77 + 0x77 + 0x79 + 0x9 + >; +}; From 578e168387dace1e4d146d8b7c8570b18dec238e Mon Sep 17 00:00:00 2001 From: Da Xue Date: Tue, 10 Jun 2025 19:08:20 +0000 Subject: [PATCH 018/103] arm64: dts: rockchip: roc-3328-cc: use 1600 ddr4 timing Swap the ROC-3328-CC from DDR4 666 to 1600 timing to boost performance. Signed-off-by: Da Xue Signed-off-by: Christian Hewitt Reviewed-by: Kever Yang --- arch/arm/dts/rk3328-roc-cc-u-boot.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi b/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi index 582d6ba49b4..c47d29c59de 100644 --- a/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi +++ b/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi @@ -4,7 +4,7 @@ */ #include "rk3328-u-boot.dtsi" -#include "rk3328-sdram-ddr4-666.dtsi" +#include "rk3328-sdram-ddr4-1600.dtsi" / { smbios { From 571244f5749e493ffc9dae5aad1445e0a6ed0572 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 1 Jul 2025 19:03:45 -0600 Subject: [PATCH 019/103] usb: gadget: rockchip: Add missing dependency The rockchip usb gadget driver cannot build without platform specific headers being available. Express that requirement in Kconfig as well. Signed-off-by: Tom Rini Reviewed-by: Quentin Schulz Reviewed-by: Kever Yang --- drivers/usb/gadget/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index 46a83141481..b0decd7b251 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -202,6 +202,7 @@ config USB_FUNCTION_MASS_STORAGE config USB_FUNCTION_ROCKUSB bool "Enable USB rockusb gadget" + depends on ARCH_ROCKCHIP help Rockusb protocol is widely used by Rockchip SoC based devices. It can read/write info, image to/from devices. This enables the USB part of From 9bd3fc8cd976e66b869e243d22fe37d836bbf318 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 1 Jul 2025 19:03:46 -0600 Subject: [PATCH 020/103] usb: gadget: rockchip: Fix spacing around the Kconfig option This Kconfig option used spaces and not tabs for indentation. Switch to tabs. Signed-off-by: Tom Rini Reviewed-by: Quentin Schulz Reviewed-by: Kever Yang --- drivers/usb/gadget/Kconfig | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index b0decd7b251..6201663317b 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -201,13 +201,13 @@ config USB_FUNCTION_MASS_STORAGE the eMMC/SD card content to HOST PC so it can be mounted. config USB_FUNCTION_ROCKUSB - bool "Enable USB rockusb gadget" + bool "Enable USB rockusb gadget" depends on ARCH_ROCKCHIP - help - Rockusb protocol is widely used by Rockchip SoC based devices. It can - read/write info, image to/from devices. This enables the USB part of - the rockusb gadget.for more detail about Rockusb protocol, please see - doc/README.rockusb + help + Rockusb protocol is widely used by Rockchip SoC based devices. It can + read/write info, image to/from devices. This enables the USB part of + the rockusb gadget.for more detail about Rockusb protocol, please see + doc/README.rockusb config USB_FUNCTION_SDP bool "Enable USB SDP (Serial Download Protocol)" From d079cdbc53026dca2c4209ee71c883de7fe0cc14 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Fri, 1 Aug 2025 20:32:37 +0000 Subject: [PATCH 021/103] rng: rockchip_rng: Add compatible for RK3576 The RK3576 SoC contains a RKRNG block that can be used to generate random numbers using the rockchip_rng driver. Add compatible for RK3576 to support random numbers: => rng list RNG #0 - rng@2a410000 => rng 00000000: 36 dd ab 98 ec fb fe d1 cf 36 b3 e1 9b 3d 00 90 6........6...=.. 00000010: f5 84 de 75 6b 27 48 9e 13 62 12 6c 50 ca 47 1a ...uk'H..b.lP.G. 00000020: b3 4d fc 43 c5 b5 2d be 07 27 03 26 bb 69 61 2a .M.C..-..'.&.ia* 00000030: 6f 70 01 83 4e ce 91 7a 5a 6c 7c 00 43 87 3e c5 op..N..zZl|.C.>. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- drivers/rng/rockchip_rng.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/rng/rockchip_rng.c b/drivers/rng/rockchip_rng.c index d854ea90044..8cf750e043c 100644 --- a/drivers/rng/rockchip_rng.c +++ b/drivers/rng/rockchip_rng.c @@ -393,6 +393,10 @@ static const struct udevice_id rockchip_rng_match[] = { .compatible = "rockchip,rk3588-rng", .data = (ulong)&rk_trngv1_soc_data, }, + { + .compatible = "rockchip,rk3576-rng", + .data = (ulong)&rkrng_soc_data, + }, { .compatible = "rockchip,rkrng", .data = (ulong)&rkrng_soc_data, From dd2c7df419ae8a5cc5f7ee0480218b0ae28d4926 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Fri, 1 Aug 2025 20:32:38 +0000 Subject: [PATCH 022/103] rockchip: Add default USB_GADGET_PRODUCT_NUM for RK3576 Use 0x350e as the default USB Product ID for Rockchip RK3576, same PID being used by the BootROM when the device is in MASKROM mode. Signed-off-by: Jonas Karlman Reviewed-by: Mattijs Korpershoek Reviewed-by: Kever Yang --- drivers/usb/gadget/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index 6201663317b..0121f9872ae 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -86,6 +86,7 @@ config USB_GADGET_PRODUCT_NUM default 0x350a if ROCKCHIP_RK3568 default 0x350b if ROCKCHIP_RK3588 default 0x350c if ROCKCHIP_RK3528 + default 0x350e if ROCKCHIP_RK3576 default 0x0 help Product ID of the USB device emulated, reported to the host device. From 108d9f11ea928a80976db80b5ff723ce8170ebe1 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Fri, 1 Aug 2025 20:32:39 +0000 Subject: [PATCH 023/103] board: rockchip: Add minimal generic RK3576 board Add a minimal generic RK3576 board that only have eMMC, SDMMC and USB OTG enabled. This defconfig can be used to boot from eMMC or SD-card on most RK3576 boards that follow reference board design. eMMC and SD-card boot tested on: - ArmSoM CM5 - ArmSoM Sige5 - FriendlyElec NanoPi M5 - Luckfox Omni3576 - Toybrick TB-RK3576D Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rk3576-generic-u-boot.dtsi | 3 ++ arch/arm/dts/rk3576-generic.dts | 63 +++++++++++++++++++++++ arch/arm/mach-rockchip/rk3576/MAINTAINERS | 5 ++ configs/generic-rk3576_defconfig | 50 ++++++++++++++++++ doc/board/rockchip/rockchip.rst | 1 + 5 files changed, 122 insertions(+) create mode 100644 arch/arm/dts/rk3576-generic-u-boot.dtsi create mode 100644 arch/arm/dts/rk3576-generic.dts create mode 100644 arch/arm/mach-rockchip/rk3576/MAINTAINERS create mode 100644 configs/generic-rk3576_defconfig diff --git a/arch/arm/dts/rk3576-generic-u-boot.dtsi b/arch/arm/dts/rk3576-generic-u-boot.dtsi new file mode 100644 index 00000000000..632fabb6af5 --- /dev/null +++ b/arch/arm/dts/rk3576-generic-u-boot.dtsi @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3576-u-boot.dtsi" diff --git a/arch/arm/dts/rk3576-generic.dts b/arch/arm/dts/rk3576-generic.dts new file mode 100644 index 00000000000..123be5378d9 --- /dev/null +++ b/arch/arm/dts/rk3576-generic.dts @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Minimal generic DT for RK3576 with eMMC, SD-card and USB OTG enabled + */ + +/dts-v1/; + +#include +#include "rk3576.dtsi" + +/ { + model = "Generic RK3576"; + compatible = "rockchip,rk3576"; + + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; + }; + + chosen { + stdout-path = "serial0:1500000n8"; + }; +}; + +&sdhci { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + no-sd; + no-sdio; + non-removable; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + disable-wp; + no-mmc; + no-sdio; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&uart0 { + pinctrl-0 = <&uart0m0_xfer>; + status = "okay"; +}; + +&usb_drd0_dwc3 { + dr_mode = "peripheral"; + maximum-speed = "high-speed"; + phys = <&u2phy0_otg>; + phy-names = "usb2-phy"; + status = "okay"; +}; diff --git a/arch/arm/mach-rockchip/rk3576/MAINTAINERS b/arch/arm/mach-rockchip/rk3576/MAINTAINERS new file mode 100644 index 00000000000..b5190c81846 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3576/MAINTAINERS @@ -0,0 +1,5 @@ +GENERIC-RK3576 +M: Jonas Karlman +S: Maintained +F: arch/arm/dts/rk3576-generic* +F: configs/generic-rk3576_defconfig diff --git a/configs/generic-rk3576_defconfig b/configs/generic-rk3576_defconfig new file mode 100644 index 00000000000..5e25653820c --- /dev/null +++ b/configs/generic-rk3576_defconfig @@ -0,0 +1,50 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_DEFAULT_DEVICE_TREE="rk3576-generic" +CONFIG_ROCKCHIP_RK3576=y +CONFIG_SYS_LOAD_ADDR=0x40c00800 +CONFIG_DEBUG_UART_BASE=0x2AD40000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +# CONFIG_BOOTMETH_VBE is not set +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3576-generic.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_MAX_SIZE=0x40000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMINFO_MAP=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MISC=y +CONFIG_CMD_MMC=y +CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_RNG=y +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_OF_UPSTREAM is not set +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_NO_NET=y +# CONFIG_ADC is not set +# CONFIG_USB_FUNCTION_FASTBOOT is not set +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSRESET_PSCI=y +CONFIG_USB=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_ROCKUSB=y +CONFIG_ERRNO_STR=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index a2d8a715a4b..4d27b809980 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -135,6 +135,7 @@ List of mainline supported Rockchip boards: * rk3576 - Firefly ROC-RK3576-PC (roc-pc-rk3576) + - Generic RK3576 (generic-rk3576) * rk3588 - ArmSoM Sige7 (sige7-rk3588) From a72e8feaca46ed41a8d6bb4e8c5961a29fe7a39e Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Fri, 1 Aug 2025 20:32:40 +0000 Subject: [PATCH 024/103] rockchip: rk3576: Implement checkboard() to print SoC variant Implement checkboard() to print current SoC model used by a board when U-Boot proper is running. U-Boot 2025.04 (Apr 22 2025 - 20:43:17 +0000) Model: Generic RK3576 SoC: RK3576 DRAM: 8 GiB Information about the SoC model and variant is read from OTP. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/rk3576/rk3576.c | 48 ++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm/mach-rockchip/rk3576/rk3576.c b/arch/arm/mach-rockchip/rk3576/rk3576.c index ba5c94b4b3d..2b1318f9532 100644 --- a/arch/arm/mach-rockchip/rk3576/rk3576.c +++ b/arch/arm/mach-rockchip/rk3576/rk3576.c @@ -3,6 +3,10 @@ * Copyright (c) 2024 Rockchip Electronics Co., Ltd */ +#define LOG_CATEGORY LOGC_ARCH + +#include +#include #include #include #include @@ -153,3 +157,47 @@ int arch_cpu_init(void) return 0; } + +#define RK3576_OTP_CPU_CODE_OFFSET 0x02 +#define RK3576_OTP_SPECIFICATION_OFFSET 0x08 + +int checkboard(void) +{ + u8 cpu_code[2], specification; + struct udevice *dev; + char suffix[2]; + int ret; + + if (!IS_ENABLED(CONFIG_ROCKCHIP_OTP) || !CONFIG_IS_ENABLED(MISC)) + return 0; + + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_DRIVER_GET(rockchip_otp), &dev); + if (ret) { + log_debug("Could not find otp device, ret=%d\n", ret); + return 0; + } + + /* cpu-code: SoC model, e.g. 0x35 0x76 */ + ret = misc_read(dev, RK3576_OTP_CPU_CODE_OFFSET, cpu_code, 2); + if (ret < 0) { + log_debug("Could not read cpu-code, ret=%d\n", ret); + return 0; + } + + /* specification: SoC variant, e.g. 0xA for RK3576J */ + ret = misc_read(dev, RK3576_OTP_SPECIFICATION_OFFSET, &specification, 1); + if (ret < 0) { + log_debug("Could not read specification, ret=%d\n", ret); + return 0; + } + specification &= 0x1f; + + /* for RK3576J i.e. '@' + 0xA = 'J' */ + suffix[0] = specification > 1 ? '@' + specification : '\0'; + suffix[1] = '\0'; + + printf("SoC: RK%02x%02x%s\n", cpu_code[0], cpu_code[1], suffix); + + return 0; +} From bdcda6be27b69a6e7ced1d59f5d6ceb07c5414ac Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Fri, 1 Aug 2025 20:32:41 +0000 Subject: [PATCH 025/103] arm: dts: rockchip: Include OTP in U-Boot pre-reloc phase for RK3576 Update rk3576-u-boot.dtsi to include OTP in U-Boot pre-reloc phase for checkboard() to be able to read information about the running SoC model and variant from OTP and print it during boot: U-Boot 2025.04 (Apr 22 2025 - 20:43:17 +0000) Model: Generic RK3576 SoC: RK3576 DRAM: 8 GiB Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rk3576-u-boot.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/dts/rk3576-u-boot.dtsi b/arch/arm/dts/rk3576-u-boot.dtsi index be99a48a630..fb5a107f47d 100644 --- a/arch/arm/dts/rk3576-u-boot.dtsi +++ b/arch/arm/dts/rk3576-u-boot.dtsi @@ -49,6 +49,10 @@ bootph-all; }; +&otp { + bootph-some-ram; +}; + &pcfg_pull_none { bootph-all; }; From 2d87afba58b95487f88717df33e16a909f90592a Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Fri, 1 Aug 2025 20:32:42 +0000 Subject: [PATCH 026/103] usb: dwc3-generic: Use combined glue and ctrl node for RK3576 Like Rockchip RK3328, RK3568 and RK3588, the RK3576 also have a single node to represent the glue and ctrl for USB 3.0. Use rk_ops as driver data to select correct ctrl node for RK3576 DWC3. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- drivers/usb/dwc3/dwc3-generic.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c index 3cda2b74b7e..cdb997ea6e4 100644 --- a/drivers/usb/dwc3/dwc3-generic.c +++ b/drivers/usb/dwc3/dwc3-generic.c @@ -699,6 +699,7 @@ static const struct udevice_id dwc3_glue_ids[] = { { .compatible = "rockchip,rk3328-dwc3", .data = (ulong)&rk_ops }, { .compatible = "rockchip,rk3399-dwc3" }, { .compatible = "rockchip,rk3568-dwc3", .data = (ulong)&rk_ops }, + { .compatible = "rockchip,rk3576-dwc3", .data = (ulong)&rk_ops }, { .compatible = "rockchip,rk3588-dwc3", .data = (ulong)&rk_ops }, { .compatible = "qcom,dwc3", .data = (ulong)&qcom_ops }, { .compatible = "fsl,imx8mp-dwc3", .data = (ulong)&imx8mp_ops }, From b518886f6d7061c127628c1e12f3921c49ffeaee Mon Sep 17 00:00:00 2001 From: Frank Wang Date: Fri, 1 Aug 2025 20:32:43 +0000 Subject: [PATCH 027/103] phy: rockchip-inno-usb2: Add support for RK3576 Add support for the USB2.0 PHYs used in the RK3576 SoC. Config values are taken from vendor U-Boot linux-6.1-stan-rkr5 tag. Signed-off-by: Frank Wang Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c index 3cc5956aed5..03fe1b38175 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c @@ -465,6 +465,28 @@ static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = { { /* sentinel */ } }; +static const struct rockchip_usb2phy_cfg rk3576_phy_cfgs[] = { + { + .reg = 0x0000, + .clkout_ctl = { 0x0008, 0, 0, 1, 0 }, + .port_cfgs = { + [USB2PHY_PORT_OTG] = { + .phy_sus = { 0x0000, 1, 0, 2, 1 }, + } + }, + }, + { + .reg = 0x2000, + .clkout_ctl = { 0x2008, 0, 0, 1, 0 }, + .port_cfgs = { + [USB2PHY_PORT_OTG] = { + .phy_sus = { 0x2000, 1, 0, 2, 1 }, + } + }, + }, + { /* sentinel */ } +}; + static const struct rockchip_usb2phy_cfg rk3588_phy_cfgs[] = { { .reg = 0x0000, @@ -526,6 +548,10 @@ static const struct udevice_id rockchip_usb2phy_ids[] = { .compatible = "rockchip,rk3568-usb2phy", .data = (ulong)&rk3568_phy_cfgs, }, + { + .compatible = "rockchip,rk3576-usb2phy", + .data = (ulong)&rk3576_phy_cfgs, + }, { .compatible = "rockchip,rk3588-usb2phy", .data = (ulong)&rk3588_phy_cfgs, From 0d966d3932e2e5e7d14301da9ced0d7a62fce367 Mon Sep 17 00:00:00 2001 From: Frank Wang Date: Fri, 1 Aug 2025 20:32:44 +0000 Subject: [PATCH 028/103] phy: rockchip: usbdp: Add support for RK3576 Add support for the USB3.0+DP PHY used in the RK3576 SoC. Config values are taken from vendor U-Boot linux-6.1-stan-rkr5 tag. Signed-off-by: Frank Wang Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- drivers/phy/rockchip/phy-rockchip-usbdp.c | 26 +++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockchip/phy-rockchip-usbdp.c index 9deec47ae46..ed0441842a1 100644 --- a/drivers/phy/rockchip/phy-rockchip-usbdp.c +++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c @@ -813,6 +813,28 @@ static const char * const rk3588_udphy_rst_l[] = { "init", "cmn", "lane", "pcs_apb", "pma_apb" }; +static const struct rockchip_udphy_cfg rk3576_udphy_cfgs = { + .num_phys = 1, + .phy_ids = { + 0x2b010000, + }, + .num_rsts = ARRAY_SIZE(rk3588_udphy_rst_l), + .rst_list = rk3588_udphy_rst_l, + .grfcfg = { + /* u2phy-grf */ + .bvalid_phy_con = { 0x0010, 1, 0, 0x2, 0x3 }, + .bvalid_grf_con = { 0x0000, 15, 14, 0x1, 0x3 }, + + /* usb-grf */ + .usb3otg0_cfg = { 0x0030, 15, 0, 0x1100, 0x0188 }, + + /* usbdpphy-grf */ + .low_pwrn = { 0x0004, 13, 13, 0, 1 }, + .rx_lfps = { 0x0004, 14, 14, 0, 1 }, + }, + .combophy_init = rk3588_udphy_init, +}; + static const struct rockchip_udphy_cfg rk3588_udphy_cfgs = { .num_phys = 2, .phy_ids = { @@ -838,6 +860,10 @@ static const struct rockchip_udphy_cfg rk3588_udphy_cfgs = { }; static const struct udevice_id rockchip_udphy_dt_match[] = { + { + .compatible = "rockchip,rk3576-usbdp-phy", + .data = (ulong)&rk3576_udphy_cfgs + }, { .compatible = "rockchip,rk3588-usbdp-phy", .data = (ulong)&rk3588_udphy_cfgs From 2a6039a20994c192edb6786fa97714180bd663cf Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Fri, 1 Aug 2025 20:43:37 +0000 Subject: [PATCH 029/103] rockchip: clk: clk_rk3576: Add dummy CLK_REF_PCIEx_PHY support Add dummy support for the CLK_REF_PCIEx_PHY clocks to allow probe of the phy-rockchip-naneng-combphy driver on RK3576. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- drivers/clk/rockchip/clk_rk3576.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/rockchip/clk_rk3576.c b/drivers/clk/rockchip/clk_rk3576.c index e84a0943a94..125b08ee832 100644 --- a/drivers/clk/rockchip/clk_rk3576.c +++ b/drivers/clk/rockchip/clk_rk3576.c @@ -2168,6 +2168,8 @@ static ulong rk3576_clk_set_rate(struct clk *clk, ulong rate) case CLK_CPLL_DIV10: case FCLK_DDR_CM0_CORE: case ACLK_PHP_ROOT: + case CLK_REF_PCIE0_PHY: + case CLK_REF_PCIE1_PHY: ret = 0; break; #ifndef CONFIG_SPL_BUILD From cca7e79c7a42067fd8e65f4d2d2c73a98e42cd2e Mon Sep 17 00:00:00 2001 From: Jon Lin Date: Fri, 1 Aug 2025 20:43:38 +0000 Subject: [PATCH 030/103] phy: rockchip: naneng-combphy: Add support for RK3576 Add support for the PCIe/USB3/SATA combo PHYs used in the RK3576 SoC. Config values are taken from vendor U-Boot linux-6.1-stan-rkr5 tag. Signed-off-by: Jon Lin Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- .../rockchip/phy-rockchip-naneng-combphy.c | 147 ++++++++++++++++++ 1 file changed, 147 insertions(+) diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c index 5145b517aa4..e6fb0bce522 100644 --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c @@ -453,6 +453,149 @@ static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = { .combphy_cfg = rk3568_combphy_cfg, }; +static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv) +{ + const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; + u32 val; + + switch (priv->mode) { + case PHY_TYPE_PCIE: + param_write(priv->phy_grf, &cfg->con0_for_pcie, true); + param_write(priv->phy_grf, &cfg->con1_for_pcie, true); + param_write(priv->phy_grf, &cfg->con2_for_pcie, true); + param_write(priv->phy_grf, &cfg->con3_for_pcie, true); + break; + case PHY_TYPE_USB3: + /* Set SSC downward spread spectrum */ + val = readl(priv->mmio + (0x1f << 2)); + val &= ~GENMASK(5, 4); + val |= 0x01 << 4; + writel(val, priv->mmio + 0x7c); + + /* Enable adaptive CTLE for USB3.0 Rx */ + val = readl(priv->mmio + (0x0e << 2)); + val &= ~GENMASK(0, 0); + val |= 0x01; + writel(val, priv->mmio + (0x0e << 2)); + + /* Set PLL KVCO fine tuning signals */ + val = readl(priv->mmio + (0x20 << 2)); + val &= ~(0x7 << 2); + val |= 0x2 << 2; + writel(val, priv->mmio + (0x20 << 2)); + + /* Set PLL LPF R1 to su_trim[10:7]=1001 */ + writel(0x4, priv->mmio + (0xb << 2)); + + /* Set PLL input clock divider 1/2 */ + val = readl(priv->mmio + (0x5 << 2)); + val &= ~(0x3 << 6); + val |= 0x1 << 6; + writel(val, priv->mmio + (0x5 << 2)); + + /* Set PLL loop divider */ + writel(0x32, priv->mmio + (0x11 << 2)); + + /* Set PLL KVCO to min and set PLL charge pump current to max */ + writel(0xf0, priv->mmio + (0xa << 2)); + + /* Set Rx squelch input filler bandwidth */ + writel(0x0d, priv->mmio + (0x14 << 2)); + + param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); + param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); + param_write(priv->phy_grf, &cfg->usb_mode_set, true); + param_write(priv->pipe_grf, &cfg->u3otg1_port_en, true); + break; + case PHY_TYPE_SATA: + /* Enable adaptive CTLE for SATA Rx */ + val = readl(priv->mmio + (0x0e << 2)); + val &= ~GENMASK(0, 0); + val |= 0x01; + writel(val, priv->mmio + (0x0e << 2)); + /* Set tx_rterm = 50 ohm and rx_rterm = 43.5 ohm */ + writel(0x8F, priv->mmio + (0x06 << 2)); + + param_write(priv->phy_grf, &cfg->con0_for_sata, true); + param_write(priv->phy_grf, &cfg->con1_for_sata, true); + param_write(priv->phy_grf, &cfg->con2_for_sata, true); + param_write(priv->phy_grf, &cfg->con3_for_sata, true); + param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); + param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true); + break; + case PHY_TYPE_SGMII: + case PHY_TYPE_QSGMII: + default: + dev_err(priv->dev, "incompatible PHY type\n"); + return -EINVAL; + } + + /* 100MHz refclock signal is good */ + clk_set_rate(&priv->ref_clk, 100000000); + param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); + if (priv->mode == PHY_TYPE_PCIE) { + /* gate_tx_pck_sel length select work for L1SS */ + writel(0xc0, priv->mmio + 0x74); + + /* PLL KVCO tuning fine */ + val = readl(priv->mmio + (0x20 << 2)); + val &= ~(0x7 << 2); + val |= 0x2 << 2; + writel(val, priv->mmio + (0x20 << 2)); + + /* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */ + writel(0x4c, priv->mmio + (0x1b << 2)); + + /* Set up su_trim: T3_P1 650mv */ + writel(0x90, priv->mmio + (0xa << 2)); + writel(0x43, priv->mmio + (0xb << 2)); + writel(0x88, priv->mmio + (0xc << 2)); + writel(0x56, priv->mmio + (0xd << 2)); + } + + return 0; +} + +static const struct rockchip_combphy_grfcfg rk3576_combphy_grfcfgs = { + /* pipe-phy-grf */ + .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, + .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, + .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, + .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, + .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, + .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, + .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, + .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 }, + .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 }, + .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, + .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, + .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, + .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, + .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, + .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, + .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, + .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, + .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, + .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0129 }, + .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0000 }, + .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c1 }, + .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x0407 }, + /* php-grf */ + .pipe_con0_for_sata = { 0x001C, 2, 0, 0x00, 0x2 }, + .pipe_con1_for_sata = { 0x0020, 2, 0, 0x00, 0x2 }, + .u3otg1_port_en = { 0x0038, 15, 0, 0x0181, 0x1100 }, +}; + +static const struct rockchip_combphy_cfg rk3576_combphy_cfgs = { + .num_phys = 2, + .phy_ids = { + 0x2b050000, + 0x2b060000, + }, + .grfcfg = &rk3576_combphy_grfcfgs, + .combphy_cfg = rk3576_combphy_cfg, +}; + static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv) { const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; @@ -564,6 +707,10 @@ static const struct udevice_id rockchip_combphy_ids[] = { .compatible = "rockchip,rk3568-naneng-combphy", .data = (ulong)&rk3568_combphy_cfgs }, + { + .compatible = "rockchip,rk3576-naneng-combphy", + .data = (ulong)&rk3576_combphy_cfgs + }, { .compatible = "rockchip,rk3588-naneng-combphy", .data = (ulong)&rk3588_combphy_cfgs From ae2faeae673479014846c0c6280edb46782cf950 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Fri, 1 Aug 2025 20:43:39 +0000 Subject: [PATCH 031/103] board: rockchip: Add ArmSoM Sige5 ArmSoM-Sige5 adopts the second-generation 8nm high-performance AIOT platform Rockchip RK3576, with a 6 TOPS computing power NPU and support for up to 16GB of large memory. It supports 4K video encoding and decoding, offers rich interfaces including dual gigabit Ethernet ports, WiFi 6 & BT5, and various video outputs. Features tested on a ArmSoM Sige5 v1.1: - SD-card boot - eMMC boot - Ethernet - PCIe NVMe Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rk3576-armsom-sige5-u-boot.dtsi | 18 ++++++ arch/arm/mach-rockchip/rk3576/MAINTAINERS | 6 ++ configs/sige5-rk3576_defconfig | 66 ++++++++++++++++++++ doc/board/rockchip/rockchip.rst | 1 + 4 files changed, 91 insertions(+) create mode 100644 arch/arm/dts/rk3576-armsom-sige5-u-boot.dtsi create mode 100644 configs/sige5-rk3576_defconfig diff --git a/arch/arm/dts/rk3576-armsom-sige5-u-boot.dtsi b/arch/arm/dts/rk3576-armsom-sige5-u-boot.dtsi new file mode 100644 index 00000000000..7e0530d85d1 --- /dev/null +++ b/arch/arm/dts/rk3576-armsom-sige5-u-boot.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3576-u-boot.dtsi" + +/ { + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; + }; +}; + +&red_led { + default-state = "on"; +}; + +&sdhci { + cap-mmc-highspeed; +}; diff --git a/arch/arm/mach-rockchip/rk3576/MAINTAINERS b/arch/arm/mach-rockchip/rk3576/MAINTAINERS index b5190c81846..94ef74d429f 100644 --- a/arch/arm/mach-rockchip/rk3576/MAINTAINERS +++ b/arch/arm/mach-rockchip/rk3576/MAINTAINERS @@ -3,3 +3,9 @@ M: Jonas Karlman S: Maintained F: arch/arm/dts/rk3576-generic* F: configs/generic-rk3576_defconfig + +SIGE5-RK3576 +M: Jonas Karlman +S: Maintained +F: arch/arm/dts/rk3576-armsom-sige5* +F: configs/sige5-rk3576_defconfig diff --git a/configs/sige5-rk3576_defconfig b/configs/sige5-rk3576_defconfig new file mode 100644 index 00000000000..c515e145595 --- /dev/null +++ b/configs/sige5-rk3576_defconfig @@ -0,0 +1,66 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3576-armsom-sige5" +CONFIG_ROCKCHIP_RK3576=y +CONFIG_SYS_LOAD_ADDR=0x40c00800 +CONFIG_DEBUG_UART_BASE=0x2AD40000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3576-armsom-sige5.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_MAX_SIZE=0x40000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMINFO_MAP=y +CONFIG_CMD_ADC=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MISC=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_RNG=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +# CONFIG_USB_FUNCTION_FASTBOOT is not set +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_ROCKCHIP=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_PHY_ROCKCHIP_USBDP=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSRESET_PSCI=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_ROCKUSB=y +CONFIG_ERRNO_STR=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 4d27b809980..1ac44ba0a52 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -134,6 +134,7 @@ List of mainline supported Rockchip boards: - Radxa ROCK 3B (rock-3b-rk3568) * rk3576 + - ArmSoM Sige5 (sige5-rk3576) - Firefly ROC-RK3576-PC (roc-pc-rk3576) - Generic RK3576 (generic-rk3576) From 009bc00bf91bcd3076992a85077de82340e33219 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Fri, 27 Jun 2025 15:30:16 +0200 Subject: [PATCH 032/103] rockchip: tiger-rk3588: enable "env erase" command Erasing the environment to start from scratch is actually very useful and "env erase" is the proper way to do it instead of using "env default -a && env save", so let's enable support for it. Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang --- configs/tiger-rk3588_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/tiger-rk3588_defconfig b/configs/tiger-rk3588_defconfig index 335ea4d8de3..8ba2a996ee2 100644 --- a/configs/tiger-rk3588_defconfig +++ b/configs/tiger-rk3588_defconfig @@ -35,6 +35,7 @@ CONFIG_SPL_ATF=y # CONFIG_BOOTM_RTEMS is not set # CONFIG_BOOTM_VXWORKS is not set # CONFIG_CMD_ELF is not set +CONFIG_CMD_ERASEENV=y CONFIG_CMD_ADC=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y From 3c8b94ac91ea01debad4978111f1e96b37bd409f Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Fri, 27 Jun 2025 15:30:17 +0200 Subject: [PATCH 033/103] rockchip: jaguar-rk3588: enable "env erase" command Erasing the environment to start from scratch is actually very useful and "env erase" is the proper way to do it instead of using "env default -a && env save", so let's enable support for it. Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang --- configs/jaguar-rk3588_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/jaguar-rk3588_defconfig b/configs/jaguar-rk3588_defconfig index 13cff7b1a02..378c48963f7 100644 --- a/configs/jaguar-rk3588_defconfig +++ b/configs/jaguar-rk3588_defconfig @@ -34,6 +34,7 @@ CONFIG_SPL_ATF=y # CONFIG_BOOTM_RTEMS is not set # CONFIG_BOOTM_VXWORKS is not set # CONFIG_CMD_ELF is not set +CONFIG_CMD_ERASEENV=y CONFIG_CMD_ADC=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y From 755653c06c5dbe33e4cc342496935a1fd2a44fb5 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Fri, 27 Jun 2025 15:30:18 +0200 Subject: [PATCH 034/103] rockchip: ringneck-px30: enable "env erase" command Erasing the environment to start from scratch is actually very useful and "env erase" is the proper way to do it instead of using "env default -a && env save", so let's enable support for it. Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang --- configs/ringneck-px30_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/ringneck-px30_defconfig b/configs/ringneck-px30_defconfig index ba15e386770..2240ba80e5e 100644 --- a/configs/ringneck-px30_defconfig +++ b/configs/ringneck-px30_defconfig @@ -40,6 +40,7 @@ CONFIG_SPL_ATF=y # CONFIG_CMD_VBE is not set # CONFIG_BOOTM_VXWORKS is not set # CONFIG_CMD_ELF is not set +CONFIG_CMD_ERASEENV=y # CONFIG_CMD_LZMADEC is not set # CONFIG_CMD_UNZIP is not set CONFIG_CMD_BIND=y From a979380123e5e0da6b45eff0aec0ba71fd0440c6 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Fri, 27 Jun 2025 15:30:19 +0200 Subject: [PATCH 035/103] rockchip: puma-rk3399: enable "env erase" command Erasing the environment to start from scratch is actually very useful and "env erase" is the proper way to do it instead of using "env default -a && env save", so let's enable support for it. Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang --- configs/puma-rk3399_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig index 817d4fe1d64..2070d534232 100644 --- a/configs/puma-rk3399_defconfig +++ b/configs/puma-rk3399_defconfig @@ -36,6 +36,7 @@ CONFIG_TPL_GPIO=y # CONFIG_BOOTM_RTEMS is not set # CONFIG_CMD_VBE is not set # CONFIG_BOOTM_VXWORKS is not set +CONFIG_CMD_ERASEENV=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y From de0c91e7a7605b047d3dc96f9e1c02701af6d716 Mon Sep 17 00:00:00 2001 From: Jakob Unterwurzacher Date: Tue, 17 Jun 2025 10:42:52 +0200 Subject: [PATCH 036/103] board: rockchip: unblock CAN bus in spl_board_init on Jaguar GPIO0_B7 is routed to TXI of the on-board CAN transceiver. The line has a pull-down per SoC default. This means the CAN transceiver transmits a dominant zero and blocks the CAN bus until Linux boots and reconfigures the pin. Let's switch to pull-up as soon as we can (i.e. in SPL). This cuts down the "bus is blocked" time from 10 seconds to < 1 second. Of course, to this needs CONFIG_SPL_BOARD_INIT, so enable it the Jaguar defconfig. Signed-off-by: Jakob Unterwurzacher Reviewed-by: Kever Yang --- .../jaguar_rk3588/jaguar_rk3588.c | 19 +++++++++++++++++++ configs/jaguar-rk3588_defconfig | 1 + 2 files changed, 20 insertions(+) diff --git a/board/theobroma-systems/jaguar_rk3588/jaguar_rk3588.c b/board/theobroma-systems/jaguar_rk3588/jaguar_rk3588.c index a6d44f10db3..3f484646701 100644 --- a/board/theobroma-systems/jaguar_rk3588/jaguar_rk3588.c +++ b/board/theobroma-systems/jaguar_rk3588/jaguar_rk3588.c @@ -51,3 +51,22 @@ int rockchip_early_misc_init_r(void) return 0; } + +#define GPIO0B7_PU_EN BIT(15) + +void spl_board_init(void) +{ + /* + * GPIO0_B7 is routed to CAN TX. This SoC pin has a pull-down per default. + * So on power-up, we block the CAN bus with a dominant zero. We want to keep + * this blocking time to a minimum, so we want to get this pin high in SPL. + * + * The CAN driver in Linux disables the pull-down and sets the pin to + * output high. We don't have a CAN driver in U-Boot and don't need one, + * so we just use the easiest way to get the pin high, which is setting a + * pull-up. + */ + struct rk3588_pmu2_ioc * const ioc = (void *)PMU2_IOC_BASE; + + rk_setreg(&ioc->gpio0b_p, GPIO0B7_PU_EN); +} diff --git a/configs/jaguar-rk3588_defconfig b/configs/jaguar-rk3588_defconfig index 378c48963f7..3ed07d18e10 100644 --- a/configs/jaguar-rk3588_defconfig +++ b/configs/jaguar-rk3588_defconfig @@ -27,6 +27,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-jaguar.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CYCLIC=y CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_BOARD_INIT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_ATF=y # CONFIG_BOOTM_NETBSD is not set From 6048bbbb920373ac19bbcd7aa6bb61654bc92885 Mon Sep 17 00:00:00 2001 From: Marius Dinu Date: Wed, 11 Jun 2025 11:04:54 +0000 Subject: [PATCH 037/103] rk3288: add fdtoverlay_addr_r to default env rk3288 is missing fdtoverlay_addr_r. The new addresses match those used by rk3308. Tested on Asus TinkerBoard S. Signed-off-by: Marius Dinu Cc: Simon Glass Cc: Philipp Tomsich Cc: Kever Yang Reviewed-by: Quentin Schulz Reviewed-by: Kever Yang --- include/configs/rk3288_common.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index 0c449e31099..52c3695ff8e 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -18,7 +18,8 @@ #define ENV_MEM_LAYOUT_SETTINGS \ "scriptaddr=0x00000000\0" \ "pxefile_addr_r=0x00100000\0" \ - "fdt_addr_r=0x01f00000\0" \ + "fdt_addr_r=0x01e00000\0" \ + "fdtoverlay_addr_r=0x01f00000\0" \ "kernel_addr_r=0x02000000\0" \ "ramdisk_addr_r=0x04000000\0" From 9b3b5e03b8ddb548e6ece7b35ad1d52b5363abf2 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Wed, 30 Jul 2025 23:52:42 +0000 Subject: [PATCH 038/103] rockchip: rk3528-generic: Fix boot after dts/upstream v6.16-dts merge The rk3528-generic target can no longer boot after v6.16-dts was merged into dts/upstream, and instead end up in a boot loop: No serial driver found resetting ... After Linux commit 34d2730fbbdd ("arm64: dts: rockchip: move rk3528 i2c+uart aliases to board files") there is no longer an alias for serial0 defined for the U-Boot only rk3528-generic device tree. Add a board specific aliases node that include the missing serial0 alias to resolve the boot issue and ensure that stdout-path = "serial0:..." can be resolved by U-Boot. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rk3528-generic.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/dts/rk3528-generic.dts b/arch/arm/dts/rk3528-generic.dts index 3f6f0bed108..fe9e72c41cd 100644 --- a/arch/arm/dts/rk3528-generic.dts +++ b/arch/arm/dts/rk3528-generic.dts @@ -10,6 +10,11 @@ model = "Generic RK3528"; compatible = "rockchip,rk3528"; + aliases { + mmc0 = &sdhci; + serial0 = &uart0; + }; + chosen { stdout-path = "serial0:1500000n8"; }; From 2e3b37d589d3ccb3c7c11c0cca01f330a040c863 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Wed, 30 Jul 2025 23:52:43 +0000 Subject: [PATCH 039/103] arm: dts: rockchip: Use sdmmc node from dts/upstream on RK3528 Drop the sdmmc node from soc u-boot.dtsi and instead use the sdmmc node from rk3528.dtsi with v6.16-dts now merged to dts/upstream. This cleanup has no intended functional change. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rk3528-generic-u-boot.dtsi | 9 --------- arch/arm/dts/rk3528-generic.dts | 12 +++++++++++- arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi | 9 --------- arch/arm/dts/rk3528-u-boot.dtsi | 18 ------------------ 4 files changed, 11 insertions(+), 37 deletions(-) diff --git a/arch/arm/dts/rk3528-generic-u-boot.dtsi b/arch/arm/dts/rk3528-generic-u-boot.dtsi index cc830b51456..9e1fb2a7eef 100644 --- a/arch/arm/dts/rk3528-generic-u-boot.dtsi +++ b/arch/arm/dts/rk3528-generic-u-boot.dtsi @@ -1,12 +1,3 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) #include "rk3528-u-boot.dtsi" - -&sdmmc { - bus-width = <4>; - cap-sd-highspeed; - disable-wp; - no-mmc; - no-sdio; - status = "okay"; -}; diff --git a/arch/arm/dts/rk3528-generic.dts b/arch/arm/dts/rk3528-generic.dts index fe9e72c41cd..637ca03325e 100644 --- a/arch/arm/dts/rk3528-generic.dts +++ b/arch/arm/dts/rk3528-generic.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Minimal generic DT for RK3528 with eMMC enabled + * Minimal generic DT for RK3528 with eMMC and SD-card enabled */ /dts-v1/; @@ -12,6 +12,7 @@ aliases { mmc0 = &sdhci; + mmc1 = &sdmmc; serial0 = &uart0; }; @@ -30,6 +31,15 @@ status = "okay"; }; +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + disable-wp; + no-mmc; + no-sdio; + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0m0_xfer>; diff --git a/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi b/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi index 1372d8f1e38..05a58c136bc 100644 --- a/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi +++ b/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi @@ -5,12 +5,3 @@ &sdhci { mmc-hs200-1_8v; }; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - vmmc-supply = <&vcc_3v3>; - status = "okay"; -}; diff --git a/arch/arm/dts/rk3528-u-boot.dtsi b/arch/arm/dts/rk3528-u-boot.dtsi index eb6a55cd5c9..a18d33b3d36 100644 --- a/arch/arm/dts/rk3528-u-boot.dtsi +++ b/arch/arm/dts/rk3528-u-boot.dtsi @@ -27,24 +27,6 @@ compatible = "rockchip,rk3528-otp"; reg = <0x0 0xffce0000 0x0 0x4000>; }; - - sdmmc: mmc@ffc30000 { - compatible = "rockchip,rk3528-dw-mshc", - "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xffc30000 0x0 0x4000>; - clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SRC_SDMMC0>; - clock-names = "biu", "ciu"; - fifo-depth = <0x100>; - interrupts = ; - max-frequency = <150000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_bus4>, <&sdmmc_clk>, <&sdmmc_cmd>, - <&sdmmc_det>; - resets = <&cru SRST_H_SDMMC0>; - reset-names = "reset"; - rockchip,default-sample-phase = <90>; - status = "disabled"; - }; }; }; From 95ae8b040b891596c5a7916a0955d7820fc9e380 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Wed, 30 Jul 2025 23:52:44 +0000 Subject: [PATCH 040/103] arm: dts: rockchip: Set init-microvolt for pwm-regulators on Radxa E20C Radxa E20C has two main pwm-regulators, vdd_arm and vdd_logic. Add init-microvolt props to ensure the regulators are initialized at the recommended power-on sequence voltage instead of at max voltage. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi b/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi index 05a58c136bc..16c47e6b9a9 100644 --- a/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi +++ b/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi @@ -5,3 +5,11 @@ &sdhci { mmc-hs200-1_8v; }; + +&vdd_arm { + regulator-init-microvolt = <953000>; +}; + +&vdd_logic { + regulator-init-microvolt = <900000>; +}; From 58d39bbd773965404cd8cc41ebb94488b48ac1a4 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Wed, 30 Jul 2025 23:52:45 +0000 Subject: [PATCH 041/103] rockchip: rk3528: Disable USB3OTG U3 port early The RK3528 SoC comes with USB OTG support using a DWC3 controller with a USB2 PHY and a USB3 PHY (COMBPHY). Some board designs may not use the COMBPHY for USB3 purpose. For these board to use USB OTG the input clock source must change to use UTMI clk instead of PIPE clk. Change to always disable the USB3OTG U3 port early and leave it to the COMBPHY driver to re-enable the U3 port when a usb3-phy is described in the board device tree. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/rk3528/rk3528.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/mach-rockchip/rk3528/rk3528.c b/arch/arm/mach-rockchip/rk3528/rk3528.c index 4892ff6ba9d..f9bfc445b85 100644 --- a/arch/arm/mach-rockchip/rk3528/rk3528.c +++ b/arch/arm/mach-rockchip/rk3528/rk3528.c @@ -9,6 +9,9 @@ #include #include +#define VPU_GRF_BASE 0xff340000 +#define USB3OTG_CON1 0x44 + #define FIREWALL_DDR_BASE 0xff2e0000 #define FW_DDR_MST6_REG 0x58 #define FW_DDR_MST7_REG 0x5c @@ -69,6 +72,9 @@ int arch_cpu_init(void) val = readl(FIREWALL_DDR_BASE + FW_DDR_MST16_REG); writel(val & 0xffff0000, FIREWALL_DDR_BASE + FW_DDR_MST16_REG); + /* Disable USB3OTG U3 port, later enabled in COMBPHY driver */ + writel(0xffff0181, VPU_GRF_BASE + USB3OTG_CON1); + return 0; } From 281c66f39b0e6b3b520976ad0535939141f148b8 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Wed, 30 Jul 2025 23:52:46 +0000 Subject: [PATCH 042/103] rockchip: clk: clk_rk3528: Add dummy CLK_REF_PCIE_INNER_PHY support Add dummy support for the CLK_REF_PCIE_INNER_PHY clock to allow probe of the phy-rockchip-naneng-combphy driver on RK3528. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- drivers/clk/rockchip/clk_rk3528.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/rockchip/clk_rk3528.c b/drivers/clk/rockchip/clk_rk3528.c index 06f20895acc..d58557ff56d 100644 --- a/drivers/clk/rockchip/clk_rk3528.c +++ b/drivers/clk/rockchip/clk_rk3528.c @@ -1535,6 +1535,7 @@ static ulong rk3528_clk_set_rate(struct clk *clk, ulong rate) /* Might occur in cru assigned-clocks, can be ignored here */ case ACLK_BUS_VOPGL_ROOT: case BCLK_EMMC: + case CLK_REF_PCIE_INNER_PHY: case XIN_OSC0_DIV: ret = 0; break; From 0f310a08951c6ba99256928454bee3d81b6191b6 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Wed, 30 Jul 2025 23:52:47 +0000 Subject: [PATCH 043/103] usb: dwc3-generic: Use combined glue and ctrl node for RK3528 Like Rockchip RK3328, RK3568 and RK3588, the RK3528 also have a single node to represent the glue and ctrl for USB 3.0. Use rk_ops as driver data to select correct ctrl node for RK3528 DWC3. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- drivers/usb/dwc3/dwc3-generic.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c index cdb997ea6e4..c09014aec60 100644 --- a/drivers/usb/dwc3/dwc3-generic.c +++ b/drivers/usb/dwc3/dwc3-generic.c @@ -698,6 +698,7 @@ static const struct udevice_id dwc3_glue_ids[] = { { .compatible = "ti,am654-dwc3" }, { .compatible = "rockchip,rk3328-dwc3", .data = (ulong)&rk_ops }, { .compatible = "rockchip,rk3399-dwc3" }, + { .compatible = "rockchip,rk3528-dwc3", .data = (ulong)&rk_ops }, { .compatible = "rockchip,rk3568-dwc3", .data = (ulong)&rk_ops }, { .compatible = "rockchip,rk3576-dwc3", .data = (ulong)&rk_ops }, { .compatible = "rockchip,rk3588-dwc3", .data = (ulong)&rk_ops }, From dfc6ec058e80b9d45654fc85e00ecaec03d4f3c9 Mon Sep 17 00:00:00 2001 From: Jianwei Zheng Date: Wed, 30 Jul 2025 23:52:48 +0000 Subject: [PATCH 044/103] phy: rockchip: naneng-combphy: Add support for RK3528 Add support for the PCIe/USB3 combo PHY used in the RK3528 SoC. Config values are taken from vendor U-Boot linux-6.1-stan-rkr5 tag. Signed-off-by: Jianwei Zheng Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- .../rockchip/phy-rockchip-naneng-combphy.c | 102 ++++++++++++++++++ 1 file changed, 102 insertions(+) diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c index e6fb0bce522..6d8d10750b1 100644 --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c @@ -37,6 +37,7 @@ struct rockchip_combphy_grfcfg { struct combphy_reg pipe_rxterm_set; struct combphy_reg pipe_txelec_set; struct combphy_reg pipe_txcomp_set; + struct combphy_reg pipe_clk_24m; struct combphy_reg pipe_clk_25m; struct combphy_reg pipe_clk_100m; struct combphy_reg pipe_phymode_sel; @@ -310,6 +311,103 @@ static int rockchip_combphy_probe(struct udevice *udev) return rockchip_combphy_parse_dt(udev, priv); } +static int rk3528_combphy_cfg(struct rockchip_combphy_priv *priv) +{ + const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; + u32 val; + + switch (priv->mode) { + case PHY_TYPE_PCIE: + /* Set SSC downward spread spectrum */ + val = readl(priv->mmio + 0x18); + val &= ~GENMASK(5, 4); + val |= 0x01 << 4; + writel(val, priv->mmio + 0x18); + + param_write(priv->phy_grf, &cfg->con0_for_pcie, true); + param_write(priv->phy_grf, &cfg->con1_for_pcie, true); + param_write(priv->phy_grf, &cfg->con2_for_pcie, true); + param_write(priv->phy_grf, &cfg->con3_for_pcie, true); + break; + case PHY_TYPE_USB3: + /* Set SSC downward spread spectrum */ + val = readl(priv->mmio + 0x18); + val &= ~GENMASK(5, 4); + val |= 0x01 << 4; + writel(val, priv->mmio + 0x18); + + /* Enable adaptive CTLE for USB3.0 Rx */ + val = readl(priv->mmio + 0x200); + val &= ~GENMASK(17, 17); + val |= 0x01 << 17; + writel(val, priv->mmio + 0x200); + + /* Set Rx squelch input filler bandwidth */ + val = readl(priv->mmio + 0x20c); + val &= ~GENMASK(2, 0); + val |= 0x06; + writel(val, priv->mmio + 0x20c); + + param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); + param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); + param_write(priv->phy_grf, &cfg->usb_mode_set, true); + param_write(priv->pipe_grf, &cfg->u3otg0_port_en, true); + break; + default: + dev_err(priv->dev, "incompatible PHY type\n"); + return -EINVAL; + } + + param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); + + if (priv->mode == PHY_TYPE_PCIE) { + /* PLL KVCO tuning fine */ + val = readl(priv->mmio + 0x18); + val &= ~(0x7 << 10); + val |= 0x2 << 10; + writel(val, priv->mmio + 0x18); + + /* su_trim[6:4]=111, [10:7]=1001, [2:0]=000 */ + val = readl(priv->mmio + 0x108); + val &= ~(0x7f7); + val |= 0x4f0; + writel(val, priv->mmio + 0x108); + } + + return 0; +} + +static const struct rockchip_combphy_grfcfg rk3528_combphy_grfcfgs = { + /* pipe-phy-grf */ + .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, + .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, + .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, + .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, + .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, + .pipe_clk_24m = { 0x0004, 14, 13, 0x00, 0x00 }, + .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, + .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, + .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, + .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, + .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, + .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, + .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x110 }, + .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x00 }, + .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x101 }, + .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, + /* pipe-grf */ + .u3otg0_port_en = { 0x0044, 15, 0, 0x0181, 0x1100 }, +}; + +static const struct rockchip_combphy_cfg rk3528_combphy_cfgs = { + .num_phys = 1, + .phy_ids = { + 0xffdc0000, + }, + .grfcfg = &rk3528_combphy_grfcfgs, + .combphy_cfg = rk3528_combphy_cfg, +}; + static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv) { const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; @@ -703,6 +801,10 @@ static const struct rockchip_combphy_cfg rk3588_combphy_cfgs = { }; static const struct udevice_id rockchip_combphy_ids[] = { + { + .compatible = "rockchip,rk3528-naneng-combphy", + .data = (ulong)&rk3528_combphy_cfgs + }, { .compatible = "rockchip,rk3568-naneng-combphy", .data = (ulong)&rk3568_combphy_cfgs From 50c8b58eeab7708e76f82cf9a93bb7c5feb60ed6 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Wed, 30 Jul 2025 23:52:49 +0000 Subject: [PATCH 045/103] rockchip: rk3528-radxa-e20c: Enable USB gadget Kconfig options Radxa E20C has a USB OTG Type-C port for Debug and Data. Add required Kconfig options to use USB gadget features once pending USB nodes finally lands in dts/upstream by a future sync. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- configs/radxa-e20c-rk3528_defconfig | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/configs/radxa-e20c-rk3528_defconfig b/configs/radxa-e20c-rk3528_defconfig index f5e097f3edf..0941d1b9be8 100644 --- a/configs/radxa-e20c-rk3528_defconfig +++ b/configs/radxa-e20c-rk3528_defconfig @@ -20,6 +20,8 @@ CONFIG_CMD_GPT=y CONFIG_CMD_MISC=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_RNG=y CONFIG_CMD_REGULATOR=y @@ -28,6 +30,7 @@ CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigne CONFIG_BUTTON=y CONFIG_BUTTON_ADC=y CONFIG_BUTTON_GPIO=y +# CONFIG_USB_FUNCTION_FASTBOOT is not set CONFIG_ROCKCHIP_GPIO=y CONFIG_LED=y CONFIG_LED_GPIO=y @@ -43,6 +46,7 @@ CONFIG_DM_MDIO=y CONFIG_DWC_ETH_QOS=y CONFIG_DWC_ETH_QOS_ROCKCHIP=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y CONFIG_REGULATOR_PWM=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_PWM_ROCKCHIP=y @@ -50,6 +54,12 @@ CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_ROCKUSB=y CONFIG_ERRNO_STR=y From 4e3d2972d1bb3f891a8c827553524328d6679d14 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Wed, 13 Aug 2025 16:07:39 +0200 Subject: [PATCH 046/103] dt-bindings: mfd: rk806: Allow to customize PMIC reset mode The RK806 PMIC allows to configure its reset/restart behavior whenever the PMIC is reset either programmatically or via some external pins (e.g. PWRCTRL or RESETB). The following modes exist: - 0; restart PMU, - 1; reset all power off reset registers and force state to switch to ACTIVE mode, - 2; same as mode 1 and also pull RESETB pin down for 5ms, For example, some hardware may require a full restart (mode 0) in order to function properly as regulators are shortly interrupted in this mode. This is the case for RK3588 Jaguar and RK3588 Tiger which have a companion microcontroller running on an independent power supply and monitoring the PMIC power rail to know the state of the main system. When it detects a restart, it resets its own IPs exposed to the main system as if to simulate its own reset. Failing to perform this fake reset of the microcontroller may break things (e.g. watchdog not automatically disabled, buzzer still running until manually disabled, leftover configuration from previous main system state, etc...). Some other systems may be depending on the power rails to not be interrupted even for a small amount of time[1]. This allows to specify how the PMIC should perform on the hardware level and may differ between hardware designs, so a DT property seems warranted. I unfortunately do not see how this could be made generic enough to make it a non-vendor property. [1] https://lore.kernel.org/linux-rockchip/2577051.irdbgypaU6@workhorse/ Reviewed-by: Krzysztof Kozlowski Signed-off-by: Quentin Schulz Reviewed-by: "Rob Herring (Arm)" Link: https://lore.kernel.org/r/20250627-rk8xx-rst-fun-v4-1-ce05d041b45f@cherry.de Signed-off-by: Lee Jones [ upstream commit: 404005d1083997daec7236620b9ba14bccdce449 ] (cherry picked from commit 8ee72356e9844265334fd344bc05139d1f615c4d) Reviewed-by: Kever Yang --- dts/upstream/Bindings/mfd/rockchip,rk806.yaml | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/dts/upstream/Bindings/mfd/rockchip,rk806.yaml b/dts/upstream/Bindings/mfd/rockchip,rk806.yaml index 3c2b06629b7..eb5bca31948 100644 --- a/dts/upstream/Bindings/mfd/rockchip,rk806.yaml +++ b/dts/upstream/Bindings/mfd/rockchip,rk806.yaml @@ -31,6 +31,27 @@ properties: system-power-controller: true + rockchip,reset-mode: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2] + description: + Mode to use when a reset of the PMIC is triggered. + + The reset can be triggered either programmatically, via one of + the PWRCTRL pins (provided additional configuration) or + asserting RESETB pin low. + + The following modes are supported + + - 0; restart PMU, + - 1; reset all power off reset registers and force state to + switch to ACTIVE mode, + - 2; same as mode 1 and also pull RESETB pin down for 5ms, + + For example, some hardware may require a full restart (mode 0) + in order to function properly as regulators are shortly + interrupted in this mode. + vcc1-supply: description: The input supply for dcdc-reg1. From 289083811724327844e69f21e6785d8cd3f358fe Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Wed, 13 Aug 2025 16:07:40 +0200 Subject: [PATCH 047/103] arm64: dts: rockchip: add header for RK8XX PMIC constants To make it easier to read the device tree, let's add constants for the rockchip,reset-mode property values that are currently only applicable to RK806 PMIC. Signed-off-by: Quentin Schulz [dt-maintainers did not consider this part of the binding, so we're keeping the header in the devicetree directory] Link: https://lore.kernel.org/r/20250627-rk8xx-rst-fun-v4-3-ce05d041b45f@cherry.de Signed-off-by: Heiko Stuebner [ upstream commit: 304be20e65ca08fc2e9cb58eb939a0054d8a8b81 ] (cherry picked from commit 0e417bfcbc385c127c7f5ea01df6289aed8325c2) Reviewed-by: Kever Yang --- dts/upstream/src/arm64/rockchip/rk8xx.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 dts/upstream/src/arm64/rockchip/rk8xx.h diff --git a/dts/upstream/src/arm64/rockchip/rk8xx.h b/dts/upstream/src/arm64/rockchip/rk8xx.h new file mode 100644 index 00000000000..a6fbef71c06 --- /dev/null +++ b/dts/upstream/src/arm64/rockchip/rk8xx.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) */ +/* + * Device Tree defines for Rockchip RK8xx PMICs + * + * Copyright 2025 Cherry Embedded Solutions GmbH + * + * Author: Quentin Schulz + */ + +#ifndef _DT_MFD_ROCKCHIP_RK8XX_H +#define _DT_MFD_ROCKCHIP_RK8XX_H + +/* For use with rockchip,reset-mode property */ +#define RK806_RESTART 0 +#define RK806_RESET 1 +#define RK806_RESET_NOTIFY 2 + +#endif From 8df0eba814f666e92056909f59fd70b8e0af812d Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Wed, 13 Aug 2025 16:07:41 +0200 Subject: [PATCH 048/103] arm64: dts: rockchip: force PMIC reset behavior to restart PMU on RK3588 Jaguar The bootloader for RK3588 Jaguar currently forces the PMIC reset behavior (stored in RST_FUN bitfield in register SYS_CFG3 of the PMIC) to 0b1X which is incorrect for our devices. It is required to restart the PMU as otherwise the companion microcontroller cannot detect the PMIC (and by extension the full product and main SoC) being rebooted which is an issue as that is used to reset a few things like the PWM beeper and watchdogs. Let's add the new rockchip,reset-mode property to make sure the PMIC reset behavior is the expected one. Signed-off-by: Quentin Schulz Link: https://lore.kernel.org/r/20250627-rk8xx-rst-fun-v4-4-ce05d041b45f@cherry.de Signed-off-by: Heiko Stuebner [ upstream commit: ee907113430aa02a8202c91bb574c385ecc28aa2 ] (cherry picked from commit 8bd14566b75f9409de703a0d2f9a0704b71a7ebe) Reviewed-by: Kever Yang --- dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts b/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts index ebe77cdd24e..176925d0a1a 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts +++ b/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts @@ -10,6 +10,7 @@ #include #include #include +#include "rk8xx.h" #include "rk3588.dtsi" / { @@ -693,6 +694,7 @@ vcc13-supply = <&vcc_1v1_nldo_s3>; vcc14-supply = <&vcc_1v1_nldo_s3>; vcca-supply = <&vcc5v0_sys>; + rockchip,reset-mode = ; rk806_dvs1_null: dvs1-null-pins { pins = "gpio_pwrctrl1"; From 82d832716235f0f04782e66d7b25e711fe6afd6c Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Wed, 13 Aug 2025 16:07:42 +0200 Subject: [PATCH 049/103] arm64: dts: rockchip: force PMIC reset behavior to restart PMU on RK3588 Tiger The bootloader for RK3588 Tiger currently forces the PMIC reset behavior (stored in RST_FUN bitfield in register SYS_CFG3 of the PMIC) to 0b1X which is incorrect for our devices. It is required to restart the PMU as otherwise the companion microcontroller cannot detect the PMIC (and by extension the full product and main SoC) being rebooted which is an issue as that is used to reset a few things like the PWM beeper and watchdogs. Let's add the new rockchip,reset-mode property to make sure the PMIC reset behavior is the expected one. Signed-off-by: Quentin Schulz Link: https://lore.kernel.org/r/20250627-rk8xx-rst-fun-v4-5-ce05d041b45f@cherry.de Signed-off-by: Heiko Stuebner [ upstream commit: e82f642b9821384045915dc30e73df7de8424827 ] (cherry picked from commit d9c568906be166834f4f977bc7f704176bac5b8a) Reviewed-by: Kever Yang --- dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi index c4933a08dd1..b44e89e1bb1 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include "rk8xx.h" #include "rk3588.dtsi" / { @@ -440,6 +441,7 @@ vcc13-supply = <&vcc_1v1_nldo_s3>; vcc14-supply = <&vcc_1v1_nldo_s3>; vcca-supply = <&vcc5v0_sys>; + rockchip,reset-mode = ; rk806_dvs1_null: dvs1-null-pins { pins = "gpio_pwrctrl1"; From 1961bba4bc341573db98a6fd34eac771e914681f Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Wed, 13 Aug 2025 16:07:43 +0200 Subject: [PATCH 050/103] power: rk8xx: allow to customize RK806 reset mode The RK806 PMIC has a bitfield for configuring the restart/reset behavior (which I assume Rockchip calls "function") whenever the PMIC is reset either programmatically (c.f. DEV_RST in the datasheet) or via PWRCTRL or RESETB pins. For RK806, the following values are possible for RST_FUN: 0b00 means "Restart PMU" 0b01 means "Reset all the power off reset registers, forcing the state to switch to ACTIVE mode" 0b10 means "Reset all the power off reset registers, forcing the state to switch to ACTIVE mode, and simultaneously pull down the RESETB PIN for 5mS before releasing" 0b11 means the same as for 0b10 just above. This adds the appropriate logic in the driver to parse the new rockchip,reset-mode DT property to pass this information. It just happens that the values in the binding match the values to write in the bitfield so no mapping is necessary. For backward compatibility reasons, if the property is missing we set it to 0b10 (i.e. BIT(7)) like before this commit was merged instead of leaving it untouched like in the kernel driver. Note that this does nothing useful for U-Boot at the moment as the ways to reset the device (e.g. via `reset` command) doesn't interact with the RK8xx PMIC and simply does a CPU reset. Considering the upstream Linux kernel left this register untouched until (assumed) v6.17[1], this is useful for cases in which the U-Boot bootloader has this patch (and running with a DT with rockchip,reset-mode property set) and running an upstream kernel before (assumed) v6.17, or alternatively later without the property in the kernel DT. [1] https://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd.git/commit/?id=87b48d86b77686013f5c2a8866ed299312b671db Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang --- drivers/power/pmic/rk8xx.c | 21 ++++++++++++--------- include/power/rk8xx_pmic.h | 2 ++ 2 files changed, 14 insertions(+), 9 deletions(-) diff --git a/drivers/power/pmic/rk8xx.c b/drivers/power/pmic/rk8xx.c index 3bc696d4caa..d11f7a7886e 100644 --- a/drivers/power/pmic/rk8xx.c +++ b/drivers/power/pmic/rk8xx.c @@ -89,11 +89,6 @@ void rk8xx_off_for_plugin(struct udevice *dev) } } -static struct reg_data rk806_init_reg[] = { - /* RST_FUN */ - { RK806_REG_SYS_CFG3, BIT(7), GENMASK(7, 6)}, -}; - static struct reg_data rk817_init_reg[] = { /* enable the under-voltage protection, * the under-voltage protection will shutdown the LDO3 and reset the PMIC @@ -306,12 +301,20 @@ static int rk8xx_probe(struct udevice *dev) value = (power_en2 & 0x0f) | ((power_en3 & 0x0f) << 4); pmic_reg_write(dev, RK817_POWER_EN_SAVE1, value); break; - case RK806_ID: + case RK806_ID: { + u32 rst_fun = 2; + on_source = RK806_ON_SOURCE; off_source = RK806_OFF_SOURCE; - init_data = rk806_init_reg; - init_data_num = ARRAY_SIZE(rk806_init_reg); - break; + + ret = dev_read_u32(dev, "rockchip,reset-mode", &rst_fun); + if (ret) + debug("rockchip,reset-mode property missing, defaulting to %d\n", + rst_fun); + + pmic_clrsetbits(dev, RK806_REG_SYS_CFG3, RK806_RST_FUN_MSK, + FIELD_PREP(RK806_RST_FUN_MSK, rst_fun)); + break; } default: printf("Unknown PMIC: RK%x!!\n", show_variant); return -EINVAL; diff --git a/include/power/rk8xx_pmic.h b/include/power/rk8xx_pmic.h index 31221aa46b6..913b6ebe6d9 100644 --- a/include/power/rk8xx_pmic.h +++ b/include/power/rk8xx_pmic.h @@ -212,6 +212,8 @@ enum { #define RK817_POWER_EN_SAVE0 0x99 #define RK817_POWER_EN_SAVE1 0xa4 +#define RK806_RST_FUN_MSK GENMASK(7, 6) + #define RK806_POWER_EN(x) (0x00 + (x)) /* POWER_ENx register lower 4 bits are write-protected unless the associated top bit is set */ #define RK806_POWER_EN_CLRSETBITS(bit, val) (((val) << (bit)) | (1 << ((bit) + 4))) From 97b0f9f8ce4fc8d994fad60660e1daba2da190e9 Mon Sep 17 00:00:00 2001 From: Andrew Goodbody Date: Thu, 31 Jul 2025 12:46:10 +0100 Subject: [PATCH 051/103] mmc: rockchip_sdhci: Do not test unsigned for being less than 0 In rockchip_sdhci_execute_tuning the variable tuning_loop_counter is tested for being less than 0. Ensure that it is a signed type by declaring it as s8 instead of char. This issue was found by Smatch. Signed-off-by: Andrew Goodbody Reviewed-by: Peng Fan Reviewed-by: Kever Yang --- drivers/mmc/rockchip_sdhci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c index 761e3619329..5e025d76a82 100644 --- a/drivers/mmc/rockchip_sdhci.c +++ b/drivers/mmc/rockchip_sdhci.c @@ -500,7 +500,7 @@ static int rockchip_sdhci_execute_tuning(struct mmc *mmc, u8 opcode) { struct rockchip_sdhc *priv = dev_get_priv(mmc->dev); struct sdhci_host *host = &priv->host; - char tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT; + s8 tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT; struct mmc_cmd cmd; u32 ctrl, blk_size; int ret; From b2ebdd592ecd1309e26a7c428200b9d6c0ce9700 Mon Sep 17 00:00:00 2001 From: Diederik de Haas Date: Thu, 31 Jul 2025 14:47:05 +0200 Subject: [PATCH 052/103] rockchip: rk3568-nanopi-r5s: Enable ROCKUSB on NanoPi R5S Enable the needed modules so that ROCKUSB can be used to update the NanoPi R5S. Signed-off-by: Diederik de Haas Reviewed-by: Kever Yang --- configs/nanopi-r5s-rk3568_defconfig | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/configs/nanopi-r5s-rk3568_defconfig b/configs/nanopi-r5s-rk3568_defconfig index 8e5e7e3e1e5..1653ab8b44f 100644 --- a/configs/nanopi-r5s-rk3568_defconfig +++ b/configs/nanopi-r5s-rk3568_defconfig @@ -28,6 +28,8 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set @@ -38,6 +40,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y CONFIG_SPL_CLK=y +# CONFIG_USB_FUNCTION_FASTBOOT is not set CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y @@ -73,4 +76,8 @@ CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_ROCKUSB=y CONFIG_ERRNO_STR=y From ffa1485c8173668424ca0ad87020966658092772 Mon Sep 17 00:00:00 2001 From: Niu Zhihong Date: Wed, 23 Jul 2025 12:22:17 +0800 Subject: [PATCH 053/103] board: rockchip: Add Xunlong Orange Pi 5 Ultra The Orange Pi 5 Ultra is another board in the Orange Pi 5 family. Orange Pi 5 Ultra uses Rockchip RK3588, a new generation of octa-core 64-bit ARM processor, which includes quad-core A76 and quad-core A55. Features tested on a Orange Pi 5 Ultra 16GB: - SD-card boot - eMMC boot ROCKCHIP_TPL: https://github.com/rockchip-linux/rkbin/tree/master/bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v1.18.bin BL31: https://github.com/rockchip-linux/rkbin/tree/master/bin/rk35/rk3588_bl31_v1.48.elf Signed-off-by: Niu Zhihong Reviewed-by: Kever Yang --- .../dts/rk3588-orangepi-5-ultra-u-boot.dtsi | 20 +++++ board/rockchip/evb_rk3588/MAINTAINERS | 6 ++ board/xunlong/orangepi-5-ultra-rk3588/Kconfig | 12 +++ .../orangepi-5-ultra-rk3588/MAINTAINERS | 6 ++ configs/orangepi-5-ultra-rk3588_defconfig | 88 +++++++++++++++++++ doc/board/rockchip/rockchip.rst | 1 + 6 files changed, 133 insertions(+) create mode 100644 arch/arm/dts/rk3588-orangepi-5-ultra-u-boot.dtsi create mode 100644 board/xunlong/orangepi-5-ultra-rk3588/Kconfig create mode 100644 board/xunlong/orangepi-5-ultra-rk3588/MAINTAINERS create mode 100644 configs/orangepi-5-ultra-rk3588_defconfig diff --git a/arch/arm/dts/rk3588-orangepi-5-ultra-u-boot.dtsi b/arch/arm/dts/rk3588-orangepi-5-ultra-u-boot.dtsi new file mode 100644 index 00000000000..1ab31a4ec5a --- /dev/null +++ b/arch/arm/dts/rk3588-orangepi-5-ultra-u-boot.dtsi @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3588-u-boot.dtsi" + +&fspim1_pins { + bootph-pre-ram; + bootph-some-ram; +}; + +&sdhci { + cap-mmc-highspeed; + mmc-hs200-1_8v; +}; + +&sfc { + flash@0 { + bootph-pre-ram; + bootph-some-ram; + }; +}; diff --git a/board/rockchip/evb_rk3588/MAINTAINERS b/board/rockchip/evb_rk3588/MAINTAINERS index 1232f05a387..379c85f48a4 100644 --- a/board/rockchip/evb_rk3588/MAINTAINERS +++ b/board/rockchip/evb_rk3588/MAINTAINERS @@ -48,3 +48,9 @@ S: Maintained F: configs/orangepi-5-plus-rk3588_defconfig F: arch/arm/dts/rk3588-orangepi-5-plus.dts F: arch/arm/dts/rk3588-orangepi-5-plus-u-boot.dtsi + +ORANGEPI-5-RK3588-ULTRA +M: Niu Zhihong +S: Maintained +F: configs/orangepi-5-ultra-rk3588_defconfig +F: arch/arm/dts/rk3588-orangepi-5-ultra-u-boot.dtsi diff --git a/board/xunlong/orangepi-5-ultra-rk3588/Kconfig b/board/xunlong/orangepi-5-ultra-rk3588/Kconfig new file mode 100644 index 00000000000..43fc96b04c0 --- /dev/null +++ b/board/xunlong/orangepi-5-ultra-rk3588/Kconfig @@ -0,0 +1,12 @@ +if TARGET_ORANGEPI_5_ULTRA_RK3588 + +config SYS_BOARD + default "orangepi-5-ultra-rk3588" + +config SYS_VENDOR + default "xunlong" + +config SYS_CONFIG_NAME + default "evb_rk3588" + +endif diff --git a/board/xunlong/orangepi-5-ultra-rk3588/MAINTAINERS b/board/xunlong/orangepi-5-ultra-rk3588/MAINTAINERS new file mode 100644 index 00000000000..be9c93f6b9d --- /dev/null +++ b/board/xunlong/orangepi-5-ultra-rk3588/MAINTAINERS @@ -0,0 +1,6 @@ +ORANGEPI-5-RK3588-ULTRA +M: Niu Zhihong +S: Maintained +F: board/xunlong/orangepi-5-rk3588-ultra +F: configs/orangepi-5-ultra-rk3588_defconfig +F: arch/arm/dts/rk3588-orangepi-5-ultra.dts diff --git a/configs/orangepi-5-ultra-rk3588_defconfig b/configs/orangepi-5-ultra-rk3588_defconfig new file mode 100644 index 00000000000..f3274325922 --- /dev/null +++ b/configs/orangepi-5-ultra-rk3588_defconfig @@ -0,0 +1,88 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SF_DEFAULT_SPEED=80000000 +CONFIG_SF_DEFAULT_MODE=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588-orangepi-5-ultra" +CONFIG_ROCKCHIP_RK3588=y +CONFIG_ROCKCHIP_SPI_IMAGE=y +CONFIG_SPL_SERIAL=y +CONFIG_TARGET_EVB_RK3588=y +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_SF_DEFAULT_BUS=5 +CONFIG_DEBUG_UART_BASE=0xFEB50000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-orangepi-5-ultra.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_AHCI_PCI=y +CONFIG_DWC_AHCI=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_XMC=y +CONFIG_PHYLIB=y +CONFIG_RTL8169=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_PHY_ROCKCHIP_USBDP=y +CONFIG_SPL_PINCTRL=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_SCSI=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SFC=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_ERRNO_STR=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 1ac44ba0a52..de3aa79cb5c 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -164,6 +164,7 @@ List of mainline supported Rockchip boards: - Xunlong Orange Pi 5 (orangepi-5-rk3588s) - Xunlong Orange Pi 5 Max (orangepi-5-max-rk3588) - Xunlong Orange Pi 5 Plus (orangepi-5-plus-rk3588) + - Xunlong Orange Pi 5 Ultra (orangepi-5-ultra-rk3588) - Yanyi Tech CoolPi 4 Model B (coolpi-4b-rk3588s) - Yanyi Tech CoolPi CM5 EVB (coolpi-cm5-evb-rk3588) - Yanyi Tech CoolPi CM5 GenBook (coolpi-cm5-genbook-rk3588) From 0336e97b1187f7f54e11c6cb9f3fa938cc11204e Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Mon, 21 Jul 2025 22:07:10 +0000 Subject: [PATCH 054/103] phy: rockchip: usbdp: Fix Generic PHY reference counting Generic PHY reference counting helps ensure driver ops for init/exit and power on/off are called at correct state. For this to work the PHY driver must initialize PHY-id to a persistent value in of_xlate ops. The Rockchip USBDP PHY driver does not initialize the PHY-id field, this typically lead to use of unshared reference counting among different struct phy instances. Initialize the PHY-id in of_xlate ops to ensure use of shared reference counting among all struct phy instances. E.g. on a ROCK 5B following could be observed: => usb start starting USB... [...] Bus usb@fc400000: 2 USB Device(s) found scanning usb for storage devices... 1 Storage Device(s) found => usb reset resetting USB... [...] rockchip_udphy phy@fed90000: cmn ana lcpll lock timeout rockchip_udphy phy@fed90000: failed to init usbdp combophy rockchip_udphy phy@fed90000: PHY: Failed to init phy@fed90000: -110. Can't init PHY1 Bus usb@fc400000: probe failed, error -110 scanning usb for storage devices... 0 Storage Device(s) found With shared reference counting this is fixed: => usb reset resetting USB... [...] Bus usb@fc400000: 2 USB Device(s) found scanning usb for storage devices... 1 Storage Device(s) found Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- drivers/phy/rockchip/phy-rockchip-usbdp.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockchip/phy-rockchip-usbdp.c index ed0441842a1..c88eb0c1611 100644 --- a/drivers/phy/rockchip/phy-rockchip-usbdp.c +++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c @@ -587,12 +587,16 @@ static int udphy_power_off(struct rockchip_udphy *udphy, u8 mode) static int rockchip_u3phy_of_xlate(struct phy *phy, struct ofnode_phandle_args *args) { + struct rockchip_udphy *udphy = dev_get_priv(phy->dev); + if (args->args_count == 0) return -EINVAL; if (args->args[0] != PHY_TYPE_USB3) return -EINVAL; + phy->id = udphy->id; + return 0; } From 1e8370318f89b4a15d5ff9259363e44a852541b2 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Mon, 21 Jul 2025 22:07:11 +0000 Subject: [PATCH 055/103] phy: rockchip: usbdp: Simplify init ops With working shared reference counting for Generic PHY ops there is no need for the Rockchip USBDP PHY driver to keep its own status (reference counting) handling. Simplify the init ops now that shared reference counting is working. This also removes the unused mode_change handling as part of the simplication. No runtime change is expected with this simplication. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- drivers/phy/rockchip/phy-rockchip-usbdp.c | 71 +++-------------------- 1 file changed, 8 insertions(+), 63 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockchip/phy-rockchip-usbdp.c index c88eb0c1611..cca67dd3611 100644 --- a/drivers/phy/rockchip/phy-rockchip-usbdp.c +++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c @@ -96,9 +96,7 @@ struct rockchip_udphy { /* PHY status management */ bool flip; - bool mode_change; u8 mode; - u8 status; /* utilized for USB */ bool hs; /* flag for high-speed */ @@ -525,65 +523,6 @@ static int udphy_parse_dt(struct rockchip_udphy *udphy, struct udevice *dev) return 0; } -static int udphy_power_on(struct rockchip_udphy *udphy, u8 mode) -{ - int ret; - - if (!(udphy->mode & mode)) { - dev_info(udphy->dev, "mode 0x%02x is not support\n", mode); - return 0; - } - - if (udphy->status == UDPHY_MODE_NONE) { - udphy->mode_change = false; - ret = udphy_setup(udphy); - if (ret) - return ret; - - if (udphy->mode & UDPHY_MODE_USB) - udphy_u3_port_disable(udphy, false); - } else if (udphy->mode_change) { - udphy->mode_change = false; - udphy->status = UDPHY_MODE_NONE; - if (udphy->mode == UDPHY_MODE_DP) - udphy_u3_port_disable(udphy, true); - - ret = udphy_disable(udphy); - if (ret) - return ret; - ret = udphy_setup(udphy); - if (ret) - return ret; - } - - udphy->status |= mode; - - return 0; -} - -static int udphy_power_off(struct rockchip_udphy *udphy, u8 mode) -{ - int ret; - - if (!(udphy->mode & mode)) { - dev_info(udphy->dev, "mode 0x%02x is not supported\n", mode); - return 0; - } - - if (!udphy->status) - return 0; - - udphy->status &= ~mode; - - if (udphy->status == UDPHY_MODE_NONE) { - ret = udphy_disable(udphy); - if (ret) - return ret; - } - - return 0; -} - static int rockchip_u3phy_of_xlate(struct phy *phy, struct ofnode_phandle_args *args) { @@ -603,6 +542,7 @@ static int rockchip_u3phy_of_xlate(struct phy *phy, static int rockchip_u3phy_init(struct phy *phy) { struct rockchip_udphy *udphy = dev_get_priv(phy->dev); + int ret; /* DP only or high-speed, disable U3 port */ if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) { @@ -610,7 +550,12 @@ static int rockchip_u3phy_init(struct phy *phy) return 0; } - return udphy_power_on(udphy, UDPHY_MODE_USB); + ret = udphy_setup(udphy); + if (ret) + return ret; + + udphy_u3_port_disable(udphy, false); + return 0; } static int rockchip_u3phy_exit(struct phy *phy) @@ -621,7 +566,7 @@ static int rockchip_u3phy_exit(struct phy *phy) if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) return 0; - return udphy_power_off(udphy, UDPHY_MODE_USB); + return udphy_disable(udphy); } static const struct phy_ops rockchip_u3phy_ops = { From dfd2774cfc4434ef35b48febcd1dc1860a3dc8f8 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Mon, 21 Jul 2025 22:07:12 +0000 Subject: [PATCH 056/103] phy: rockchip: naneng-combphy: Fix Generic PHY reference counting Generic PHY reference counting helps ensure driver ops for init/exit and power on/off are called at correct state. For this to work the PHY driver must initialize PHY-id to a persistent value in of_xlate ops. The Rockchip COMBPHY driver does not initialize the PHY-id field, this typically lead to use of unshared reference counting among different struct phy instances. Initialize the PHY-id in of_xlate ops to ensure use of shared reference counting among all struct phy instances. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c index 6d8d10750b1..a66be0608d4 100644 --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c @@ -224,6 +224,7 @@ static int rockchip_combphy_xlate(struct phy *phy, struct ofnode_phandle_args *a return -EINVAL; } + phy->id = priv->id; priv->mode = args->args[0]; return 0; From 8a3d377d4ccd409b56b9a6eef20613472e4471fd Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Mon, 21 Jul 2025 22:07:13 +0000 Subject: [PATCH 057/103] phy: rockchip: naneng-combphy: Simplify init ops The init ops for Rockchip COMBPHY driver is more complex than it needs to be, e.g. declaring multiple init functions that only differ in the error message. Simplify the init ops based on code from the Linux mainline driver. This change also ensure that errors returned from combphy_cfg() and reset_deassert_bulk() is propertly propagated to the caller. No other runtime change is expected with this simplication. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- .../rockchip/phy-rockchip-naneng-combphy.c | 111 ++++-------------- 1 file changed, 24 insertions(+), 87 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c index a66be0608d4..9345378aa50 100644 --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c @@ -99,89 +99,6 @@ static int param_write(struct regmap *base, return regmap_write(base, reg->offset, val); } -static int rockchip_combphy_pcie_init(struct rockchip_combphy_priv *priv) -{ - int ret = 0; - - if (priv->cfg->combphy_cfg) { - ret = priv->cfg->combphy_cfg(priv); - if (ret) { - dev_err(priv->dev, "failed to init phy for pcie\n"); - return ret; - } - } - - return ret; -} - -static int rockchip_combphy_usb3_init(struct rockchip_combphy_priv *priv) -{ - int ret = 0; - - if (priv->cfg->combphy_cfg) { - ret = priv->cfg->combphy_cfg(priv); - if (ret) { - dev_err(priv->dev, "failed to init phy for usb3\n"); - return ret; - } - } - - return ret; -} - -static int rockchip_combphy_sata_init(struct rockchip_combphy_priv *priv) -{ - int ret = 0; - - if (priv->cfg->combphy_cfg) { - ret = priv->cfg->combphy_cfg(priv); - if (ret) { - dev_err(priv->dev, "failed to init phy for sata\n"); - return ret; - } - } - - return ret; -} - -static int rockchip_combphy_sgmii_init(struct rockchip_combphy_priv *priv) -{ - int ret = 0; - - if (priv->cfg->combphy_cfg) { - ret = priv->cfg->combphy_cfg(priv); - if (ret) { - dev_err(priv->dev, "failed to init phy for sgmii\n"); - return ret; - } - } - - return ret; -} - -static int rockchip_combphy_set_mode(struct rockchip_combphy_priv *priv) -{ - switch (priv->mode) { - case PHY_TYPE_PCIE: - rockchip_combphy_pcie_init(priv); - break; - case PHY_TYPE_USB3: - rockchip_combphy_usb3_init(priv); - break; - case PHY_TYPE_SATA: - rockchip_combphy_sata_init(priv); - break; - case PHY_TYPE_SGMII: - case PHY_TYPE_QSGMII: - return rockchip_combphy_sgmii_init(priv); - default: - dev_err(priv->dev, "incompatible PHY type\n"); - return -EINVAL; - } - - return 0; -} - static int rockchip_combphy_init(struct phy *phy) { struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev); @@ -191,12 +108,32 @@ static int rockchip_combphy_init(struct phy *phy) if (ret < 0 && ret != -ENOSYS) return ret; - ret = rockchip_combphy_set_mode(priv); + switch (priv->mode) { + case PHY_TYPE_PCIE: + case PHY_TYPE_USB3: + case PHY_TYPE_SATA: + case PHY_TYPE_SGMII: + case PHY_TYPE_QSGMII: + if (priv->cfg->combphy_cfg) + ret = priv->cfg->combphy_cfg(priv); + else + ret = 0; + break; + default: + dev_err(priv->dev, "incompatible PHY type\n"); + ret = -EINVAL; + break; + } + + if (ret) { + dev_err(priv->dev, "failed to init phy for phy type %x\n", priv->mode); + goto err_clk; + } + + ret = reset_deassert_bulk(&priv->phy_rsts); if (ret) goto err_clk; - reset_deassert_bulk(&priv->phy_rsts); - return 0; err_clk: @@ -306,7 +243,7 @@ static int rockchip_combphy_probe(struct udevice *udev) } priv->dev = udev; - priv->mode = PHY_TYPE_SATA; + priv->mode = PHY_NONE; priv->cfg = phy_cfg; return rockchip_combphy_parse_dt(udev, priv); From 12dd645914a4e5e65d92a4754d0dacbdbf1e4a55 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Mon, 21 Jul 2025 22:07:14 +0000 Subject: [PATCH 058/103] phy: rockchip: naneng-combphy: Use syscon_regmap_lookup_by_phandle Change to use syscon_regmap_lookup_by_phandle() helper instead of finding the syscon udevice and making a call to syscon_get_regmap(). No runtime change is expected with this simplication. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- .../phy/rockchip/phy-rockchip-naneng-combphy.c | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c index 9345378aa50..d602f965d6a 100644 --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c @@ -176,22 +176,19 @@ static const struct phy_ops rockchip_combphy_ops = { static int rockchip_combphy_parse_dt(struct udevice *dev, struct rockchip_combphy_priv *priv) { - struct udevice *syscon; int ret; - ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pipe-grf", &syscon); - if (ret) { - dev_err(dev, "failed to find peri_ctrl pipe-grf regmap"); - return ret; + priv->pipe_grf = syscon_regmap_lookup_by_phandle(dev, "rockchip,pipe-grf"); + if (IS_ERR(priv->pipe_grf)) { + dev_err(dev, "failed to find peri_ctrl pipe-grf regmap\n"); + return PTR_ERR(priv->pipe_grf); } - priv->pipe_grf = syscon_get_regmap(syscon); - ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pipe-phy-grf", &syscon); - if (ret) { + priv->phy_grf = syscon_regmap_lookup_by_phandle(dev, "rockchip,pipe-phy-grf"); + if (IS_ERR(priv->phy_grf)) { dev_err(dev, "failed to find peri_ctrl pipe-phy-grf regmap\n"); - return ret; + return PTR_ERR(priv->phy_grf); } - priv->phy_grf = syscon_get_regmap(syscon); ret = clk_get_by_index(dev, 0, &priv->ref_clk); if (ret) { From c8e6a7131d58511129cdec16f269600b51f0a45a Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Mon, 21 Jul 2025 22:07:15 +0000 Subject: [PATCH 059/103] phy: rockchip: inno-usb2: Fix improper use of UCLASS_PHY The Rockchip USB2PHY glue driver improperly present itself as a UCLASS_PHY driver, without ever implementing the required phy_ops. This is something that in special circumstances can lead to a NULL pointer dereference followed by a SError crash. Change the glue driver to use UCLASS_NOP to fix this. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c index 03fe1b38175..4ea6600ce7f 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c @@ -573,7 +573,7 @@ U_BOOT_DRIVER(rockchip_usb2phy_clock) = { U_BOOT_DRIVER(rockchip_usb2phy) = { .name = "rockchip_usb2phy", - .id = UCLASS_PHY, + .id = UCLASS_NOP, .of_match = rockchip_usb2phy_ids, .probe = rockchip_usb2phy_probe, .bind = rockchip_usb2phy_bind, From fca01a8792e6ed48a00e08124d55f4f74e47b11d Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Mon, 21 Jul 2025 22:07:16 +0000 Subject: [PATCH 060/103] phy: rockchip: typec: Fix improper use of UCLASS_PHY The Rockchip TypeC glue driver improperly present itself as a UCLASS_PHY driver, without ever implementing the required phy_ops. This is something that in special circumstances can lead to a NULL pointer dereference followed by a SError crash. Change the glue driver to use UCLASS_NOP to fix this. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- drivers/phy/rockchip/phy-rockchip-typec.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/phy/rockchip/phy-rockchip-typec.c b/drivers/phy/rockchip/phy-rockchip-typec.c index c48a5cd5267..66d1d32d25c 100644 --- a/drivers/phy/rockchip/phy-rockchip-typec.c +++ b/drivers/phy/rockchip/phy-rockchip-typec.c @@ -788,7 +788,7 @@ U_BOOT_DRIVER(rockchip_tcphy_usb3_port) = { U_BOOT_DRIVER(rockchip_typec_phy) = { .name = "rockchip_typec_phy", - .id = UCLASS_PHY, + .id = UCLASS_NOP, .of_match = rockchip_typec_phy_ids, .probe = rockchip_tcphy_probe, .bind = rockchip_tcphy_bind, From 9d39a56922878562b263e45f45523021cf5e7789 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Mon, 21 Jul 2025 22:07:17 +0000 Subject: [PATCH 061/103] rockchip: rk3588: Disable USB3OTG U3 ports early The RK3588 SoC comes with USB OTG support using a DWC3 controller with a USB2 PHY and a USB3 PHY (USBDP PHY). Some board designs may not use the USBDP PHY for USB3 purpose. For these board to use USB OTG the input clock source must change to use UTMI clk instead of PIPE clk. Change to always disable the USB3OTG U3 ports early and leave it to the USBDP PHY driver to re-enable the U3 port when a usb3-phy is described in the board device tree. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/rk3588/rk3588.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c b/arch/arm/mach-rockchip/rk3588/rk3588.c index e2278ff792b..c01a4002089 100644 --- a/arch/arm/mach-rockchip/rk3588/rk3588.c +++ b/arch/arm/mach-rockchip/rk3588/rk3588.c @@ -15,6 +15,10 @@ #include #include +#define USB_GRF_BASE 0xfd5ac000 +#define USB3OTG0_CON1 0x001c +#define USB3OTG1_CON1 0x0034 + #define FIREWALL_DDR_BASE 0xfe030000 #define FW_DDR_MST5_REG 0x54 #define FW_DDR_MST13_REG 0x74 @@ -184,6 +188,10 @@ int arch_cpu_init(void) /* Disable JTAG exposed on SDMMC */ rk_clrreg(&sys_grf->soc_con[6], SYS_GRF_FORCE_JTAG); #endif + + /* Disable USB3OTG U3 ports, later enabled by USBDP PHY driver */ + writel(0xffff0188, USB_GRF_BASE + USB3OTG0_CON1); + writel(0xffff0188, USB_GRF_BASE + USB3OTG1_CON1); #endif return 0; From be585d4916864387c53c82b4bde7f04093aac440 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Mon, 21 Jul 2025 22:07:18 +0000 Subject: [PATCH 062/103] rockchip: rk3576: Disable USB3OTG0 U3 port early The RK3576 SoC comes with USB OTG support using a DWC3 controller with a USB2 PHY and a USB3 PHY (USBDP PHY). Some board designs may not use the USBDP PHY for USB3 purpose. For these board to use USB OTG the input clock source must change to use UTMI clk instead of PIPE clk. Change to always disable the USB3OTG0 U3 port early and leave it to the USBDP PHY driver to re-enable the U3 port when a usb3-phy is described in the board device tree. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/rk3576/rk3576.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/mach-rockchip/rk3576/rk3576.c b/arch/arm/mach-rockchip/rk3576/rk3576.c index 2b1318f9532..a6c2fbdc484 100644 --- a/arch/arm/mach-rockchip/rk3576/rk3576.c +++ b/arch/arm/mach-rockchip/rk3576/rk3576.c @@ -33,6 +33,9 @@ #define SGRF_DOMAIN_CON4 0x10 #define SGRF_DOMAIN_CON5 0x14 +#define USB_GRF_BASE 0x2601E000 +#define USB3OTG0_CON1 0x0030 + const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { [BROM_BOOTSOURCE_EMMC] = "/soc/mmc@2a330000", [BROM_BOOTSOURCE_SD] = "/soc/mmc@2a310000", @@ -155,6 +158,9 @@ int arch_cpu_init(void) */ writel(0xffffff00, SYS_SGRF_BASE + SYS_SGRF_SOC_CON20); + /* Disable USB3OTG0 U3 port, later enabled by USBDP PHY driver */ + writel(0xffff0188, USB_GRF_BASE + USB3OTG0_CON1); + return 0; } From 0e68a93d7c220e37cf6ffe88ba47373e39fe5001 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Mon, 21 Jul 2025 22:07:19 +0000 Subject: [PATCH 063/103] rockchip: rk3588-generic: Move usb nodes to board dts After the commit 7a53abb18325 ("rockchip: rk3588: Remove USB3 DRD nodes in u-boot.dtsi") was merged for v2024.10 there is no reason to keep the usb nodes for the Generic RK3588 board in the board u-boot.dtsi. Move usb related nodes from board u-boot.dtsi to main board device tree. While at it, also drop use of the usb3-phy as we only want to enable the usb2-phy to be compatible with as many boards as possible. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rk3588-generic-u-boot.dtsi | 18 ------------------ arch/arm/dts/rk3588-generic.dts | 16 ++++++++++++++++ configs/generic-rk3588_defconfig | 1 - 3 files changed, 16 insertions(+), 19 deletions(-) diff --git a/arch/arm/dts/rk3588-generic-u-boot.dtsi b/arch/arm/dts/rk3588-generic-u-boot.dtsi index f67301d87a6..853ed58cfe5 100644 --- a/arch/arm/dts/rk3588-generic-u-boot.dtsi +++ b/arch/arm/dts/rk3588-generic-u-boot.dtsi @@ -1,21 +1,3 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) #include "rk3588s-u-boot.dtsi" - -&u2phy0 { - status = "okay"; -}; - -&u2phy0_otg { - status = "okay"; -}; - -&usbdp_phy0 { - status = "okay"; -}; - -&usb_host0_xhci { - dr_mode = "peripheral"; - maximum-speed = "high-speed"; - status = "okay"; -}; diff --git a/arch/arm/dts/rk3588-generic.dts b/arch/arm/dts/rk3588-generic.dts index 95d757676f1..6740f9866f1 100644 --- a/arch/arm/dts/rk3588-generic.dts +++ b/arch/arm/dts/rk3588-generic.dts @@ -39,7 +39,23 @@ status = "okay"; }; +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + &uart2 { pinctrl-0 = <&uart2m0_xfer>; status = "okay"; }; + +&usb_host0_xhci { + dr_mode = "peripheral"; + maximum-speed = "high-speed"; + phys = <&u2phy0_otg>; + phy-names = "usb2-phy"; + status = "okay"; +}; diff --git a/configs/generic-rk3588_defconfig b/configs/generic-rk3588_defconfig index ed2f936b324..dfa8efabe6b 100644 --- a/configs/generic-rk3588_defconfig +++ b/configs/generic-rk3588_defconfig @@ -53,7 +53,6 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y -CONFIG_PHY_ROCKCHIP_USBDP=y CONFIG_SPL_PINCTRL=y CONFIG_SPL_RAM=y CONFIG_BAUDRATE=1500000 From c04fb8b505658af98b7a7b9a22647a29d8fbceb0 Mon Sep 17 00:00:00 2001 From: Andrew Goodbody Date: Mon, 11 Aug 2025 13:05:15 +0100 Subject: [PATCH 064/103] efi: serial: Use correct EFI status type int is not sufficient to hold and test the return from an EFI function call. Use efi_status_t instead so that the test can work as expected. This issue was found by Smatch. Fixes: 275854baeeec ("efi: Add a serial driver") Signed-off-by: Andrew Goodbody Reviewed-by: Heinrich Schuchardt --- drivers/serial/serial_efi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/serial/serial_efi.c b/drivers/serial/serial_efi.c index 5733eaaf9d4..d3cd4de34a2 100644 --- a/drivers/serial/serial_efi.c +++ b/drivers/serial/serial_efi.c @@ -33,7 +33,7 @@ int serial_efi_setbrg(struct udevice *dev, int baudrate) static int serial_efi_get_key(struct serial_efi_priv *priv) { - int ret; + efi_status_t ret; if (priv->have_key) return 0; From 4910a7cc696ffa3a36e23a215523d1ff31a5c8a1 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 12 Aug 2025 12:01:32 -0600 Subject: [PATCH 065/103] efi_loader: Make EFI_VARIABLES_PRESEED depend on !COMPILE_TEST When doing compile testing build we cannot rely on having a valid file for EFI_VAR_SEED_FILE to exist, so disable this option when doing compile tests. Signed-off-by: Tom Rini Reviewed-by: Ilias Apalodimas Acked-by: Heinrich Schuchardt --- lib/efi_loader/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig index c2aa88f59fb..a7092c2e8a8 100644 --- a/lib/efi_loader/Kconfig +++ b/lib/efi_loader/Kconfig @@ -195,6 +195,7 @@ endchoice config EFI_VARIABLES_PRESEED bool "Initial values for UEFI variables" + depends on !COMPILE_TEST depends on !EFI_MM_COMM_TEE help Include a file with the initial values for non-volatile UEFI variables From 6deac6147bdba45e4bb74b608e301cb18a708b79 Mon Sep 17 00:00:00 2001 From: Jan Kiszka Date: Tue, 19 Aug 2025 16:33:52 +0200 Subject: [PATCH 066/103] efi: Select also CMD_DHCP from EFI_HTTP_BOOT This is needed because distro_efi_read_bootflow_net will then need dhcp_run which is not already enabled by CMD_NET. Signed-off-by: Jan Kiszka Reviewed-by: Heinrich Schuchardt --- lib/efi_loader/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig index a7092c2e8a8..900113ca3e9 100644 --- a/lib/efi_loader/Kconfig +++ b/lib/efi_loader/Kconfig @@ -565,6 +565,7 @@ config EFI_HTTP_BOOT bool "EFI HTTP Boot support" depends on NET || NET_LWIP select CMD_NET + select CMD_DHCP select CMD_DNS select CMD_WGET select BLKMAP From 6a006c56ee80ed0ad3fc8a35d96f1a184fbed53e Mon Sep 17 00:00:00 2001 From: Adriano Carvalho Date: Mon, 25 Aug 2025 23:32:28 +0100 Subject: [PATCH 067/103] doc: Fix obvious typos and minor improvements These are fixes to what looks like obvious typos. Some minor improvments are also included, such as: - Write "symbolic link" instead of symlink - Correct capitalization for LLVM (all caps) - Remove dead link and surrounding sentence Signed-off-by: Adriano Carvalho --- doc/build/clang.rst | 8 +++--- doc/build/gen_compile_commands.rst | 2 +- doc/build/tools.rst | 9 +++---- tools/buildman/buildman.rst | 41 +++++++++++++++--------------- 4 files changed, 29 insertions(+), 31 deletions(-) diff --git a/doc/build/clang.rst b/doc/build/clang.rst index 09bb988e923..a83ecb4fdc6 100644 --- a/doc/build/clang.rst +++ b/doc/build/clang.rst @@ -46,9 +46,9 @@ It can also be used to compile sandbox: FreeBSD 11 ---------- -Since llvm 3.4 is currently in the base system, the integrated assembler as -is incapable of building U-Boot. Therefore gas from devel/arm-gnueabi-binutils -is used instead. It needs a symlink to be picked up correctly though: +Since LLVM 3.4 is currently in the base system, the integrated assembler is +incapable of building U-Boot. Therefore gas from devel/arm-gnueabi-binutils is +used instead. It needs a symbolic link to be picked up correctly though: .. code-block:: bash @@ -64,7 +64,7 @@ The following commands compile U-Boot using the Clang xdev toolchain. gmake rpi_2_defconfig gmake CC="clang -target arm-freebsd-eabi --sysroot /usr/arm-freebsd" -j8 -Given that U-Boot will default to gcc, above commands can be +Given that U-Boot will default to gcc, the commands above can be simplified with a simple wrapper script - saved as /usr/local/bin/arm-gnueabi-freebsd-gcc - listed below: diff --git a/doc/build/gen_compile_commands.rst b/doc/build/gen_compile_commands.rst index d503764f9e3..5eb9e4ccb0a 100644 --- a/doc/build/gen_compile_commands.rst +++ b/doc/build/gen_compile_commands.rst @@ -39,7 +39,7 @@ course) to have an up-to-date database. The database will be in the root of the repository. No further modifications are needed for it to be usable by the LSP, unless you set a name for the database -other than it's default one (compile_commands.json). +other than the default one (compile_commands.json). Compatible IDEs --------------- diff --git a/doc/build/tools.rst b/doc/build/tools.rst index 5bfa05b2325..1cc8eb93230 100644 --- a/doc/build/tools.rst +++ b/doc/build/tools.rst @@ -8,7 +8,7 @@ Building tools for Linux ------------------------ To allow distributions to distribute all possible tools in a generic way, -avoiding the need of specific tools building for each machine, a tools only +avoiding the need of specific building tools for each machine, a tools-only defconfig file is provided. Using this, we can build the tools by doing:: @@ -30,9 +30,8 @@ installed all required packages below in order to build these host tools:: * diffutils (3.7) * openssl-devel (1.1.1.d) -Note the version numbers in these parentheses above are the package versions -at the time being when writing this document. The MSYS2 installer tested is -http://repo.msys2.org/distrib/x86_64/msys2-x86_64-20190524.exe. +Note that the version numbers in parentheses above are the package versions at +the time of writing this document. There are 3 MSYS subsystems installed: MSYS2, MinGW32 and MinGW64. Each subsystem provides an environment to build Windows applications. The MSYS2 @@ -50,7 +49,7 @@ Launch the MSYS2 shell of the MSYS2 environment, and do the following:: Building without Python ----------------------- -The tools-only builds bytes pylibfdt by default. To disable this, use the +The tools-only builds pylibfdt by default. To disable this, use the NO_PYTHON variable:: NO_PYTHON=1 make tools-only_defconfig tools-only diff --git a/tools/buildman/buildman.rst b/tools/buildman/buildman.rst index 8c45a841024..a30cd645bc0 100644 --- a/tools/buildman/buildman.rst +++ b/tools/buildman/buildman.rst @@ -22,10 +22,10 @@ example Raspberry Pi 2): What is this? ------------- -This tool handles building U-Boot to check that you have not broken it -with your patch series. It can build each individual commit and report -which boards fail on which commits, and which errors come up. It aims -to make full use of multi-processor machines. +This tool builds U-Boot to check that you have not broken it with your +patch series. It can build each individual commit and report which boards +fail on which commits, and which errors come up. It aims to make full use +of multi-processor machines. A key feature of buildman is its output summary, which allows warnings, errors or image size increases in a particular commit or board to be @@ -83,7 +83,7 @@ incremental build (i.e. not using 'make xxx_defconfig' unless you use -C). Eventually the thread reaches the last commit and stops. If a commit causes an error or warning, buildman will try it again after reconfiguring (but see -Q). Thus some commits may be built twice, with the first result silently -discarded. Lots of errors and warnings will causes lots of reconfigures and your +discarded. Lots of errors and warnings will cause lots of reconfigures and your build will be very slow. This is because a file that produces just a warning would not normally be rebuilt in an incremental build. Once a thread finishes building all the commits for a board, it starts on the commits for another @@ -154,7 +154,7 @@ means to build all arm boards except nvidia, freescale and anything ending with 'ball'. For building specific boards you can use the --boards (or --bo) option, which -takes a comma-separated list of board target names and be used multiple times +takes a comma-separated list of board target names and can be used multiple times on the command line: .. code-block:: bash @@ -212,7 +212,7 @@ Setting up The toolchain-alias section indicates that the i386 toolchain should be used to build x86 commits. - Note that you can also specific exactly toolchain prefixes if you like:: + Note that you can also specify toolchain prefixes if you like:: [toolchain-prefix] arm: /opt/arm-eabi-4.6/bin/arm-eabi- @@ -243,9 +243,9 @@ Setting up This tells buildman to use a compiler wrapper in front of CROSS_COMPILE. In this example, ccache. It doesn't affect the toolchain scan. The wrapper is - added when CROSS_COMPILE environtal variable is set. The name in this - section is ignored. If more than one line is provided, only the last one - is taken. + added when the CROSS_COMPILE environment variable is set. The tag name in + this section is not important. If more than one line is provided, only the + last one is used. #. Make sure you have the required Python pre-requisites @@ -484,7 +484,7 @@ Setting up How to run it ------------- -First do a dry run using the -n flag: (replace with a real, local +First do a dry run using the -n flag (replace with a real, local branch with a valid upstream): .. code-block:: bash @@ -898,7 +898,7 @@ The .buildman settings file The .buildman file provides information about the available toolchains and also allows build flags to be passed to 'make'. It consists of several -sections, with the section name in square brackets. Within each section are +sections, with the section name in square brackets. Within each section there are a set of (tag, value) pairs. '[global]' section @@ -939,8 +939,7 @@ a set of (tag, value) pairs. '[toolchain-prefix]' section This can be used to provide the full toolchain-prefix for one or more architectures. The full CROSS_COMPILE prefix must be provided. These - typically have a higher priority than matches in the '[toolchain]', due to - this prefix. + typically have a higher priority than matches in the '[toolchain]'. The tilde character ``~`` is supported in paths, to represent the home directory. @@ -1062,7 +1061,7 @@ For example:: + u-boot.cfg: CONFIG_SPL_ENV_SUPPORT=1 CONFIG_SPL_NET=1 + u-boot-spl.cfg: CONFIG_SPL_MMC=1 CONFIG_SPL_NAND_SUPPORT=1 + all: CONFIG_SPL_ENV_SUPPORT=1 CONFIG_SPL_MMC=1 CONFIG_SPL_NAND_SUPPORT=1 CONFIG_SPL_NET=1 - am335x_evm_usbspl : + am335x_evm_usbspl: + u-boot.cfg: CONFIG_SPL_ENV_SUPPORT=1 CONFIG_SPL_NET=1 + u-boot-spl.cfg: CONFIG_SPL_MMC=1 CONFIG_SPL_NAND_SUPPORT=1 + all: CONFIG_SPL_ENV_SUPPORT=1 CONFIG_SPL_MMC=1 CONFIG_SPL_NAND_SUPPORT=1 CONFIG_SPL_NET=1 @@ -1073,15 +1072,15 @@ This shows that commit 44 enabled three new options for the board am335x_evm_usbspl which were not enabled in commit 43. There is also a summary for 'arm' showing all the changes detected for that architecture. In this case there is only one board with changes, so 'arm' output is the -same as 'am335x_evm_usbspl'/ +same as 'am335x_evm_usbspl'. The -K option uses the u-boot.cfg, spl/u-boot-spl.cfg and tpl/u-boot-tpl.cfg files which are produced by a build. If all you want is to check the configuration you can in fact avoid doing a full build, using --config-only. -This tells buildman to configuration U-Boot and create the .cfg files, but not +This tells buildman to configure U-Boot and create the .cfg files, but not actually build the source. This is 5-10 times faster than doing a full build. -By default buildman considers the follow two configuration methods +By default buildman considers the following two configuration methods equivalent:: #define CONFIG_SOME_OPTION @@ -1089,7 +1088,7 @@ equivalent:: CONFIG_SOME_OPTION=y The former would appear in a header filer and the latter in a defconfig -file. The achieve this, buildman considers 'y' to be '1' in configuration +file. To achieve this, buildman considers 'y' to be '1' in configuration variables. This avoids lots of useless output when converting a CONFIG option to Kconfig. To disable this behaviour, use --squash-config-y. @@ -1364,7 +1363,7 @@ regeneration of the file - in that case buildman exits after writing the file with exit code 2 if there was an error in the maintainer files. To use the default filename, use a hyphen, i.e. `-R -`. -You should use 'buildman -nv ' instead of greoing the boards.cfg file, +You should use 'buildman -nv ' instead of greping the boards.cfg file, since it may be dropped altogether in future. @@ -1378,7 +1377,7 @@ Use the `--maintainer-check` option to check this:: WARNING: board/mikrotik/crs3xx-98dx3236/MAINTAINERS: missing defconfig ending at line 7 WARNING: no maintainers for 'clearfog_spi' -Buildman returns with an exit code of 2 if there area any warnings. +Buildman returns with an exit code of 2 if there are any warnings. An experimental `--full-check option` also checks for boards which don't have a CONFIG_TARGET_xxx where xxx corresponds to their defconfig filename. This is From 45d32d2911b8b854abfd56ca6691bf5d47825656 Mon Sep 17 00:00:00 2001 From: Adriano Carvalho Date: Mon, 25 Aug 2025 23:32:29 +0100 Subject: [PATCH 068/103] doc: Quote all long form options using double backticks/grave accents Otherwise, the two dashes are rendered as just one. Signed-off-by: Adriano Carvalho --- tools/buildman/buildman.rst | 50 ++++++++++++++++++------------------- 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/tools/buildman/buildman.rst b/tools/buildman/buildman.rst index a30cd645bc0..3b51b9ed2b3 100644 --- a/tools/buildman/buildman.rst +++ b/tools/buildman/buildman.rst @@ -100,8 +100,8 @@ threads do not affect the state of your git repository. Any checkouts done by the thread affect only the working directory for that thread. Buildman automatically selects the correct tool chain for each board. You -must supply suitable tool chains (see --fetch-arch), but buildman takes care -of selecting the right one. +must supply suitable tool chains (see ``--fetch-arch``), but buildman takes +care of selecting the right one. Buildman generally builds a branch (with the -b flag), and in this case builds the upstream commit as well, for comparison. So even if you have one @@ -153,9 +153,9 @@ You can also use -x to specifically exclude some boards. For example: means to build all arm boards except nvidia, freescale and anything ending with 'ball'. -For building specific boards you can use the --boards (or --bo) option, which -takes a comma-separated list of board target names and can be used multiple times -on the command line: +For building specific boards you can use the ``--boards`` (or ``--bo``) option, +which takes a comma-separated list of board target names and can be used +multiple times on the command line: .. code-block:: bash @@ -492,7 +492,7 @@ branch with a valid upstream): ./tools/buildman/buildman -b -n If it can't detect the upstream branch, try checking out the branch, and -doing something like 'git branch --set-upstream-to upstream/master' +doing something like ``git branch --set-upstream-to upstream/master`` or something similar. Buildman will try to guess a suitable upstream branch if it can't find one (you will see a message like "Guessing upstream as ..."). You can also use the -c option to manually specify the number of commits to @@ -731,17 +731,17 @@ Note that the 'text' region and 'rodata' are split out. You should add the two together to get the total read-only size (reported as the first column in the output from binutil's 'size' utility). -A useful option is --step which lets you skip some commits. For example ---step 2 will show the image sizes for only every 2nd commit (so it will +A useful option is ``--step`` which lets you skip some commits. For example +``--step 2`` will show the image sizes for only every 2nd commit (so it will compare the image sizes of the 1st, 3rd, 5th... commits). You can also use ---step 0 which will compare only the first and last commits. This is useful +``--step 0`` which will compare only the first and last commits. This is useful for an overview of how your entire series affects code size. It will build only the upstream commit and your final branch commit. You can also use -d to see a detailed size breakdown for each board. This list is sorted in order from largest growth to largest reduction. -It is even possible to go a little further with the -B option (--bloat). This +It is even possible to go a little further with the -B option (``--bloat``). This shows where U-Boot has bloated, breaking the size change down to the function level. Example output is below:: @@ -924,7 +924,7 @@ a set of (tag, value) pairs. This lists the available toolchains. The tag here doesn't matter, but make sure it is unique. The value is the path to the toolchain. Buildman will look in that path for a file ending in 'gcc'. It will then execute - it to check that it is a C compiler, passing only the --version flag to + it to check that it is a C compiler, passing only the ``--version`` flag to it. If the return code is 0, buildman assumes that it is a valid C compiler. It uses the first part of the name as the architecture and strips off the last part when setting the CROSS_COMPILE environment @@ -1005,7 +1005,7 @@ By default, buildman doesn't execute 'make mrproper' prior to building the first commit for each board. This reduces the amount of work 'make' does, and hence speeds up the build. To force use of 'make mrproper', use -the -m flag. This flag will slow down any buildman invocation, since it increases the amount -of work done on any build. An alternative is to use the --fallback-mrproper +of work done on any build. An alternative is to use the ``--fallback-mrproper`` flag, which retries the build with 'make mrproper' only after a build failure. One possible application of buildman is as part of a continual edit, build, @@ -1040,7 +1040,7 @@ of the source tree, thus allowing rapid tested evolution of the code:: ./tools/buildman/buildman -Pr tegra -Note also the `--dtc-skip` option which uses the system device-tree compiler to +Note also the ``--dtc-skip`` option which uses the system device-tree compiler to avoid needing to build it for each board. This can save 10-20% of build time. An alternative is to set DTC=/path/to/dtc when running buildman. @@ -1076,7 +1076,7 @@ same as 'am335x_evm_usbspl'. The -K option uses the u-boot.cfg, spl/u-boot-spl.cfg and tpl/u-boot-tpl.cfg files which are produced by a build. If all you want is to check the -configuration you can in fact avoid doing a full build, using --config-only. +configuration you can in fact avoid doing a full build, using ``--config-only``. This tells buildman to configure U-Boot and create the .cfg files, but not actually build the source. This is 5-10 times faster than doing a full build. @@ -1090,7 +1090,7 @@ equivalent:: The former would appear in a header filer and the latter in a defconfig file. To achieve this, buildman considers 'y' to be '1' in configuration variables. This avoids lots of useless output when converting a CONFIG -option to Kconfig. To disable this behaviour, use --squash-config-y. +option to Kconfig. To disable this behaviour, use ``--squash-config-y``. Checking the environment @@ -1165,7 +1165,7 @@ Link-time optimisation (LTO) is designed to reduce code size by globally optimising the U-Boot build. Unfortunately this can dramatically slow down builds. This is particularly noticeable when running a lot of builds. -Use the -L (--no-lto) flag to disable LTO. +Use the -L (``--no-lto``) flag to disable LTO. .. code-block:: bash @@ -1195,7 +1195,7 @@ each error line. Also, buildman prints information about what it is about to do, along with a summary at the end. When using buildman from an IDE, it is helpful to drop this behaviour. Use the --I/--ide option for that. You might find -W helpful also so that warnings do +``-I/--ide`` option for that. You might also find -W helpful so that warnings do not cause the build to fail: .. code-block:: bash @@ -1287,7 +1287,7 @@ rebuild. You can use -f to work around that. Other options ------------- -Buildman has various other command-line options. Try --help to see them. +Buildman has various other command-line options. Try ``--help`` to see them. To find out what toolchain prefix buildman will use for a build, use the -A option. @@ -1325,11 +1325,11 @@ figure out the root cause of the build failure. For situations where buildman is invoked from multiple running processes, it is sometimes useful to have buildman wait until the others have finished. Use the ---process-limit option for this: --process-limit 1 will allow only one buildman -to process jobs at a time. +``--process-limit`` option for this: ``--process-limit 1`` will allow only one +buildman to process jobs at a time. To build a particular target, rather than the default U-Boot target, use the -`--target` option. This is unlikely to be useful unless you are building a +``--target`` option. This is unlikely to be useful unless you are building a single board. Buildman normally builds out-of-tree, meaning that the source directory is not @@ -1358,7 +1358,7 @@ Using boards.cfg This file is no-longer needed by buildman but it is still generated in the working directory. This helps avoid a delay on every build, since scanning all -the Kconfig files takes a few seconds. Use the `-R ` flag to force +the Kconfig files takes a few seconds. Use the ``-R `` flag to force regeneration of the file - in that case buildman exits after writing the file with exit code 2 if there was an error in the maintainer files. To use the default filename, use a hyphen, i.e. `-R -`. @@ -1371,7 +1371,7 @@ Checking maintainers -------------------- Sometimes a board is added without a corresponding entry in a MAINTAINERS file. -Use the `--maintainer-check` option to check this:: +Use the ``--maintainer-check`` option to check this:: $ buildman --maintainer-check WARNING: board/mikrotik/crs3xx-98dx3236/MAINTAINERS: missing defconfig ending at line 7 @@ -1379,8 +1379,8 @@ Use the `--maintainer-check` option to check this:: Buildman returns with an exit code of 2 if there are any warnings. -An experimental `--full-check option` also checks for boards which don't have a -CONFIG_TARGET_xxx where xxx corresponds to their defconfig filename. This is +An experimental ``--full-check option`` also checks for boards which don't have +a CONFIG_TARGET_xxx where xxx corresponds to their defconfig filename. This is not strictly necessary, but may be useful information. From 76733999b04849ae85c5233f59cce9023c0d45b4 Mon Sep 17 00:00:00 2001 From: Adriano Carvalho Date: Mon, 25 Aug 2025 23:32:30 +0100 Subject: [PATCH 069/103] doc: Use "supports" instead of "has" Strictly speaking, "has" doesn't make sense. "supports" seems like a better word and it probably was what the original author meant. Signed-off-by: Adriano Carvalho --- tools/buildman/buildman.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/buildman/buildman.rst b/tools/buildman/buildman.rst index 3b51b9ed2b3..49ac5caeb14 100644 --- a/tools/buildman/buildman.rst +++ b/tools/buildman/buildman.rst @@ -476,7 +476,7 @@ Setting up Buildman should now be set up to use your new toolchain. - At the time of writing, U-Boot has these architectures: + At the time of writing, U-Boot supports these architectures: arc, arm, m68k, microblaze, mips, nios2, powerpc, sandbox, sh, x86, xtensa From b14d24af409470c380ce67abfd6e2b40bc055c2f Mon Sep 17 00:00:00 2001 From: Adriano Carvalho Date: Mon, 25 Aug 2025 23:32:31 +0100 Subject: [PATCH 070/103] doc: Add riscv and unfold the list with the architecture/code name riscv was missing from the list. To some, the architecture's name may not be obvious from the code name. Signed-off-by: Adriano Carvalho --- tools/buildman/buildman.rst | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/tools/buildman/buildman.rst b/tools/buildman/buildman.rst index 49ac5caeb14..368ef5c6f19 100644 --- a/tools/buildman/buildman.rst +++ b/tools/buildman/buildman.rst @@ -478,7 +478,20 @@ Setting up At the time of writing, U-Boot supports these architectures: - arc, arm, m68k, microblaze, mips, nios2, powerpc, sandbox, sh, x86, xtensa + - ARC (arc) + - ARM (arm) + - Motorola 68k (m68k) + - MicroBlaze (microblaze) + - MIPS (mips) + - Nios II (nios2) + - PowerPC (powerpc) + - RISC-V (riscv) + - Sandbox (sandbox) + - SuperH (sh) + - x86 (x86) + - Xtensa (xtensa) + + Each entry list the architecture's name, followed by its code name in U-Boot. How to run it From 77c72bcb0d1b7b3e25761468749eece98232e9f0 Mon Sep 17 00:00:00 2001 From: Adriano Carvalho Date: Mon, 25 Aug 2025 23:32:32 +0100 Subject: [PATCH 071/103] doc: Rephrase in a simpler way It reads a bit nicer. Signed-off-by: Adriano Carvalho --- tools/buildman/buildman.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/buildman/buildman.rst b/tools/buildman/buildman.rst index 368ef5c6f19..a6ae9b0a9d1 100644 --- a/tools/buildman/buildman.rst +++ b/tools/buildman/buildman.rst @@ -1188,7 +1188,7 @@ Use the -L (``--no-lto``) flag to disable LTO. Doing a simple build -------------------- -In some cases you just want to build a single board and get the full output, use +In case you want to build a single board and get the full output, use the -w option, for example: .. code-block:: bash From ac0e3d2541adad8bd8b78bf8f55b970820c0f6a7 Mon Sep 17 00:00:00 2001 From: Adriano Carvalho Date: Mon, 25 Aug 2025 23:32:33 +0100 Subject: [PATCH 072/103] doc: Rephrase to be more clear It might not be clear what is meant with "to make sure the shell leaves it alone". Signed-off-by: Adriano Carvalho --- tools/buildman/buildman.rst | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/tools/buildman/buildman.rst b/tools/buildman/buildman.rst index a6ae9b0a9d1..709fe82f845 100644 --- a/tools/buildman/buildman.rst +++ b/tools/buildman/buildman.rst @@ -1273,8 +1273,9 @@ Some options have values, in which case you can change them: buildman -a 'BOOTCOMMAND="echo hello"' CONFIG_SYS_LOAD_ADDR=0x1000 -Note that you must put quotes around string options and the whole thing must be -in single quotes, to make sure the shell leave it alone. +Note that you must put quotes around string options and the whole argument must +be in single quotes to ensure that the shell recognizes it as a single +argument. If you try to set an option that does not exist, or that cannot be changed for some other reason (e.g. it is 'selected' by another option), then buildman From 01bf38a05ea5e7dbe30a8170dc4fcf82399228d3 Mon Sep 17 00:00:00 2001 From: Adriano Carvalho Date: Mon, 25 Aug 2025 23:32:34 +0100 Subject: [PATCH 073/103] doc: Rephrase to read a bit nicer Reads better. Signed-off-by: Adriano Carvalho --- tools/buildman/buildman.rst | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tools/buildman/buildman.rst b/tools/buildman/buildman.rst index 709fe82f845..dafac017f0e 100644 --- a/tools/buildman/buildman.rst +++ b/tools/buildman/buildman.rst @@ -1294,8 +1294,8 @@ shows an error:: One major caveat with this feature with branches (-b) is that buildman does not name the output directories differently when you change the configuration, so -doing the same build again with different configuration will not trigger a -rebuild. You can use -f to work around that. +doing the same build with a different configuration will not trigger a rebuild. +You can use -f to work around that. Other options @@ -1357,7 +1357,7 @@ directory. Build summary ------------- -When buildman finishes it shows a summary, something like this:: +When Buildman finishes, it displays a summary, similar to the following: Completed: 5 total built, duration 0:00:21, rate 0.24 From 0492657c74f517dae71ed4864ef10bb05e22a2d4 Mon Sep 17 00:00:00 2001 From: Adriano Carvalho Date: Mon, 25 Aug 2025 23:32:35 +0100 Subject: [PATCH 074/103] doc: Rephrase to be more precise and less confusing (build) It was "... doing the same build ... will not trigger a rebuild". Signed-off-by: Adriano Carvalho --- tools/buildman/buildman.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/buildman/buildman.rst b/tools/buildman/buildman.rst index dafac017f0e..6b382942ac8 100644 --- a/tools/buildman/buildman.rst +++ b/tools/buildman/buildman.rst @@ -1294,7 +1294,7 @@ shows an error:: One major caveat with this feature with branches (-b) is that buildman does not name the output directories differently when you change the configuration, so -doing the same build with a different configuration will not trigger a rebuild. +re-launching Buildman with an updated configuration will not trigger a rebuild. You can use -f to work around that. From 1041ce48a9942ac6fcb580c8973d420dbe53a8ae Mon Sep 17 00:00:00 2001 From: Adriano Carvalho Date: Mon, 25 Aug 2025 23:32:36 +0100 Subject: [PATCH 075/103] doc: Capitalize the word Buildman whenever it's used as a proper noun This consistency reads a bit nicer. Signed-off-by: Adriano Carvalho --- doc/build/reproducible.rst | 2 +- tools/buildman/buildman.rst | 106 ++++++++++++++++++------------------ 2 files changed, 54 insertions(+), 54 deletions(-) diff --git a/doc/build/reproducible.rst b/doc/build/reproducible.rst index 8b030f469d7..1512129e374 100644 --- a/doc/build/reproducible.rst +++ b/doc/build/reproducible.rst @@ -24,4 +24,4 @@ This date is shown when we launch U-Boot: ./u-boot -T U-Boot 2023.01 (Jan 01 2023 - 00:00:00 +0000) -The same effect can be obtained with buildman using the `-r` flag. +The same effect can be obtained with Buildman using the `-r` flag. diff --git a/tools/buildman/buildman.rst b/tools/buildman/buildman.rst index 6b382942ac8..9e850b26ec0 100644 --- a/tools/buildman/buildman.rst +++ b/tools/buildman/buildman.rst @@ -6,7 +6,7 @@ Buildman build tool Quick-start ----------- -If you just want to quickly set up buildman so you can build something (for +If you just want to quickly set up Buildman so you can build something (for example Raspberry Pi 2): .. code-block:: bash @@ -27,7 +27,7 @@ patch series. It can build each individual commit and report which boards fail on which commits, and which errors come up. It aims to make full use of multi-processor machines. -A key feature of buildman is its output summary, which allows warnings, +A key feature of Buildman is its output summary, which allows warnings, errors or image size increases in a particular commit or board to be quickly identified and the offending commit pinpointed. This can be a big help for anyone working with >10 patches at a time. @@ -63,7 +63,7 @@ can be run repeatedly on the same branch after making changes to commits on that branch. In this case it will automatically rebuild commits which have changed (and remove its old results for that commit). It is possible to build a branch for one board, then later build it for another board. This adds to -the output, so now you have results for two boards. If you want buildman to +the output, so now you have results for two boards. If you want Buildman to re-build a commit it has already built (e.g. because of a toolchain update), use the -f flag. @@ -81,7 +81,7 @@ a time. A thread starts at the first commit, configures the source for your board and builds it. Then it checks out the next commit and does an incremental build (i.e. not using 'make xxx_defconfig' unless you use -C). Eventually the thread reaches the last commit and stops. If a commit causes -an error or warning, buildman will try it again after reconfiguring (but see +an error or warning, Buildman will try it again after reconfiguring (but see -Q). Thus some commits may be built twice, with the first result silently discarded. Lots of errors and warnings will cause lots of reconfigures and your build will be very slow. This is because a file that produces just a warning @@ -100,14 +100,14 @@ threads do not affect the state of your git repository. Any checkouts done by the thread affect only the working directory for that thread. Buildman automatically selects the correct tool chain for each board. You -must supply suitable tool chains (see ``--fetch-arch``), but buildman takes +must supply suitable tool chains (see ``--fetch-arch``), but Buildman takes care of selecting the right one. Buildman generally builds a branch (with the -b flag), and in this case builds the upstream commit as well, for comparison. So even if you have one commit in your branch, two commits will be built. Put all your commits in a branch, set the branch's upstream to a valid value, and all will be well. -Otherwise buildman will perform random actions. Use -n to check what the +Otherwise Buildman will perform random actions. Use -n to check what the random actions might be. Buildman effectively has two modes: without -s it builds, with -s it @@ -115,7 +115,7 @@ summarises the results of previous (or active) builds. If you just want to build the current source tree, leave off the -b flag. This will display results and errors as they happen. You can still look at -them later using -se. Note that buildman will assume that the source has +them later using -se. Note that Buildman will assume that the source has changed, and will build all specified boards in this case. Buildman is optimised for building many commits at once, for many boards. @@ -183,7 +183,7 @@ Setting up git checkout -b my-branch origin/master # Add some commits to the branch, reading for testing -#. Create ~/.buildman to tell buildman where to find tool chains (see +#. Create ~/.buildman to tell Buildman where to find tool chains (see buildman_settings_ for details). As an example:: # Buildman settings file @@ -222,18 +222,18 @@ Setting up [toolchain-prefix] arm: /opt/arm-eabi-4.6/bin/arm-eabi-gcc - This tells buildman that you want to use this exact toolchain for the arm + This tells Buildman that you want to use this exact toolchain for the arm architecture. This will override any toolchains found by searching using the [toolchain] settings. - Since the toolchain prefix is an explicit request, buildman will report an + Since the toolchain prefix is an explicit request, Buildman will report an error if a toolchain is not found with that prefix. The current PATH will be searched, so it is possible to use:: [toolchain-prefix] arm: arm-none-eabi- - and buildman will find arm-none-eabi-gcc in /usr/bin if you have it + and Buildman will find arm-none-eabi-gcc in /usr/bin if you have it installed. Another example:: @@ -241,7 +241,7 @@ Setting up [toolchain-wrapper] wrapper: ccache - This tells buildman to use a compiler wrapper in front of CROSS_COMPILE. In + This tells Buildman to use a compiler wrapper in front of CROSS_COMPILE. In this example, ccache. It doesn't affect the toolchain scan. The wrapper is added when the CROSS_COMPILE environment variable is set. The tag name in this section is not important. If more than one line is provided, only the @@ -440,7 +440,7 @@ Setting up You can download toolchains and update the [toolchain] section of the settings file to find them. - To make this easier, buildman can automatically download and install + To make this easier, Buildman can automatically download and install toolchains from kernel.org. First list the available architectures:: $ ./tools/buildman/buildman --fetch-arch list @@ -541,7 +541,7 @@ As an example:: This shows that it will build all 1059 boards, using 4 threads (because we have a 4-core CPU). Each thread will run with -j1, meaning that each make job will use a single CPU. The list of commits to be built helps you -confirm that things look about right. Notice that buildman has chosen a +confirm that things look about right. Notice that Buildman has chosen a 'base' directory for you, immediately above your source tree. Buildman works entirely inside the base directory, here ../lcd9b, @@ -653,7 +653,7 @@ But if you did want to see just the errors for lubbock, use: If you see error lines marked with '-', that means that the errors were fixed by that commit. Sometimes commits can be in the wrong order, so that a breakage is introduced for a few commits and fixed by later commits. This -shows up clearly with buildman. You can then reorder the commits and try +shows up clearly with Buildman. You can then reorder the commits and try again. At commit 16, the error moves: you can see that the old error at line 120 @@ -683,7 +683,7 @@ err Output from stderr, if any. Errors and warnings appear here. log - Output from stdout. Normally there isn't any since buildman runs in silent + Output from stdout. Normally there isn't any since Buildman runs in silent mode. Use -V to force a verbose build (this passes V=1 to 'make') toolchain @@ -938,7 +938,7 @@ a set of (tag, value) pairs. make sure it is unique. The value is the path to the toolchain. Buildman will look in that path for a file ending in 'gcc'. It will then execute it to check that it is a C compiler, passing only the ``--version`` flag to - it. If the return code is 0, buildman assumes that it is a valid C + it. If the return code is 0, Buildman assumes that it is a valid C compiler. It uses the first part of the name as the architecture and strips off the last part when setting the CROSS_COMPILE environment variable (parts are delimited with a hyphen). @@ -961,12 +961,12 @@ a set of (tag, value) pairs. This converts toolchain architecture names to U-Boot names. For example, if an x86 toolchains is called i386-linux-gcc it will not normally be used for architecture 'x86'. Adding 'x86: i386 x86_64' to this section - will tell buildman that the i386 and x86_64 toolchains can be used for + will tell Buildman that the i386 and x86_64 toolchains can be used for the x86 architecture. '[make-flags]' section U-Boot's build system supports a few flags (such as BUILD_TAG) which - affect the build product. These flags can be specified in the buildman + affect the build product. These flags can be specified in the Buildman settings file. They can also be useful when building U-Boot against other open source software. @@ -995,7 +995,7 @@ Quick Sanity Check ------------------ If you have made changes and want to do a quick sanity check of the -currently checked-out source, run buildman without the -b flag. This will +currently checked-out source, run Buildman without the -b flag. This will build the selected boards and display build status as it runs (i.e. -v is enabled automatically). Use -e to see errors/warnings as well. @@ -1014,29 +1014,29 @@ will build commits in us-buildman that are not in upstream/master. Building Faster --------------- -By default, buildman doesn't execute 'make mrproper' prior to building the +By default, Buildman doesn't execute 'make mrproper' prior to building the first commit for each board. This reduces the amount of work 'make' does, and hence speeds up the build. To force use of 'make mrproper', use -the -m flag. -This flag will slow down any buildman invocation, since it increases the amount +This flag will slow down any Buildman invocation, since it increases the amount of work done on any build. An alternative is to use the ``--fallback-mrproper`` flag, which retries the build with 'make mrproper' only after a build failure. -One possible application of buildman is as part of a continual edit, build, -edit, build, ... cycle; repeatedly applying buildman to the same change or +One possible application of Buildman is as part of a continual edit, build, +edit, build, ... cycle; repeatedly applying Buildman to the same change or series of changes while making small incremental modifications to the source each time. This provides quick feedback regarding the correctness of recent -modifications. In this scenario, buildman's default choice of build directory +modifications. In this scenario, Buildman's default choice of build directory causes more build work to be performed than strictly necessary. -By default, each buildman thread uses a single directory for all builds. When a +By default, each Buildman thread uses a single directory for all builds. When a thread builds multiple boards, the configuration built in this directory will cycle through various different configurations, one per board built by the thread. Variations in the configuration will force a rebuild of affected source -files when a thread switches between boards. Ideally, such buildman-induced +files when a thread switches between boards. Ideally, such Buildman-induced rebuilds would not happen, thus allowing the build to operate as efficiently as -the build system and source changes allow. buildman's -P flag may be used to +the build system and source changes allow. Buildman's -P flag may be used to enable this; -P causes each board to be built in a separate (board-specific) -directory, thus avoiding any buildman-induced configuration changes in any +directory, thus avoiding any Buildman-induced configuration changes in any build directory. U-Boot's build system embeds information such as a build timestamp into the @@ -1055,7 +1055,7 @@ of the source tree, thus allowing rapid tested evolution of the code:: Note also the ``--dtc-skip`` option which uses the system device-tree compiler to avoid needing to build it for each board. This can save 10-20% of build time. -An alternative is to set DTC=/path/to/dtc when running buildman. +An alternative is to set DTC=/path/to/dtc when running Buildman. Checking configuration ---------------------- @@ -1090,10 +1090,10 @@ same as 'am335x_evm_usbspl'. The -K option uses the u-boot.cfg, spl/u-boot-spl.cfg and tpl/u-boot-tpl.cfg files which are produced by a build. If all you want is to check the configuration you can in fact avoid doing a full build, using ``--config-only``. -This tells buildman to configure U-Boot and create the .cfg files, but not +This tells Buildman to configure U-Boot and create the .cfg files, but not actually build the source. This is 5-10 times faster than doing a full build. -By default buildman considers the following two configuration methods +By default Buildman considers the following two configuration methods equivalent:: #define CONFIG_SOME_OPTION @@ -1101,7 +1101,7 @@ equivalent:: CONFIG_SOME_OPTION=y The former would appear in a header filer and the latter in a defconfig -file. To achieve this, buildman considers 'y' to be '1' in configuration +file. To achieve this, Buildman considers 'y' to be '1' in configuration variables. This avoids lots of useless output when converting a CONFIG option to Kconfig. To disable this behaviour, use ``--squash-config-y``. @@ -1132,7 +1132,7 @@ and 'brppt1_spi', removing a trailing semicolon. 'brppt1_nand' gained an a value for 'altbootcmd', but lost one for ' altbootcmd'. The -U option uses the u-boot.env files which are produced by a build. -Internally, buildman writes out an out-env file into the build directory for +Internally, Buildman writes out an out-env file into the build directory for later comparison. defconfig fragments @@ -1202,12 +1202,12 @@ specify the output directory with -o when using -w. Support for IDEs (Integrated Development Environments) ------------------------------------------------------ -Normally buildman summarises the output and shows information indicating the +Normally Buildman summarises the output and shows information indicating the meaning of each line of output. For example a '+' symbol appears at the start of -each error line. Also, buildman prints information about what it is about to do, +each error line. Also, Buildman prints information about what it is about to do, along with a summary at the end. -When using buildman from an IDE, it is helpful to drop this behaviour. Use the +When using Buildman from an IDE, it is helpful to drop this behaviour. Use the ``-I/--ide`` option for that. You might also find -W helpful so that warnings do not cause the build to fail: @@ -1227,12 +1227,12 @@ Typically a missing external blob causes a build failure. For build testing of a lot of boards, or boards for which you do not have the blobs, you can use the -M flag to allow missing blobs. This marks the build as if it succeeded, although with warnings shown, including 'Some images are invalid'. If any boards -fail in this way, buildman exits with status 101. +fail in this way, Buildman exits with status 101. -To convert warnings to errors, use -E. To make buildman return success with +To convert warnings to errors, use -E. To make Buildman return success with these warnings, use -W. -It is generally safe to default to enabling -M for all runs of buildman, so long +It is generally safe to default to enabling -M for all runs of Buildman, so long as you check the exit code. To do this, add:: allow-missing = "always" @@ -1278,7 +1278,7 @@ be in single quotes to ensure that the shell recognizes it as a single argument. If you try to set an option that does not exist, or that cannot be changed for -some other reason (e.g. it is 'selected' by another option), then buildman +some other reason (e.g. it is 'selected' by another option), then Buildman shows an error:: $ buildman --board sandbox -a FRED @@ -1292,7 +1292,7 @@ shows an error:: FRED Missing expected line: CONFIG_FRED=y -One major caveat with this feature with branches (-b) is that buildman does not +One major caveat with this feature with branches (-b) is that Buildman does not name the output directories differently when you change the configuration, so re-launching Buildman with an updated configuration will not trigger a rebuild. You can use -f to work around that. @@ -1303,7 +1303,7 @@ Other options Buildman has various other command-line options. Try ``--help`` to see them. -To find out what toolchain prefix buildman will use for a build, use the -A +To find out what toolchain prefix Buildman will use for a build, use the -A option. To request that compiler warnings be promoted to errors, use -E. This passes the @@ -1326,21 +1326,21 @@ warnings are found. Note that it can be useful to combine -E and -W. This means that all compiler warnings will produce failures (code 100) and all other warnings will produce success (since 101 is changed to 0). -If there are both warnings and errors, errors win, so buildman returns 100. +If there are both warnings and errors, errors win, so Buildman returns 100. The -y option is provided (for use with -s) to ignore the bountiful device-tree -warnings. Similarly, -Y tells buildman to ignore the migration warnings. +warnings. Similarly, -Y tells Buildman to ignore the migration warnings. -Sometimes you might get an error in a thread that is not handled by buildman, +Sometimes you might get an error in a thread that is not handled by Buildman, perhaps due to a failure of a tool that it calls. You might see the output, but -then buildman hangs. Failing to handle any eventuality is a bug in buildman and +then Buildman hangs. Failing to handle any eventuality is a bug in Buildman and should be reported. But you can use -T0 to disable threading and hopefully figure out the root cause of the build failure. -For situations where buildman is invoked from multiple running processes, it is -sometimes useful to have buildman wait until the others have finished. Use the +For situations where Buildman is invoked from multiple running processes, it is +sometimes useful to have Buildman wait until the others have finished. Use the ``--process-limit`` option for this: ``--process-limit 1`` will allow only one -buildman to process jobs at a time. +Buildman to process jobs at a time. To build a particular target, rather than the default U-Boot target, use the ``--target`` option. This is unlikely to be useful unless you are building a @@ -1348,7 +1348,7 @@ single board. Buildman normally builds out-of-tree, meaning that the source directory is not disturbed by the build. Use `-i` to do an in-tree build instead. Note that this -does not affect the source directory, since buildman creates a separate git +does not affect the source directory, since Buildman creates a separate git 'worktree' for each board. This means that it is possible to do an in-tree build of an entire branch, or even a 'current source' build for multiple boards. As a special case, you can use `-wi` to do an in-tree build in the current @@ -1370,10 +1370,10 @@ U-Boot build. Using boards.cfg ---------------- -This file is no-longer needed by buildman but it is still generated in the +This file is no-longer needed by Buildman but it is still generated in the working directory. This helps avoid a delay on every build, since scanning all the Kconfig files takes a few seconds. Use the ``-R `` flag to force -regeneration of the file - in that case buildman exits after writing the file +regeneration of the file - in that case Buildman exits after writing the file with exit code 2 if there was an error in the maintainer files. To use the default filename, use a hyphen, i.e. `-R -`. From d20b8792c5228a8d9f20943660d61ea5b2c60232 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 18 Aug 2025 08:47:15 +0200 Subject: [PATCH 076/103] arm: Fix swtiching typo This should say 'switching', so fix it. Signed-off-by: Simon Glass Reviewed-by: Heinrich Schuchardt Reviewed-by: Quentin Schulz Signed-off-by: Heinrich Schuchardt --- arch/arm/lib/bootm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index 7eb764e1f4e..ca4cec61f22 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -183,7 +183,7 @@ __weak void setup_board_tags(struct tag **in_params) {} static void do_nonsec_virt_switch(void) { smp_kick_all_cpus(); - dcache_disable(); /* flush cache before swtiching to EL2 */ + dcache_disable(); /* flush cache before switching to EL2 */ } #endif From c901732558fbee5b798bb7a065f7832d3a6bbc84 Mon Sep 17 00:00:00 2001 From: Andrew Goodbody Date: Wed, 23 Jul 2025 17:04:41 +0100 Subject: [PATCH 077/103] clk: exynos: Fix always true test In exynos7420_peric1_get_rate the variable ret is declared as an 'unsigned int' but is then used to receive the return value of clk_get_by_index which returns an int. The value of ret is then tested for being less than 0 which will always fail for an unsigned variable. Fix this by declaring ret as an 'int' so that the test for the error condition is valid. This issue was found by Smatch. Signed-off-by: Andrew Goodbody Signed-off-by: Minkyu Kang --- drivers/clk/exynos/clk-exynos7420.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/exynos/clk-exynos7420.c b/drivers/clk/exynos/clk-exynos7420.c index 3aa751bf4e4..7de4e688f03 100644 --- a/drivers/clk/exynos/clk-exynos7420.c +++ b/drivers/clk/exynos/clk-exynos7420.c @@ -192,7 +192,7 @@ static int exynos7420_clk_top0_probe(struct udevice *dev) static ulong exynos7420_peric1_get_rate(struct clk *clk) { struct clk in_clk; - unsigned int ret; + int ret; unsigned long freq = 0; switch (clk->id) { From 3b36c242eb338f19c4436f5deba66a65ee85071d Mon Sep 17 00:00:00 2001 From: Sam Protsenko Date: Wed, 6 Aug 2025 17:27:01 -0500 Subject: [PATCH 078/103] usb: host: dwc3-of-simple: Add exynos850 compatible Enable support for Exynos850 SoC in DWC3 host glue layer driver. Signed-off-by: Sam Protsenko Reviewed-by: Marek Vasut Signed-off-by: Minkyu Kang --- drivers/usb/host/dwc3-of-simple.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/usb/host/dwc3-of-simple.c b/drivers/usb/host/dwc3-of-simple.c index d52e7d22d1a..362178b7900 100644 --- a/drivers/usb/host/dwc3-of-simple.c +++ b/drivers/usb/host/dwc3-of-simple.c @@ -91,6 +91,7 @@ static int dwc3_of_simple_remove(struct udevice *dev) static const struct udevice_id dwc3_of_simple_ids[] = { { .compatible = "amlogic,meson-gxl-dwc3" }, { .compatible = "rockchip,rk3399-dwc3" }, + { .compatible = "samsung,exynos850-dwusb3" }, { .compatible = "ti,dwc3" }, { } }; From cb64735bdd487ebc6f8eff790bd966152e9e466b Mon Sep 17 00:00:00 2001 From: Sam Protsenko Date: Wed, 6 Aug 2025 17:27:02 -0500 Subject: [PATCH 079/103] board: samsung: e850-96: Set ethaddr Set the environment variable for Ethernet MAC address (ethaddr). Use the SoC ID to make sure it's unique. It'll be formatted in a way that follows the consecutive style of the serial number ("serial#" variable), i.e.: OTP_CHIPID0 = 0xf51c8113 OTP_CHIPID1 = 0x236 get_chip_id() = 0x236f51c8113 serial# = 00000236f51c8113 ethaddr = 02:36:f5:1c:81:13 where corresponding bytes of the MAC address are: mac_addr[0] = 0x02 // OTP_CHIPID1[15:8] mac_addr[1] = 0x36 // OTP_CHIPID1[7:0] mac_addr[2] = 0xf5 // OTP_CHIPID0[31:24] mac_addr[3] = 0x1c // OTP_CHIPID0[23:16] mac_addr[4] = 0x81 // OTP_CHIPID0[15:8] mac_addr[5] = 0x13 // OTP_CHIPID0[7:0] because OTP_CHIPID1 has only 16 significant bits (with actual ID values), and all 32 bits of OTP_CHIPID0 are significant. Signed-off-by: Sam Protsenko Signed-off-by: Minkyu Kang --- board/samsung/e850-96/e850-96.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/board/samsung/e850-96/e850-96.c b/board/samsung/e850-96/e850-96.c index a6c264d1248..d489716bfdf 100644 --- a/board/samsung/e850-96/e850-96.c +++ b/board/samsung/e850-96/e850-96.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include "fw.h" @@ -92,11 +93,35 @@ static void setup_serial(void) env_set("serial#", serial_str); } +static void setup_ethaddr(void) +{ + u64 serial_num; + u32 mac_hi, mac_lo; + u8 mac_addr[6]; + + if (env_get("ethaddr")) + return; + + serial_num = get_chip_id(); + mac_lo = (u32)serial_num; /* OTP_CHIPID0 */ + mac_hi = (u32)(serial_num >> 32UL); /* OTP_CHIPID1 */ + mac_addr[0] = (mac_hi >> 8) & 0xff; + mac_addr[1] = mac_hi & 0xff; + mac_addr[2] = (mac_lo >> 24) & 0xff; + mac_addr[3] = (mac_lo >> 16) & 0xff; + mac_addr[4] = (mac_lo >> 8) & 0xff; + mac_addr[5] = mac_lo & 0xff; + mac_addr[0] &= ~0x1; /* make sure it's not a multicast address */ + if (is_valid_ethaddr(mac_addr)) + eth_env_set_enetaddr("ethaddr", mac_addr); +} + int board_late_init(void) { int err; setup_serial(); + setup_ethaddr(); /* * Do this in board_late_init() to make sure MMC is not probed before From 6ebd9aa6d3aad4e87aed58400fdd56c69db48c70 Mon Sep 17 00:00:00 2001 From: Sam Protsenko Date: Wed, 6 Aug 2025 17:27:03 -0500 Subject: [PATCH 080/103] board: samsung: e850-96: Add ACPM code Add functions to access I3C bus via APM (Active Power Management) core by using ACPM IPC protocol. It will be further used for configuring PMIC chip voltage regulators. Signed-off-by: Sam Protsenko Signed-off-by: Minkyu Kang --- board/samsung/e850-96/Makefile | 2 +- board/samsung/e850-96/acpm.c | 169 +++++++++++++++++++++++++++++++++ board/samsung/e850-96/acpm.h | 27 ++++++ 3 files changed, 197 insertions(+), 1 deletion(-) create mode 100644 board/samsung/e850-96/acpm.c create mode 100644 board/samsung/e850-96/acpm.h diff --git a/board/samsung/e850-96/Makefile b/board/samsung/e850-96/Makefile index 71d46ea3d2b..08eb8dca5bf 100644 --- a/board/samsung/e850-96/Makefile +++ b/board/samsung/e850-96/Makefile @@ -3,4 +3,4 @@ # Copyright (C) 2024, Linaro Limited # Sam Protsenko -obj-y := e850-96.o fw.o +obj-y := e850-96.o fw.o acpm.o diff --git a/board/samsung/e850-96/acpm.c b/board/samsung/e850-96/acpm.c new file mode 100644 index 00000000000..1cc5c6d0e4a --- /dev/null +++ b/board/samsung/e850-96/acpm.c @@ -0,0 +1,169 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2025 Linaro Ltd. + * Author: Sam Protsenko + * + * ACPM (Active Clock and Power Management) is an IPC protocol for communicating + * with APM (Active Power Management) core. The message exchange between AP + * (Application Processor) and APM is happening by using shared memory in SRAM + * (iRAM) and generating interrupts using Mailbox block. By using this IPC + * interface it's possible to offload power management tasks to APM core, which + * acts as a supervisor for CPU. One of the main tasks of APM is controlling + * PMIC chip over I3C bus. So in order to access PMIC chip registers it's + * recommended to do so by sending corresponding commands to APM via ACPM IPC + * protocol. The IPC interaction sequence looks like this: + * + * AP (CPU) <-> ACPM IPC (Mailbox + SRAM) <-> APM <-> I3C <-> PMIC + * + * This file contains functions for accessing I3C bus via APM block using + * ACPM IPC. + */ + +#include +#include +#include +#include "acpm.h" + +/* Mailbox registers */ +#define MBOX_INTGR0 0x8 /* Interrupt Generation */ +#define MBOX_INTCR1 0x20 /* Interrupt Clear */ +#define MBOX_INTSR1 0x28 /* Interrupt Status */ +#define MBOX_INTGR_OFFSET 16 +#define MBOX_TIMEOUT (1 * USEC_PER_SEC) + +/* APM shared memory registers */ +#define SHMEM_SR0 0x0 +#define SHMEM_SR1 0x4 +#define SHMEM_SR2 0x8 +#define SHMEM_SR3 0xc + +/* IPC functions */ +#define IPC_FUNC_READ 0x0 +#define IPC_FUNC_WRITE 0x1 +/* Command 0 shifts and masks */ +#define IPC_REG_SHIFT 0 +#define IPC_REG_MASK 0xff +#define IPC_TYPE_SHIFT 8 +#define IPC_TYPE_MASK 0xf +#define IPC_CHANNEL_SHIFT 12 +#define IPC_CHANNEL_MASK 0xf +/* Command 1 shifts and masks */ +#define IPC_FUNC_SHIFT 0 +#define IPC_FUNC_MASK 0xff +#define IPC_WRITE_VAL_SHIFT 8 +#define IPC_WRITE_VAL_MASK 0xff +/* Command 3 shifts and masks */ +#define IPC_DEST_SHIFT 8 +#define IPC_DEST_MASK 0xff +#define IPC_RETURN_SHIFT 24 +#define IPC_RETURN_MASK 0xff + +/** + * acpm_ipc_send_data_async() - Send data to I3C block over ACPM IPC + * @acpm: ACPM data + * @cmd0: Command 0 value to send + * @cmd1: Command 1 value to send + */ +static void acpm_ipc_send_data_async(struct acpm *acpm, u32 cmd0, u32 cmd1) +{ + u32 irq_bit = 1 << acpm->ipc_ch; + u32 intgr = irq_bit << MBOX_INTGR_OFFSET; + + /* Write data to the shared memory */ + writel(cmd0, acpm->sram_base + SHMEM_SR0); + writel(cmd1, acpm->sram_base + SHMEM_SR1); + dsb(); + + /* Generate interrupt for I3C block */ + writel(intgr, acpm->mbox_base + MBOX_INTGR0); +} + +/** + * acpm_ipc_wait_resp() - Read response data from I3C block over ACPM IPC + * @acpm: ACPM data + * @cmd2: Will contain read value for command 2 + * @cmd3: Will contain read value for command 3 + * + * Return: 0 on success or negative value on error. + */ +static int acpm_ipc_wait_resp(struct acpm *acpm, u32 *cmd2, u32 *cmd3) +{ + u32 irq_bit = 1 << acpm->ipc_ch; + u32 reg; + int ret; + + /* Wait for the interrupt from I3C block */ + ret = readl_poll_timeout(acpm->mbox_base + MBOX_INTSR1, reg, + reg & irq_bit, MBOX_TIMEOUT); + if (ret < 0) + return ret; + + /* Clear the interrupt */ + writel(irq_bit, acpm->mbox_base + MBOX_INTCR1); + + /* Read data from the shared memory */ + *cmd2 = readl(acpm->sram_base + SHMEM_SR2); + *cmd3 = readl(acpm->sram_base + SHMEM_SR3); + + return 0; +} + +/** + * acpm_i3c_read() - Read an I3C register of some I3C slave device + * @acpm: ACPM data + * @ch: I3C channel (bus) number (0-15) + * @addr: I3C address of slave device (0-15) + * @reg: Address of I3C register in the slave device to read from + * @val: Will contain the read value + * + * Return: 0 on success or non-zero code on error (may be positive). + */ +int acpm_i3c_read(struct acpm *acpm, u8 ch, u8 addr, u8 reg, u8 *val) +{ + u32 cmd[4] = { 0 }; + u8 ret; + + cmd[0] = (ch & IPC_CHANNEL_MASK) << IPC_CHANNEL_SHIFT | + (addr & IPC_TYPE_MASK) << IPC_TYPE_SHIFT | + (reg & IPC_REG_MASK) << IPC_REG_SHIFT; + cmd[1] = IPC_FUNC_READ << IPC_FUNC_SHIFT; + + acpm_ipc_send_data_async(acpm, cmd[0], cmd[1]); + ret = acpm_ipc_wait_resp(acpm, &cmd[2], &cmd[3]); + if (ret) + return ret; + + *val = (cmd[3] >> IPC_DEST_SHIFT) & IPC_DEST_MASK; + ret = (cmd[3] >> IPC_RETURN_SHIFT) & IPC_RETURN_MASK; + return ret; +} + +/** + * acpm_i3c_write() - Write an I3C register of some I3C slave device + * @acpm: ACPM data + * @ch: I3C channel (bus) number (0-15) + * @addr: I3C address of slave device (0-15) + * @reg: Address of I3C register in the slave device to write into + * @val: Value to write + * + * Return: 0 on success or non-zero code on error (may be positive). + */ +int acpm_i3c_write(struct acpm *acpm, u8 ch, u8 addr, u8 reg, u8 val) +{ + u32 cmd[4] = { 0 }; + u8 ret; + + cmd[0] = (ch & IPC_CHANNEL_MASK) << IPC_CHANNEL_SHIFT | + (addr & IPC_TYPE_MASK) << IPC_TYPE_SHIFT | + (reg & IPC_REG_MASK) << IPC_REG_SHIFT; + cmd[1] = IPC_FUNC_WRITE << IPC_FUNC_SHIFT | + (val & IPC_WRITE_VAL_MASK) << IPC_WRITE_VAL_SHIFT; + + acpm_ipc_send_data_async(acpm, cmd[0], cmd[1]); + ret = acpm_ipc_wait_resp(acpm, &cmd[2], &cmd[3]); + if (ret) + return ret; + + ret = (cmd[3] >> IPC_RETURN_SHIFT) & IPC_RETURN_MASK; + return ret; +} diff --git a/board/samsung/e850-96/acpm.h b/board/samsung/e850-96/acpm.h new file mode 100644 index 00000000000..9373969209f --- /dev/null +++ b/board/samsung/e850-96/acpm.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2025 Linaro Ltd. + * Sam Protsenko + */ + +#ifndef __E850_96_ACPM_H +#define __E850_96_ACPM_H + +#include + +/** + * struct acpm - Data for I3C communication over ACPM IPC protocol + * @mbox_base: Base address of APM mailbox block + * @sram_base: Base address of shared memory used for APM messages + * @ipc_ch: Mailbox channel number used for communication with I3C block (0-15) + */ +struct acpm { + void __iomem *mbox_base; + void __iomem *sram_base; + u8 ipc_ch; +}; + +int acpm_i3c_read(struct acpm *acpm, u8 ch, u8 addr, u8 reg, u8 *val); +int acpm_i3c_write(struct acpm *acpm, u8 ch, u8 addr, u8 reg, u8 val); + +#endif /* __E850_96_ACPM_H */ From 17b1d78484446215320de90b4f6df13fbc85b6a3 Mon Sep 17 00:00:00 2001 From: Sam Protsenko Date: Wed, 6 Aug 2025 17:27:04 -0500 Subject: [PATCH 081/103] board: samsung: e850-96: Add PMIC code Add functions for configuring voltage regulators on S2MPU12 PMIC chip for E850-96 board. The chip is accessed by commanding APM core (via ACPM IPC protocol) to perform corresponding transfers over I3C bus. The most important regulator being set up is LDO24 used for LAN9514 chip power. As LAN9514 implements USB hub and Ethernet controller functionality, it's crucial to enable and configure LDO24 to be able to use it further. While at it, configure the rest of regulators that might be needed later, both in the bootloader and in kernel. Signed-off-by: Sam Protsenko Signed-off-by: Minkyu Kang --- board/samsung/e850-96/Makefile | 2 +- board/samsung/e850-96/pmic.c | 144 +++++++++++++++++++++++++++++++++ board/samsung/e850-96/pmic.h | 14 ++++ 3 files changed, 159 insertions(+), 1 deletion(-) create mode 100644 board/samsung/e850-96/pmic.c create mode 100644 board/samsung/e850-96/pmic.h diff --git a/board/samsung/e850-96/Makefile b/board/samsung/e850-96/Makefile index 08eb8dca5bf..76b8d47994e 100644 --- a/board/samsung/e850-96/Makefile +++ b/board/samsung/e850-96/Makefile @@ -3,4 +3,4 @@ # Copyright (C) 2024, Linaro Limited # Sam Protsenko -obj-y := e850-96.o fw.o acpm.o +obj-y := e850-96.o fw.o acpm.o pmic.o diff --git a/board/samsung/e850-96/pmic.c b/board/samsung/e850-96/pmic.c new file mode 100644 index 00000000000..037fd4844c5 --- /dev/null +++ b/board/samsung/e850-96/pmic.c @@ -0,0 +1,144 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2025 Linaro Ltd. + * Author: Sam Protsenko + * + * This file contains functions for S2MPU12 PMIC regulators configuration. + * + * Example of voltage calculation for LDO24 and LDO32: + * - V_min = 1800 mV + * - V_step = 25 mV + * - V_wanted = 3300 mV + * - register value: (V_wanted - V_min) / V_step = 60 = 0x3c + * + * NOTE: 0x3c value might mean different voltage for other LDOs. + */ + +#include +#include +#include "pmic.h" + +/* PMIC definitions */ +#define S2MPU12_CHANNEL 0 /* I3C bus number of PMIC */ +#define S2MPU12_PM_ADDR 0x1 /* I3C slave addr of PM part */ + +/* PMIC I3C registers */ +#define S2MPU12_PM_LDO1_CTRL 0x2b +#define S2MPU12_PM_LDO_CTRL(n) (S2MPU12_PM_LDO1_CTRL + (n) - 1) + +/* LDOx_CTRL values */ +#define S2MPU12_LDO_CTRL_OUT_MASK (0x3 << 6) +#define S2MPU12_LDO_CTRL_OUT_ALWAYS_ON (0x3 << 6) + +struct pmic_ldo { + u8 num; /* LDO number */ + u8 en; /* "enable" bits value in LDOx_CTRL register */ + u8 out; /* "output voltage" bits value in LDOx_CTRL register */ +}; + +/* List of LDOs to enable only */ +static u8 pmic_ldos_en[] = { + 2, /* 1.8V/450mA: multiple lines */ + 11, /* 3.0V/150mA: AVDD33_USB20 */ + 23, /* 2.85V/800mA: VDD_EMMC_2P85 */ + 27, /* 3.0V/150mA: MIPI_SWITCH_3V3 */ + 28, /* 1.8V/150mA: HDMI_CONV_1V8 */ + 30, /* 1.8V/150mA: NPU_VDD18 */ +}; + +/* List of LDOs to enable and set output voltage */ +static struct pmic_ldo pmic_ldos_en_out[] = { + { + .num = 24, /* 3.0V/800mA: VDD_LAN (LAN9514) */ + .en = S2MPU12_LDO_CTRL_OUT_ALWAYS_ON, + .out = 0x3c, /* means 3.3V for LDO24 */ + }, { + .num = 32, /* 3.3V/300mA: CAM_VDD (RPi camera module) */ + .en = S2MPU12_LDO_CTRL_OUT_ALWAYS_ON, + .out = 0x3c, /* means 3.3V for LDO32 */ + }, +}; + +/* Enable specified LDO */ +static int pmic_ldo_set_en(struct acpm *acpm, u8 ldo) +{ + const u8 reg = S2MPU12_PM_LDO_CTRL(ldo); + u8 val; + int err; + + err = acpm_i3c_read(acpm, S2MPU12_CHANNEL, S2MPU12_PM_ADDR, reg, &val); + if (err) + return err; + + val &= ~S2MPU12_LDO_CTRL_OUT_MASK; + val |= S2MPU12_LDO_CTRL_OUT_ALWAYS_ON; + + return acpm_i3c_write(acpm, S2MPU12_CHANNEL, S2MPU12_PM_ADDR, reg, val); +} + +/* Enable specified LDO and set its voltage to 0xc0 value */ +static int pmic_ldo_set_en_out(struct acpm *acpm, struct pmic_ldo *ldo) +{ + const u8 reg = S2MPU12_PM_LDO_CTRL(ldo->num); + const u8 val = ldo->en | ldo->out; + + return acpm_i3c_write(acpm, S2MPU12_CHANNEL, S2MPU12_PM_ADDR, reg, val); +} + +#ifdef DEBUG +static void pmic_trace_ldo(struct acpm *acpm, u8 ldo) +{ + const u8 reg = S2MPU12_PM_LDO_CTRL(ldo); + u8 val; + int err; + + err = acpm_i3c_read(acpm, S2MPU12_CHANNEL, S2MPU12_PM_ADDR, reg, &val); + if (err) + printf(" S2MPU12_PM_LDO%u_CTRL: Read error!\n", ldo); + else + printf(" S2MPU12_PM_LDO%u_CTRL: 0x%x\n", ldo, val); +} + +static void pmic_trace_ldos(struct acpm *acpm) +{ + size_t i; + + printf("Tracing LDOs...\n"); + for (i = 0; i < ARRAY_SIZE(pmic_ldos_en); ++i) + pmic_trace_ldo(acpm, pmic_ldos_en[i]); + for (i = 0; i < ARRAY_SIZE(pmic_ldos_en_out); ++i) + pmic_trace_ldo(acpm, pmic_ldos_en_out[i].num); +} +#endif + +/** + * pmic_init() - Enable power regulators in S2MPU12 PMIC. + * @acpm: Data for I3C communication with PMIC over ACPM protocol + * + * Enable LDOs needed for devices used in the bootloader and kernel. + * + * Return: 0 on success or non-zero code on error. + */ +int pmic_init(struct acpm *acpm) +{ + size_t i; + int err; + + for (i = 0; i < ARRAY_SIZE(pmic_ldos_en); ++i) { + err = pmic_ldo_set_en(acpm, pmic_ldos_en[i]); + if (err) + return -EIO; + } + + for (i = 0; i < ARRAY_SIZE(pmic_ldos_en_out); ++i) { + err = pmic_ldo_set_en_out(acpm, &pmic_ldos_en_out[i]); + if (err) + return -EIO; + } + +#ifdef DEBUG + pmic_trace_ldos(acpm); +#endif + + return 0; +} diff --git a/board/samsung/e850-96/pmic.h b/board/samsung/e850-96/pmic.h new file mode 100644 index 00000000000..46624c2ebd4 --- /dev/null +++ b/board/samsung/e850-96/pmic.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2025 Linaro Ltd. + * Sam Protsenko + */ + +#ifndef __E850_96_PMIC_H +#define __E850_96_PMIC_H + +#include "acpm.h" + +int pmic_init(struct acpm *acpm); + +#endif /* __E850_96_PMIC_H */ From 8fefc2eb9610b75270f0376980dae952d16fc84b Mon Sep 17 00:00:00 2001 From: Sam Protsenko Date: Wed, 6 Aug 2025 17:27:05 -0500 Subject: [PATCH 082/103] board: samsung: e850-96: Configure PMIC regulators Make use of PMIC configuration routines and enable all LDOs that might be useful for bootloader and kernel. The most crucial regulator being enabled at the moment is LDO24 which provides power to LAN9514 chip. That makes Ethernet controller and USB hub functional. Signed-off-by: Sam Protsenko Signed-off-by: Minkyu Kang --- board/samsung/e850-96/e850-96.c | 31 ++++++++++++++++++++++++++++--- 1 file changed, 28 insertions(+), 3 deletions(-) diff --git a/board/samsung/e850-96/e850-96.c b/board/samsung/e850-96/e850-96.c index d489716bfdf..2cf874fcf7a 100644 --- a/board/samsung/e850-96/e850-96.c +++ b/board/samsung/e850-96/e850-96.c @@ -11,11 +11,18 @@ #include #include #include "fw.h" +#include "pmic.h" /* OTP Controller base address and register offsets */ -#define EXYNOS850_OTP_BASE 0x10000000 -#define OTP_CHIPID0 0x4 -#define OTP_CHIPID1 0x8 +#define EXYNOS850_OTP_BASE 0x10000000 +#define OTP_CHIPID0 0x4 +#define OTP_CHIPID1 0x8 + +/* ACPM and PMIC definitions */ +#define EXYNOS850_MBOX_APM2AP_BASE 0x11900000 +#define EXYNOS850_APM_SRAM_BASE 0x02039000 /* in iRAM */ +#define EXYNOS850_APM_SHMEM_OFFSET 0x3200 +#define EXYNOS850_IPC_AP_I3C 10 struct efi_fw_image fw_images[] = { { @@ -56,6 +63,13 @@ struct efi_capsule_update_info update_info = { .images = fw_images, }; +static struct acpm acpm = { + .mbox_base = (void __iomem *)EXYNOS850_MBOX_APM2AP_BASE, + .sram_base = (void __iomem *)(EXYNOS850_APM_SRAM_BASE + + EXYNOS850_APM_SHMEM_OFFSET), + .ipc_ch = EXYNOS850_IPC_AP_I3C, +}; + int dram_init(void) { return fdtdec_setup_mem_size_base(); @@ -133,3 +147,14 @@ int board_late_init(void) return 0; } + +int power_init_board(void) +{ + int err; + + err = pmic_init(&acpm); + if (err) + printf("ERROR: Failed to configure PMIC (%d)\n", err); + + return 0; +} From c542140d7cade7d2f14a7a0f260de9b196a97d00 Mon Sep 17 00:00:00 2001 From: Sam Protsenko Date: Wed, 6 Aug 2025 17:27:06 -0500 Subject: [PATCH 083/103] board: samsung: e850-96: Extract device info from fw loading code Make it possible to provide the information about storage device where LDFW firmware resides to the firmware loading routine. The firmware loader code shouldn't have that data hard-coded anyway, and it also allows for implementing more dynamic behavior later, like choosing the storage device containing LDFW via some environment variables. No functional change. Signed-off-by: Sam Protsenko Signed-off-by: Minkyu Kang --- board/samsung/e850-96/e850-96.c | 9 ++++++- board/samsung/e850-96/fw.c | 47 ++++++++++++++++++++------------- board/samsung/e850-96/fw.h | 4 ++- 3 files changed, 39 insertions(+), 21 deletions(-) diff --git a/board/samsung/e850-96/e850-96.c b/board/samsung/e850-96/e850-96.c index 2cf874fcf7a..b5f6ba23432 100644 --- a/board/samsung/e850-96/e850-96.c +++ b/board/samsung/e850-96/e850-96.c @@ -24,6 +24,12 @@ #define EXYNOS850_APM_SHMEM_OFFSET 0x3200 #define EXYNOS850_IPC_AP_I3C 10 +/* LDFW firmware definitions */ +#define LDFW_NWD_ADDR 0x88000000 +#define EMMC_IFNAME "mmc" +#define EMMC_DEV_NUM 0 +#define EMMC_ESP_PART 1 + struct efi_fw_image fw_images[] = { { .image_type_id = E850_96_FWBL1_IMAGE_GUID, @@ -141,7 +147,8 @@ int board_late_init(void) * Do this in board_late_init() to make sure MMC is not probed before * efi_init_early(). */ - err = load_ldfw(); + err = load_ldfw(EMMC_IFNAME, EMMC_DEV_NUM, EMMC_ESP_PART, + LDFW_NWD_ADDR); if (err) printf("ERROR: LDFW loading failed (%d)\n", err); diff --git a/board/samsung/e850-96/fw.c b/board/samsung/e850-96/fw.c index 8f64e759b43..64235c01a25 100644 --- a/board/samsung/e850-96/fw.c +++ b/board/samsung/e850-96/fw.c @@ -11,13 +11,9 @@ #include #include "fw.h" -#define EMMC_IFACE "mmc" -#define EMMC_DEV_NUM 0 #define LDFW_RAW_PART "ldfw" -#define LDFW_FAT_PART "esp" #define LDFW_FAT_PATH "/EFI/firmware/ldfw.bin" -#define LDFW_NWD_ADDR 0x88000000 #define LDFW_MAGIC 0x10adab1e #define SMC_CMD_LOAD_LDFW -0x500 #define SDM_HW_RESET_STATUS 0x1230 @@ -39,21 +35,25 @@ struct ldfw_header { }; /* Load LDFW binary as a file from FAT partition */ -static int read_fw_from_fat(const char *part_name, const char *path, void *buf) +static int read_fw_from_fat(const char *ifname, int dev, int part, + const char *path, void *buf) { - char dev_part_str[8]; + struct blk_desc *blk_desc; loff_t len_read; int err; - snprintf(dev_part_str, sizeof(dev_part_str), "%d#%s", EMMC_DEV_NUM, - LDFW_FAT_PART); - - err = fs_set_blk_dev(EMMC_IFACE, dev_part_str, FS_TYPE_FAT); - if (err) { - debug("%s: Can't set block device\n", __func__); + blk_desc = blk_get_dev(ifname, dev); + if (!blk_desc) { + debug("%s: Can't get block device\n", __func__); return -ENODEV; } + err = fs_set_blk_dev_with_part(blk_desc, part); + if (err) { + debug("%s: Can't set partition\n", __func__); + return -ENOENT; + } + err = fs_read(path, (ulong)buf, 0, 0, &len_read); if (err) { debug("%s: Can't read LDFW file\n", __func__); @@ -64,16 +64,17 @@ static int read_fw_from_fat(const char *part_name, const char *path, void *buf) } /* Load LDFW binary from raw partition on block device into RAM buffer */ -static int read_fw_from_raw(const char *part_name, void *buf) +static int read_fw_from_raw(const char *ifname, int dev, const char *part_name, + void *buf) { struct blk_desc *blk_desc; struct disk_partition part; unsigned long cnt; int part_num; - blk_desc = blk_get_dev(EMMC_IFACE, EMMC_DEV_NUM); + blk_desc = blk_get_dev(ifname, dev); if (!blk_desc) { - debug("%s: Can't get eMMC device\n", __func__); + debug("%s: Can't get block device\n", __func__); return -ENODEV; } @@ -92,9 +93,17 @@ static int read_fw_from_raw(const char *part_name, void *buf) return 0; } -int load_ldfw(void) +/** + * load_ldfw - Load the loadable firmware (LDFW) + * @ifname: Interface name of the block device to load the firmware from + * @dev: Device number + * @part: Partition number + * @addr: Temporary memory (Normal World) to use for loading the firmware + * + * Return: 0 on success or a negative value on error. + */ +int load_ldfw(const char *ifname, int dev, int part, phys_addr_t addr) { - const phys_addr_t addr = (phys_addr_t)LDFW_NWD_ADDR; struct ldfw_header *hdr; struct arm_smccc_res res; void *buf = (void *)addr; @@ -102,9 +111,9 @@ int load_ldfw(void) int err, i; /* First try to read LDFW from EFI partition, then from the raw one */ - err = read_fw_from_fat(LDFW_FAT_PART, LDFW_FAT_PATH, buf); + err = read_fw_from_fat(ifname, dev, part, LDFW_FAT_PATH, buf); if (err) { - err = read_fw_from_raw(LDFW_RAW_PART, buf); + err = read_fw_from_raw(ifname, dev, LDFW_RAW_PART, buf); if (err) return err; } diff --git a/board/samsung/e850-96/fw.h b/board/samsung/e850-96/fw.h index 472664e4ed2..73d9615d4a9 100644 --- a/board/samsung/e850-96/fw.h +++ b/board/samsung/e850-96/fw.h @@ -7,6 +7,8 @@ #ifndef __E850_96_FW_H #define __E850_96_FW_H -int load_ldfw(void); +#include + +int load_ldfw(const char *ifname, int dev, int part, phys_addr_t addr); #endif /* __E850_96_FW_H */ From 75f75832d0a97a8c1e1167eb3a6d3dbd1d4eae54 Mon Sep 17 00:00:00 2001 From: Sam Protsenko Date: Wed, 6 Aug 2025 17:27:07 -0500 Subject: [PATCH 084/103] board: samsung: e850-96: Add bootdev var to choose boot device Provide a way for the user to select which storage to load the LDFW firmware from, by setting the corresponding environment variables: - bootdev: block device interface name - bootdevnum: block device number - bootdevpart: partition number This might be useful when the OS is flashed and booted from a different storage device than eMMC (e.g. USB flash drive). In this case it should be sufficient to just set: => setenv bootdev usb => env save assuming that the USB drive layout follows the same partitioning scheme as defined in $partitions. Signed-off-by: Sam Protsenko Signed-off-by: Minkyu Kang --- board/samsung/e850-96/e850-96.c | 38 +++++++++++++++++++++++++-------- 1 file changed, 29 insertions(+), 9 deletions(-) diff --git a/board/samsung/e850-96/e850-96.c b/board/samsung/e850-96/e850-96.c index b5f6ba23432..3df241edde2 100644 --- a/board/samsung/e850-96/e850-96.c +++ b/board/samsung/e850-96/e850-96.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include "fw.h" #include "pmic.h" @@ -136,21 +137,40 @@ static void setup_ethaddr(void) eth_env_set_enetaddr("ethaddr", mac_addr); } -int board_late_init(void) +/* + * Call this in board_late_init() to avoid probing block devices before + * efi_init_early(). + */ +void load_firmware(void) { + const char *ifname; + ulong dev, part; int err; - setup_serial(); - setup_ethaddr(); + ifname = env_get("bootdev"); + if (!ifname) + ifname = EMMC_IFNAME; + dev = env_get_ulong("bootdevnum", 10, EMMC_DEV_NUM); + part = env_get_ulong("bootdevpart", 10, EMMC_ESP_PART); - /* - * Do this in board_late_init() to make sure MMC is not probed before - * efi_init_early(). - */ - err = load_ldfw(EMMC_IFNAME, EMMC_DEV_NUM, EMMC_ESP_PART, - LDFW_NWD_ADDR); + if (!strcmp(ifname, "usb")) { + printf("Starting USB (bootdev=usb)...\n"); + err = usb_init(); + if (err) + return; + } + + printf("Loading LDFW firmware (from %s %ld)...\n", ifname, dev); + err = load_ldfw(ifname, dev, part, LDFW_NWD_ADDR); if (err) printf("ERROR: LDFW loading failed (%d)\n", err); +} + +int board_late_init(void) +{ + setup_serial(); + setup_ethaddr(); + load_firmware(); return 0; } From e52e4320ba8db5a0a42f0bf53b7ac98fcfa83a14 Mon Sep 17 00:00:00 2001 From: Sam Protsenko Date: Wed, 6 Aug 2025 17:27:08 -0500 Subject: [PATCH 085/103] configs: e850-96: Disable CONFIG_DEFAULT_FDT_FILE Linux kernel should use some separate device tree obtained from another source anyway. For example the dtb file can be read from /boot directory in eMMC rootfs partition, either by GRUB or U-Boot. Using U-Boot's device tree blob to provide it to the kernel (when CONFIG_DEFAULT_FDT_FILE is set and nobody else overrides this choice) might lead to undesired effects when booting the OS. For example, if a user sets "dr_mode" property to "host" value in U-Boot's dts to enable USB host capabilities in U-Boot, it might confuse usb-conn-gpio driver in Linux kernel later like this: platform connector: deferred probe pending: usb-conn-gpio: failed to get role switch Disable CONFIG_DEFAULT_FDT_FILE option to avoid any possible confusion. Signed-off-by: Sam Protsenko Signed-off-by: Minkyu Kang --- board/samsung/e850-96/e850-96.env | 2 +- configs/e850-96_defconfig | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/board/samsung/e850-96/e850-96.env b/board/samsung/e850-96/e850-96.env index aed7a71046d..992318b0ab2 100644 --- a/board/samsung/e850-96/e850-96.env +++ b/board/samsung/e850-96/e850-96.env @@ -5,7 +5,7 @@ fdt_addr_r=0x8c000000 scriptaddr=0x8c100000 pxefile_addr_r=0x8c200000 ramdisk_addr_r=0x8c300000 -fdtfile=CONFIG_DEFAULT_FDT_FILE +fdtfile=exynos/exynos850-e850-96.dtb dfu_alt_info= rawemmc raw 0 0x747c000 mmcpart 1; diff --git a/configs/e850-96_defconfig b/configs/e850-96_defconfig index b4066d87460..412c99468f2 100644 --- a/configs/e850-96_defconfig +++ b/configs/e850-96_defconfig @@ -19,7 +19,6 @@ CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y CONFIG_EFI_CAPSULE_ON_DISK=y CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y CONFIG_BOOTSTD_FULL=y -CONFIG_DEFAULT_FDT_FILE="exynos850-e850-96.dtb" # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_BOARD_INIT is not set CONFIG_BOARD_LATE_INIT=y From 88a465b47cd625775cc0a693b1d86914ca76cf5f Mon Sep 17 00:00:00 2001 From: Sam Protsenko Date: Wed, 6 Aug 2025 17:27:09 -0500 Subject: [PATCH 086/103] configs: e850-96: Enable USB host support Exynos850 SoC has a dual-role USB controller which can be configured in USB host role. As it's the only one USB controller on the board, it's shared between "device" USB connector (micro-USB) and host USB connectors. The hardware automatically powers on the host related parts when the micro-USB cable (for device role) is being disconnected. Also, as U-Boot lacks dynamic USB role switching capability, the only way to switch the role at the moment is to modify "dr_mode" property in U-Boot's device tree file here: dts/upstream/src/arm64/exynos/exynos850-e850-96.dts This won't affect the dynamic role switching later in Linux kernel, as a separate (different) device tree blob is provided to the kernel. Enable the USB host support and corresponding commands to make it functional in E850-96 board. Signed-off-by: Sam Protsenko Signed-off-by: Minkyu Kang --- configs/e850-96_defconfig | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/configs/e850-96_defconfig b/configs/e850-96_defconfig index 412c99468f2..d7cd1b4b8ba 100644 --- a/configs/e850-96_defconfig +++ b/configs/e850-96_defconfig @@ -29,6 +29,8 @@ CONFIG_CMD_CLK=y CONFIG_CMD_DFU=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_EFIDEBUG=y # CONFIG_CMD_DATE is not set CONFIG_CMD_RTC=y @@ -63,6 +65,9 @@ CONFIG_SYSRESET=y CONFIG_SYSRESET_SYSCON=y CONFIG_USB=y CONFIG_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_GADGET=y From e1d02147b3f015139e3dcc705a97486b07b640ca Mon Sep 17 00:00:00 2001 From: Sam Protsenko Date: Wed, 6 Aug 2025 17:27:10 -0500 Subject: [PATCH 087/103] configs: e850-96: Enable Ethernet LAN9514 is a chip on E850-96 board which acts as a USB host hub and Ethernet controller. It's controlled via USB lines when DWC3 is configured to be in USB host role (by setting the "dr_mode" property to "host" value in e850-96 dts file). Enable network support and LAN9514 chip support. This makes Ethernet functional on E850-96 board. Signed-off-by: Sam Protsenko Signed-off-by: Minkyu Kang --- configs/e850-96_defconfig | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/configs/e850-96_defconfig b/configs/e850-96_defconfig index d7cd1b4b8ba..8f9659ce050 100644 --- a/configs/e850-96_defconfig +++ b/configs/e850-96_defconfig @@ -42,7 +42,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_REDUNDANT=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 -CONFIG_NO_NET=y +CONFIG_NET_LWIP=y CONFIG_CLK_EXYNOS850=y CONFIG_DFU_MMC=y CONFIG_USB_FUNCTION_FASTBOOT=y @@ -70,6 +70,8 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_SMSC95XX=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Samsung" CONFIG_USB_GADGET_VENDOR_NUM=0x18d1 From bd903be32409de11e0f71e6a28835d4333c3e418 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Mon, 1 Sep 2025 08:50:13 +0300 Subject: [PATCH 088/103] ARM: tegra20: transformer: fix Hall sensor behavior Hall sensor found in SL101 is not used for closed dock detection as on TF101 or TF101G, it is used to detect if keyboard slider is out. To address this, lets move Lid sensor switch into TF101/G trees and add Tablet mode switch into SL101 tree. Signed-off-by: Svyatoslav Ryhel --- arch/arm/dts/tegra20-asus-sl101.dts | 10 ++++++++++ arch/arm/dts/tegra20-asus-tf101.dts | 10 ++++++++++ arch/arm/dts/tegra20-asus-tf101g.dts | 10 ++++++++++ arch/arm/dts/tegra20-asus-transformer.dtsi | 6 ------ 4 files changed, 30 insertions(+), 6 deletions(-) diff --git a/arch/arm/dts/tegra20-asus-sl101.dts b/arch/arm/dts/tegra20-asus-sl101.dts index b4709c3e9a4..9f78b0febf3 100644 --- a/arch/arm/dts/tegra20-asus-sl101.dts +++ b/arch/arm/dts/tegra20-asus-sl101.dts @@ -6,4 +6,14 @@ / { model = "ASUS EeePad Slider SL101"; compatible = "asus,sl101", "nvidia,tegra20"; + + extcon-keys { + compatible = "gpio-keys"; + + switch-tablet-mode { + label = "Tablet Mode"; + gpios = <&gpio TEGRA_GPIO(S, 4) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; }; diff --git a/arch/arm/dts/tegra20-asus-tf101.dts b/arch/arm/dts/tegra20-asus-tf101.dts index 7c734fb5b19..03ba78c5dc2 100644 --- a/arch/arm/dts/tegra20-asus-tf101.dts +++ b/arch/arm/dts/tegra20-asus-tf101.dts @@ -6,4 +6,14 @@ / { model = "ASUS EeePad Transformer TF101"; compatible = "asus,tf101", "nvidia,tegra20"; + + extcon-keys { + compatible = "gpio-keys"; + + switch-dock-hall-sensor { + label = "Lid sensor"; + gpios = <&gpio TEGRA_GPIO(S, 4) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; }; diff --git a/arch/arm/dts/tegra20-asus-tf101g.dts b/arch/arm/dts/tegra20-asus-tf101g.dts index f49a358a267..44d5fdfc2b5 100644 --- a/arch/arm/dts/tegra20-asus-tf101g.dts +++ b/arch/arm/dts/tegra20-asus-tf101g.dts @@ -6,4 +6,14 @@ / { model = "ASUS EeePad Transformer TF101G"; compatible = "asus,tf101g", "nvidia,tegra20"; + + extcon-keys { + compatible = "gpio-keys"; + + switch-dock-hall-sensor { + label = "Lid sensor"; + gpios = <&gpio TEGRA_GPIO(S, 4) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; }; diff --git a/arch/arm/dts/tegra20-asus-transformer.dtsi b/arch/arm/dts/tegra20-asus-transformer.dtsi index 61b1cea6e90..df078a6fcdc 100644 --- a/arch/arm/dts/tegra20-asus-transformer.dtsi +++ b/arch/arm/dts/tegra20-asus-transformer.dtsi @@ -497,12 +497,6 @@ gpios = <&gpio TEGRA_GPIO(Q, 5) GPIO_ACTIVE_LOW>; linux,code = ; }; - - switch-dock-hall-sensor { - label = "Lid sensor"; - gpios = <&gpio TEGRA_GPIO(S, 4) GPIO_ACTIVE_LOW>; - linux,code = ; - }; }; panel: panel { From 392b5b426cfc40f94803688fe63f72d83d0a5e70 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Mon, 1 Sep 2025 08:43:40 +0300 Subject: [PATCH 089/103] board: transformer-t20: add separate env for SL101 SL101 unlike TF101/G has no Lid sensor, so lets add a separate env for SL101 without Lid sensor used. Signed-off-by: Svyatoslav Ryhel --- board/asus/transformer-t20/configs/sl101.config | 1 + board/asus/transformer-t20/sl101.env | 15 +++++++++++++++ 2 files changed, 16 insertions(+) create mode 100644 board/asus/transformer-t20/sl101.env diff --git a/board/asus/transformer-t20/configs/sl101.config b/board/asus/transformer-t20/configs/sl101.config index 4f639e1b412..87c6f7a216d 100644 --- a/board/asus/transformer-t20/configs/sl101.config +++ b/board/asus/transformer-t20/configs/sl101.config @@ -1 +1,2 @@ +CONFIG_ENV_SOURCE_FILE="sl101" CONFIG_DEFAULT_DEVICE_TREE="tegra20-asus-sl101" diff --git a/board/asus/transformer-t20/sl101.env b/board/asus/transformer-t20/sl101.env new file mode 100644 index 00000000000..f2bf298a997 --- /dev/null +++ b/board/asus/transformer-t20/sl101.env @@ -0,0 +1,15 @@ +#include + +button_cmd_0_name=Volume Down +button_cmd_0=bootmenu +partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs} +boot_dev=1 + +bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu +bootmenu_1=mount external storage=usb start && ums 0 mmc 1; bootmenu +bootmenu_2=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu +bootmenu_3=update bootloader=run flash_uboot +bootmenu_4=reboot RCM=enterrcm +bootmenu_5=reboot=reset +bootmenu_6=power off=poweroff +bootmenu_delay=-1 From 869a18c7e3cbfae613d7829139635de62e96b36c Mon Sep 17 00:00:00 2001 From: Henrik Grimler Date: Fri, 22 Aug 2025 20:54:38 +0200 Subject: [PATCH 090/103] ARM: exynos: use correct exynos4210-origen SoC in Kconfig There exists both a Origen board based on exynos4210, and a board based on exynos4412. U-boot only supports the one based on exynos 4210, but Kconfig string was accidentally written as Exynos4412 Origen in previous migration to Kconfig. Fix the string to clear up confusion, and to not give the impression that both types of Origen boards are supported. Fixes: 72df68cc6b73 ("exynos: kconfig: move board select menu and common settings") Signed-off-by: Henrik Grimler Signed-off-by: Minkyu Kang --- arch/arm/mach-exynos/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 28193039cb8..2cd67d02386 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -88,7 +88,7 @@ config TARGET_S5PC210_UNIVERSAL select MISC_COMMON config TARGET_ORIGEN - bool "Exynos4412 Origen board" + bool "Exynos4210 Origen board" select EXYNOS4210 select SUPPORT_SPL From 354b3d789289ceeba0ce1e911def9f3d28ee8c98 Mon Sep 17 00:00:00 2001 From: Henrik Grimler Date: Fri, 22 Aug 2025 20:54:39 +0200 Subject: [PATCH 091/103] ARM: exynos: pinmux: fix parentheses alignments For multi-line commands the lines should preferably be aligned with the opening parenthesis. Signed-off-by: Henrik Grimler Signed-off-by: Minkyu Kang --- arch/arm/mach-exynos/pinmux.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-exynos/pinmux.c b/arch/arm/mach-exynos/pinmux.c index 48c325190d5..bd82e1ac750 100644 --- a/arch/arm/mach-exynos/pinmux.c +++ b/arch/arm/mach-exynos/pinmux.c @@ -102,7 +102,7 @@ static int exynos5_mmc_config(int peripheral, int flags) } if ((flags & PINMUX_FLAG_8BIT_MODE) && !start_ext) { debug("SDMMC device %d does not support 8bit mode", - peripheral); + peripheral); return -1; } if (flags & PINMUX_FLAG_8BIT_MODE) { @@ -902,7 +902,7 @@ static int exynos4_pinmux_decode_periph_id(const void *blob, int node) u32 cell[3]; err = fdtdec_get_int_array(blob, node, "interrupts", cell, - ARRAY_SIZE(cell)); + ARRAY_SIZE(cell)); if (err) { debug(" invalid peripheral id\n"); return PERIPH_ID_NONE; @@ -917,7 +917,7 @@ static int exynos5_pinmux_decode_periph_id(const void *blob, int node) u32 cell[3]; err = fdtdec_get_int_array(blob, node, "interrupts", cell, - ARRAY_SIZE(cell)); + ARRAY_SIZE(cell)); if (err) return PERIPH_ID_NONE; From 949f71c13eafdaf699d4cb0ecdd6fa2950d7d01f Mon Sep 17 00:00:00 2001 From: Henrik Grimler Date: Fri, 22 Aug 2025 20:54:40 +0200 Subject: [PATCH 092/103] ARM: exynos: pinmux: add newlines to debug messages To make stdout messages easier to read and understand. Signed-off-by: Henrik Grimler Signed-off-by: Minkyu Kang --- arch/arm/mach-exynos/pinmux.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/arm/mach-exynos/pinmux.c b/arch/arm/mach-exynos/pinmux.c index bd82e1ac750..ed46ea03355 100644 --- a/arch/arm/mach-exynos/pinmux.c +++ b/arch/arm/mach-exynos/pinmux.c @@ -32,7 +32,7 @@ static void exynos5_uart_config(int peripheral) count = 2; break; default: - debug("%s: invalid peripheral %d", __func__, peripheral); + debug("%s: invalid peripheral %d\n", __func__, peripheral); return; } for (i = start; i < start + count; i++) { @@ -63,7 +63,7 @@ static void exynos5420_uart_config(int peripheral) count = 2; break; default: - debug("%s: invalid peripheral %d", __func__, peripheral); + debug("%s: invalid peripheral %d\n", __func__, peripheral); return; } @@ -97,11 +97,11 @@ static int exynos5_mmc_config(int peripheral, int flags) start_ext = 0; break; default: - debug("%s: invalid peripheral %d", __func__, peripheral); + debug("%s: invalid peripheral %d\n", __func__, peripheral); return -1; } if ((flags & PINMUX_FLAG_8BIT_MODE) && !start_ext) { - debug("SDMMC device %d does not support 8bit mode", + debug("SDMMC device %d does not support 8bit mode\n", peripheral); return -1; } @@ -145,12 +145,12 @@ static int exynos5420_mmc_config(int peripheral, int flags) break; default: start = 0; - debug("%s: invalid peripheral %d", __func__, peripheral); + debug("%s: invalid peripheral %d\n", __func__, peripheral); return -1; } if ((flags & PINMUX_FLAG_8BIT_MODE) && !start_ext) { - debug("SDMMC device %d does not support 8bit mode", + debug("SDMMC device %d does not support 8bit mode\n", peripheral); return -1; } @@ -453,7 +453,7 @@ void exynos5420_spi_config(int peripheral) default: cfg = 0; pin = 0; - debug("%s: invalid peripheral %d", __func__, peripheral); + debug("%s: invalid peripheral %d\n", __func__, peripheral); return; } @@ -522,7 +522,7 @@ static int exynos5_pinmux_config(int peripheral, int flags) gpio_cfg_pin(EXYNOS5_GPIO_B20, S5P_GPIO_FUNC(2)); break; default: - debug("%s: invalid peripheral %d", __func__, peripheral); + debug("%s: invalid peripheral %d\n", __func__, peripheral); return -1; } @@ -570,7 +570,7 @@ static int exynos5420_pinmux_config(int peripheral, int flags) gpio_cfg_pin(EXYNOS5420_GPIO_B20, S5P_GPIO_FUNC(2)); break; default: - debug("%s: invalid peripheral %d", __func__, peripheral); + debug("%s: invalid peripheral %d\n", __func__, peripheral); return -1; } @@ -683,7 +683,7 @@ static void exynos4_uart_config(int peripheral) count = 2; break; default: - debug("%s: invalid peripheral %d", __func__, peripheral); + debug("%s: invalid peripheral %d\n", __func__, peripheral); return; } for (i = start; i < (start + count); i++) { @@ -797,7 +797,7 @@ static void exynos4x12_uart_config(int peripheral) count = 2; break; default: - debug("%s: invalid peripheral %d", __func__, peripheral); + debug("%s: invalid peripheral %d\n", __func__, peripheral); return; } for (i = start; i < (start + count); i++) { @@ -834,7 +834,7 @@ static int exynos4_pinmux_config(int peripheral, int flags) debug("SDMMC device %d not implemented\n", peripheral); return -1; default: - debug("%s: invalid peripheral %d", __func__, peripheral); + debug("%s: invalid peripheral %d\n", __func__, peripheral); return -1; } @@ -869,7 +869,7 @@ static int exynos4x12_pinmux_config(int peripheral, int flags) debug("SDMMC device %d not implemented\n", peripheral); return -1; default: - debug("%s: invalid peripheral %d", __func__, peripheral); + debug("%s: invalid peripheral %d\n", __func__, peripheral); return -1; } From 8705ee4b6d3665f096017aaef5c1496ba7c74cc3 Mon Sep 17 00:00:00 2001 From: Andrew Goodbody Date: Thu, 7 Aug 2025 15:41:18 +0100 Subject: [PATCH 093/103] pinctrl: rzg2l: Variable may not have been assigned to In rzg2l_pinconf_set and rzg2l_get_pin_muxing if the call to rzg2l_selector_decode fails then the variable pin may not have been assigned to. Remove the use of pin from the error message. Also update the error message to show the invalid selector used instead of port which will be the error code returned. This issue was found by Smatch. Signed-off-by: Andrew Goodbody Reviewed-by: Paul Barker Reviewed-by: Marek Vasut --- drivers/pinctrl/renesas/rzg2l-pfc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/renesas/rzg2l-pfc.c b/drivers/pinctrl/renesas/rzg2l-pfc.c index 3c751e9473a..4a75e0b2372 100644 --- a/drivers/pinctrl/renesas/rzg2l-pfc.c +++ b/drivers/pinctrl/renesas/rzg2l-pfc.c @@ -353,7 +353,7 @@ static int rzg2l_pinconf_set(struct udevice *dev, unsigned int pin_selector, /* The pin selector refers to a multiplexed pin */ int port = rzg2l_selector_decode(data, pin_selector, &pin); if (port < 0) { - dev_err(dev, "Invalid pin selector %u:%u\n", port, pin); + dev_err(dev, "Invalid pin selector %u\n", pin_selector); return port; } @@ -550,7 +550,7 @@ static int rzg2l_get_pin_muxing(struct udevice *dev, unsigned int selector, port = rzg2l_selector_decode(data, selector, &pin); if (port < 0) { - dev_err(dev, "Invalid pin selector %u:%u\n", port, pin); + dev_err(dev, "Invalid pin selector %u\n", selector); return port; } From 93c3404de9b2320bfd07cd3ce4ab0660f0d39523 Mon Sep 17 00:00:00 2001 From: Andrew Goodbody Date: Mon, 1 Sep 2025 16:13:14 +0100 Subject: [PATCH 094/103] spi: exynos: Remove extra term from test In spi_rx_tx there comes a test for execution of a code block that allows execution if rxp is not NULL or stopping is true. However all the code in this block relies on rxp being valid so allowing entry just if stopping is true does not make sense. So remove this from the test expression leaving just a NULL check for rxp. This issue was found by Smatch. Signed-off-by: Andrew Goodbody Signed-off-by: Minkyu Kang --- drivers/spi/exynos_spi.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/drivers/spi/exynos_spi.c b/drivers/spi/exynos_spi.c index 1b9bf004b7c..7f2965f8321 100644 --- a/drivers/spi/exynos_spi.c +++ b/drivers/spi/exynos_spi.c @@ -105,14 +105,10 @@ static int spi_rx_tx(struct exynos_spi_priv *priv, int todo, uint out_bytes, in_bytes; int toread; unsigned start = get_timer(0); - int stopping; int step; out_bytes = in_bytes = todo; - stopping = priv->skip_preamble && (flags & SPI_XFER_END) && - !(priv->mode & SPI_SLAVE); - /* * Try to transfer words if we can. This helps read performance at * SPI clock speeds above about 20MHz. @@ -161,12 +157,10 @@ static int spi_rx_tx(struct exynos_spi_priv *priv, int todo, while (rx_lvl >= step) { temp = readl(®s->rx_data); if (priv->skip_preamble) { - if (temp == SPI_PREAMBLE_END_BYTE) { + if (temp == SPI_PREAMBLE_END_BYTE) priv->skip_preamble = 0; - stopping = 0; - } } else { - if (rxp || stopping) { + if (rxp) { if (step == 4) *(uint32_t *)rxp = temp; else From 275978df0dfa79ef369623ef933549344e2a478c Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 3 Sep 2025 13:23:57 +0200 Subject: [PATCH 095/103] ARM: renesas: Enable CONFIG_ENV_VARS_UBOOT_CONFIG on all boards The CONFIG_ENV_VARS_UBOOT_CONFIG extends U-Boot environment with variables arch/board/board_name/soc/vendor, which can be used to discern different devices from each other based purely on U-Boot environment variables. Signed-off-by: Marek Vasut --- configs/renesas_rcar.config | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/renesas_rcar.config b/configs/renesas_rcar.config index db5846e992c..45776be62ea 100644 --- a/configs/renesas_rcar.config +++ b/configs/renesas_rcar.config @@ -18,6 +18,7 @@ CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_SPI=y CONFIG_DM_SPI_FLASH=y CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_FIT=y CONFIG_HUSH_PARSER=y CONFIG_MTD=y From b5294efd21369db75cf2176fdce93d14cd8485ca Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 3 Sep 2025 13:23:23 +0200 Subject: [PATCH 096/103] arm64: renesas: r8a779g3: Use $loadaddr in bootcmd on Retronix R-Car V4H Sparrow Hawk board Avoid use of hard-coded address in boot command, instead use $loadaddr which is the default load address. This improves consistency of the environment on this board. Signed-off-by: Marek Vasut --- configs/r8a779g3_sparrowhawk_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/r8a779g3_sparrowhawk_defconfig b/configs/r8a779g3_sparrowhawk_defconfig index 9cee4d287ef..2d1abf6f26d 100644 --- a/configs/r8a779g3_sparrowhawk_defconfig +++ b/configs/r8a779g3_sparrowhawk_defconfig @@ -18,7 +18,7 @@ CONFIG_SYS_BARGSIZE=2048 CONFIG_SYS_CBSIZE=2048 CONFIG_BAUDRATE=921600 CONFIG_BINMAN=y -CONFIG_BOOTCOMMAND="tftp 0x50000000 fitImage && bootm 0x50000000" +CONFIG_BOOTCOMMAND="tftp ${loadaddr} fitImage && bootm ${loadaddr}" CONFIG_DEFAULT_FDT_FILE="r8a779g3-sparrow-hawk.dtb" CONFIG_CMD_REMOTEPROC=y CONFIG_GPIO_HOG=y From 5138d3a561dc9441f956378aa649f7804874e8b8 Mon Sep 17 00:00:00 2001 From: Anurag Dutta Date: Mon, 1 Sep 2025 11:46:56 +0530 Subject: [PATCH 097/103] include: env: ti: Use .env for environment variables Add omap common environment variables to .env. We retain the old-style C environment .h files to maintain compatibility with other omap devices that have not moved to using .env yet. Signed-off-by: Anurag Dutta --- include/configs/ti_omap5_common.h | 228 ------------------------------ include/env/ti/dfu.env | 53 +++++++ 2 files changed, 53 insertions(+), 228 deletions(-) create mode 100644 include/env/ti/dfu.env diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index 39102f15eb9..9e02b0d0040 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -39,216 +39,6 @@ #define DFUARGS #endif -#include -#include - -#ifndef CONSOLEDEV -#define CONSOLEDEV "ttyS2" -#endif - -#ifndef PARTS_DEFAULT -/* - * Default GPT tables for eMMC (Linux and Android). Notes: - * 1. Keep partitions aligned to erase group size (512 KiB) when possible - * 2. Keep partitions in sync with DFU_ALT_INFO_EMMC (see dfu.h) - * 3. Keep 'bootloader' partition (U-Boot proper) start address in sync with - * CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR (see common/spl/Kconfig) - */ -#define PARTS_DEFAULT \ - /* Linux partitions */ \ - "uuid_disk=${uuid_gpt_disk};" \ - "name=bootloader,start=384K,size=1792K,uuid=${uuid_gpt_bootloader};" \ - "name=rootfs,start=2688K,size=-,uuid=${uuid_gpt_rootfs}\0" \ - /* Android partitions */ \ - "partitions_android=" \ - "uuid_disk=${uuid_gpt_disk};" \ - "name=xloader,start=128K,size=256K,uuid=${uuid_gpt_xloader};" \ - "name=bootloader,size=2048K,uuid=${uuid_gpt_bootloader};" \ - "name=uboot-env,start=2432K,size=256K,uuid=${uuid_gpt_reserved};" \ - "name=misc,size=128K,uuid=${uuid_gpt_misc};" \ - "name=boot_a,size=20M,uuid=${uuid_gpt_boot_a};" \ - "name=boot_b,size=20M,uuid=${uuid_gpt_boot_b};" \ - "name=dtbo_a,size=8M,uuid=${uuid_gpt_dtbo_a};" \ - "name=dtbo_b,size=8M,uuid=${uuid_gpt_dtbo_b};" \ - "name=vbmeta_a,size=64K,uuid=${uuid_gpt_vbmeta_a};" \ - "name=vbmeta_b,size=64K,uuid=${uuid_gpt_vbmeta_b};" \ - "name=recovery,size=64M,uuid=${uuid_gpt_recovery};" \ - "name=super,size=2560M,uuid=${uuid_gpt_super};" \ - "name=metadata,size=16M,uuid=${uuid_gpt_metadata};" \ - "name=userdata,size=-,uuid=${uuid_gpt_userdata}" -#endif /* PARTS_DEFAULT */ - -#if defined(CONFIG_CMD_AVB) -#define AVB_VERIFY_CHECK "if run avb_verify; then " \ - "echo AVB verification OK.;" \ - "set bootargs $bootargs $avb_bootargs;" \ - "else " \ - "echo AVB verification failed.;" \ - "exit; fi;" -#define AVB_VERIFY_CMD "avb_verify=avb init 1; avb verify $slot_suffix;\0" -#else -#define AVB_VERIFY_CHECK "" -#define AVB_VERIFY_CMD "" -#endif - -#define CONTROL_PARTITION "misc" - -#if defined(CONFIG_CMD_BCB) && defined(CONFIG_ANDROID_AB) -#define AB_SELECT_SLOT \ - "if part number mmc 1 " CONTROL_PARTITION " control_part_number; " \ - "then " \ - "echo " CONTROL_PARTITION \ - " partition number:${control_part_number};" \ - "bcb ab_select slot_name mmc ${mmcdev}:${control_part_number};" \ - "else " \ - "echo " CONTROL_PARTITION " partition not found;" \ - "exit;" \ - "fi;" \ - "setenv slot_suffix _${slot_name};" -#define AB_SELECT_ARGS \ - "setenv bootargs_ab androidboot.slot_suffix=${slot_suffix}; " \ - "echo A/B cmdline addition: ${bootargs_ab};" \ - "setenv bootargs ${bootargs} ${bootargs_ab};" -#else -#define AB_SELECT_SLOT "" -#define AB_SELECT_ARGS "" -#endif - -/* - * Prepares complete device tree blob for current board (for Android boot). - * - * Boot image or recovery image should be loaded into $loadaddr prior to running - * these commands. The logic of these commnads is next: - * - * 1. Read correct DTB for current SoC/board from boot image in $loadaddr - * to $fdtaddr - * 2. Merge all needed DTBO for current board from 'dtbo' partition into read - * DTB - * 3. User should provide $fdtaddr as 3rd argument to 'bootm' - */ -#define PREPARE_FDT \ - "echo Preparing FDT...; " \ - "if test $board_name = am57xx_evm_reva3; then " \ - "echo \" Reading DTBO partition...\"; " \ - "part start mmc ${mmcdev} dtbo${slot_suffix} p_dtbo_start; " \ - "part size mmc ${mmcdev} dtbo${slot_suffix} p_dtbo_size; " \ - "mmc read ${dtboaddr} ${p_dtbo_start} ${p_dtbo_size}; " \ - "echo \" Reading DTB for AM57x EVM RevA3...\"; " \ - "abootimg get dtb --index=0 dtb_start dtb_size; " \ - "cp.b $dtb_start $fdtaddr $dtb_size; " \ - "fdt addr $fdtaddr 0x80000; " \ - "echo \" Applying DTBOs for AM57x EVM RevA3...\"; " \ - "adtimg addr $dtboaddr; " \ - "adtimg get dt --index=0 dtbo0_addr dtbo0_size; " \ - "fdt apply $dtbo0_addr; " \ - "adtimg get dt --index=1 dtbo1_addr dtbo1_size; " \ - "fdt apply $dtbo1_addr; " \ - "elif test $board_name = beagle_x15_revc; then " \ - "echo \" Reading DTB for Beagle X15 RevC...\"; " \ - "abootimg get dtb --index=0 dtb_start dtb_size; " \ - "cp.b $dtb_start $fdtaddr $dtb_size; " \ - "fdt addr $fdtaddr 0x80000; " \ - "else " \ - "echo Error: Android boot is not supported for $board_name; " \ - "exit; " \ - "fi; " \ - -#define DEFAULT_COMMON_BOOT_TI_ARGS \ - "console=" CONSOLEDEV ",115200n8\0" \ - "fdtfile=undefined\0" \ - "finduuid=part uuid mmc 0:2 uuid\0" \ - "usbtty=cdc_acm\0" \ - "vram=16M\0" \ - AVB_VERIFY_CMD \ - "partitions=" PARTS_DEFAULT "\0" \ - "optargs=\0" \ - "dofastboot=0\0" \ - "emmc_android_boot=" \ - "setenv mmcdev 1; " \ - "mmc dev $mmcdev; " \ - "mmc rescan; " \ - AB_SELECT_SLOT \ - "if bcb load " __stringify(CONFIG_FASTBOOT_FLASH_MMC_DEV) " " \ - CONTROL_PARTITION "; then " \ - "setenv ardaddr -; " \ - "if bcb test command = bootonce-bootloader; then " \ - "echo Android: Bootloader boot...; " \ - "bcb clear command; bcb store; " \ - "fastboot 1; " \ - "exit; " \ - "elif bcb test command = boot-recovery; then " \ - "echo Android: Recovery boot...; " \ - "setenv ardaddr $loadaddr;" \ - "setenv apart recovery; " \ - "else " \ - "echo Android: Normal boot...; " \ - "setenv ardaddr $loadaddr; " \ - "setenv apart boot${slot_suffix}; " \ - "fi; " \ - "else " \ - "echo Warning: BCB is corrupted or does not exist; " \ - "echo Android: Normal boot...; " \ - "fi; " \ - "setenv eval_bootargs setenv bootargs $bootargs; " \ - "run eval_bootargs; " \ - "setenv machid fe6; " \ - AVB_VERIFY_CHECK \ - AB_SELECT_ARGS \ - "if part start mmc $mmcdev $apart boot_start; then " \ - "part size mmc $mmcdev $apart boot_size; " \ - "mmc read $loadaddr $boot_start $boot_size; " \ - PREPARE_FDT \ - "bootm $loadaddr $ardaddr $fdtaddr; " \ - "else " \ - "echo $apart partition not found; " \ - "exit; " \ - "fi;\0" - -#define DEFAULT_FDT_TI_ARGS \ - "findfdt="\ - "if test $board_name = omap5_uevm; then " \ - "setenv fdtfile omap5-uevm.dtb; fi; " \ - "if test $board_name = dra7xx; then " \ - "setenv fdtfile dra7-evm.dtb; fi;" \ - "if test $board_name = dra72x-revc; then " \ - "setenv fdtfile dra72-evm-revc.dtb; fi;" \ - "if test $board_name = dra72x; then " \ - "setenv fdtfile dra72-evm.dtb; fi;" \ - "if test $board_name = dra71x; then " \ - "setenv fdtfile dra71-evm.dtb; fi;" \ - "if test $board_name = dra76x_acd; then " \ - "setenv fdtfile dra76-evm.dtb; fi;" \ - "if test $board_name = beagle_x15; then " \ - "setenv fdtfile am57xx-beagle-x15.dtb; fi;" \ - "if test $board_name = beagle_x15_revb1; then " \ - "setenv fdtfile am57xx-beagle-x15-revb1.dtb; fi;" \ - "if test $board_name = beagle_x15_revc; then " \ - "setenv fdtfile am57xx-beagle-x15-revc.dtb; fi;" \ - "if test $board_name = am5729_beagleboneai; then " \ - "setenv fdtfile am5729-beagleboneai.dtb; fi;" \ - "if test $board_name = am572x_idk; then " \ - "setenv fdtfile am572x-idk.dtb; fi;" \ - "if test $board_name = am574x_idk; then " \ - "setenv fdtfile am574x-idk.dtb; fi;" \ - "if test $board_name = am57xx_evm; then " \ - "setenv fdtfile am57xx-beagle-x15.dtb; fi;" \ - "if test $board_name = am57xx_evm_reva3; then " \ - "setenv fdtfile am57xx-beagle-x15.dtb; fi;" \ - "if test $board_name = am571x_idk; then " \ - "setenv fdtfile am571x-idk.dtb; fi;" \ - "if test $fdtfile = undefined; then " \ - "echo WARNING: Could not determine device tree to use; fi; \0" - -#define GET_OVERLAY_MMC_TI_ARGS \ - "get_overlay_mmc=" \ - "fdt address ${fdtaddr};" \ - "fdt resize 0x100000;" \ - "for overlay in $name_overlays;" \ - "do;" \ - "load mmc ${bootpart} ${dtboaddr} ${bootdir}/dtb/${overlay} &&" \ - "fdt apply ${dtboaddr};" \ - "done;\0" \ - #define BOOT_TARGET_DEVICES(func) \ func(TI_MMC, ti_mmc, na) \ func(MMC, mmc, 0) \ @@ -265,24 +55,6 @@ #include #define CFG_EXTRA_ENV_SETTINGS \ - DEFAULT_LINUX_BOOT_ENV \ - DEFAULT_MMC_TI_ARGS \ - "bootpart=0:2\0" \ - "bootdir=/boot\0" \ - "get_name_kern=" \ - "if test $boot_fit -eq 1; then " \ - "setenv bootfile fitImage; " \ - "else " \ - "setenv bootfile zImage; " \ - "fi\0" \ - DEFAULT_FIT_TI_ARGS \ - "get_fit_config=setenv name_fit_config ${fdtfile}\0" \ - DEFAULT_COMMON_BOOT_TI_ARGS \ - DEFAULT_FDT_TI_ARGS \ - GET_OVERLAY_MMC_TI_ARGS \ - DFUARGS \ - NETARGS \ - NANDARGS \ BOOTENV /* diff --git a/include/env/ti/dfu.env b/include/env/ti/dfu.env new file mode 100644 index 00000000000..b925730c6f5 --- /dev/null +++ b/include/env/ti/dfu.env @@ -0,0 +1,53 @@ +dfu_alt_info_mmc= + boot part 0 1; + rootfs part 0 2; + MLO fat 0 1; + MLO.raw raw 0x100 0x200; + u-boot.img.raw raw 0x300 0x1000; + u-env.raw raw 0x1300 0x200; + spl-os-args.raw raw 0x1500 0x200; + spl-os-image.raw raw 0x1700 0x6900; + spl-os-args fat 0 1; + spl-os-image fat 0 1; + u-boot.img fat 0 1; + uEnv.txt fat 0 1 + +dfu_alt_info_emmc= + rawemmc raw 0 3751936; + boot part 1 1; + rootfs part 1 2; + MLO fat 1 1; + MLO.raw raw 0x100 0x200; + u-boot.img.raw raw 0x300 0x1000; + u-env.raw raw 0x1300 0x200; + spl-os-args.raw raw 0x1500 0x200; + spl-os-image.raw raw 0x1700 0x6900; + spl-os-args fat 1 1; + spl-os-image fat 1 1; + u-boot.img fat 1 1; + uEnv.txt fat 1 1 + +#if CONFIG_MTD_RAW_NAND +dfu_alt_info_nand= + SPL part 0 1; + SPL.backup1 part 0 2; + SPL.backup2 part 0 3; + SPL.backup3 part 0 4; + u-boot part 0 5; + u-boot-spl-os part 0 6; + kernel part 0 8; + rootfs part 0 9 +#endif + +dfu_alt_info_ram= + kernel ram 0x80200000 0x4000000; + fdt ram 0x80f80000 0x80000; + ramdisk ram 0x81000000 0x4000000 + +dfu_alt_info_qspi= + MLO raw 0x0 0x040000; + u-boot.img raw 0x040000 0x0100000; + u-boot-spl-os raw 0x140000 0x080000; + u-boot-env raw 0x1C0000 0x010000; + u-boot-env.backup raw 0x1D0000 0x010000; + kernel raw 0x1E0000 0x800000 From bc020bf53adca747a533a364969bc6396ef58b13 Mon Sep 17 00:00:00 2001 From: Anurag Dutta Date: Mon, 1 Sep 2025 11:46:57 +0530 Subject: [PATCH 098/103] board: ti: am57xx: Change to using .env Move to using .env file for setting up environment variables for am57xx and dra7xx. Signed-off-by: Anurag Dutta --- board/ti/am57xx/Kconfig | 12 +++ board/ti/am57xx/am57xx.env | 162 +++++++++++++++++++++++++++++++++++ include/configs/am57xx_evm.h | 19 +--- include/configs/dra7xx_evm.h | 24 ------ 4 files changed, 175 insertions(+), 42 deletions(-) create mode 100644 board/ti/am57xx/am57xx.env diff --git a/board/ti/am57xx/Kconfig b/board/ti/am57xx/Kconfig index 0c566820158..b6943938391 100644 --- a/board/ti/am57xx/Kconfig +++ b/board/ti/am57xx/Kconfig @@ -9,6 +9,18 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "am57xx_evm" +config ENV_SOURCE_FILE + default "am57xx" + +source "board/ti/common/Kconfig" + +endif + +if TARGET_DRA7XX_EVM + +config ENV_SOURCE_FILE + default "am57xx" + source "board/ti/common/Kconfig" endif diff --git a/board/ti/am57xx/am57xx.env b/board/ti/am57xx/am57xx.env new file mode 100644 index 00000000000..7d029a3e859 --- /dev/null +++ b/board/ti/am57xx/am57xx.env @@ -0,0 +1,162 @@ +#include +#include +#include + +bootpart=0:2 +bootdir=/boot +get_name_kern= + if test $boot_fit -eq 1; then + setenv bootfile fitImage; + else + setenv bootfile zImage; + fi +get_fit_config=setenv name_fit_config ${fdtfile} +console=ttyS2,115200n8 +fdtfile=undefined +finduuid=part uuid mmc 0:2 uuid +usbtty=cdc_acm +vram=16M + +#if CONFIG_CMD_AVB +avb_verify=avb init 1; avb verify $slot_suffix; +#endif + +partitions=uuid_disk=${uuid_gpt_disk}; + name=bootloader,start=384K,size=1792K,uuid=${uuid_gpt_bootloader}; + name=rootfs,start=2688K,size=-,uuid=${uuid_gpt_rootfs} + partitions_android= + uuid_disk=${uuid_gpt_disk}; + name=xloader,start=128K,size=256K,uuid=${uuid_gpt_xloader}; + name=bootloader,size=2048K,uuid=${uuid_gpt_bootloader}; + name=uboot-env,start=2432K,size=256K,uuid=${uuid_gpt_reserved}; + name=misc,size=128K,uuid=${uuid_gpt_misc}; + name=boot_a,size=20M,uuid=${uuid_gpt_boot_a}; + name=boot_b,size=20M,uuid=${uuid_gpt_boot_b}; + name=dtbo_a,size=8M,uuid=${uuid_gpt_dtbo_a}; + name=dtbo_b,size=8M,uuid=${uuid_gpt_dtbo_b}; + name=vbmeta_a,size=64K,uuid=${uuid_gpt_vbmeta_a}; + name=vbmeta_b,size=64K,uuid=${uuid_gpt_vbmeta_b}; + name=recovery,size=64M,uuid=${uuid_gpt_recovery}; + name=super,size=2560M,uuid=${uuid_gpt_super}; + name=metadata,size=16M,uuid=${uuid_gpt_metadata}; + name=userdata,size=-,uuid=${uuid_gpt_userdata} +optargs= +dofastboot=0 +emmc_android_boot= + setenv mmcdev 1; + mmc dev $mmcdev; + mmc rescan; +#if CONFIG_CMD_BCB +#if CONFIG_ANDROID_AB + if part number mmc 1 misc control_part_number; then + echo "misc partition number:${control_part_number};" + bcb ab_select slot_name mmc ${mmcdev}:${control_part_number}; + else + echo "misc partition not found;" + exit; + fi; + setenv slot_suffix _${slot_name}; +#endif +#endif +if bcb load CONFIG_FASTBOOT_FLASH_MMC_DEV misc; then + setenv ardaddr -; + if bcb test command = bootonce-bootloader; then + echo "Android: Bootloader boot..."; + bcb clear command; bcb store; + fastboot 1; + exit; + elif bcb test command = boot-recovery; then + echo "Android: Recovery boot..."; + setenv ardaddr $loadaddr; + setenv apart recovery; + else + echo "Android: Normal boot..."; + setenv ardaddr $loadaddr; + setenv apart boot${slot_suffix}; + fi; +else + echo "Warning: BCB is corrupted or does not exist"; + echo "Android: Normal boot..."; +fi; +setenv eval_bootargs setenv bootargs $bootargs; +run eval_bootargs; +setenv machid fe6; +#if CONFIG_CMD_AVB +if run avb_verify; then + echo "AVB verification OK."; + set bootargs $bootargs $avb_bootargs; +else + echo "AVB verification failed."; + exit; +fi; +#endif +#if CONFIG_CMD_BCB +#if CONFIG_ANDROID_AB +setenv bootargs_ab androidboot.slot_suffix=${slot_suffix}; +echo "A/B cmdline addition: ${bootargs_ab}"; +setenv bootargs ${bootargs} ${bootargs_ab}; +#endif +#endif +if part start mmc $mmcdev $apart boot_start; then + part size mmc $mmcdev $apart boot_size; + mmc read $loadaddr $boot_start $boot_size; + echo "Preparing FDT..."; + if test $board_name = am57xx_evm_reva3; then + echo " Reading DTBO partition..."; + part start mmc ${mmcdev} dtbo${slot_suffix} p_dtbo_start; + part size mmc ${mmcdev} dtbo${slot_suffix} p_dtbo_size; + mmc read ${dtboaddr} ${p_dtbo_start} ${p_dtbo_size}; + echo " Reading DTB for AM57x EVM RevA3..."; + abootimg get dtb --index=0 dtb_start dtb_size; + cp.b $dtb_start $fdtaddr $dtb_size; + fdt addr $fdtaddr 0x80000; + echo " Applying DTBOs for AM57x EVM RevA3..."; + adtimg addr $dtboaddr; + adtimg get dt --index=0 dtbo0_addr dtbo0_size; + fdt apply $dtbo0_addr; + adtimg get dt --index=1 dtbo1_addr dtbo1_size; + fdt apply $dtbo1_addr; + elif test $board_name = beagle_x15_revc; then + echo " Reading DTB for Beagle X15 RevC..."; + abootimg get dtb --index=0 dtb_start dtb_size; + cp.b $dtb_start $fdtaddr $dtb_size; + fdt addr $fdtaddr 0x80000; + else + echo "Error: Android boot is not supported for $board_name"; + exit; + fi; + bootm $loadaddr $ardaddr $fdtaddr; +else + echo "$apart partition not found"; + exit; +fi; +get_overlay_mmc= + fdt address ${fdtaddr}; + fdt resize 0x100000; + for overlay in $name_overlays; + do; + load mmc ${bootpart} ${dtboaddr} ${bootdir}/dtb/${overlay}; + fdt apply ${dtboaddr}; + done; +#if CONFIG_CMD_NET +static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off +nfsopts=nolock +rootpath=/export/rootfs +netloadimage=tftp ${loadaddr} ${bootfile} +netloadfdt=tftp ${fdtaddr} ${fdtfile} +netargs=setenv bootargs console=${console} ${optargs} + root=/dev/nfs + nfsroot=${serverip}:${rootpath},${nfsopts} rw + ip=dhcp +netboot=echo Booting from network ...; + setenv autoload no; + dhcp; + run netloadimage; + run netloadfdt; + run netargs; + bootz ${loadaddr} - ${fdtaddr} +#endif +#if CONFIG_MTD_RAW_NAND +#include +#endif +dfu_bufsiz=0x10000 diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h index 266b77fbf68..8c29c940478 100644 --- a/include/configs/am57xx_evm.h +++ b/include/configs/am57xx_evm.h @@ -11,30 +11,13 @@ #ifndef __CONFIG_AM57XX_EVM_H #define __CONFIG_AM57XX_EVM_H -#include #include #define CFG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */ #define CFG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ #define CFG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ -#ifndef CONFIG_XPL_BUILD -#define DFUARGS \ - "dfu_bufsiz=0x10000\0" \ - DFU_ALT_INFO_MMC \ - DFU_ALT_INFO_EMMC \ - DFU_ALT_INFO_RAM \ - DFU_ALT_INFO_QSPI -#else -#ifdef CONFIG_SPL_DFU -#define DFUARGS \ - "dfu_bufsiz=0x10000\0" \ - DFU_ALT_INFO_RAM -#endif -#endif - -#include - /* CPSW Ethernet */ +#include #endif /* __CONFIG_AM57XX_EVM_H */ diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 3c960ca2ce2..9df7ef055bf 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -11,40 +11,16 @@ #ifndef __CONFIG_DRA7XX_EVM_H #define __CONFIG_DRA7XX_EVM_H -#include - #define CFG_MAX_MEM_MAPPED 0x80000000 #ifndef CONFIG_QSPI_BOOT /* MMC ENV related defines */ #endif -#if (CONFIG_CONS_INDEX == 1) -#define CONSOLEDEV "ttyS0" -#elif (CONFIG_CONS_INDEX == 3) -#define CONSOLEDEV "ttyS2" -#endif #define CFG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */ #define CFG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ #define CFG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ -#ifndef CONFIG_XPL_BUILD -#define DFUARGS \ - "dfu_bufsiz=0x10000\0" \ - DFU_ALT_INFO_MMC \ - DFU_ALT_INFO_EMMC \ - DFU_ALT_INFO_RAM \ - DFU_ALT_INFO_QSPI -#endif - -#ifdef CONFIG_XPL_BUILD -#ifdef CONFIG_SPL_DFU -#define DFUARGS \ - "dfu_bufsiz=0x10000\0" \ - DFU_ALT_INFO_RAM -#endif -#endif - #include /* NAND support */ From 649f4a7d3ca753991c27c9c159a0aacc9954d96f Mon Sep 17 00:00:00 2001 From: Anurag Dutta Date: Mon, 1 Sep 2025 11:46:58 +0530 Subject: [PATCH 099/103] board: ti: am57xx: Set fdtfile from C code instead of findfdt script We now can provide a map and have the standard fdtfile variable set from code itself. This allows for bootstd to "just work". Signed-off-by: Anurag Dutta --- board/ti/am57xx/board.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c index fc0d87daae4..4091601d4f2 100644 --- a/board/ti/am57xx/board.c +++ b/board/ti/am57xx/board.c @@ -42,6 +42,7 @@ #include "../common/board_detect.h" #include "../common/cape_detect.h" +#include "../common/fdt_ops.h" #include "mux_data.h" #ifdef CONFIG_SUPPORT_EMMC_BOOT @@ -577,6 +578,18 @@ void do_board_detect(void) "Board: %s REV %s\n", bname, board_ti_get_rev()); } +static struct ti_fdt_map ti_omap_am57_evm_fdt_map[] = { + {"beagle_x15", "ti/omap/am57xx-beagle-x15.dtb"}, + {"beagle_x15_revb1", "ti/omap/am57xx-beagle-x15-revb1.dtb"}, + {"beagle_x15_revc", "ti/omap/am57xx-beagle-x15-revc.dtb"}, + {"am5729_beagleboneai", "ti/omap/am5729-beagleboneai.dtb"}, + {"am572x_idk", "ti/omap/am572x-idk.dtb"}, + {"am574x_idk", "ti/omap/am574x-idk.dtb"}, + {"am57xx_evm", "ti/omap/am57xx-beagle-x15.dtb"}, + {"am57xx_evm_reva3", "ti/omap/am57xx-beagle-x15.dtb"}, + {"am571x_idk", "ti/omap/am571x-idk.dtb"}, +}; + static void setup_board_eeprom_env(void) { char *name = "beagle_x15"; @@ -614,6 +627,7 @@ static void setup_board_eeprom_env(void) invalid_eeprom: set_board_info_env(name); + ti_set_fdt_env(name, ti_omap_am57_evm_fdt_map); } #endif /* CONFIG_XPL_BUILD */ From 878888fd07bab1ed97f7f0fef7f6e93269074da4 Mon Sep 17 00:00:00 2001 From: Anurag Dutta Date: Mon, 1 Sep 2025 11:46:59 +0530 Subject: [PATCH 100/103] board: ti: dra7xx: Set fdtfile from C code instead of findfdt script We now can provide a map and have the standard fdtfile variable set from code itself. This allows for bootstd to "just work". Signed-off-by: Anurag Dutta --- board/ti/dra7xx/evm.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 98d63e14e29..0966db2bb62 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -38,6 +38,7 @@ #include "mux_data.h" #include "../common/board_detect.h" +#include "../common/fdt_ops.h" #define board_is_dra76x_evm() board_ti_is("DRA76/7x") #define board_is_dra74x_evm() board_ti_is("5777xCPU") @@ -665,6 +666,15 @@ static int device_okay(const char *path) } #endif +static struct ti_fdt_map ti_omap_dra7_evm_fdt_map[] = { + {"omap5_uevm", "ti/omap/omap5-uevm.dtb"}, + {"dra7xx", "ti/omap/dra7-evm.dtb"}, + {"dra72x-revc", "ti/omap/dra72-evm-revc.dtb"}, + {"dra72x", "ti/omap/dra72-evm.dtb"}, + {"dra71x", "ti/omap/dra71-evm.dtb"}, + {"dra76x_acd", "ti/omap/dra76-evm.dtb"}, +}; + int board_late_init(void) { #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG @@ -686,6 +696,7 @@ int board_late_init(void) } set_board_info_env(name); + ti_set_fdt_env(name, ti_omap_dra7_evm_fdt_map); /* * Default FIT boot on HS devices. Non FIT images are not allowed From 8c981709e03a1bf63d6069ece02d48aab8e6ccae Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 8 Sep 2025 08:51:08 -0600 Subject: [PATCH 101/103] configs: Resync with savedefconfig Resync all defconfig files using qconfig.py Signed-off-by: Tom Rini --- configs/p3450-0000_defconfig | 10 +++++----- configs/surface-2_defconfig | 2 -- 2 files changed, 5 insertions(+), 7 deletions(-) diff --git a/configs/p3450-0000_defconfig b/configs/p3450-0000_defconfig index 3b4b863100f..2ebcf8b83fc 100644 --- a/configs/p3450-0000_defconfig +++ b/configs/p3450-0000_defconfig @@ -14,26 +14,26 @@ CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="tegra210-p3450-0000" CONFIG_SYS_BOOTM_LEN=0x800000 CONFIG_SYS_LOAD_ADDR=0x80080000 -CONFIG_HAS_BOARD_SIZE_LIMIT=y -CONFIG_BOARD_SIZE_LIMIT=753664 CONFIG_TEGRA210=y CONFIG_TARGET_P3450_0000=y CONFIG_TEGRA_GPU=y CONFIG_PCI=y +CONFIG_HAS_BOARD_SIZE_LIMIT=y +CONFIG_BOARD_SIZE_LIMIT=753664 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_SYS_PBSIZE=2089 CONFIG_CONSOLE_MUX=y CONFIG_SYS_STDIO_DEREGISTER=y CONFIG_SYS_PROMPT="Tegra210 (P3450-0000) # " +# CONFIG_BOOTM_PLAN9 is not set # CONFIG_BOOTM_RTEMS is not set # CONFIG_BOOTM_VXWORKS is not set -# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_GO is not set # CONFIG_CMD_IMI is not set # CONFIG_CRC32_VERIFY is not set CONFIG_CMD_DFU=y -# CONFIG_CMD_ELF is not set -# CONFIG_CMD_GO is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/surface-2_defconfig b/configs/surface-2_defconfig index 7b71fa2b4ea..6e287539f53 100644 --- a/configs/surface-2_defconfig +++ b/configs/surface-2_defconfig @@ -51,8 +51,6 @@ CONFIG_DTB_RESELECT=y CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 CONFIG_BUTTON=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x91000000 From bc52200ebf5ad9549081ebb65d54de6fce5ca8c5 Mon Sep 17 00:00:00 2001 From: Boon Khai Ng Date: Tue, 26 Aug 2025 11:05:05 +0800 Subject: [PATCH 102/103] MAINTAINERS: Add entry for DesignWare XGMAC driver Add a MAINTAINERS entry for the DesignWare XGMAC network driver to ensure future patches are properly routed for review and support. Signed-off-by: Boon Khai Ng Reviewed-by: Tom Rini --- drivers/net/MAINTAINERS | 6 ++++++ 1 file changed, 6 insertions(+) create mode 100644 drivers/net/MAINTAINERS diff --git a/drivers/net/MAINTAINERS b/drivers/net/MAINTAINERS new file mode 100644 index 00000000000..fd002295d0c --- /dev/null +++ b/drivers/net/MAINTAINERS @@ -0,0 +1,6 @@ +NETWORK DW XGMAC +M: Boon Khai Ng +S: Supported +F: drivers/net/dwc_eth_xgmac.c +F: drivers/net/dwc_eth_xgmac.h +F: drivers/net/dwc_eth_xgmac_socfpga.c From 7a4f3c5652157cbb3d26a7728bfe537ea483efc9 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 8 Sep 2025 10:17:59 -0600 Subject: [PATCH 103/103] Prepare v2025.10-rc4 Signed-off-by: Tom Rini --- Makefile | 2 +- doc/develop/release_cycle.rst | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index b4f10c08d75..9d2ac0c726d 100644 --- a/Makefile +++ b/Makefile @@ -3,7 +3,7 @@ VERSION = 2025 PATCHLEVEL = 10 SUBLEVEL = -EXTRAVERSION = -rc3 +EXTRAVERSION = -rc4 NAME = # *DOCUMENTATION* diff --git a/doc/develop/release_cycle.rst b/doc/develop/release_cycle.rst index ae6200a1880..daf73e207d4 100644 --- a/doc/develop/release_cycle.rst +++ b/doc/develop/release_cycle.rst @@ -77,7 +77,7 @@ For the next scheduled release, release candidates were made on:: * U-Boot |next_ver|-rc3 was released on Mon 25 August 2025. -.. * U-Boot |next_ver|-rc4 was released on Mon 08 September 2025. +* U-Boot |next_ver|-rc4 was released on Mon 08 September 2025. .. * U-Boot |next_ver|-rc5 was released on Mon 22 September 2025.