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Merge tag 'u-boot-rockchip-20250831' of https://source.denx.de/u-boot/custodians/u-boot-rockchip

Browse Source 
CI: https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/27522

- New Board support:
  rk3588 Xunlong Orange Pi 5 Ultra;
  rk3588s GameForce Ace;
  rk3576 ArmSoM Sige5;

- rk3328 soc fixes;
- usb controller and phy fixes;
- new rk3328 ddr timing;
- other board level updates;
This commit is contained in:
Tom Rini 2025-09-01 09:50:01 -06:00
commit d367be2b13
55 changed files with 1327 additions and 239 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm/dts/px30-u-boot.dtsi
View File

@ -27,6 +27,10 @@
};
};
&otp {
bootph-some-ram;
};
&uart2 {
clock-frequency = <24000000>;
bootph-all;

2
arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
View File

@ -4,7 +4,7 @@
*/
#include "rk3328-u-boot.dtsi"
#include "rk3328-sdram-ddr4-666.dtsi"
#include "rk3328-sdram-ddr4-1600.dtsi"
/ {
smbios {

226
arch/arm/dts/rk3328-sdram-ddr4-1600.dtsi Normal file
View File

@ -0,0 +1,226 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
// Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd.
&dmc {
rockchip,sdram-params = <
0x1
0xA
0x2
0x1
0x0
0x0
0x11
0x0
0x11
0x0
0
0x94496354
0x00000000
0x0000002a
0x000004e2
0x00000015
0x0000034a
0x000000ff
800
0
1
0
0
0x00000000
0x43041010
0x00000064
0x0061008c
0x000000d0
0x000200c5
0x000000d4
0x00500000
0x000000d8
0x00000100
0x000000dc
0x03140401
0x000000e0
0x00000000
0x000000e4
0x00110000
0x000000e8
0x00000420
0x000000ec
0x00000400
0x000000f4
0x000f011f
0x00000100
0x0c0e1b0e
0x00000104
0x00030314
0x00000108
0x0506050b
0x0000010c
0x0040400c
0x00000110
0x06030307
0x00000114
0x04040302
0x00000120
0x06060b06
0x00000124
0x00020308
0x00000180
0x01000040
0x00000184
0x00000000
0x00000190
0x07040003
0x00000198
0x05001100
0x000001a0
0xc0400003
0x00000240
0x0600060c
0x00000244
0x00000201
0x00000250
0x00000f00
0x00000490
0x00000001
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0x00000004
0x0000000c
0x00000028
0x0000000c
0x0000002c
0x00000000
0x00000030
0x00000009
0xffffffff
0xffffffff
0x77
0x88
0x79
0x79
0x87
0x97
0x87
0x78
0x77
0x78
0x87
0x88
0x87
0x87
0x77
0x78
0x78
0x78
0x78
0x78
0x78
0x78
0x78
0x78
0x69
0x9
0x77
0x78
0x77
0x78
0x77
0x78
0x77
0x78
0x77
0x79
0x9
0x78
0x78
0x78
0x78
0x78
0x78
0x78
0x78
0x78
0x69
0x9
0x77
0x78
0x77
0x77
0x77
0x77
0x77
0x77
0x77
0x79
0x9
0x78
0x78
0x78
0x78
0x78
0x78
0x78
0x78
0x78
0x69
0x9
0x77
0x78
0x77
0x78
0x77
0x78
0x77
0x78
0x77
0x79
0x9
0x78
0x78
0x78
0x78
0x78
0x78
0x78
0x78
0x78
0x69
0x9
0x77
0x78
0x77
0x77
0x77
0x77
0x77
0x77
0x77
0x79
0x9
>;
};

9
arch/arm/dts/rk3528-generic-u-boot.dtsi
View File

@ -1,12 +1,3 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
#include "rk3528-u-boot.dtsi"
&sdmmc {
bus-width = <4>;
cap-sd-highspeed;
disable-wp;
no-mmc;
no-sdio;
status = "okay";
};

17
arch/arm/dts/rk3528-generic.dts
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Minimal generic DT for RK3528 with eMMC enabled
* Minimal generic DT for RK3528 with eMMC and SD-card enabled
*/
/dts-v1/;
@ -10,6 +10,12 @@
model = "Generic RK3528";
compatible = "rockchip,rk3528";
aliases {
mmc0 = &sdhci;
mmc1 = &sdmmc;
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:1500000n8";
};
@ -25,6 +31,15 @@
status = "okay";
};
&sdmmc {
bus-width = <4>;
cap-sd-highspeed;
disable-wp;
no-mmc;
no-sdio;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0m0_xfer>;

13
arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi
View File

@ -6,11 +6,10 @@
mmc-hs200-1_8v;
};
&sdmmc {
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
disable-wp;
vmmc-supply = <&vcc_3v3>;
status = "okay";
&vdd_arm {
regulator-init-microvolt = <953000>;
};
&vdd_logic {
regulator-init-microvolt = <900000>;
};

18
arch/arm/dts/rk3528-u-boot.dtsi
View File

@ -27,24 +27,6 @@
compatible = "rockchip,rk3528-otp";
reg = <0x0 0xffce0000 0x0 0x4000>;
};
sdmmc: mmc@ffc30000 {
compatible = "rockchip,rk3528-dw-mshc",
"rockchip,rk3288-dw-mshc";
reg = <0x0 0xffc30000 0x0 0x4000>;
clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SRC_SDMMC0>;
clock-names = "biu", "ciu";
fifo-depth = <0x100>;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
max-frequency = <150000000>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_bus4>, <&sdmmc_clk>, <&sdmmc_cmd>,
<&sdmmc_det>;
resets = <&cru SRST_H_SDMMC0>;
reset-names = "reset";
rockchip,default-sample-phase = <90>;
status = "disabled";
};
};
};

18
arch/arm/dts/rk3576-armsom-sige5-u-boot.dtsi Normal file
View File

@ -0,0 +1,18 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
#include "rk3576-u-boot.dtsi"
/ {
aliases {
mmc0 = &sdhci;
mmc1 = &sdmmc;
};
};
&red_led {
default-state = "on";
};
&sdhci {
cap-mmc-highspeed;
};

3
arch/arm/dts/rk3576-generic-u-boot.dtsi Normal file
View File

@ -0,0 +1,3 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
#include "rk3576-u-boot.dtsi"

63
arch/arm/dts/rk3576-generic.dts Normal file
View File

@ -0,0 +1,63 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Minimal generic DT for RK3576 with eMMC, SD-card and USB OTG enabled
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "rk3576.dtsi"
/ {
model = "Generic RK3576";
compatible = "rockchip,rk3576";
aliases {
mmc0 = &sdhci;
mmc1 = &sdmmc;
};
chosen {
stdout-path = "serial0:1500000n8";
};
};
&sdhci {
bus-width = <8>;
cap-mmc-highspeed;
mmc-hs200-1_8v;
no-sd;
no-sdio;
non-removable;
status = "okay";
};
&sdmmc {
bus-width = <4>;
cap-sd-highspeed;
disable-wp;
no-mmc;
no-sdio;
status = "okay";
};
&u2phy0 {
status = "okay";
};
&u2phy0_otg {
status = "okay";
};
&uart0 {
pinctrl-0 = <&uart0m0_xfer>;
status = "okay";
};
&usb_drd0_dwc3 {
dr_mode = "peripheral";
maximum-speed = "high-speed";
phys = <&u2phy0_otg>;
phy-names = "usb2-phy";
status = "okay";
};

4
arch/arm/dts/rk3576-u-boot.dtsi
View File

@ -49,6 +49,10 @@
bootph-all;
};
&otp {
bootph-some-ram;
};
&pcfg_pull_none {
bootph-all;
};

18
arch/arm/dts/rk3588-generic-u-boot.dtsi
View File

@ -1,21 +1,3 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
#include "rk3588s-u-boot.dtsi"
&u2phy0 {
status = "okay";
};
&u2phy0_otg {
status = "okay";
};
&usbdp_phy0 {
status = "okay";
};
&usb_host0_xhci {
dr_mode = "peripheral";
maximum-speed = "high-speed";
status = "okay";
};

16
arch/arm/dts/rk3588-generic.dts
View File

@ -39,7 +39,23 @@
status = "okay";
};
&u2phy0 {
status = "okay";
};
&u2phy0_otg {
status = "okay";
};
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
status = "okay";
};
&usb_host0_xhci {
dr_mode = "peripheral";
maximum-speed = "high-speed";
phys = <&u2phy0_otg>;
phy-names = "usb2-phy";
status = "okay";
};

20
arch/arm/dts/rk3588-orangepi-5-ultra-u-boot.dtsi Normal file
View File

@ -0,0 +1,20 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
#include "rk3588-u-boot.dtsi"
&fspim1_pins {
bootph-pre-ram;
bootph-some-ram;
};
&sdhci {
cap-mmc-highspeed;
mmc-hs200-1_8v;
};
&sfc {
flash@0 {
bootph-pre-ram;
bootph-some-ram;
};
};

61
arch/arm/mach-rockchip/px30/px30.c
View File

@ -2,10 +2,14 @@
/*
* Copyright (c) 2017 Rockchip Electronics Co., Ltd
*/
#define LOG_CATEGORY LOGC_ARCH
#include <clk.h>
#include <dm.h>
#include <fdt_support.h>
#include <init.h>
#include <misc.h>
#include <spl.h>
#include <asm/armv8/mmu.h>
#include <asm/arch-rockchip/bootrom.h>
@ -15,6 +19,7 @@
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/cru_px30.h>
#include <dt-bindings/clock/px30-cru.h>
#include <linux/bitfield.h>
const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
[BROM_BOOTSOURCE_EMMC] = "/mmc@ff390000",
@ -442,3 +447,59 @@ void board_debug_uart_init(void)
#endif /* CONFIG_DEBUG_UART_BASE && CONFIG_DEBUG_UART_BASE == ... */
}
#endif /* CONFIG_DEBUG_UART_BOARD_INIT */
#define PX30_OTP_SPECIFICATION_OFFSET 0x06
#define DDR_GRF_BASE_ADDR 0xff630000
#define DDR_GRF_CON(n) (0 + (n) * 4)
int checkboard(void)
{
struct udevice *dev;
u8 specification;
u32 base_soc;
int ret;
if (!IS_ENABLED(CONFIG_ROCKCHIP_OTP) || !CONFIG_IS_ENABLED(MISC))
return 0;
ret = uclass_get_device_by_driver(UCLASS_MISC,
DM_DRIVER_GET(rockchip_otp), &dev);
if (ret) {
log_debug("Could not find otp device, ret=%d\n", ret);
return 0;
}
/* base SoC: 0x26334b52 for RK3326; 0x30335850 for PX30 */
ret = misc_read(dev, 0, &base_soc, 4);
if (ret < 0) {
log_debug("Could not read specification, ret=%d\n", ret);
return 0;
}
if (base_soc != 0x26334b52 && base_soc != 0x30335850) {
log_debug("Could not identify SoC, got 0x%04x in OTP\n", base_soc);
return 0;
}
/* SoC variant: 0x21 for PX30/PX30S/RK3326/RK3326S; 0x2b for PX30K */
ret = misc_read(dev, PX30_OTP_SPECIFICATION_OFFSET, &specification, 1);
if (ret < 0) {
log_debug("Could not read specification, ret=%d\n", ret);
return 0;
}
if (specification == 0x2b) {
printf("SoC: PX30K\n");
return 0;
}
/* From vendor kernel: drivers/soc/rockchip/rockchip-cpuinfo.c */
specification = FIELD_GET(GENMASK(15, 14),
readl(DDR_GRF_BASE_ADDR + DDR_GRF_CON(1)));
log_debug("DDR specification is %d\n", specification);
printf("SoC: %s%s\n", base_soc == 0x26334b52 ? "RK3326" : "PX30",
specification == 0x3 ? "S" : "");
return 0;
}

6
arch/arm/mach-rockchip/rk3528/rk3528.c
View File

@ -9,6 +9,9 @@
#include <asm/arch-rockchip/bootrom.h>
#include <asm/arch-rockchip/hardware.h>
#define VPU_GRF_BASE 0xff340000
#define USB3OTG_CON1 0x44
#define FIREWALL_DDR_BASE 0xff2e0000
#define FW_DDR_MST6_REG 0x58
#define FW_DDR_MST7_REG 0x5c
@ -69,6 +72,9 @@ int arch_cpu_init(void)
val = readl(FIREWALL_DDR_BASE + FW_DDR_MST16_REG);
writel(val & 0xffff0000, FIREWALL_DDR_BASE + FW_DDR_MST16_REG);
/* Disable USB3OTG U3 port, later enabled in COMBPHY driver */
writel(0xffff0181, VPU_GRF_BASE + USB3OTG_CON1);
return 0;
}

11
arch/arm/mach-rockchip/rk3576/MAINTAINERS Normal file
View File

@ -0,0 +1,11 @@
GENERIC-RK3576
M: Jonas Karlman <jonas@kwiboo.se>
S: Maintained
F: arch/arm/dts/rk3576-generic*
F: configs/generic-rk3576_defconfig
SIGE5-RK3576
M: Jonas Karlman <jonas@kwiboo.se>
S: Maintained
F: arch/arm/dts/rk3576-armsom-sige5*
F: configs/sige5-rk3576_defconfig

54
arch/arm/mach-rockchip/rk3576/rk3576.c
View File

@ -3,6 +3,10 @@
* Copyright (c) 2024 Rockchip Electronics Co., Ltd
*/
#define LOG_CATEGORY LOGC_ARCH
#include <dm.h>
#include <misc.h>
#include <asm/armv8/mmu.h>
#include <asm/arch-rockchip/bootrom.h>
#include <asm/arch-rockchip/hardware.h>
@ -29,6 +33,9 @@
#define SGRF_DOMAIN_CON4 0x10
#define SGRF_DOMAIN_CON5 0x14
#define USB_GRF_BASE 0x2601E000
#define USB3OTG0_CON1 0x0030
const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
[BROM_BOOTSOURCE_EMMC] = "/soc/mmc@2a330000",
[BROM_BOOTSOURCE_SD] = "/soc/mmc@2a310000",
@ -151,5 +158,52 @@ int arch_cpu_init(void)
*/
writel(0xffffff00, SYS_SGRF_BASE + SYS_SGRF_SOC_CON20);
/* Disable USB3OTG0 U3 port, later enabled by USBDP PHY driver */
writel(0xffff0188, USB_GRF_BASE + USB3OTG0_CON1);
return 0;
}
#define RK3576_OTP_CPU_CODE_OFFSET 0x02
#define RK3576_OTP_SPECIFICATION_OFFSET 0x08
int checkboard(void)
{
u8 cpu_code[2], specification;
struct udevice *dev;
char suffix[2];
int ret;
if (!IS_ENABLED(CONFIG_ROCKCHIP_OTP) || !CONFIG_IS_ENABLED(MISC))
return 0;
ret = uclass_get_device_by_driver(UCLASS_MISC,
DM_DRIVER_GET(rockchip_otp), &dev);
if (ret) {
log_debug("Could not find otp device, ret=%d\n", ret);
return 0;
}
/* cpu-code: SoC model, e.g. 0x35 0x76 */
ret = misc_read(dev, RK3576_OTP_CPU_CODE_OFFSET, cpu_code, 2);
if (ret < 0) {
log_debug("Could not read cpu-code, ret=%d\n", ret);
return 0;
}
/* specification: SoC variant, e.g. 0xA for RK3576J */
ret = misc_read(dev, RK3576_OTP_SPECIFICATION_OFFSET, &specification, 1);
if (ret < 0) {
log_debug("Could not read specification, ret=%d\n", ret);
return 0;
}
specification &= 0x1f;
/* for RK3576J i.e. '@' + 0xA = 'J' */
suffix[0] = specification > 1 ? '@' + specification : '\0';
suffix[1] = '\0';
printf("SoC: RK%02x%02x%s\n", cpu_code[0], cpu_code[1], suffix);
return 0;
}

18
arch/arm/mach-rockchip/rk3588/Kconfig
View File

@ -27,6 +27,23 @@ config TARGET_CM3588_NAS_RK3588
- 3.5mm Headphone out, 2.0mm PH-2A Mic in
- 5V Fan connector, PWM beeper, IR receiver, RTC battery connector
config TARGET_GAMEFORCE_ACE_RK3588S
bool "GameForce Ace"
help
The GameForce Ace is a handheld game console from GameForce with
the Rockchip RK3588S SoC.
Hardware features:
- Rockchip RK3588S SoC
- 12GB LPDDR4x RAM
- 128GB eMMC
- MicroSD card slot
- 1x USB 3.0 Type-C with DP AltMode support
- 1x HDMI 2.1 micro-HDMI out
- 1920x1080 touchscreen MIPI-DSI panel
- Analog joysticks and L/R triggers
- 16 digital buttons
config TARGET_GENBOOK_CM5_RK3588
bool "Cool Pi CM5 GenBook"
help
@ -410,6 +427,7 @@ source "board/friendlyelec/cm3588-nas-rk3588/Kconfig"
source "board/friendlyelec/nanopc-t6-rk3588/Kconfig"
source "board/friendlyelec/nanopi-r6c-rk3588s/Kconfig"
source "board/friendlyelec/nanopi-r6s-rk3588s/Kconfig"
source "board/gameforce/ace-rk3588s/Kconfig"
source "board/hardkernel/odroid_m2/Kconfig"
source "board/indiedroid/nova/Kconfig"
source "board/khadas/khadas-edge2-rk3588s/Kconfig"

8
arch/arm/mach-rockchip/rk3588/rk3588.c
View File

@ -15,6 +15,10 @@
#include <asm/arch-rockchip/hardware.h>
#include <asm/arch-rockchip/ioc_rk3588.h>
#define USB_GRF_BASE 0xfd5ac000
#define USB3OTG0_CON1 0x001c
#define USB3OTG1_CON1 0x0034
#define FIREWALL_DDR_BASE 0xfe030000
#define FW_DDR_MST5_REG 0x54
#define FW_DDR_MST13_REG 0x74
@ -184,6 +188,10 @@ int arch_cpu_init(void)
/* Disable JTAG exposed on SDMMC */
rk_clrreg(&sys_grf->soc_con[6], SYS_GRF_FORCE_JTAG);
#endif
/* Disable USB3OTG U3 ports, later enabled by USBDP PHY driver */
writel(0xffff0188, USB_GRF_BASE + USB3OTG0_CON1);
writel(0xffff0188, USB_GRF_BASE + USB3OTG1_CON1);
#endif
return 0;

9
board/gameforce/ace-rk3588s/Kconfig Normal file
View File

@ -0,0 +1,9 @@
if TARGET_GAMEFORCE_ACE_RK3588S
config SYS_BOARD
default "gameforce-ace-rk3588s"
config SYS_VENDOR
default "GameForce"
endif

5
board/gameforce/ace-rk3588s/MAINTAINERS Normal file
View File

@ -0,0 +1,5 @@
GAMEFORCE-ACE-RK3588S
M: Chris Morgan <macromorgan@hotmail.com>
S: Maintained
F: board/gameforce/ace-rk3588s/
F: configs/gameforce-ace-rk3588s_defconfig

6
board/rockchip/evb_rk3588/MAINTAINERS
View File

@ -48,3 +48,9 @@ S: Maintained
F: configs/orangepi-5-plus-rk3588_defconfig
F: arch/arm/dts/rk3588-orangepi-5-plus.dts
F: arch/arm/dts/rk3588-orangepi-5-plus-u-boot.dtsi
ORANGEPI-5-RK3588-ULTRA
M: Niu Zhihong <zhihong@nzhnb.com>
S: Maintained
F: configs/orangepi-5-ultra-rk3588_defconfig
F: arch/arm/dts/rk3588-orangepi-5-ultra-u-boot.dtsi

19
board/theobroma-systems/jaguar_rk3588/jaguar_rk3588.c
View File

@ -51,3 +51,22 @@ int rockchip_early_misc_init_r(void)
return 0;
}
#define GPIO0B7_PU_EN BIT(15)
void spl_board_init(void)
{
/*
* GPIO0_B7 is routed to CAN TX. This SoC pin has a pull-down per default.
* So on power-up, we block the CAN bus with a dominant zero. We want to keep
* this blocking time to a minimum, so we want to get this pin high in SPL.
*
* The CAN driver in Linux disables the pull-down and sets the pin to
* output high. We don't have a CAN driver in U-Boot and don't need one,
* so we just use the easiest way to get the pin high, which is setting a
* pull-up.
*/
struct rk3588_pmu2_ioc * const ioc = (void *)PMU2_IOC_BASE;
rk_setreg(&ioc->gpio0b_p, GPIO0B7_PU_EN);
}

12
board/xunlong/orangepi-5-ultra-rk3588/Kconfig Normal file
View File

@ -0,0 +1,12 @@
if TARGET_ORANGEPI_5_ULTRA_RK3588
config SYS_BOARD
default "orangepi-5-ultra-rk3588"
config SYS_VENDOR
default "xunlong"
config SYS_CONFIG_NAME
default "evb_rk3588"
endif

6
board/xunlong/orangepi-5-ultra-rk3588/MAINTAINERS Normal file
View File

@ -0,0 +1,6 @@
ORANGEPI-5-RK3588-ULTRA
M: Niu Zhihong <zhihong@nzhnb.com>
S: Maintained
F: board/xunlong/orangepi-5-rk3588-ultra
F: configs/orangepi-5-ultra-rk3588_defconfig
F: arch/arm/dts/rk3588-orangepi-5-ultra.dts

67
configs/gameforce-ace-rk3588s_defconfig Normal file
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@ -0,0 +1,67 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588s-gameforce-ace"
CONFIG_ROCKCHIP_RK3588=y
CONFIG_SPL_SERIAL=y
CONFIG_SYS_LOAD_ADDR=0xc00800
CONFIG_DEBUG_UART_BASE=0xFEB50000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-gameforce-ace.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF=y
CONFIG_CMD_MMC=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_NO_NET=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
CONFIG_BUTTON=y
CONFIG_BUTTON_ADC=y
CONFIG_BUTTON_GPIO=y
CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_MISC=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
CONFIG_PHY_ROCKCHIP_USBDP=y
CONFIG_SPL_PINCTRL=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
# CONFIG_RAM_ROCKCHIP_DEBUG is not set
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_ERRNO_STR=y

50
configs/generic-rk3576_defconfig Normal file
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@ -0,0 +1,50 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_DEFAULT_DEVICE_TREE="rk3576-generic"
CONFIG_ROCKCHIP_RK3576=y
CONFIG_SYS_LOAD_ADDR=0x40c00800
CONFIG_DEBUG_UART_BASE=0x2AD40000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
# CONFIG_BOOTMETH_VBE is not set
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3576-generic.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_MAX_SIZE=0x40000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMINFO_MAP=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MISC=y
CONFIG_CMD_MMC=y
CONFIG_CMD_ROCKUSB=y
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_RNG=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_OF_UPSTREAM is not set
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_NO_NET=y
# CONFIG_ADC is not set
# CONFIG_USB_FUNCTION_FASTBOOT is not set
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET_PSCI=y
CONFIG_USB=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_FUNCTION_ROCKUSB=y
CONFIG_ERRNO_STR=y

1
configs/generic-rk3588_defconfig
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@ -53,7 +53,6 @@ CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_USBDP=y
CONFIG_SPL_PINCTRL=y
CONFIG_SPL_RAM=y
CONFIG_BAUDRATE=1500000

2
configs/jaguar-rk3588_defconfig
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@ -27,6 +27,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-jaguar.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_CYCLIC=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF=y
# CONFIG_BOOTM_NETBSD is not set
@ -34,6 +35,7 @@ CONFIG_SPL_ATF=y
# CONFIG_BOOTM_RTEMS is not set
# CONFIG_BOOTM_VXWORKS is not set
# CONFIG_CMD_ELF is not set
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_ADC=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y

7
configs/nanopi-r5s-rk3568_defconfig
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@ -28,6 +28,8 @@ CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
CONFIG_CMD_ROCKUSB=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
# CONFIG_SPL_DOS_PARTITION is not set
@ -38,6 +40,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_CLK=y
# CONFIG_USB_FUNCTION_FASTBOOT is not set
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
@ -73,4 +76,8 @@ CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_SPL_USB_DWC3_GENERIC=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_FUNCTION_ROCKUSB=y
CONFIG_ERRNO_STR=y

88
configs/orangepi-5-ultra-rk3588_defconfig Normal file
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@ -0,0 +1,88 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SF_DEFAULT_SPEED=80000000
CONFIG_SF_DEFAULT_MODE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588-orangepi-5-ultra"
CONFIG_ROCKCHIP_RK3588=y
CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_SPL_SERIAL=y
CONFIG_TARGET_EVB_RK3588=y
CONFIG_SYS_LOAD_ADDR=0xc00800
CONFIG_SF_DEFAULT_BUS=5
CONFIG_DEBUG_UART_BASE=0xFEB50000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_PCI=y
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-orangepi-5-ultra.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_REGULATOR=y
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
CONFIG_AHCI_PCI=y
CONFIG_DWC_AHCI=y
CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_XMC=y
CONFIG_PHYLIB=y
CONFIG_RTL8169=y
CONFIG_NVME_PCI=y
CONFIG_PCIE_DW_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
CONFIG_PHY_ROCKCHIP_USBDP=y
CONFIG_SPL_PINCTRL=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
CONFIG_SCSI=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_ROCKCHIP_SFC=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_ERRNO_STR=y

1
configs/puma-rk3399_defconfig
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@ -36,6 +36,7 @@ CONFIG_TPL_GPIO=y
# CONFIG_BOOTM_RTEMS is not set
# CONFIG_CMD_VBE is not set
# CONFIG_BOOTM_VXWORKS is not set
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y

10
configs/radxa-e20c-rk3528_defconfig
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@ -20,6 +20,8 @@ CONFIG_CMD_GPT=y
CONFIG_CMD_MISC=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_ROCKUSB=y
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_RNG=y
CONFIG_CMD_REGULATOR=y
@ -28,6 +30,7 @@ CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigne
CONFIG_BUTTON=y
CONFIG_BUTTON_ADC=y
CONFIG_BUTTON_GPIO=y
# CONFIG_USB_FUNCTION_FASTBOOT is not set
CONFIG_ROCKCHIP_GPIO=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
@ -43,6 +46,7 @@ CONFIG_DM_MDIO=y
CONFIG_DWC_ETH_QOS=y
CONFIG_DWC_ETH_QOS_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
CONFIG_REGULATOR_PWM=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_PWM_ROCKCHIP=y
@ -50,6 +54,12 @@ CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_FUNCTION_ROCKUSB=y
CONFIG_ERRNO_STR=y

1
configs/ringneck-px30_defconfig
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@ -40,6 +40,7 @@ CONFIG_SPL_ATF=y
# CONFIG_CMD_VBE is not set
# CONFIG_BOOTM_VXWORKS is not set
# CONFIG_CMD_ELF is not set
CONFIG_CMD_ERASEENV=y
# CONFIG_CMD_LZMADEC is not set
# CONFIG_CMD_UNZIP is not set
CONFIG_CMD_BIND=y

66
configs/sige5-rk3576_defconfig Normal file
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@ -0,0 +1,66 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3576-armsom-sige5"
CONFIG_ROCKCHIP_RK3576=y
CONFIG_SYS_LOAD_ADDR=0x40c00800
CONFIG_DEBUG_UART_BASE=0x2AD40000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_PCI=y
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3576-armsom-sige5.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_MAX_SIZE=0x40000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMINFO_MAP=y
CONFIG_CMD_ADC=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MISC=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
CONFIG_CMD_ROCKUSB=y
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_RNG=y
CONFIG_CMD_REGULATOR=y
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
# CONFIG_USB_FUNCTION_FASTBOOT is not set
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_PHY_REALTEK=y
CONFIG_DWC_ETH_QOS=y
CONFIG_DWC_ETH_QOS_ROCKCHIP=y
CONFIG_NVME_PCI=y
CONFIG_PCIE_DW_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
CONFIG_PHY_ROCKCHIP_USBDP=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET_PSCI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_FUNCTION_ROCKUSB=y
CONFIG_ERRNO_STR=y

1
configs/tiger-rk3588_defconfig
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@ -35,6 +35,7 @@ CONFIG_SPL_ATF=y
# CONFIG_BOOTM_RTEMS is not set
# CONFIG_BOOTM_VXWORKS is not set
# CONFIG_CMD_ELF is not set
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_ADC=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y

4
doc/board/rockchip/rockchip.rst
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@ -134,7 +134,9 @@ List of mainline supported Rockchip boards:
- Radxa ROCK 3B (rock-3b-rk3568)
* rk3576
- ArmSoM Sige5 (sige5-rk3576)
- Firefly ROC-RK3576-PC (roc-pc-rk3576)
- Generic RK3576 (generic-rk3576)
* rk3588
- ArmSoM Sige7 (sige7-rk3588)
@ -145,6 +147,7 @@ List of mainline supported Rockchip boards:
- FriendlyElec NanoPC-T6 (nanopc-t6-rk3588)
- FriendlyElec NanoPi R6C (nanopi-r6c-rk3588s)
- FriendlyElec NanoPi R6S (nanopi-r6s-rk3588s)
- GameForce Ace (gameforce-ace-rk3588s)
- Generic RK3588S/RK3588 (generic-rk3588)
- Hardkernel ODROID-M2 (odroid-m2-rk3588s)
- Indiedroid Nova (nova-rk3588s)
@ -161,6 +164,7 @@ List of mainline supported Rockchip boards:
- Xunlong Orange Pi 5 (orangepi-5-rk3588s)
- Xunlong Orange Pi 5 Max (orangepi-5-max-rk3588)
- Xunlong Orange Pi 5 Plus (orangepi-5-plus-rk3588)
- Xunlong Orange Pi 5 Ultra (orangepi-5-ultra-rk3588)
- Yanyi Tech CoolPi 4 Model B (coolpi-4b-rk3588s)
- Yanyi Tech CoolPi CM5 EVB (coolpi-cm5-evb-rk3588)
- Yanyi Tech CoolPi CM5 GenBook (coolpi-cm5-genbook-rk3588)

1
drivers/clk/rockchip/clk_rk3528.c
View File

@ -1535,6 +1535,7 @@ static ulong rk3528_clk_set_rate(struct clk *clk, ulong rate)
/* Might occur in cru assigned-clocks, can be ignored here */
case ACLK_BUS_VOPGL_ROOT:
case BCLK_EMMC:
case CLK_REF_PCIE_INNER_PHY:
case XIN_OSC0_DIV:
ret = 0;
break;

2
drivers/clk/rockchip/clk_rk3576.c
View File

@ -2168,6 +2168,8 @@ static ulong rk3576_clk_set_rate(struct clk *clk, ulong rate)
case CLK_CPLL_DIV10:
case FCLK_DDR_CM0_CORE:
case ACLK_PHP_ROOT:
case CLK_REF_PCIE0_PHY:
case CLK_REF_PCIE1_PHY:
ret = 0;
break;
#ifndef CONFIG_SPL_BUILD

2
drivers/mmc/rockchip_sdhci.c
View File

@ -500,7 +500,7 @@ static int rockchip_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
{
struct rockchip_sdhc *priv = dev_get_priv(mmc->dev);
struct sdhci_host *host = &priv->host;
char tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT;
s8 tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT;
struct mmc_cmd cmd;
u32 ctrl, blk_size;
int ret;

47
drivers/phy/rockchip/phy-rockchip-inno-usb2.c
View File

@ -167,20 +167,27 @@ static struct phy_ops rockchip_usb2phy_ops = {
.of_xlate = rockchip_usb2phy_of_xlate,
};
static void rockchip_usb2phy_clkout_ctl(struct clk *clk, struct regmap **base,
const struct usb2phy_reg **clkout_ctl)
static int rockchip_usb2phy_clkout_ctl(struct clk *clk, struct regmap **base,
const struct usb2phy_reg **clkout_ctl)
{
struct udevice *parent = dev_get_parent(clk->dev);
struct rockchip_usb2phy *priv = dev_get_priv(parent);
const struct rockchip_usb2phy_cfg *phy_cfg = priv->phy_cfg;
if (priv->phy_cfg->clkout_ctl_phy.enable) {
// phy_cfg can be NULL if this function called before probe (when parent
// clocks are enabled)
if (!phy_cfg)
return -EINVAL;
if (phy_cfg->clkout_ctl_phy.enable) {
*base = priv->phy_base;
*clkout_ctl = &phy_cfg->clkout_ctl_phy;
} else {
*base = priv->reg_base;
*clkout_ctl = &phy_cfg->clkout_ctl;
}
return 0;
}
/**
@ -206,7 +213,8 @@ int rockchip_usb2phy_clk_enable(struct clk *clk)
const struct usb2phy_reg *clkout_ctl;
struct regmap *base;
rockchip_usb2phy_clkout_ctl(clk, &base, &clkout_ctl);
if (rockchip_usb2phy_clkout_ctl(clk, &base, &clkout_ctl))
return -ENOSYS;
/* turn on 480m clk output if it is off */
if (!property_enabled(base, clkout_ctl)) {
@ -230,7 +238,8 @@ int rockchip_usb2phy_clk_disable(struct clk *clk)
const struct usb2phy_reg *clkout_ctl;
struct regmap *base;
rockchip_usb2phy_clkout_ctl(clk, &base, &clkout_ctl);
if (rockchip_usb2phy_clkout_ctl(clk, &base, &clkout_ctl))
return -ENOSYS;
/* turn off 480m clk output */
property_enable(base, clkout_ctl, false);
@ -456,6 +465,28 @@ static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = {
{ /* sentinel */ }
};
static const struct rockchip_usb2phy_cfg rk3576_phy_cfgs[] = {
{
.reg = 0x0000,
.clkout_ctl = { 0x0008, 0, 0, 1, 0 },
.port_cfgs = {
[USB2PHY_PORT_OTG] = {
.phy_sus = { 0x0000, 1, 0, 2, 1 },
}
},
},
{
.reg = 0x2000,
.clkout_ctl = { 0x2008, 0, 0, 1, 0 },
.port_cfgs = {
[USB2PHY_PORT_OTG] = {
.phy_sus = { 0x2000, 1, 0, 2, 1 },
}
},
},
{ /* sentinel */ }
};
static const struct rockchip_usb2phy_cfg rk3588_phy_cfgs[] = {
{
.reg = 0x0000,
@ -517,6 +548,10 @@ static const struct udevice_id rockchip_usb2phy_ids[] = {
.compatible = "rockchip,rk3568-usb2phy",
.data = (ulong)&rk3568_phy_cfgs,
},
{
.compatible = "rockchip,rk3576-usb2phy",
.data = (ulong)&rk3576_phy_cfgs,
},
{
.compatible = "rockchip,rk3588-usb2phy",
.data = (ulong)&rk3588_phy_cfgs,
@ -538,7 +573,7 @@ U_BOOT_DRIVER(rockchip_usb2phy_clock) = {
U_BOOT_DRIVER(rockchip_usb2phy) = {
.name = "rockchip_usb2phy",
.id = UCLASS_PHY,
.id = UCLASS_NOP,
.of_match = rockchip_usb2phy_ids,
.probe = rockchip_usb2phy_probe,
.bind = rockchip_usb2phy_bind,

378
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
View File

@ -37,6 +37,7 @@ struct rockchip_combphy_grfcfg {
struct combphy_reg pipe_rxterm_set;
struct combphy_reg pipe_txelec_set;
struct combphy_reg pipe_txcomp_set;
struct combphy_reg pipe_clk_24m;
struct combphy_reg pipe_clk_25m;
struct combphy_reg pipe_clk_100m;
struct combphy_reg pipe_phymode_sel;
@ -98,89 +99,6 @@ static int param_write(struct regmap *base,
return regmap_write(base, reg->offset, val);
}
static int rockchip_combphy_pcie_init(struct rockchip_combphy_priv *priv)
{
int ret = 0;
if (priv->cfg->combphy_cfg) {
ret = priv->cfg->combphy_cfg(priv);
if (ret) {
dev_err(priv->dev, "failed to init phy for pcie\n");
return ret;
}
}
return ret;
}
static int rockchip_combphy_usb3_init(struct rockchip_combphy_priv *priv)
{
int ret = 0;
if (priv->cfg->combphy_cfg) {
ret = priv->cfg->combphy_cfg(priv);
if (ret) {
dev_err(priv->dev, "failed to init phy for usb3\n");
return ret;
}
}
return ret;
}
static int rockchip_combphy_sata_init(struct rockchip_combphy_priv *priv)
{
int ret = 0;
if (priv->cfg->combphy_cfg) {
ret = priv->cfg->combphy_cfg(priv);
if (ret) {
dev_err(priv->dev, "failed to init phy for sata\n");
return ret;
}
}
return ret;
}
static int rockchip_combphy_sgmii_init(struct rockchip_combphy_priv *priv)
{
int ret = 0;
if (priv->cfg->combphy_cfg) {
ret = priv->cfg->combphy_cfg(priv);
if (ret) {
dev_err(priv->dev, "failed to init phy for sgmii\n");
return ret;
}
}
return ret;
}
static int rockchip_combphy_set_mode(struct rockchip_combphy_priv *priv)
{
switch (priv->mode) {
case PHY_TYPE_PCIE:
rockchip_combphy_pcie_init(priv);
break;
case PHY_TYPE_USB3:
rockchip_combphy_usb3_init(priv);
break;
case PHY_TYPE_SATA:
rockchip_combphy_sata_init(priv);
break;
case PHY_TYPE_SGMII:
case PHY_TYPE_QSGMII:
return rockchip_combphy_sgmii_init(priv);
default:
dev_err(priv->dev, "incompatible PHY type\n");
return -EINVAL;
}
return 0;
}
static int rockchip_combphy_init(struct phy *phy)
{
struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev);
@ -190,12 +108,32 @@ static int rockchip_combphy_init(struct phy *phy)
if (ret < 0 && ret != -ENOSYS)
return ret;
ret = rockchip_combphy_set_mode(priv);
switch (priv->mode) {
case PHY_TYPE_PCIE:
case PHY_TYPE_USB3:
case PHY_TYPE_SATA:
case PHY_TYPE_SGMII:
case PHY_TYPE_QSGMII:
if (priv->cfg->combphy_cfg)
ret = priv->cfg->combphy_cfg(priv);
else
ret = 0;
break;
default:
dev_err(priv->dev, "incompatible PHY type\n");
ret = -EINVAL;
break;
}
if (ret) {
dev_err(priv->dev, "failed to init phy for phy type %x\n", priv->mode);
goto err_clk;
}
ret = reset_deassert_bulk(&priv->phy_rsts);
if (ret)
goto err_clk;
reset_deassert_bulk(&priv->phy_rsts);
return 0;
err_clk:
@ -223,6 +161,7 @@ static int rockchip_combphy_xlate(struct phy *phy, struct ofnode_phandle_args *a
return -EINVAL;
}
phy->id = priv->id;
priv->mode = args->args[0];
return 0;
@ -237,22 +176,19 @@ static const struct phy_ops rockchip_combphy_ops = {
static int rockchip_combphy_parse_dt(struct udevice *dev,
struct rockchip_combphy_priv *priv)
{
struct udevice *syscon;
int ret;
ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pipe-grf", &syscon);
if (ret) {
dev_err(dev, "failed to find peri_ctrl pipe-grf regmap");
return ret;
priv->pipe_grf = syscon_regmap_lookup_by_phandle(dev, "rockchip,pipe-grf");
if (IS_ERR(priv->pipe_grf)) {
dev_err(dev, "failed to find peri_ctrl pipe-grf regmap\n");
return PTR_ERR(priv->pipe_grf);
}
priv->pipe_grf = syscon_get_regmap(syscon);
ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pipe-phy-grf", &syscon);
if (ret) {
priv->phy_grf = syscon_regmap_lookup_by_phandle(dev, "rockchip,pipe-phy-grf");
if (IS_ERR(priv->phy_grf)) {
dev_err(dev, "failed to find peri_ctrl pipe-phy-grf regmap\n");
return ret;
return PTR_ERR(priv->phy_grf);
}
priv->phy_grf = syscon_get_regmap(syscon);
ret = clk_get_by_index(dev, 0, &priv->ref_clk);
if (ret) {
@ -304,12 +240,109 @@ static int rockchip_combphy_probe(struct udevice *udev)
}
priv->dev = udev;
priv->mode = PHY_TYPE_SATA;
priv->mode = PHY_NONE;
priv->cfg = phy_cfg;
return rockchip_combphy_parse_dt(udev, priv);
}
static int rk3528_combphy_cfg(struct rockchip_combphy_priv *priv)
{
const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
u32 val;
switch (priv->mode) {
case PHY_TYPE_PCIE:
/* Set SSC downward spread spectrum */
val = readl(priv->mmio + 0x18);
val &= ~GENMASK(5, 4);
val |= 0x01 << 4;
writel(val, priv->mmio + 0x18);
param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
break;
case PHY_TYPE_USB3:
/* Set SSC downward spread spectrum */
val = readl(priv->mmio + 0x18);
val &= ~GENMASK(5, 4);
val |= 0x01 << 4;
writel(val, priv->mmio + 0x18);
/* Enable adaptive CTLE for USB3.0 Rx */
val = readl(priv->mmio + 0x200);
val &= ~GENMASK(17, 17);
val |= 0x01 << 17;
writel(val, priv->mmio + 0x200);
/* Set Rx squelch input filler bandwidth */
val = readl(priv->mmio + 0x20c);
val &= ~GENMASK(2, 0);
val |= 0x06;
writel(val, priv->mmio + 0x20c);
param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
param_write(priv->phy_grf, &cfg->usb_mode_set, true);
param_write(priv->pipe_grf, &cfg->u3otg0_port_en, true);
break;
default:
dev_err(priv->dev, "incompatible PHY type\n");
return -EINVAL;
}
param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
if (priv->mode == PHY_TYPE_PCIE) {
/* PLL KVCO tuning fine */
val = readl(priv->mmio + 0x18);
val &= ~(0x7 << 10);
val |= 0x2 << 10;
writel(val, priv->mmio + 0x18);
/* su_trim[6:4]=111, [10:7]=1001, [2:0]=000 */
val = readl(priv->mmio + 0x108);
val &= ~(0x7f7);
val |= 0x4f0;
writel(val, priv->mmio + 0x108);
}
return 0;
}
static const struct rockchip_combphy_grfcfg rk3528_combphy_grfcfgs = {
/* pipe-phy-grf */
.pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 },
.usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 },
.pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 },
.pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 },
.pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 },
.pipe_clk_24m = { 0x0004, 14, 13, 0x00, 0x00 },
.pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 },
.pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 },
.pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 },
.pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 },
.pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 },
.pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 },
.con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x110 },
.con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x00 },
.con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x101 },
.con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 },
/* pipe-grf */
.u3otg0_port_en = { 0x0044, 15, 0, 0x0181, 0x1100 },
};
static const struct rockchip_combphy_cfg rk3528_combphy_cfgs = {
.num_phys = 1,
.phy_ids = {
0xffdc0000,
},
.grfcfg = &rk3528_combphy_grfcfgs,
.combphy_cfg = rk3528_combphy_cfg,
};
static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
{
const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
@ -453,6 +486,149 @@ static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = {
.combphy_cfg = rk3568_combphy_cfg,
};
static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv)
{
const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
u32 val;
switch (priv->mode) {
case PHY_TYPE_PCIE:
param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
break;
case PHY_TYPE_USB3:
/* Set SSC downward spread spectrum */
val = readl(priv->mmio + (0x1f << 2));
val &= ~GENMASK(5, 4);
val |= 0x01 << 4;
writel(val, priv->mmio + 0x7c);
/* Enable adaptive CTLE for USB3.0 Rx */
val = readl(priv->mmio + (0x0e << 2));
val &= ~GENMASK(0, 0);
val |= 0x01;
writel(val, priv->mmio + (0x0e << 2));
/* Set PLL KVCO fine tuning signals */
val = readl(priv->mmio + (0x20 << 2));
val &= ~(0x7 << 2);
val |= 0x2 << 2;
writel(val, priv->mmio + (0x20 << 2));
/* Set PLL LPF R1 to su_trim[10:7]=1001 */
writel(0x4, priv->mmio + (0xb << 2));
/* Set PLL input clock divider 1/2 */
val = readl(priv->mmio + (0x5 << 2));
val &= ~(0x3 << 6);
val |= 0x1 << 6;
writel(val, priv->mmio + (0x5 << 2));
/* Set PLL loop divider */
writel(0x32, priv->mmio + (0x11 << 2));
/* Set PLL KVCO to min and set PLL charge pump current to max */
writel(0xf0, priv->mmio + (0xa << 2));
/* Set Rx squelch input filler bandwidth */
writel(0x0d, priv->mmio + (0x14 << 2));
param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
param_write(priv->phy_grf, &cfg->usb_mode_set, true);
param_write(priv->pipe_grf, &cfg->u3otg1_port_en, true);
break;
case PHY_TYPE_SATA:
/* Enable adaptive CTLE for SATA Rx */
val = readl(priv->mmio + (0x0e << 2));
val &= ~GENMASK(0, 0);
val |= 0x01;
writel(val, priv->mmio + (0x0e << 2));
/* Set tx_rterm = 50 ohm and rx_rterm = 43.5 ohm */
writel(0x8F, priv->mmio + (0x06 << 2));
param_write(priv->phy_grf, &cfg->con0_for_sata, true);
param_write(priv->phy_grf, &cfg->con1_for_sata, true);
param_write(priv->phy_grf, &cfg->con2_for_sata, true);
param_write(priv->phy_grf, &cfg->con3_for_sata, true);
param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true);
param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true);
break;
case PHY_TYPE_SGMII:
case PHY_TYPE_QSGMII:
default:
dev_err(priv->dev, "incompatible PHY type\n");
return -EINVAL;
}
/* 100MHz refclock signal is good */
clk_set_rate(&priv->ref_clk, 100000000);
param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
if (priv->mode == PHY_TYPE_PCIE) {
/* gate_tx_pck_sel length select work for L1SS */
writel(0xc0, priv->mmio + 0x74);
/* PLL KVCO tuning fine */
val = readl(priv->mmio + (0x20 << 2));
val &= ~(0x7 << 2);
val |= 0x2 << 2;
writel(val, priv->mmio + (0x20 << 2));
/* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */
writel(0x4c, priv->mmio + (0x1b << 2));
/* Set up su_trim: T3_P1 650mv */
writel(0x90, priv->mmio + (0xa << 2));
writel(0x43, priv->mmio + (0xb << 2));
writel(0x88, priv->mmio + (0xc << 2));
writel(0x56, priv->mmio + (0xd << 2));
}
return 0;
}
static const struct rockchip_combphy_grfcfg rk3576_combphy_grfcfgs = {
/* pipe-phy-grf */
.pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 },
.usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 },
.pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 },
.pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 },
.pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 },
.pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 },
.pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 },
.pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 },
.pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 },
.pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 },
.pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 },
.pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 },
.pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 },
.pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 },
.con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 },
.con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 },
.con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 },
.con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 },
.con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0129 },
.con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0000 },
.con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c1 },
.con3_for_sata = { 0x000c, 15, 0, 0x00, 0x0407 },
/* php-grf */
.pipe_con0_for_sata = { 0x001C, 2, 0, 0x00, 0x2 },
.pipe_con1_for_sata = { 0x0020, 2, 0, 0x00, 0x2 },
.u3otg1_port_en = { 0x0038, 15, 0, 0x0181, 0x1100 },
};
static const struct rockchip_combphy_cfg rk3576_combphy_cfgs = {
.num_phys = 2,
.phy_ids = {
0x2b050000,
0x2b060000,
},
.grfcfg = &rk3576_combphy_grfcfgs,
.combphy_cfg = rk3576_combphy_cfg,
};
static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv)
{
const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
@ -560,10 +736,18 @@ static const struct rockchip_combphy_cfg rk3588_combphy_cfgs = {
};
static const struct udevice_id rockchip_combphy_ids[] = {
{
.compatible = "rockchip,rk3528-naneng-combphy",
.data = (ulong)&rk3528_combphy_cfgs
},
{
.compatible = "rockchip,rk3568-naneng-combphy",
.data = (ulong)&rk3568_combphy_cfgs
},
{
.compatible = "rockchip,rk3576-naneng-combphy",
.data = (ulong)&rk3576_combphy_cfgs
},
{
.compatible = "rockchip,rk3588-naneng-combphy",
.data = (ulong)&rk3588_combphy_cfgs

2
drivers/phy/rockchip/phy-rockchip-typec.c
View File

@ -788,7 +788,7 @@ U_BOOT_DRIVER(rockchip_tcphy_usb3_port) = {
U_BOOT_DRIVER(rockchip_typec_phy) = {
.name = "rockchip_typec_phy",
.id = UCLASS_PHY,
.id = UCLASS_NOP,
.of_match = rockchip_typec_phy_ids,
.probe = rockchip_tcphy_probe,
.bind = rockchip_tcphy_bind,

101
drivers/phy/rockchip/phy-rockchip-usbdp.c
View File

@ -96,9 +96,7 @@ struct rockchip_udphy {
/* PHY status management */
bool flip;
bool mode_change;
u8 mode;
u8 status;
/* utilized for USB */
bool hs; /* flag for high-speed */
@ -525,80 +523,26 @@ static int udphy_parse_dt(struct rockchip_udphy *udphy, struct udevice *dev)
return 0;
}
static int udphy_power_on(struct rockchip_udphy *udphy, u8 mode)
{
int ret;
if (!(udphy->mode & mode)) {
dev_info(udphy->dev, "mode 0x%02x is not support\n", mode);
return 0;
}
if (udphy->status == UDPHY_MODE_NONE) {
udphy->mode_change = false;
ret = udphy_setup(udphy);
if (ret)
return ret;
if (udphy->mode & UDPHY_MODE_USB)
udphy_u3_port_disable(udphy, false);
} else if (udphy->mode_change) {
udphy->mode_change = false;
udphy->status = UDPHY_MODE_NONE;
if (udphy->mode == UDPHY_MODE_DP)
udphy_u3_port_disable(udphy, true);
ret = udphy_disable(udphy);
if (ret)
return ret;
ret = udphy_setup(udphy);
if (ret)
return ret;
}
udphy->status |= mode;
return 0;
}
static int udphy_power_off(struct rockchip_udphy *udphy, u8 mode)
{
int ret;
if (!(udphy->mode & mode)) {
dev_info(udphy->dev, "mode 0x%02x is not supported\n", mode);
return 0;
}
if (!udphy->status)
return 0;
udphy->status &= ~mode;
if (udphy->status == UDPHY_MODE_NONE) {
ret = udphy_disable(udphy);
if (ret)
return ret;
}
return 0;
}
static int rockchip_u3phy_of_xlate(struct phy *phy,
struct ofnode_phandle_args *args)
{
struct rockchip_udphy *udphy = dev_get_priv(phy->dev);
if (args->args_count == 0)
return -EINVAL;
if (args->args[0] != PHY_TYPE_USB3)
return -EINVAL;
phy->id = udphy->id;
return 0;
}
static int rockchip_u3phy_init(struct phy *phy)
{
struct rockchip_udphy *udphy = dev_get_priv(phy->dev);
int ret;
/* DP only or high-speed, disable U3 port */
if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) {
@ -606,7 +550,12 @@ static int rockchip_u3phy_init(struct phy *phy)
return 0;
}
return udphy_power_on(udphy, UDPHY_MODE_USB);
ret = udphy_setup(udphy);
if (ret)
return ret;
udphy_u3_port_disable(udphy, false);
return 0;
}
static int rockchip_u3phy_exit(struct phy *phy)
@ -617,7 +566,7 @@ static int rockchip_u3phy_exit(struct phy *phy)
if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs)
return 0;
return udphy_power_off(udphy, UDPHY_MODE_USB);
return udphy_disable(udphy);
}
static const struct phy_ops rockchip_u3phy_ops = {
@ -813,6 +762,28 @@ static const char * const rk3588_udphy_rst_l[] = {
"init", "cmn", "lane", "pcs_apb", "pma_apb"
};
static const struct rockchip_udphy_cfg rk3576_udphy_cfgs = {
.num_phys = 1,
.phy_ids = {
0x2b010000,
},
.num_rsts = ARRAY_SIZE(rk3588_udphy_rst_l),
.rst_list = rk3588_udphy_rst_l,
.grfcfg = {
/* u2phy-grf */
.bvalid_phy_con = { 0x0010, 1, 0, 0x2, 0x3 },
.bvalid_grf_con = { 0x0000, 15, 14, 0x1, 0x3 },
/* usb-grf */
.usb3otg0_cfg = { 0x0030, 15, 0, 0x1100, 0x0188 },
/* usbdpphy-grf */
.low_pwrn = { 0x0004, 13, 13, 0, 1 },
.rx_lfps = { 0x0004, 14, 14, 0, 1 },
},
.combophy_init = rk3588_udphy_init,
};
static const struct rockchip_udphy_cfg rk3588_udphy_cfgs = {
.num_phys = 2,
.phy_ids = {
@ -838,6 +809,10 @@ static const struct rockchip_udphy_cfg rk3588_udphy_cfgs = {
};
static const struct udevice_id rockchip_udphy_dt_match[] = {
{
.compatible = "rockchip,rk3576-usbdp-phy",
.data = (ulong)&rk3576_udphy_cfgs
},
{
.compatible = "rockchip,rk3588-usbdp-phy",
.data = (ulong)&rk3588_udphy_cfgs

21
drivers/power/pmic/rk8xx.c
View File

@ -89,11 +89,6 @@ void rk8xx_off_for_plugin(struct udevice *dev)
}
}
static struct reg_data rk806_init_reg[] = {
/* RST_FUN */
{ RK806_REG_SYS_CFG3, BIT(7), GENMASK(7, 6)},
};
static struct reg_data rk817_init_reg[] = {
/* enable the under-voltage protection,
* the under-voltage protection will shutdown the LDO3 and reset the PMIC
@ -306,12 +301,20 @@ static int rk8xx_probe(struct udevice *dev)
value = (power_en2 & 0x0f) | ((power_en3 & 0x0f) << 4);
pmic_reg_write(dev, RK817_POWER_EN_SAVE1, value);
break;
case RK806_ID:
case RK806_ID: {
u32 rst_fun = 2;
on_source = RK806_ON_SOURCE;
off_source = RK806_OFF_SOURCE;
init_data = rk806_init_reg;
init_data_num = ARRAY_SIZE(rk806_init_reg);
break;
ret = dev_read_u32(dev, "rockchip,reset-mode", &rst_fun);
if (ret)
debug("rockchip,reset-mode property missing, defaulting to %d\n",
rst_fun);
pmic_clrsetbits(dev, RK806_REG_SYS_CFG3, RK806_RST_FUN_MSK,
FIELD_PREP(RK806_RST_FUN_MSK, rst_fun));
break; }
default:
printf("Unknown PMIC: RK%x!!\n", show_variant);
return -EINVAL;

4
drivers/rng/rockchip_rng.c
View File

@ -393,6 +393,10 @@ static const struct udevice_id rockchip_rng_match[] = {
.compatible = "rockchip,rk3588-rng",
.data = (ulong)&rk_trngv1_soc_data,
},
{
.compatible = "rockchip,rk3576-rng",
.data = (ulong)&rkrng_soc_data,
},
{
.compatible = "rockchip,rkrng",
.data = (ulong)&rkrng_soc_data,

2
drivers/usb/dwc3/dwc3-generic.c
View File

@ -698,7 +698,9 @@ static const struct udevice_id dwc3_glue_ids[] = {
{ .compatible = "ti,am654-dwc3" },
{ .compatible = "rockchip,rk3328-dwc3", .data = (ulong)&rk_ops },
{ .compatible = "rockchip,rk3399-dwc3" },
{ .compatible = "rockchip,rk3528-dwc3", .data = (ulong)&rk_ops },
{ .compatible = "rockchip,rk3568-dwc3", .data = (ulong)&rk_ops },
{ .compatible = "rockchip,rk3576-dwc3", .data = (ulong)&rk_ops },
{ .compatible = "rockchip,rk3588-dwc3", .data = (ulong)&rk_ops },
{ .compatible = "qcom,dwc3", .data = (ulong)&qcom_ops },
{ .compatible = "fsl,imx8mp-dwc3", .data = (ulong)&imx8mp_ops },

14
drivers/usb/gadget/Kconfig
View File

@ -86,6 +86,7 @@ config USB_GADGET_PRODUCT_NUM
default 0x350a if ROCKCHIP_RK3568
default 0x350b if ROCKCHIP_RK3588
default 0x350c if ROCKCHIP_RK3528
default 0x350e if ROCKCHIP_RK3576
default 0x0
help
Product ID of the USB device emulated, reported to the host device.
@ -201,12 +202,13 @@ config USB_FUNCTION_MASS_STORAGE
the eMMC/SD card content to HOST PC so it can be mounted.
config USB_FUNCTION_ROCKUSB
bool "Enable USB rockusb gadget"
help
Rockusb protocol is widely used by Rockchip SoC based devices. It can
read/write info, image to/from devices. This enables the USB part of
the rockusb gadget.for more detail about Rockusb protocol, please see
doc/README.rockusb
bool "Enable USB rockusb gadget"
depends on ARCH_ROCKCHIP
help
Rockusb protocol is widely used by Rockchip SoC based devices. It can
read/write info, image to/from devices. This enables the USB part of
the rockusb gadget.for more detail about Rockusb protocol, please see
doc/README.rockusb
config USB_FUNCTION_SDP
bool "Enable USB SDP (Serial Download Protocol)"

21
dts/upstream/Bindings/mfd/rockchip,rk806.yaml
View File

@ -31,6 +31,27 @@ properties:
system-power-controller: true
rockchip,reset-mode:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2]
description:
Mode to use when a reset of the PMIC is triggered.
The reset can be triggered either programmatically, via one of
the PWRCTRL pins (provided additional configuration) or
asserting RESETB pin low.
The following modes are supported
- 0; restart PMU,
- 1; reset all power off reset registers and force state to
switch to ACTIVE mode,
- 2; same as mode 1 and also pull RESETB pin down for 5ms,
For example, some hardware may require a full restart (mode 0)
in order to function properly as regulators are shortly
interrupted in this mode.
vcc1-supply:
description:
The input supply for dcdc-reg1.

2
dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts
View File

@ -10,6 +10,7 @@
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/soc/rockchip,vop2.h>
#include <dt-bindings/usb/pd.h>
#include "rk8xx.h"
#include "rk3588.dtsi"
/ {
@ -693,6 +694,7 @@
vcc13-supply = <&vcc_1v1_nldo_s3>;
vcc14-supply = <&vcc_1v1_nldo_s3>;
vcca-supply = <&vcc5v0_sys>;
rockchip,reset-mode = <RK806_RESTART>;
rk806_dvs1_null: dvs1-null-pins {
pins = "gpio_pwrctrl1";

2
dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi
View File

@ -6,6 +6,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include "rk8xx.h"
#include "rk3588.dtsi"
/ {
@ -440,6 +441,7 @@
vcc13-supply = <&vcc_1v1_nldo_s3>;
vcc14-supply = <&vcc_1v1_nldo_s3>;
vcca-supply = <&vcc5v0_sys>;
rockchip,reset-mode = <RK806_RESTART>;
rk806_dvs1_null: dvs1-null-pins {
pins = "gpio_pwrctrl1";

18
dts/upstream/src/arm64/rockchip/rk8xx.h Normal file
View File

@ -0,0 +1,18 @@
/* SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) */
/*
* Device Tree defines for Rockchip RK8xx PMICs
*
* Copyright 2025 Cherry Embedded Solutions GmbH
*
* Author: Quentin Schulz <quentin.schulz@cherry.de>
*/
#ifndef _DT_MFD_ROCKCHIP_RK8XX_H
#define _DT_MFD_ROCKCHIP_RK8XX_H
/* For use with rockchip,reset-mode property */
#define RK806_RESTART 0
#define RK806_RESET 1
#define RK806_RESET_NOTIFY 2
#endif

3
include/configs/rk3288_common.h
View File

@ -18,7 +18,8 @@
#define ENV_MEM_LAYOUT_SETTINGS \
"scriptaddr=0x00000000\0" \
"pxefile_addr_r=0x00100000\0" \
"fdt_addr_r=0x01f00000\0" \
"fdt_addr_r=0x01e00000\0" \
"fdtoverlay_addr_r=0x01f00000\0" \
"kernel_addr_r=0x02000000\0" \
"ramdisk_addr_r=0x04000000\0"

2
include/power/rk8xx_pmic.h
View File

@ -212,6 +212,8 @@ enum {
#define RK817_POWER_EN_SAVE0 0x99
#define RK817_POWER_EN_SAVE1 0xa4
#define RK806_RST_FUN_MSK GENMASK(7, 6)
#define RK806_POWER_EN(x) (0x00 + (x))
/* POWER_ENx register lower 4 bits are write-protected unless the associated top bit is set */
#define RK806_POWER_EN_CLRSETBITS(bit, val) (((val) << (bit)) | (1 << ((bit) + 4)))