From 1848a504379531eb726d29b355f9038d194e8430 Mon Sep 17 00:00:00 2001 From: Alex Shumsky Date: Thu, 3 Jul 2025 09:04:48 +0300 Subject: [PATCH 01/50] rockchip: rockchip-inno-usb2: Fix Synchronous Abort on usb start Fix NULL pointer dereference that happen when rockchip-inno-usb2 clock enabled before device probe. This early clock enable call happen in process of parent clock activation added in ac30d90f3367. Fixes: 229218373c22 ("phy: rockchip-inno-usb2: Add support for clkout_ctl_phy"). Fixes: ac30d90f3367 ("clk: Ensure the parent clocks are enabled while reparenting") Co-authored-by: Jonas Karlman Signed-off-by: Alex Shumsky Reviewed-by: Jonas Karlman Reviewed-by: Kever Yang --- drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c index 88b33de1b2a..3cc5956aed5 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c @@ -167,20 +167,27 @@ static struct phy_ops rockchip_usb2phy_ops = { .of_xlate = rockchip_usb2phy_of_xlate, }; -static void rockchip_usb2phy_clkout_ctl(struct clk *clk, struct regmap **base, - const struct usb2phy_reg **clkout_ctl) +static int rockchip_usb2phy_clkout_ctl(struct clk *clk, struct regmap **base, + const struct usb2phy_reg **clkout_ctl) { struct udevice *parent = dev_get_parent(clk->dev); struct rockchip_usb2phy *priv = dev_get_priv(parent); const struct rockchip_usb2phy_cfg *phy_cfg = priv->phy_cfg; - if (priv->phy_cfg->clkout_ctl_phy.enable) { + // phy_cfg can be NULL if this function called before probe (when parent + // clocks are enabled) + if (!phy_cfg) + return -EINVAL; + + if (phy_cfg->clkout_ctl_phy.enable) { *base = priv->phy_base; *clkout_ctl = &phy_cfg->clkout_ctl_phy; } else { *base = priv->reg_base; *clkout_ctl = &phy_cfg->clkout_ctl; } + + return 0; } /** @@ -206,7 +213,8 @@ int rockchip_usb2phy_clk_enable(struct clk *clk) const struct usb2phy_reg *clkout_ctl; struct regmap *base; - rockchip_usb2phy_clkout_ctl(clk, &base, &clkout_ctl); + if (rockchip_usb2phy_clkout_ctl(clk, &base, &clkout_ctl)) + return -ENOSYS; /* turn on 480m clk output if it is off */ if (!property_enabled(base, clkout_ctl)) { @@ -230,7 +238,8 @@ int rockchip_usb2phy_clk_disable(struct clk *clk) const struct usb2phy_reg *clkout_ctl; struct regmap *base; - rockchip_usb2phy_clkout_ctl(clk, &base, &clkout_ctl); + if (rockchip_usb2phy_clkout_ctl(clk, &base, &clkout_ctl)) + return -ENOSYS; /* turn off 480m clk output */ property_enable(base, clkout_ctl, false); From 2390eb8b614e4dc038bc41706821b275c367d55d Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Tue, 10 Jun 2025 11:42:50 +0200 Subject: [PATCH 02/50] rockchip: px30/rk3326: Implement checkboard() to print SoC variant This implements checkboard() to print the current SoC model used by a board, e.g. one of: SoC: PX30 SoC: PX30S SoC: PX30K SoC: RK3326 SoC: RK3326S when U-Boot proper is running. The information is read from the OTP and also the DDR_GRF. There's no public information as far as I know about the layout and stored information on OTP but this was provided by Rockchip themselves through their support channel. The OTP stores the information of whether the SoC is PX30K or something else. To differentiate between PX30/RK3326 and PX30S/RK3326S, one needs to read some undocumented bitfield in a DDR_GRF register as done in vendor kernel, c.f. https://github.com/armbian/linux-rockchip/blob/rk-6.1-rkr5.1/drivers/soc/rockchip/rockchip-cpuinfo.c#L118-L133. I do not own a PX30S, nor RK3326/RK3326S so cannot test it works properly. Also add the OTP node to the pre-relocation phase of U-Boot proper so that the SoC variant can be printed when DISPLAY_BOARDINFO is enabled. This is not required if DISPLAY_BOARDINFO_LATE is enabled because this happens after relocation. If both are enabled, then the SoC variant will be printed twice in the boot log, e.g.: U-Boot 2025.07-rc3-00014-g7cb731574ae6-dirty (May 28 2025 - 13:52:47 +0200) Model: Theobroma Systems PX30-uQ7 SoM on Haikou devkit SoC: PX30 <---- due to DISPLAY_BOARDINFO DRAM: 2 GiB PMIC: RK809 (on=0x40, off=0x00) Core: 293 devices, 27 uclasses, devicetree: separate MMC: mmc@ff370000: 1, mmc@ff390000: 0 Loading Environment from MMC... Reading from MMC(1)... OK In: serial@ff030000 Out: serial@ff030000 Err: serial@ff030000 Model: Theobroma Systems PX30-uQ7 SoM on Haikou devkit SoC: PX30 <----- due to DISPLAY_BOARDINFO_LATE Net: eth0: ethernet@ff360000 Signed-off-by: Quentin Schulz Reviewed-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/px30-u-boot.dtsi | 4 ++ arch/arm/mach-rockchip/px30/px30.c | 61 ++++++++++++++++++++++++++++++ 2 files changed, 65 insertions(+) diff --git a/arch/arm/dts/px30-u-boot.dtsi b/arch/arm/dts/px30-u-boot.dtsi index 157d0ea6930..2f726b0aaba 100644 --- a/arch/arm/dts/px30-u-boot.dtsi +++ b/arch/arm/dts/px30-u-boot.dtsi @@ -27,6 +27,10 @@ }; }; +&otp { + bootph-some-ram; +}; + &uart2 { clock-frequency = <24000000>; bootph-all; diff --git a/arch/arm/mach-rockchip/px30/px30.c b/arch/arm/mach-rockchip/px30/px30.c index 8ce9ac561f0..5a5c119328f 100644 --- a/arch/arm/mach-rockchip/px30/px30.c +++ b/arch/arm/mach-rockchip/px30/px30.c @@ -2,10 +2,14 @@ /* * Copyright (c) 2017 Rockchip Electronics Co., Ltd */ + +#define LOG_CATEGORY LOGC_ARCH + #include #include #include #include +#include #include #include #include @@ -15,6 +19,7 @@ #include #include #include +#include const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { [BROM_BOOTSOURCE_EMMC] = "/mmc@ff390000", @@ -442,3 +447,59 @@ void board_debug_uart_init(void) #endif /* CONFIG_DEBUG_UART_BASE && CONFIG_DEBUG_UART_BASE == ... */ } #endif /* CONFIG_DEBUG_UART_BOARD_INIT */ + +#define PX30_OTP_SPECIFICATION_OFFSET 0x06 + +#define DDR_GRF_BASE_ADDR 0xff630000 +#define DDR_GRF_CON(n) (0 + (n) * 4) + +int checkboard(void) +{ + struct udevice *dev; + u8 specification; + u32 base_soc; + int ret; + + if (!IS_ENABLED(CONFIG_ROCKCHIP_OTP) || !CONFIG_IS_ENABLED(MISC)) + return 0; + + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_DRIVER_GET(rockchip_otp), &dev); + if (ret) { + log_debug("Could not find otp device, ret=%d\n", ret); + return 0; + } + + /* base SoC: 0x26334b52 for RK3326; 0x30335850 for PX30 */ + ret = misc_read(dev, 0, &base_soc, 4); + if (ret < 0) { + log_debug("Could not read specification, ret=%d\n", ret); + return 0; + } + + if (base_soc != 0x26334b52 && base_soc != 0x30335850) { + log_debug("Could not identify SoC, got 0x%04x in OTP\n", base_soc); + return 0; + } + + /* SoC variant: 0x21 for PX30/PX30S/RK3326/RK3326S; 0x2b for PX30K */ + ret = misc_read(dev, PX30_OTP_SPECIFICATION_OFFSET, &specification, 1); + if (ret < 0) { + log_debug("Could not read specification, ret=%d\n", ret); + return 0; + } + + if (specification == 0x2b) { + printf("SoC: PX30K\n"); + return 0; + } + + /* From vendor kernel: drivers/soc/rockchip/rockchip-cpuinfo.c */ + specification = FIELD_GET(GENMASK(15, 14), + readl(DDR_GRF_BASE_ADDR + DDR_GRF_CON(1))); + log_debug("DDR specification is %d\n", specification); + printf("SoC: %s%s\n", base_soc == 0x26334b52 ? "RK3326" : "PX30", + specification == 0x3 ? "S" : ""); + + return 0; +} From 9d98a6b9803d9989528d320ad71d607914378d9e Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Mon, 9 Jun 2025 22:06:16 -0500 Subject: [PATCH 03/50] rockchip: Add support for GameForce Ace The GameForce Ace is an RK3588S based handheld gaming device. Signed-off-by: Chris Morgan Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/rk3588/Kconfig | 18 +++++++ board/gameforce/ace-rk3588s/Kconfig | 9 ++++ board/gameforce/ace-rk3588s/MAINTAINERS | 5 ++ configs/gameforce-ace-rk3588s_defconfig | 67 +++++++++++++++++++++++++ doc/board/rockchip/rockchip.rst | 1 + 5 files changed, 100 insertions(+) create mode 100644 board/gameforce/ace-rk3588s/Kconfig create mode 100644 board/gameforce/ace-rk3588s/MAINTAINERS create mode 100644 configs/gameforce-ace-rk3588s_defconfig diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig index 4e7942ada87..9fbe3f225aa 100644 --- a/arch/arm/mach-rockchip/rk3588/Kconfig +++ b/arch/arm/mach-rockchip/rk3588/Kconfig @@ -27,6 +27,23 @@ config TARGET_CM3588_NAS_RK3588 - 3.5mm Headphone out, 2.0mm PH-2A Mic in - 5V Fan connector, PWM beeper, IR receiver, RTC battery connector +config TARGET_GAMEFORCE_ACE_RK3588S + bool "GameForce Ace" + help + The GameForce Ace is a handheld game console from GameForce with + the Rockchip RK3588S SoC. + + Hardware features: + - Rockchip RK3588S SoC + - 12GB LPDDR4x RAM + - 128GB eMMC + - MicroSD card slot + - 1x USB 3.0 Type-C with DP AltMode support + - 1x HDMI 2.1 micro-HDMI out + - 1920x1080 touchscreen MIPI-DSI panel + - Analog joysticks and L/R triggers + - 16 digital buttons + config TARGET_GENBOOK_CM5_RK3588 bool "Cool Pi CM5 GenBook" help @@ -410,6 +427,7 @@ source "board/friendlyelec/cm3588-nas-rk3588/Kconfig" source "board/friendlyelec/nanopc-t6-rk3588/Kconfig" source "board/friendlyelec/nanopi-r6c-rk3588s/Kconfig" source "board/friendlyelec/nanopi-r6s-rk3588s/Kconfig" +source "board/gameforce/ace-rk3588s/Kconfig" source "board/hardkernel/odroid_m2/Kconfig" source "board/indiedroid/nova/Kconfig" source "board/khadas/khadas-edge2-rk3588s/Kconfig" diff --git a/board/gameforce/ace-rk3588s/Kconfig b/board/gameforce/ace-rk3588s/Kconfig new file mode 100644 index 00000000000..52f98ccf897 --- /dev/null +++ b/board/gameforce/ace-rk3588s/Kconfig @@ -0,0 +1,9 @@ +if TARGET_GAMEFORCE_ACE_RK3588S + +config SYS_BOARD + default "gameforce-ace-rk3588s" + +config SYS_VENDOR + default "GameForce" + +endif diff --git a/board/gameforce/ace-rk3588s/MAINTAINERS b/board/gameforce/ace-rk3588s/MAINTAINERS new file mode 100644 index 00000000000..dc18e7c8849 --- /dev/null +++ b/board/gameforce/ace-rk3588s/MAINTAINERS @@ -0,0 +1,5 @@ +GAMEFORCE-ACE-RK3588S +M: Chris Morgan +S: Maintained +F: board/gameforce/ace-rk3588s/ +F: configs/gameforce-ace-rk3588s_defconfig diff --git a/configs/gameforce-ace-rk3588s_defconfig b/configs/gameforce-ace-rk3588s_defconfig new file mode 100644 index 00000000000..ec725a8df40 --- /dev/null +++ b/configs/gameforce-ace-rk3588s_defconfig @@ -0,0 +1,67 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588s-gameforce-ace" +CONFIG_ROCKCHIP_RK3588=y +CONFIG_SPL_SERIAL=y +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_DEBUG_UART_BASE=0xFEB50000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-gameforce-ace.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_ATF=y +CONFIG_CMD_MMC=y +# CONFIG_CMD_SETEXPR is not set +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_NO_NET=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_BUTTON=y +CONFIG_BUTTON_ADC=y +CONFIG_BUTTON_GPIO=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MISC=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_PHY_ROCKCHIP_USBDP=y +CONFIG_SPL_PINCTRL=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +# CONFIG_RAM_ROCKCHIP_DEBUG is not set +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SPI=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_ERRNO_STR=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index b88299cbba2..a2d8a715a4b 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -145,6 +145,7 @@ List of mainline supported Rockchip boards: - FriendlyElec NanoPC-T6 (nanopc-t6-rk3588) - FriendlyElec NanoPi R6C (nanopi-r6c-rk3588s) - FriendlyElec NanoPi R6S (nanopi-r6s-rk3588s) + - GameForce Ace (gameforce-ace-rk3588s) - Generic RK3588S/RK3588 (generic-rk3588) - Hardkernel ODROID-M2 (odroid-m2-rk3588s) - Indiedroid Nova (nova-rk3588s) From d48f063a5385a1bd79f048810826c823d09be8ec Mon Sep 17 00:00:00 2001 From: Da Xue Date: Tue, 10 Jun 2025 19:08:19 +0000 Subject: [PATCH 04/50] ram: rk3328: add ddr4-1600 sdram timing Add DDR4 1600MHz SDRAM timing data from LibreComputer u-boot sources for the ROC-3328-CC board. Signed-off-by: Da Xue Signed-off-by: Christian Hewitt Reviewed-by: Kever Yang --- arch/arm/dts/rk3328-sdram-ddr4-1600.dtsi | 226 +++++++++++++++++++++++ 1 file changed, 226 insertions(+) create mode 100644 arch/arm/dts/rk3328-sdram-ddr4-1600.dtsi diff --git a/arch/arm/dts/rk3328-sdram-ddr4-1600.dtsi b/arch/arm/dts/rk3328-sdram-ddr4-1600.dtsi new file mode 100644 index 00000000000..9594bb42839 --- /dev/null +++ b/arch/arm/dts/rk3328-sdram-ddr4-1600.dtsi @@ -0,0 +1,226 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd. + +&dmc { + rockchip,sdram-params = < + 0x1 + 0xA + 0x2 + 0x1 + 0x0 + 0x0 + 0x11 + 0x0 + 0x11 + 0x0 + 0 + + 0x94496354 + 0x00000000 + 0x0000002a + 0x000004e2 + 0x00000015 + 0x0000034a + 0x000000ff + + 800 + 0 + 1 + 0 + 0 + + 0x00000000 + 0x43041010 + 0x00000064 + 0x0061008c + 0x000000d0 + 0x000200c5 + 0x000000d4 + 0x00500000 + 0x000000d8 + 0x00000100 + 0x000000dc + 0x03140401 + 0x000000e0 + 0x00000000 + 0x000000e4 + 0x00110000 + 0x000000e8 + 0x00000420 + 0x000000ec + 0x00000400 + 0x000000f4 + 0x000f011f + 0x00000100 + 0x0c0e1b0e + 0x00000104 + 0x00030314 + 0x00000108 + 0x0506050b + 0x0000010c + 0x0040400c + 0x00000110 + 0x06030307 + 0x00000114 + 0x04040302 + 0x00000120 + 0x06060b06 + 0x00000124 + 0x00020308 + 0x00000180 + 0x01000040 + 0x00000184 + 0x00000000 + 0x00000190 + 0x07040003 + 0x00000198 + 0x05001100 + 0x000001a0 + 0xc0400003 + 0x00000240 + 0x0600060c + 0x00000244 + 0x00000201 + 0x00000250 + 0x00000f00 + 0x00000490 + 0x00000001 + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + + 0x00000004 + 0x0000000c + 0x00000028 + 0x0000000c + 0x0000002c + 0x00000000 + 0x00000030 + 0x00000009 + 0xffffffff + 0xffffffff + + 0x77 + 0x88 + 0x79 + 0x79 + 0x87 + 0x97 + 0x87 + 0x78 + 0x77 + 0x78 + 0x87 + 0x88 + 0x87 + 0x87 + 0x77 + + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x69 + 0x9 + + 0x77 + 0x78 + 0x77 + 0x78 + 0x77 + 0x78 + 0x77 + 0x78 + 0x77 + 0x79 + 0x9 + + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x69 + 0x9 + + 0x77 + 0x78 + 0x77 + 0x77 + 0x77 + 0x77 + 0x77 + 0x77 + 0x77 + 0x79 + 0x9 + + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x69 + 0x9 + + 0x77 + 0x78 + 0x77 + 0x78 + 0x77 + 0x78 + 0x77 + 0x78 + 0x77 + 0x79 + 0x9 + + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x69 + 0x9 + + 0x77 + 0x78 + 0x77 + 0x77 + 0x77 + 0x77 + 0x77 + 0x77 + 0x77 + 0x79 + 0x9 + >; +}; From 578e168387dace1e4d146d8b7c8570b18dec238e Mon Sep 17 00:00:00 2001 From: Da Xue Date: Tue, 10 Jun 2025 19:08:20 +0000 Subject: [PATCH 05/50] arm64: dts: rockchip: roc-3328-cc: use 1600 ddr4 timing Swap the ROC-3328-CC from DDR4 666 to 1600 timing to boost performance. Signed-off-by: Da Xue Signed-off-by: Christian Hewitt Reviewed-by: Kever Yang --- arch/arm/dts/rk3328-roc-cc-u-boot.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi b/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi index 582d6ba49b4..c47d29c59de 100644 --- a/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi +++ b/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi @@ -4,7 +4,7 @@ */ #include "rk3328-u-boot.dtsi" -#include "rk3328-sdram-ddr4-666.dtsi" +#include "rk3328-sdram-ddr4-1600.dtsi" / { smbios { From 571244f5749e493ffc9dae5aad1445e0a6ed0572 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 1 Jul 2025 19:03:45 -0600 Subject: [PATCH 06/50] usb: gadget: rockchip: Add missing dependency The rockchip usb gadget driver cannot build without platform specific headers being available. Express that requirement in Kconfig as well. Signed-off-by: Tom Rini Reviewed-by: Quentin Schulz Reviewed-by: Kever Yang --- drivers/usb/gadget/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index 46a83141481..b0decd7b251 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -202,6 +202,7 @@ config USB_FUNCTION_MASS_STORAGE config USB_FUNCTION_ROCKUSB bool "Enable USB rockusb gadget" + depends on ARCH_ROCKCHIP help Rockusb protocol is widely used by Rockchip SoC based devices. It can read/write info, image to/from devices. This enables the USB part of From 9bd3fc8cd976e66b869e243d22fe37d836bbf318 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 1 Jul 2025 19:03:46 -0600 Subject: [PATCH 07/50] usb: gadget: rockchip: Fix spacing around the Kconfig option This Kconfig option used spaces and not tabs for indentation. Switch to tabs. Signed-off-by: Tom Rini Reviewed-by: Quentin Schulz Reviewed-by: Kever Yang --- drivers/usb/gadget/Kconfig | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index b0decd7b251..6201663317b 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -201,13 +201,13 @@ config USB_FUNCTION_MASS_STORAGE the eMMC/SD card content to HOST PC so it can be mounted. config USB_FUNCTION_ROCKUSB - bool "Enable USB rockusb gadget" + bool "Enable USB rockusb gadget" depends on ARCH_ROCKCHIP - help - Rockusb protocol is widely used by Rockchip SoC based devices. It can - read/write info, image to/from devices. This enables the USB part of - the rockusb gadget.for more detail about Rockusb protocol, please see - doc/README.rockusb + help + Rockusb protocol is widely used by Rockchip SoC based devices. It can + read/write info, image to/from devices. This enables the USB part of + the rockusb gadget.for more detail about Rockusb protocol, please see + doc/README.rockusb config USB_FUNCTION_SDP bool "Enable USB SDP (Serial Download Protocol)" From d079cdbc53026dca2c4209ee71c883de7fe0cc14 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Fri, 1 Aug 2025 20:32:37 +0000 Subject: [PATCH 08/50] rng: rockchip_rng: Add compatible for RK3576 The RK3576 SoC contains a RKRNG block that can be used to generate random numbers using the rockchip_rng driver. Add compatible for RK3576 to support random numbers: => rng list RNG #0 - rng@2a410000 => rng 00000000: 36 dd ab 98 ec fb fe d1 cf 36 b3 e1 9b 3d 00 90 6........6...=.. 00000010: f5 84 de 75 6b 27 48 9e 13 62 12 6c 50 ca 47 1a ...uk'H..b.lP.G. 00000020: b3 4d fc 43 c5 b5 2d be 07 27 03 26 bb 69 61 2a .M.C..-..'.&.ia* 00000030: 6f 70 01 83 4e ce 91 7a 5a 6c 7c 00 43 87 3e c5 op..N..zZl|.C.>. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- drivers/rng/rockchip_rng.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/rng/rockchip_rng.c b/drivers/rng/rockchip_rng.c index d854ea90044..8cf750e043c 100644 --- a/drivers/rng/rockchip_rng.c +++ b/drivers/rng/rockchip_rng.c @@ -393,6 +393,10 @@ static const struct udevice_id rockchip_rng_match[] = { .compatible = "rockchip,rk3588-rng", .data = (ulong)&rk_trngv1_soc_data, }, + { + .compatible = "rockchip,rk3576-rng", + .data = (ulong)&rkrng_soc_data, + }, { .compatible = "rockchip,rkrng", .data = (ulong)&rkrng_soc_data, From dd2c7df419ae8a5cc5f7ee0480218b0ae28d4926 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Fri, 1 Aug 2025 20:32:38 +0000 Subject: [PATCH 09/50] rockchip: Add default USB_GADGET_PRODUCT_NUM for RK3576 Use 0x350e as the default USB Product ID for Rockchip RK3576, same PID being used by the BootROM when the device is in MASKROM mode. Signed-off-by: Jonas Karlman Reviewed-by: Mattijs Korpershoek Reviewed-by: Kever Yang --- drivers/usb/gadget/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index 6201663317b..0121f9872ae 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -86,6 +86,7 @@ config USB_GADGET_PRODUCT_NUM default 0x350a if ROCKCHIP_RK3568 default 0x350b if ROCKCHIP_RK3588 default 0x350c if ROCKCHIP_RK3528 + default 0x350e if ROCKCHIP_RK3576 default 0x0 help Product ID of the USB device emulated, reported to the host device. From 108d9f11ea928a80976db80b5ff723ce8170ebe1 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Fri, 1 Aug 2025 20:32:39 +0000 Subject: [PATCH 10/50] board: rockchip: Add minimal generic RK3576 board Add a minimal generic RK3576 board that only have eMMC, SDMMC and USB OTG enabled. This defconfig can be used to boot from eMMC or SD-card on most RK3576 boards that follow reference board design. eMMC and SD-card boot tested on: - ArmSoM CM5 - ArmSoM Sige5 - FriendlyElec NanoPi M5 - Luckfox Omni3576 - Toybrick TB-RK3576D Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rk3576-generic-u-boot.dtsi | 3 ++ arch/arm/dts/rk3576-generic.dts | 63 +++++++++++++++++++++++ arch/arm/mach-rockchip/rk3576/MAINTAINERS | 5 ++ configs/generic-rk3576_defconfig | 50 ++++++++++++++++++ doc/board/rockchip/rockchip.rst | 1 + 5 files changed, 122 insertions(+) create mode 100644 arch/arm/dts/rk3576-generic-u-boot.dtsi create mode 100644 arch/arm/dts/rk3576-generic.dts create mode 100644 arch/arm/mach-rockchip/rk3576/MAINTAINERS create mode 100644 configs/generic-rk3576_defconfig diff --git a/arch/arm/dts/rk3576-generic-u-boot.dtsi b/arch/arm/dts/rk3576-generic-u-boot.dtsi new file mode 100644 index 00000000000..632fabb6af5 --- /dev/null +++ b/arch/arm/dts/rk3576-generic-u-boot.dtsi @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3576-u-boot.dtsi" diff --git a/arch/arm/dts/rk3576-generic.dts b/arch/arm/dts/rk3576-generic.dts new file mode 100644 index 00000000000..123be5378d9 --- /dev/null +++ b/arch/arm/dts/rk3576-generic.dts @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Minimal generic DT for RK3576 with eMMC, SD-card and USB OTG enabled + */ + +/dts-v1/; + +#include +#include "rk3576.dtsi" + +/ { + model = "Generic RK3576"; + compatible = "rockchip,rk3576"; + + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; + }; + + chosen { + stdout-path = "serial0:1500000n8"; + }; +}; + +&sdhci { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + no-sd; + no-sdio; + non-removable; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + disable-wp; + no-mmc; + no-sdio; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&uart0 { + pinctrl-0 = <&uart0m0_xfer>; + status = "okay"; +}; + +&usb_drd0_dwc3 { + dr_mode = "peripheral"; + maximum-speed = "high-speed"; + phys = <&u2phy0_otg>; + phy-names = "usb2-phy"; + status = "okay"; +}; diff --git a/arch/arm/mach-rockchip/rk3576/MAINTAINERS b/arch/arm/mach-rockchip/rk3576/MAINTAINERS new file mode 100644 index 00000000000..b5190c81846 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3576/MAINTAINERS @@ -0,0 +1,5 @@ +GENERIC-RK3576 +M: Jonas Karlman +S: Maintained +F: arch/arm/dts/rk3576-generic* +F: configs/generic-rk3576_defconfig diff --git a/configs/generic-rk3576_defconfig b/configs/generic-rk3576_defconfig new file mode 100644 index 00000000000..5e25653820c --- /dev/null +++ b/configs/generic-rk3576_defconfig @@ -0,0 +1,50 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_DEFAULT_DEVICE_TREE="rk3576-generic" +CONFIG_ROCKCHIP_RK3576=y +CONFIG_SYS_LOAD_ADDR=0x40c00800 +CONFIG_DEBUG_UART_BASE=0x2AD40000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +# CONFIG_BOOTMETH_VBE is not set +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3576-generic.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_MAX_SIZE=0x40000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMINFO_MAP=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MISC=y +CONFIG_CMD_MMC=y +CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_RNG=y +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_OF_UPSTREAM is not set +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_NO_NET=y +# CONFIG_ADC is not set +# CONFIG_USB_FUNCTION_FASTBOOT is not set +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSRESET_PSCI=y +CONFIG_USB=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_ROCKUSB=y +CONFIG_ERRNO_STR=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index a2d8a715a4b..4d27b809980 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -135,6 +135,7 @@ List of mainline supported Rockchip boards: * rk3576 - Firefly ROC-RK3576-PC (roc-pc-rk3576) + - Generic RK3576 (generic-rk3576) * rk3588 - ArmSoM Sige7 (sige7-rk3588) From a72e8feaca46ed41a8d6bb4e8c5961a29fe7a39e Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Fri, 1 Aug 2025 20:32:40 +0000 Subject: [PATCH 11/50] rockchip: rk3576: Implement checkboard() to print SoC variant Implement checkboard() to print current SoC model used by a board when U-Boot proper is running. U-Boot 2025.04 (Apr 22 2025 - 20:43:17 +0000) Model: Generic RK3576 SoC: RK3576 DRAM: 8 GiB Information about the SoC model and variant is read from OTP. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/rk3576/rk3576.c | 48 ++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm/mach-rockchip/rk3576/rk3576.c b/arch/arm/mach-rockchip/rk3576/rk3576.c index ba5c94b4b3d..2b1318f9532 100644 --- a/arch/arm/mach-rockchip/rk3576/rk3576.c +++ b/arch/arm/mach-rockchip/rk3576/rk3576.c @@ -3,6 +3,10 @@ * Copyright (c) 2024 Rockchip Electronics Co., Ltd */ +#define LOG_CATEGORY LOGC_ARCH + +#include +#include #include #include #include @@ -153,3 +157,47 @@ int arch_cpu_init(void) return 0; } + +#define RK3576_OTP_CPU_CODE_OFFSET 0x02 +#define RK3576_OTP_SPECIFICATION_OFFSET 0x08 + +int checkboard(void) +{ + u8 cpu_code[2], specification; + struct udevice *dev; + char suffix[2]; + int ret; + + if (!IS_ENABLED(CONFIG_ROCKCHIP_OTP) || !CONFIG_IS_ENABLED(MISC)) + return 0; + + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_DRIVER_GET(rockchip_otp), &dev); + if (ret) { + log_debug("Could not find otp device, ret=%d\n", ret); + return 0; + } + + /* cpu-code: SoC model, e.g. 0x35 0x76 */ + ret = misc_read(dev, RK3576_OTP_CPU_CODE_OFFSET, cpu_code, 2); + if (ret < 0) { + log_debug("Could not read cpu-code, ret=%d\n", ret); + return 0; + } + + /* specification: SoC variant, e.g. 0xA for RK3576J */ + ret = misc_read(dev, RK3576_OTP_SPECIFICATION_OFFSET, &specification, 1); + if (ret < 0) { + log_debug("Could not read specification, ret=%d\n", ret); + return 0; + } + specification &= 0x1f; + + /* for RK3576J i.e. '@' + 0xA = 'J' */ + suffix[0] = specification > 1 ? '@' + specification : '\0'; + suffix[1] = '\0'; + + printf("SoC: RK%02x%02x%s\n", cpu_code[0], cpu_code[1], suffix); + + return 0; +} From bdcda6be27b69a6e7ced1d59f5d6ceb07c5414ac Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Fri, 1 Aug 2025 20:32:41 +0000 Subject: [PATCH 12/50] arm: dts: rockchip: Include OTP in U-Boot pre-reloc phase for RK3576 Update rk3576-u-boot.dtsi to include OTP in U-Boot pre-reloc phase for checkboard() to be able to read information about the running SoC model and variant from OTP and print it during boot: U-Boot 2025.04 (Apr 22 2025 - 20:43:17 +0000) Model: Generic RK3576 SoC: RK3576 DRAM: 8 GiB Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rk3576-u-boot.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/dts/rk3576-u-boot.dtsi b/arch/arm/dts/rk3576-u-boot.dtsi index be99a48a630..fb5a107f47d 100644 --- a/arch/arm/dts/rk3576-u-boot.dtsi +++ b/arch/arm/dts/rk3576-u-boot.dtsi @@ -49,6 +49,10 @@ bootph-all; }; +&otp { + bootph-some-ram; +}; + &pcfg_pull_none { bootph-all; }; From 2d87afba58b95487f88717df33e16a909f90592a Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Fri, 1 Aug 2025 20:32:42 +0000 Subject: [PATCH 13/50] usb: dwc3-generic: Use combined glue and ctrl node for RK3576 Like Rockchip RK3328, RK3568 and RK3588, the RK3576 also have a single node to represent the glue and ctrl for USB 3.0. Use rk_ops as driver data to select correct ctrl node for RK3576 DWC3. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- drivers/usb/dwc3/dwc3-generic.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c index 3cda2b74b7e..cdb997ea6e4 100644 --- a/drivers/usb/dwc3/dwc3-generic.c +++ b/drivers/usb/dwc3/dwc3-generic.c @@ -699,6 +699,7 @@ static const struct udevice_id dwc3_glue_ids[] = { { .compatible = "rockchip,rk3328-dwc3", .data = (ulong)&rk_ops }, { .compatible = "rockchip,rk3399-dwc3" }, { .compatible = "rockchip,rk3568-dwc3", .data = (ulong)&rk_ops }, + { .compatible = "rockchip,rk3576-dwc3", .data = (ulong)&rk_ops }, { .compatible = "rockchip,rk3588-dwc3", .data = (ulong)&rk_ops }, { .compatible = "qcom,dwc3", .data = (ulong)&qcom_ops }, { .compatible = "fsl,imx8mp-dwc3", .data = (ulong)&imx8mp_ops }, From b518886f6d7061c127628c1e12f3921c49ffeaee Mon Sep 17 00:00:00 2001 From: Frank Wang Date: Fri, 1 Aug 2025 20:32:43 +0000 Subject: [PATCH 14/50] phy: rockchip-inno-usb2: Add support for RK3576 Add support for the USB2.0 PHYs used in the RK3576 SoC. Config values are taken from vendor U-Boot linux-6.1-stan-rkr5 tag. Signed-off-by: Frank Wang Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c index 3cc5956aed5..03fe1b38175 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c @@ -465,6 +465,28 @@ static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = { { /* sentinel */ } }; +static const struct rockchip_usb2phy_cfg rk3576_phy_cfgs[] = { + { + .reg = 0x0000, + .clkout_ctl = { 0x0008, 0, 0, 1, 0 }, + .port_cfgs = { + [USB2PHY_PORT_OTG] = { + .phy_sus = { 0x0000, 1, 0, 2, 1 }, + } + }, + }, + { + .reg = 0x2000, + .clkout_ctl = { 0x2008, 0, 0, 1, 0 }, + .port_cfgs = { + [USB2PHY_PORT_OTG] = { + .phy_sus = { 0x2000, 1, 0, 2, 1 }, + } + }, + }, + { /* sentinel */ } +}; + static const struct rockchip_usb2phy_cfg rk3588_phy_cfgs[] = { { .reg = 0x0000, @@ -526,6 +548,10 @@ static const struct udevice_id rockchip_usb2phy_ids[] = { .compatible = "rockchip,rk3568-usb2phy", .data = (ulong)&rk3568_phy_cfgs, }, + { + .compatible = "rockchip,rk3576-usb2phy", + .data = (ulong)&rk3576_phy_cfgs, + }, { .compatible = "rockchip,rk3588-usb2phy", .data = (ulong)&rk3588_phy_cfgs, From 0d966d3932e2e5e7d14301da9ced0d7a62fce367 Mon Sep 17 00:00:00 2001 From: Frank Wang Date: Fri, 1 Aug 2025 20:32:44 +0000 Subject: [PATCH 15/50] phy: rockchip: usbdp: Add support for RK3576 Add support for the USB3.0+DP PHY used in the RK3576 SoC. Config values are taken from vendor U-Boot linux-6.1-stan-rkr5 tag. Signed-off-by: Frank Wang Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- drivers/phy/rockchip/phy-rockchip-usbdp.c | 26 +++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockchip/phy-rockchip-usbdp.c index 9deec47ae46..ed0441842a1 100644 --- a/drivers/phy/rockchip/phy-rockchip-usbdp.c +++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c @@ -813,6 +813,28 @@ static const char * const rk3588_udphy_rst_l[] = { "init", "cmn", "lane", "pcs_apb", "pma_apb" }; +static const struct rockchip_udphy_cfg rk3576_udphy_cfgs = { + .num_phys = 1, + .phy_ids = { + 0x2b010000, + }, + .num_rsts = ARRAY_SIZE(rk3588_udphy_rst_l), + .rst_list = rk3588_udphy_rst_l, + .grfcfg = { + /* u2phy-grf */ + .bvalid_phy_con = { 0x0010, 1, 0, 0x2, 0x3 }, + .bvalid_grf_con = { 0x0000, 15, 14, 0x1, 0x3 }, + + /* usb-grf */ + .usb3otg0_cfg = { 0x0030, 15, 0, 0x1100, 0x0188 }, + + /* usbdpphy-grf */ + .low_pwrn = { 0x0004, 13, 13, 0, 1 }, + .rx_lfps = { 0x0004, 14, 14, 0, 1 }, + }, + .combophy_init = rk3588_udphy_init, +}; + static const struct rockchip_udphy_cfg rk3588_udphy_cfgs = { .num_phys = 2, .phy_ids = { @@ -838,6 +860,10 @@ static const struct rockchip_udphy_cfg rk3588_udphy_cfgs = { }; static const struct udevice_id rockchip_udphy_dt_match[] = { + { + .compatible = "rockchip,rk3576-usbdp-phy", + .data = (ulong)&rk3576_udphy_cfgs + }, { .compatible = "rockchip,rk3588-usbdp-phy", .data = (ulong)&rk3588_udphy_cfgs From 2a6039a20994c192edb6786fa97714180bd663cf Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Fri, 1 Aug 2025 20:43:37 +0000 Subject: [PATCH 16/50] rockchip: clk: clk_rk3576: Add dummy CLK_REF_PCIEx_PHY support Add dummy support for the CLK_REF_PCIEx_PHY clocks to allow probe of the phy-rockchip-naneng-combphy driver on RK3576. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- drivers/clk/rockchip/clk_rk3576.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/rockchip/clk_rk3576.c b/drivers/clk/rockchip/clk_rk3576.c index e84a0943a94..125b08ee832 100644 --- a/drivers/clk/rockchip/clk_rk3576.c +++ b/drivers/clk/rockchip/clk_rk3576.c @@ -2168,6 +2168,8 @@ static ulong rk3576_clk_set_rate(struct clk *clk, ulong rate) case CLK_CPLL_DIV10: case FCLK_DDR_CM0_CORE: case ACLK_PHP_ROOT: + case CLK_REF_PCIE0_PHY: + case CLK_REF_PCIE1_PHY: ret = 0; break; #ifndef CONFIG_SPL_BUILD From cca7e79c7a42067fd8e65f4d2d2c73a98e42cd2e Mon Sep 17 00:00:00 2001 From: Jon Lin Date: Fri, 1 Aug 2025 20:43:38 +0000 Subject: [PATCH 17/50] phy: rockchip: naneng-combphy: Add support for RK3576 Add support for the PCIe/USB3/SATA combo PHYs used in the RK3576 SoC. Config values are taken from vendor U-Boot linux-6.1-stan-rkr5 tag. Signed-off-by: Jon Lin Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- .../rockchip/phy-rockchip-naneng-combphy.c | 147 ++++++++++++++++++ 1 file changed, 147 insertions(+) diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c index 5145b517aa4..e6fb0bce522 100644 --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c @@ -453,6 +453,149 @@ static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = { .combphy_cfg = rk3568_combphy_cfg, }; +static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv) +{ + const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; + u32 val; + + switch (priv->mode) { + case PHY_TYPE_PCIE: + param_write(priv->phy_grf, &cfg->con0_for_pcie, true); + param_write(priv->phy_grf, &cfg->con1_for_pcie, true); + param_write(priv->phy_grf, &cfg->con2_for_pcie, true); + param_write(priv->phy_grf, &cfg->con3_for_pcie, true); + break; + case PHY_TYPE_USB3: + /* Set SSC downward spread spectrum */ + val = readl(priv->mmio + (0x1f << 2)); + val &= ~GENMASK(5, 4); + val |= 0x01 << 4; + writel(val, priv->mmio + 0x7c); + + /* Enable adaptive CTLE for USB3.0 Rx */ + val = readl(priv->mmio + (0x0e << 2)); + val &= ~GENMASK(0, 0); + val |= 0x01; + writel(val, priv->mmio + (0x0e << 2)); + + /* Set PLL KVCO fine tuning signals */ + val = readl(priv->mmio + (0x20 << 2)); + val &= ~(0x7 << 2); + val |= 0x2 << 2; + writel(val, priv->mmio + (0x20 << 2)); + + /* Set PLL LPF R1 to su_trim[10:7]=1001 */ + writel(0x4, priv->mmio + (0xb << 2)); + + /* Set PLL input clock divider 1/2 */ + val = readl(priv->mmio + (0x5 << 2)); + val &= ~(0x3 << 6); + val |= 0x1 << 6; + writel(val, priv->mmio + (0x5 << 2)); + + /* Set PLL loop divider */ + writel(0x32, priv->mmio + (0x11 << 2)); + + /* Set PLL KVCO to min and set PLL charge pump current to max */ + writel(0xf0, priv->mmio + (0xa << 2)); + + /* Set Rx squelch input filler bandwidth */ + writel(0x0d, priv->mmio + (0x14 << 2)); + + param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); + param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); + param_write(priv->phy_grf, &cfg->usb_mode_set, true); + param_write(priv->pipe_grf, &cfg->u3otg1_port_en, true); + break; + case PHY_TYPE_SATA: + /* Enable adaptive CTLE for SATA Rx */ + val = readl(priv->mmio + (0x0e << 2)); + val &= ~GENMASK(0, 0); + val |= 0x01; + writel(val, priv->mmio + (0x0e << 2)); + /* Set tx_rterm = 50 ohm and rx_rterm = 43.5 ohm */ + writel(0x8F, priv->mmio + (0x06 << 2)); + + param_write(priv->phy_grf, &cfg->con0_for_sata, true); + param_write(priv->phy_grf, &cfg->con1_for_sata, true); + param_write(priv->phy_grf, &cfg->con2_for_sata, true); + param_write(priv->phy_grf, &cfg->con3_for_sata, true); + param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); + param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true); + break; + case PHY_TYPE_SGMII: + case PHY_TYPE_QSGMII: + default: + dev_err(priv->dev, "incompatible PHY type\n"); + return -EINVAL; + } + + /* 100MHz refclock signal is good */ + clk_set_rate(&priv->ref_clk, 100000000); + param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); + if (priv->mode == PHY_TYPE_PCIE) { + /* gate_tx_pck_sel length select work for L1SS */ + writel(0xc0, priv->mmio + 0x74); + + /* PLL KVCO tuning fine */ + val = readl(priv->mmio + (0x20 << 2)); + val &= ~(0x7 << 2); + val |= 0x2 << 2; + writel(val, priv->mmio + (0x20 << 2)); + + /* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */ + writel(0x4c, priv->mmio + (0x1b << 2)); + + /* Set up su_trim: T3_P1 650mv */ + writel(0x90, priv->mmio + (0xa << 2)); + writel(0x43, priv->mmio + (0xb << 2)); + writel(0x88, priv->mmio + (0xc << 2)); + writel(0x56, priv->mmio + (0xd << 2)); + } + + return 0; +} + +static const struct rockchip_combphy_grfcfg rk3576_combphy_grfcfgs = { + /* pipe-phy-grf */ + .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, + .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, + .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, + .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, + .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, + .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, + .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, + .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 }, + .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 }, + .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, + .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, + .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, + .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, + .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, + .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, + .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, + .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, + .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, + .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0129 }, + .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0000 }, + .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c1 }, + .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x0407 }, + /* php-grf */ + .pipe_con0_for_sata = { 0x001C, 2, 0, 0x00, 0x2 }, + .pipe_con1_for_sata = { 0x0020, 2, 0, 0x00, 0x2 }, + .u3otg1_port_en = { 0x0038, 15, 0, 0x0181, 0x1100 }, +}; + +static const struct rockchip_combphy_cfg rk3576_combphy_cfgs = { + .num_phys = 2, + .phy_ids = { + 0x2b050000, + 0x2b060000, + }, + .grfcfg = &rk3576_combphy_grfcfgs, + .combphy_cfg = rk3576_combphy_cfg, +}; + static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv) { const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; @@ -564,6 +707,10 @@ static const struct udevice_id rockchip_combphy_ids[] = { .compatible = "rockchip,rk3568-naneng-combphy", .data = (ulong)&rk3568_combphy_cfgs }, + { + .compatible = "rockchip,rk3576-naneng-combphy", + .data = (ulong)&rk3576_combphy_cfgs + }, { .compatible = "rockchip,rk3588-naneng-combphy", .data = (ulong)&rk3588_combphy_cfgs From ae2faeae673479014846c0c6280edb46782cf950 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Fri, 1 Aug 2025 20:43:39 +0000 Subject: [PATCH 18/50] board: rockchip: Add ArmSoM Sige5 ArmSoM-Sige5 adopts the second-generation 8nm high-performance AIOT platform Rockchip RK3576, with a 6 TOPS computing power NPU and support for up to 16GB of large memory. It supports 4K video encoding and decoding, offers rich interfaces including dual gigabit Ethernet ports, WiFi 6 & BT5, and various video outputs. Features tested on a ArmSoM Sige5 v1.1: - SD-card boot - eMMC boot - Ethernet - PCIe NVMe Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rk3576-armsom-sige5-u-boot.dtsi | 18 ++++++ arch/arm/mach-rockchip/rk3576/MAINTAINERS | 6 ++ configs/sige5-rk3576_defconfig | 66 ++++++++++++++++++++ doc/board/rockchip/rockchip.rst | 1 + 4 files changed, 91 insertions(+) create mode 100644 arch/arm/dts/rk3576-armsom-sige5-u-boot.dtsi create mode 100644 configs/sige5-rk3576_defconfig diff --git a/arch/arm/dts/rk3576-armsom-sige5-u-boot.dtsi b/arch/arm/dts/rk3576-armsom-sige5-u-boot.dtsi new file mode 100644 index 00000000000..7e0530d85d1 --- /dev/null +++ b/arch/arm/dts/rk3576-armsom-sige5-u-boot.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3576-u-boot.dtsi" + +/ { + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; + }; +}; + +&red_led { + default-state = "on"; +}; + +&sdhci { + cap-mmc-highspeed; +}; diff --git a/arch/arm/mach-rockchip/rk3576/MAINTAINERS b/arch/arm/mach-rockchip/rk3576/MAINTAINERS index b5190c81846..94ef74d429f 100644 --- a/arch/arm/mach-rockchip/rk3576/MAINTAINERS +++ b/arch/arm/mach-rockchip/rk3576/MAINTAINERS @@ -3,3 +3,9 @@ M: Jonas Karlman S: Maintained F: arch/arm/dts/rk3576-generic* F: configs/generic-rk3576_defconfig + +SIGE5-RK3576 +M: Jonas Karlman +S: Maintained +F: arch/arm/dts/rk3576-armsom-sige5* +F: configs/sige5-rk3576_defconfig diff --git a/configs/sige5-rk3576_defconfig b/configs/sige5-rk3576_defconfig new file mode 100644 index 00000000000..c515e145595 --- /dev/null +++ b/configs/sige5-rk3576_defconfig @@ -0,0 +1,66 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3576-armsom-sige5" +CONFIG_ROCKCHIP_RK3576=y +CONFIG_SYS_LOAD_ADDR=0x40c00800 +CONFIG_DEBUG_UART_BASE=0x2AD40000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3576-armsom-sige5.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_MAX_SIZE=0x40000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMINFO_MAP=y +CONFIG_CMD_ADC=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MISC=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_RNG=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +# CONFIG_USB_FUNCTION_FASTBOOT is not set +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_ROCKCHIP=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_PHY_ROCKCHIP_USBDP=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSRESET_PSCI=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_ROCKUSB=y +CONFIG_ERRNO_STR=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 4d27b809980..1ac44ba0a52 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -134,6 +134,7 @@ List of mainline supported Rockchip boards: - Radxa ROCK 3B (rock-3b-rk3568) * rk3576 + - ArmSoM Sige5 (sige5-rk3576) - Firefly ROC-RK3576-PC (roc-pc-rk3576) - Generic RK3576 (generic-rk3576) From 009bc00bf91bcd3076992a85077de82340e33219 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Fri, 27 Jun 2025 15:30:16 +0200 Subject: [PATCH 19/50] rockchip: tiger-rk3588: enable "env erase" command Erasing the environment to start from scratch is actually very useful and "env erase" is the proper way to do it instead of using "env default -a && env save", so let's enable support for it. Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang --- configs/tiger-rk3588_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/tiger-rk3588_defconfig b/configs/tiger-rk3588_defconfig index 335ea4d8de3..8ba2a996ee2 100644 --- a/configs/tiger-rk3588_defconfig +++ b/configs/tiger-rk3588_defconfig @@ -35,6 +35,7 @@ CONFIG_SPL_ATF=y # CONFIG_BOOTM_RTEMS is not set # CONFIG_BOOTM_VXWORKS is not set # CONFIG_CMD_ELF is not set +CONFIG_CMD_ERASEENV=y CONFIG_CMD_ADC=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y From 3c8b94ac91ea01debad4978111f1e96b37bd409f Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Fri, 27 Jun 2025 15:30:17 +0200 Subject: [PATCH 20/50] rockchip: jaguar-rk3588: enable "env erase" command Erasing the environment to start from scratch is actually very useful and "env erase" is the proper way to do it instead of using "env default -a && env save", so let's enable support for it. Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang --- configs/jaguar-rk3588_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/jaguar-rk3588_defconfig b/configs/jaguar-rk3588_defconfig index 13cff7b1a02..378c48963f7 100644 --- a/configs/jaguar-rk3588_defconfig +++ b/configs/jaguar-rk3588_defconfig @@ -34,6 +34,7 @@ CONFIG_SPL_ATF=y # CONFIG_BOOTM_RTEMS is not set # CONFIG_BOOTM_VXWORKS is not set # CONFIG_CMD_ELF is not set +CONFIG_CMD_ERASEENV=y CONFIG_CMD_ADC=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y From 755653c06c5dbe33e4cc342496935a1fd2a44fb5 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Fri, 27 Jun 2025 15:30:18 +0200 Subject: [PATCH 21/50] rockchip: ringneck-px30: enable "env erase" command Erasing the environment to start from scratch is actually very useful and "env erase" is the proper way to do it instead of using "env default -a && env save", so let's enable support for it. Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang --- configs/ringneck-px30_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/ringneck-px30_defconfig b/configs/ringneck-px30_defconfig index ba15e386770..2240ba80e5e 100644 --- a/configs/ringneck-px30_defconfig +++ b/configs/ringneck-px30_defconfig @@ -40,6 +40,7 @@ CONFIG_SPL_ATF=y # CONFIG_CMD_VBE is not set # CONFIG_BOOTM_VXWORKS is not set # CONFIG_CMD_ELF is not set +CONFIG_CMD_ERASEENV=y # CONFIG_CMD_LZMADEC is not set # CONFIG_CMD_UNZIP is not set CONFIG_CMD_BIND=y From a979380123e5e0da6b45eff0aec0ba71fd0440c6 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Fri, 27 Jun 2025 15:30:19 +0200 Subject: [PATCH 22/50] rockchip: puma-rk3399: enable "env erase" command Erasing the environment to start from scratch is actually very useful and "env erase" is the proper way to do it instead of using "env default -a && env save", so let's enable support for it. Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang --- configs/puma-rk3399_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig index 817d4fe1d64..2070d534232 100644 --- a/configs/puma-rk3399_defconfig +++ b/configs/puma-rk3399_defconfig @@ -36,6 +36,7 @@ CONFIG_TPL_GPIO=y # CONFIG_BOOTM_RTEMS is not set # CONFIG_CMD_VBE is not set # CONFIG_BOOTM_VXWORKS is not set +CONFIG_CMD_ERASEENV=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y From de0c91e7a7605b047d3dc96f9e1c02701af6d716 Mon Sep 17 00:00:00 2001 From: Jakob Unterwurzacher Date: Tue, 17 Jun 2025 10:42:52 +0200 Subject: [PATCH 23/50] board: rockchip: unblock CAN bus in spl_board_init on Jaguar GPIO0_B7 is routed to TXI of the on-board CAN transceiver. The line has a pull-down per SoC default. This means the CAN transceiver transmits a dominant zero and blocks the CAN bus until Linux boots and reconfigures the pin. Let's switch to pull-up as soon as we can (i.e. in SPL). This cuts down the "bus is blocked" time from 10 seconds to < 1 second. Of course, to this needs CONFIG_SPL_BOARD_INIT, so enable it the Jaguar defconfig. Signed-off-by: Jakob Unterwurzacher Reviewed-by: Kever Yang --- .../jaguar_rk3588/jaguar_rk3588.c | 19 +++++++++++++++++++ configs/jaguar-rk3588_defconfig | 1 + 2 files changed, 20 insertions(+) diff --git a/board/theobroma-systems/jaguar_rk3588/jaguar_rk3588.c b/board/theobroma-systems/jaguar_rk3588/jaguar_rk3588.c index a6d44f10db3..3f484646701 100644 --- a/board/theobroma-systems/jaguar_rk3588/jaguar_rk3588.c +++ b/board/theobroma-systems/jaguar_rk3588/jaguar_rk3588.c @@ -51,3 +51,22 @@ int rockchip_early_misc_init_r(void) return 0; } + +#define GPIO0B7_PU_EN BIT(15) + +void spl_board_init(void) +{ + /* + * GPIO0_B7 is routed to CAN TX. This SoC pin has a pull-down per default. + * So on power-up, we block the CAN bus with a dominant zero. We want to keep + * this blocking time to a minimum, so we want to get this pin high in SPL. + * + * The CAN driver in Linux disables the pull-down and sets the pin to + * output high. We don't have a CAN driver in U-Boot and don't need one, + * so we just use the easiest way to get the pin high, which is setting a + * pull-up. + */ + struct rk3588_pmu2_ioc * const ioc = (void *)PMU2_IOC_BASE; + + rk_setreg(&ioc->gpio0b_p, GPIO0B7_PU_EN); +} diff --git a/configs/jaguar-rk3588_defconfig b/configs/jaguar-rk3588_defconfig index 378c48963f7..3ed07d18e10 100644 --- a/configs/jaguar-rk3588_defconfig +++ b/configs/jaguar-rk3588_defconfig @@ -27,6 +27,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-jaguar.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CYCLIC=y CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_BOARD_INIT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_ATF=y # CONFIG_BOOTM_NETBSD is not set From 6048bbbb920373ac19bbcd7aa6bb61654bc92885 Mon Sep 17 00:00:00 2001 From: Marius Dinu Date: Wed, 11 Jun 2025 11:04:54 +0000 Subject: [PATCH 24/50] rk3288: add fdtoverlay_addr_r to default env rk3288 is missing fdtoverlay_addr_r. The new addresses match those used by rk3308. Tested on Asus TinkerBoard S. Signed-off-by: Marius Dinu Cc: Simon Glass Cc: Philipp Tomsich Cc: Kever Yang Reviewed-by: Quentin Schulz Reviewed-by: Kever Yang --- include/configs/rk3288_common.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index 0c449e31099..52c3695ff8e 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -18,7 +18,8 @@ #define ENV_MEM_LAYOUT_SETTINGS \ "scriptaddr=0x00000000\0" \ "pxefile_addr_r=0x00100000\0" \ - "fdt_addr_r=0x01f00000\0" \ + "fdt_addr_r=0x01e00000\0" \ + "fdtoverlay_addr_r=0x01f00000\0" \ "kernel_addr_r=0x02000000\0" \ "ramdisk_addr_r=0x04000000\0" From 9b3b5e03b8ddb548e6ece7b35ad1d52b5363abf2 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Wed, 30 Jul 2025 23:52:42 +0000 Subject: [PATCH 25/50] rockchip: rk3528-generic: Fix boot after dts/upstream v6.16-dts merge The rk3528-generic target can no longer boot after v6.16-dts was merged into dts/upstream, and instead end up in a boot loop: No serial driver found resetting ... After Linux commit 34d2730fbbdd ("arm64: dts: rockchip: move rk3528 i2c+uart aliases to board files") there is no longer an alias for serial0 defined for the U-Boot only rk3528-generic device tree. Add a board specific aliases node that include the missing serial0 alias to resolve the boot issue and ensure that stdout-path = "serial0:..." can be resolved by U-Boot. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rk3528-generic.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/dts/rk3528-generic.dts b/arch/arm/dts/rk3528-generic.dts index 3f6f0bed108..fe9e72c41cd 100644 --- a/arch/arm/dts/rk3528-generic.dts +++ b/arch/arm/dts/rk3528-generic.dts @@ -10,6 +10,11 @@ model = "Generic RK3528"; compatible = "rockchip,rk3528"; + aliases { + mmc0 = &sdhci; + serial0 = &uart0; + }; + chosen { stdout-path = "serial0:1500000n8"; }; From 2e3b37d589d3ccb3c7c11c0cca01f330a040c863 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Wed, 30 Jul 2025 23:52:43 +0000 Subject: [PATCH 26/50] arm: dts: rockchip: Use sdmmc node from dts/upstream on RK3528 Drop the sdmmc node from soc u-boot.dtsi and instead use the sdmmc node from rk3528.dtsi with v6.16-dts now merged to dts/upstream. This cleanup has no intended functional change. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rk3528-generic-u-boot.dtsi | 9 --------- arch/arm/dts/rk3528-generic.dts | 12 +++++++++++- arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi | 9 --------- arch/arm/dts/rk3528-u-boot.dtsi | 18 ------------------ 4 files changed, 11 insertions(+), 37 deletions(-) diff --git a/arch/arm/dts/rk3528-generic-u-boot.dtsi b/arch/arm/dts/rk3528-generic-u-boot.dtsi index cc830b51456..9e1fb2a7eef 100644 --- a/arch/arm/dts/rk3528-generic-u-boot.dtsi +++ b/arch/arm/dts/rk3528-generic-u-boot.dtsi @@ -1,12 +1,3 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) #include "rk3528-u-boot.dtsi" - -&sdmmc { - bus-width = <4>; - cap-sd-highspeed; - disable-wp; - no-mmc; - no-sdio; - status = "okay"; -}; diff --git a/arch/arm/dts/rk3528-generic.dts b/arch/arm/dts/rk3528-generic.dts index fe9e72c41cd..637ca03325e 100644 --- a/arch/arm/dts/rk3528-generic.dts +++ b/arch/arm/dts/rk3528-generic.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Minimal generic DT for RK3528 with eMMC enabled + * Minimal generic DT for RK3528 with eMMC and SD-card enabled */ /dts-v1/; @@ -12,6 +12,7 @@ aliases { mmc0 = &sdhci; + mmc1 = &sdmmc; serial0 = &uart0; }; @@ -30,6 +31,15 @@ status = "okay"; }; +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + disable-wp; + no-mmc; + no-sdio; + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0m0_xfer>; diff --git a/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi b/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi index 1372d8f1e38..05a58c136bc 100644 --- a/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi +++ b/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi @@ -5,12 +5,3 @@ &sdhci { mmc-hs200-1_8v; }; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - vmmc-supply = <&vcc_3v3>; - status = "okay"; -}; diff --git a/arch/arm/dts/rk3528-u-boot.dtsi b/arch/arm/dts/rk3528-u-boot.dtsi index eb6a55cd5c9..a18d33b3d36 100644 --- a/arch/arm/dts/rk3528-u-boot.dtsi +++ b/arch/arm/dts/rk3528-u-boot.dtsi @@ -27,24 +27,6 @@ compatible = "rockchip,rk3528-otp"; reg = <0x0 0xffce0000 0x0 0x4000>; }; - - sdmmc: mmc@ffc30000 { - compatible = "rockchip,rk3528-dw-mshc", - "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xffc30000 0x0 0x4000>; - clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SRC_SDMMC0>; - clock-names = "biu", "ciu"; - fifo-depth = <0x100>; - interrupts = ; - max-frequency = <150000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_bus4>, <&sdmmc_clk>, <&sdmmc_cmd>, - <&sdmmc_det>; - resets = <&cru SRST_H_SDMMC0>; - reset-names = "reset"; - rockchip,default-sample-phase = <90>; - status = "disabled"; - }; }; }; From 95ae8b040b891596c5a7916a0955d7820fc9e380 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Wed, 30 Jul 2025 23:52:44 +0000 Subject: [PATCH 27/50] arm: dts: rockchip: Set init-microvolt for pwm-regulators on Radxa E20C Radxa E20C has two main pwm-regulators, vdd_arm and vdd_logic. Add init-microvolt props to ensure the regulators are initialized at the recommended power-on sequence voltage instead of at max voltage. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi b/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi index 05a58c136bc..16c47e6b9a9 100644 --- a/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi +++ b/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi @@ -5,3 +5,11 @@ &sdhci { mmc-hs200-1_8v; }; + +&vdd_arm { + regulator-init-microvolt = <953000>; +}; + +&vdd_logic { + regulator-init-microvolt = <900000>; +}; From 58d39bbd773965404cd8cc41ebb94488b48ac1a4 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Wed, 30 Jul 2025 23:52:45 +0000 Subject: [PATCH 28/50] rockchip: rk3528: Disable USB3OTG U3 port early The RK3528 SoC comes with USB OTG support using a DWC3 controller with a USB2 PHY and a USB3 PHY (COMBPHY). Some board designs may not use the COMBPHY for USB3 purpose. For these board to use USB OTG the input clock source must change to use UTMI clk instead of PIPE clk. Change to always disable the USB3OTG U3 port early and leave it to the COMBPHY driver to re-enable the U3 port when a usb3-phy is described in the board device tree. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/rk3528/rk3528.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/mach-rockchip/rk3528/rk3528.c b/arch/arm/mach-rockchip/rk3528/rk3528.c index 4892ff6ba9d..f9bfc445b85 100644 --- a/arch/arm/mach-rockchip/rk3528/rk3528.c +++ b/arch/arm/mach-rockchip/rk3528/rk3528.c @@ -9,6 +9,9 @@ #include #include +#define VPU_GRF_BASE 0xff340000 +#define USB3OTG_CON1 0x44 + #define FIREWALL_DDR_BASE 0xff2e0000 #define FW_DDR_MST6_REG 0x58 #define FW_DDR_MST7_REG 0x5c @@ -69,6 +72,9 @@ int arch_cpu_init(void) val = readl(FIREWALL_DDR_BASE + FW_DDR_MST16_REG); writel(val & 0xffff0000, FIREWALL_DDR_BASE + FW_DDR_MST16_REG); + /* Disable USB3OTG U3 port, later enabled in COMBPHY driver */ + writel(0xffff0181, VPU_GRF_BASE + USB3OTG_CON1); + return 0; } From 281c66f39b0e6b3b520976ad0535939141f148b8 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Wed, 30 Jul 2025 23:52:46 +0000 Subject: [PATCH 29/50] rockchip: clk: clk_rk3528: Add dummy CLK_REF_PCIE_INNER_PHY support Add dummy support for the CLK_REF_PCIE_INNER_PHY clock to allow probe of the phy-rockchip-naneng-combphy driver on RK3528. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- drivers/clk/rockchip/clk_rk3528.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/rockchip/clk_rk3528.c b/drivers/clk/rockchip/clk_rk3528.c index 06f20895acc..d58557ff56d 100644 --- a/drivers/clk/rockchip/clk_rk3528.c +++ b/drivers/clk/rockchip/clk_rk3528.c @@ -1535,6 +1535,7 @@ static ulong rk3528_clk_set_rate(struct clk *clk, ulong rate) /* Might occur in cru assigned-clocks, can be ignored here */ case ACLK_BUS_VOPGL_ROOT: case BCLK_EMMC: + case CLK_REF_PCIE_INNER_PHY: case XIN_OSC0_DIV: ret = 0; break; From 0f310a08951c6ba99256928454bee3d81b6191b6 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Wed, 30 Jul 2025 23:52:47 +0000 Subject: [PATCH 30/50] usb: dwc3-generic: Use combined glue and ctrl node for RK3528 Like Rockchip RK3328, RK3568 and RK3588, the RK3528 also have a single node to represent the glue and ctrl for USB 3.0. Use rk_ops as driver data to select correct ctrl node for RK3528 DWC3. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- drivers/usb/dwc3/dwc3-generic.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c index cdb997ea6e4..c09014aec60 100644 --- a/drivers/usb/dwc3/dwc3-generic.c +++ b/drivers/usb/dwc3/dwc3-generic.c @@ -698,6 +698,7 @@ static const struct udevice_id dwc3_glue_ids[] = { { .compatible = "ti,am654-dwc3" }, { .compatible = "rockchip,rk3328-dwc3", .data = (ulong)&rk_ops }, { .compatible = "rockchip,rk3399-dwc3" }, + { .compatible = "rockchip,rk3528-dwc3", .data = (ulong)&rk_ops }, { .compatible = "rockchip,rk3568-dwc3", .data = (ulong)&rk_ops }, { .compatible = "rockchip,rk3576-dwc3", .data = (ulong)&rk_ops }, { .compatible = "rockchip,rk3588-dwc3", .data = (ulong)&rk_ops }, From dfc6ec058e80b9d45654fc85e00ecaec03d4f3c9 Mon Sep 17 00:00:00 2001 From: Jianwei Zheng Date: Wed, 30 Jul 2025 23:52:48 +0000 Subject: [PATCH 31/50] phy: rockchip: naneng-combphy: Add support for RK3528 Add support for the PCIe/USB3 combo PHY used in the RK3528 SoC. Config values are taken from vendor U-Boot linux-6.1-stan-rkr5 tag. Signed-off-by: Jianwei Zheng Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- .../rockchip/phy-rockchip-naneng-combphy.c | 102 ++++++++++++++++++ 1 file changed, 102 insertions(+) diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c index e6fb0bce522..6d8d10750b1 100644 --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c @@ -37,6 +37,7 @@ struct rockchip_combphy_grfcfg { struct combphy_reg pipe_rxterm_set; struct combphy_reg pipe_txelec_set; struct combphy_reg pipe_txcomp_set; + struct combphy_reg pipe_clk_24m; struct combphy_reg pipe_clk_25m; struct combphy_reg pipe_clk_100m; struct combphy_reg pipe_phymode_sel; @@ -310,6 +311,103 @@ static int rockchip_combphy_probe(struct udevice *udev) return rockchip_combphy_parse_dt(udev, priv); } +static int rk3528_combphy_cfg(struct rockchip_combphy_priv *priv) +{ + const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; + u32 val; + + switch (priv->mode) { + case PHY_TYPE_PCIE: + /* Set SSC downward spread spectrum */ + val = readl(priv->mmio + 0x18); + val &= ~GENMASK(5, 4); + val |= 0x01 << 4; + writel(val, priv->mmio + 0x18); + + param_write(priv->phy_grf, &cfg->con0_for_pcie, true); + param_write(priv->phy_grf, &cfg->con1_for_pcie, true); + param_write(priv->phy_grf, &cfg->con2_for_pcie, true); + param_write(priv->phy_grf, &cfg->con3_for_pcie, true); + break; + case PHY_TYPE_USB3: + /* Set SSC downward spread spectrum */ + val = readl(priv->mmio + 0x18); + val &= ~GENMASK(5, 4); + val |= 0x01 << 4; + writel(val, priv->mmio + 0x18); + + /* Enable adaptive CTLE for USB3.0 Rx */ + val = readl(priv->mmio + 0x200); + val &= ~GENMASK(17, 17); + val |= 0x01 << 17; + writel(val, priv->mmio + 0x200); + + /* Set Rx squelch input filler bandwidth */ + val = readl(priv->mmio + 0x20c); + val &= ~GENMASK(2, 0); + val |= 0x06; + writel(val, priv->mmio + 0x20c); + + param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); + param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); + param_write(priv->phy_grf, &cfg->usb_mode_set, true); + param_write(priv->pipe_grf, &cfg->u3otg0_port_en, true); + break; + default: + dev_err(priv->dev, "incompatible PHY type\n"); + return -EINVAL; + } + + param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); + + if (priv->mode == PHY_TYPE_PCIE) { + /* PLL KVCO tuning fine */ + val = readl(priv->mmio + 0x18); + val &= ~(0x7 << 10); + val |= 0x2 << 10; + writel(val, priv->mmio + 0x18); + + /* su_trim[6:4]=111, [10:7]=1001, [2:0]=000 */ + val = readl(priv->mmio + 0x108); + val &= ~(0x7f7); + val |= 0x4f0; + writel(val, priv->mmio + 0x108); + } + + return 0; +} + +static const struct rockchip_combphy_grfcfg rk3528_combphy_grfcfgs = { + /* pipe-phy-grf */ + .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, + .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, + .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, + .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, + .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, + .pipe_clk_24m = { 0x0004, 14, 13, 0x00, 0x00 }, + .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, + .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, + .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, + .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, + .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, + .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, + .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x110 }, + .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x00 }, + .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x101 }, + .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, + /* pipe-grf */ + .u3otg0_port_en = { 0x0044, 15, 0, 0x0181, 0x1100 }, +}; + +static const struct rockchip_combphy_cfg rk3528_combphy_cfgs = { + .num_phys = 1, + .phy_ids = { + 0xffdc0000, + }, + .grfcfg = &rk3528_combphy_grfcfgs, + .combphy_cfg = rk3528_combphy_cfg, +}; + static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv) { const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; @@ -703,6 +801,10 @@ static const struct rockchip_combphy_cfg rk3588_combphy_cfgs = { }; static const struct udevice_id rockchip_combphy_ids[] = { + { + .compatible = "rockchip,rk3528-naneng-combphy", + .data = (ulong)&rk3528_combphy_cfgs + }, { .compatible = "rockchip,rk3568-naneng-combphy", .data = (ulong)&rk3568_combphy_cfgs From 50c8b58eeab7708e76f82cf9a93bb7c5feb60ed6 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Wed, 30 Jul 2025 23:52:49 +0000 Subject: [PATCH 32/50] rockchip: rk3528-radxa-e20c: Enable USB gadget Kconfig options Radxa E20C has a USB OTG Type-C port for Debug and Data. Add required Kconfig options to use USB gadget features once pending USB nodes finally lands in dts/upstream by a future sync. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- configs/radxa-e20c-rk3528_defconfig | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/configs/radxa-e20c-rk3528_defconfig b/configs/radxa-e20c-rk3528_defconfig index f5e097f3edf..0941d1b9be8 100644 --- a/configs/radxa-e20c-rk3528_defconfig +++ b/configs/radxa-e20c-rk3528_defconfig @@ -20,6 +20,8 @@ CONFIG_CMD_GPT=y CONFIG_CMD_MISC=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_RNG=y CONFIG_CMD_REGULATOR=y @@ -28,6 +30,7 @@ CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigne CONFIG_BUTTON=y CONFIG_BUTTON_ADC=y CONFIG_BUTTON_GPIO=y +# CONFIG_USB_FUNCTION_FASTBOOT is not set CONFIG_ROCKCHIP_GPIO=y CONFIG_LED=y CONFIG_LED_GPIO=y @@ -43,6 +46,7 @@ CONFIG_DM_MDIO=y CONFIG_DWC_ETH_QOS=y CONFIG_DWC_ETH_QOS_ROCKCHIP=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y CONFIG_REGULATOR_PWM=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_PWM_ROCKCHIP=y @@ -50,6 +54,12 @@ CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_ROCKUSB=y CONFIG_ERRNO_STR=y From 4e3d2972d1bb3f891a8c827553524328d6679d14 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Wed, 13 Aug 2025 16:07:39 +0200 Subject: [PATCH 33/50] dt-bindings: mfd: rk806: Allow to customize PMIC reset mode The RK806 PMIC allows to configure its reset/restart behavior whenever the PMIC is reset either programmatically or via some external pins (e.g. PWRCTRL or RESETB). The following modes exist: - 0; restart PMU, - 1; reset all power off reset registers and force state to switch to ACTIVE mode, - 2; same as mode 1 and also pull RESETB pin down for 5ms, For example, some hardware may require a full restart (mode 0) in order to function properly as regulators are shortly interrupted in this mode. This is the case for RK3588 Jaguar and RK3588 Tiger which have a companion microcontroller running on an independent power supply and monitoring the PMIC power rail to know the state of the main system. When it detects a restart, it resets its own IPs exposed to the main system as if to simulate its own reset. Failing to perform this fake reset of the microcontroller may break things (e.g. watchdog not automatically disabled, buzzer still running until manually disabled, leftover configuration from previous main system state, etc...). Some other systems may be depending on the power rails to not be interrupted even for a small amount of time[1]. This allows to specify how the PMIC should perform on the hardware level and may differ between hardware designs, so a DT property seems warranted. I unfortunately do not see how this could be made generic enough to make it a non-vendor property. [1] https://lore.kernel.org/linux-rockchip/2577051.irdbgypaU6@workhorse/ Reviewed-by: Krzysztof Kozlowski Signed-off-by: Quentin Schulz Reviewed-by: "Rob Herring (Arm)" Link: https://lore.kernel.org/r/20250627-rk8xx-rst-fun-v4-1-ce05d041b45f@cherry.de Signed-off-by: Lee Jones [ upstream commit: 404005d1083997daec7236620b9ba14bccdce449 ] (cherry picked from commit 8ee72356e9844265334fd344bc05139d1f615c4d) Reviewed-by: Kever Yang --- dts/upstream/Bindings/mfd/rockchip,rk806.yaml | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/dts/upstream/Bindings/mfd/rockchip,rk806.yaml b/dts/upstream/Bindings/mfd/rockchip,rk806.yaml index 3c2b06629b7..eb5bca31948 100644 --- a/dts/upstream/Bindings/mfd/rockchip,rk806.yaml +++ b/dts/upstream/Bindings/mfd/rockchip,rk806.yaml @@ -31,6 +31,27 @@ properties: system-power-controller: true + rockchip,reset-mode: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2] + description: + Mode to use when a reset of the PMIC is triggered. + + The reset can be triggered either programmatically, via one of + the PWRCTRL pins (provided additional configuration) or + asserting RESETB pin low. + + The following modes are supported + + - 0; restart PMU, + - 1; reset all power off reset registers and force state to + switch to ACTIVE mode, + - 2; same as mode 1 and also pull RESETB pin down for 5ms, + + For example, some hardware may require a full restart (mode 0) + in order to function properly as regulators are shortly + interrupted in this mode. + vcc1-supply: description: The input supply for dcdc-reg1. From 289083811724327844e69f21e6785d8cd3f358fe Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Wed, 13 Aug 2025 16:07:40 +0200 Subject: [PATCH 34/50] arm64: dts: rockchip: add header for RK8XX PMIC constants To make it easier to read the device tree, let's add constants for the rockchip,reset-mode property values that are currently only applicable to RK806 PMIC. Signed-off-by: Quentin Schulz [dt-maintainers did not consider this part of the binding, so we're keeping the header in the devicetree directory] Link: https://lore.kernel.org/r/20250627-rk8xx-rst-fun-v4-3-ce05d041b45f@cherry.de Signed-off-by: Heiko Stuebner [ upstream commit: 304be20e65ca08fc2e9cb58eb939a0054d8a8b81 ] (cherry picked from commit 0e417bfcbc385c127c7f5ea01df6289aed8325c2) Reviewed-by: Kever Yang --- dts/upstream/src/arm64/rockchip/rk8xx.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 dts/upstream/src/arm64/rockchip/rk8xx.h diff --git a/dts/upstream/src/arm64/rockchip/rk8xx.h b/dts/upstream/src/arm64/rockchip/rk8xx.h new file mode 100644 index 00000000000..a6fbef71c06 --- /dev/null +++ b/dts/upstream/src/arm64/rockchip/rk8xx.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) */ +/* + * Device Tree defines for Rockchip RK8xx PMICs + * + * Copyright 2025 Cherry Embedded Solutions GmbH + * + * Author: Quentin Schulz + */ + +#ifndef _DT_MFD_ROCKCHIP_RK8XX_H +#define _DT_MFD_ROCKCHIP_RK8XX_H + +/* For use with rockchip,reset-mode property */ +#define RK806_RESTART 0 +#define RK806_RESET 1 +#define RK806_RESET_NOTIFY 2 + +#endif From 8df0eba814f666e92056909f59fd70b8e0af812d Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Wed, 13 Aug 2025 16:07:41 +0200 Subject: [PATCH 35/50] arm64: dts: rockchip: force PMIC reset behavior to restart PMU on RK3588 Jaguar The bootloader for RK3588 Jaguar currently forces the PMIC reset behavior (stored in RST_FUN bitfield in register SYS_CFG3 of the PMIC) to 0b1X which is incorrect for our devices. It is required to restart the PMU as otherwise the companion microcontroller cannot detect the PMIC (and by extension the full product and main SoC) being rebooted which is an issue as that is used to reset a few things like the PWM beeper and watchdogs. Let's add the new rockchip,reset-mode property to make sure the PMIC reset behavior is the expected one. Signed-off-by: Quentin Schulz Link: https://lore.kernel.org/r/20250627-rk8xx-rst-fun-v4-4-ce05d041b45f@cherry.de Signed-off-by: Heiko Stuebner [ upstream commit: ee907113430aa02a8202c91bb574c385ecc28aa2 ] (cherry picked from commit 8bd14566b75f9409de703a0d2f9a0704b71a7ebe) Reviewed-by: Kever Yang --- dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts b/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts index ebe77cdd24e..176925d0a1a 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts +++ b/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts @@ -10,6 +10,7 @@ #include #include #include +#include "rk8xx.h" #include "rk3588.dtsi" / { @@ -693,6 +694,7 @@ vcc13-supply = <&vcc_1v1_nldo_s3>; vcc14-supply = <&vcc_1v1_nldo_s3>; vcca-supply = <&vcc5v0_sys>; + rockchip,reset-mode = ; rk806_dvs1_null: dvs1-null-pins { pins = "gpio_pwrctrl1"; From 82d832716235f0f04782e66d7b25e711fe6afd6c Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Wed, 13 Aug 2025 16:07:42 +0200 Subject: [PATCH 36/50] arm64: dts: rockchip: force PMIC reset behavior to restart PMU on RK3588 Tiger The bootloader for RK3588 Tiger currently forces the PMIC reset behavior (stored in RST_FUN bitfield in register SYS_CFG3 of the PMIC) to 0b1X which is incorrect for our devices. It is required to restart the PMU as otherwise the companion microcontroller cannot detect the PMIC (and by extension the full product and main SoC) being rebooted which is an issue as that is used to reset a few things like the PWM beeper and watchdogs. Let's add the new rockchip,reset-mode property to make sure the PMIC reset behavior is the expected one. Signed-off-by: Quentin Schulz Link: https://lore.kernel.org/r/20250627-rk8xx-rst-fun-v4-5-ce05d041b45f@cherry.de Signed-off-by: Heiko Stuebner [ upstream commit: e82f642b9821384045915dc30e73df7de8424827 ] (cherry picked from commit d9c568906be166834f4f977bc7f704176bac5b8a) Reviewed-by: Kever Yang --- dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi index c4933a08dd1..b44e89e1bb1 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include "rk8xx.h" #include "rk3588.dtsi" / { @@ -440,6 +441,7 @@ vcc13-supply = <&vcc_1v1_nldo_s3>; vcc14-supply = <&vcc_1v1_nldo_s3>; vcca-supply = <&vcc5v0_sys>; + rockchip,reset-mode = ; rk806_dvs1_null: dvs1-null-pins { pins = "gpio_pwrctrl1"; From 1961bba4bc341573db98a6fd34eac771e914681f Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Wed, 13 Aug 2025 16:07:43 +0200 Subject: [PATCH 37/50] power: rk8xx: allow to customize RK806 reset mode The RK806 PMIC has a bitfield for configuring the restart/reset behavior (which I assume Rockchip calls "function") whenever the PMIC is reset either programmatically (c.f. DEV_RST in the datasheet) or via PWRCTRL or RESETB pins. For RK806, the following values are possible for RST_FUN: 0b00 means "Restart PMU" 0b01 means "Reset all the power off reset registers, forcing the state to switch to ACTIVE mode" 0b10 means "Reset all the power off reset registers, forcing the state to switch to ACTIVE mode, and simultaneously pull down the RESETB PIN for 5mS before releasing" 0b11 means the same as for 0b10 just above. This adds the appropriate logic in the driver to parse the new rockchip,reset-mode DT property to pass this information. It just happens that the values in the binding match the values to write in the bitfield so no mapping is necessary. For backward compatibility reasons, if the property is missing we set it to 0b10 (i.e. BIT(7)) like before this commit was merged instead of leaving it untouched like in the kernel driver. Note that this does nothing useful for U-Boot at the moment as the ways to reset the device (e.g. via `reset` command) doesn't interact with the RK8xx PMIC and simply does a CPU reset. Considering the upstream Linux kernel left this register untouched until (assumed) v6.17[1], this is useful for cases in which the U-Boot bootloader has this patch (and running with a DT with rockchip,reset-mode property set) and running an upstream kernel before (assumed) v6.17, or alternatively later without the property in the kernel DT. [1] https://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd.git/commit/?id=87b48d86b77686013f5c2a8866ed299312b671db Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang --- drivers/power/pmic/rk8xx.c | 21 ++++++++++++--------- include/power/rk8xx_pmic.h | 2 ++ 2 files changed, 14 insertions(+), 9 deletions(-) diff --git a/drivers/power/pmic/rk8xx.c b/drivers/power/pmic/rk8xx.c index 3bc696d4caa..d11f7a7886e 100644 --- a/drivers/power/pmic/rk8xx.c +++ b/drivers/power/pmic/rk8xx.c @@ -89,11 +89,6 @@ void rk8xx_off_for_plugin(struct udevice *dev) } } -static struct reg_data rk806_init_reg[] = { - /* RST_FUN */ - { RK806_REG_SYS_CFG3, BIT(7), GENMASK(7, 6)}, -}; - static struct reg_data rk817_init_reg[] = { /* enable the under-voltage protection, * the under-voltage protection will shutdown the LDO3 and reset the PMIC @@ -306,12 +301,20 @@ static int rk8xx_probe(struct udevice *dev) value = (power_en2 & 0x0f) | ((power_en3 & 0x0f) << 4); pmic_reg_write(dev, RK817_POWER_EN_SAVE1, value); break; - case RK806_ID: + case RK806_ID: { + u32 rst_fun = 2; + on_source = RK806_ON_SOURCE; off_source = RK806_OFF_SOURCE; - init_data = rk806_init_reg; - init_data_num = ARRAY_SIZE(rk806_init_reg); - break; + + ret = dev_read_u32(dev, "rockchip,reset-mode", &rst_fun); + if (ret) + debug("rockchip,reset-mode property missing, defaulting to %d\n", + rst_fun); + + pmic_clrsetbits(dev, RK806_REG_SYS_CFG3, RK806_RST_FUN_MSK, + FIELD_PREP(RK806_RST_FUN_MSK, rst_fun)); + break; } default: printf("Unknown PMIC: RK%x!!\n", show_variant); return -EINVAL; diff --git a/include/power/rk8xx_pmic.h b/include/power/rk8xx_pmic.h index 31221aa46b6..913b6ebe6d9 100644 --- a/include/power/rk8xx_pmic.h +++ b/include/power/rk8xx_pmic.h @@ -212,6 +212,8 @@ enum { #define RK817_POWER_EN_SAVE0 0x99 #define RK817_POWER_EN_SAVE1 0xa4 +#define RK806_RST_FUN_MSK GENMASK(7, 6) + #define RK806_POWER_EN(x) (0x00 + (x)) /* POWER_ENx register lower 4 bits are write-protected unless the associated top bit is set */ #define RK806_POWER_EN_CLRSETBITS(bit, val) (((val) << (bit)) | (1 << ((bit) + 4))) From 97b0f9f8ce4fc8d994fad60660e1daba2da190e9 Mon Sep 17 00:00:00 2001 From: Andrew Goodbody Date: Thu, 31 Jul 2025 12:46:10 +0100 Subject: [PATCH 38/50] mmc: rockchip_sdhci: Do not test unsigned for being less than 0 In rockchip_sdhci_execute_tuning the variable tuning_loop_counter is tested for being less than 0. Ensure that it is a signed type by declaring it as s8 instead of char. This issue was found by Smatch. Signed-off-by: Andrew Goodbody Reviewed-by: Peng Fan Reviewed-by: Kever Yang --- drivers/mmc/rockchip_sdhci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c index 761e3619329..5e025d76a82 100644 --- a/drivers/mmc/rockchip_sdhci.c +++ b/drivers/mmc/rockchip_sdhci.c @@ -500,7 +500,7 @@ static int rockchip_sdhci_execute_tuning(struct mmc *mmc, u8 opcode) { struct rockchip_sdhc *priv = dev_get_priv(mmc->dev); struct sdhci_host *host = &priv->host; - char tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT; + s8 tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT; struct mmc_cmd cmd; u32 ctrl, blk_size; int ret; From b2ebdd592ecd1309e26a7c428200b9d6c0ce9700 Mon Sep 17 00:00:00 2001 From: Diederik de Haas Date: Thu, 31 Jul 2025 14:47:05 +0200 Subject: [PATCH 39/50] rockchip: rk3568-nanopi-r5s: Enable ROCKUSB on NanoPi R5S Enable the needed modules so that ROCKUSB can be used to update the NanoPi R5S. Signed-off-by: Diederik de Haas Reviewed-by: Kever Yang --- configs/nanopi-r5s-rk3568_defconfig | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/configs/nanopi-r5s-rk3568_defconfig b/configs/nanopi-r5s-rk3568_defconfig index 8e5e7e3e1e5..1653ab8b44f 100644 --- a/configs/nanopi-r5s-rk3568_defconfig +++ b/configs/nanopi-r5s-rk3568_defconfig @@ -28,6 +28,8 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set @@ -38,6 +40,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y CONFIG_SPL_CLK=y +# CONFIG_USB_FUNCTION_FASTBOOT is not set CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y @@ -73,4 +76,8 @@ CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_ROCKUSB=y CONFIG_ERRNO_STR=y From ffa1485c8173668424ca0ad87020966658092772 Mon Sep 17 00:00:00 2001 From: Niu Zhihong Date: Wed, 23 Jul 2025 12:22:17 +0800 Subject: [PATCH 40/50] board: rockchip: Add Xunlong Orange Pi 5 Ultra The Orange Pi 5 Ultra is another board in the Orange Pi 5 family. Orange Pi 5 Ultra uses Rockchip RK3588, a new generation of octa-core 64-bit ARM processor, which includes quad-core A76 and quad-core A55. Features tested on a Orange Pi 5 Ultra 16GB: - SD-card boot - eMMC boot ROCKCHIP_TPL: https://github.com/rockchip-linux/rkbin/tree/master/bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v1.18.bin BL31: https://github.com/rockchip-linux/rkbin/tree/master/bin/rk35/rk3588_bl31_v1.48.elf Signed-off-by: Niu Zhihong Reviewed-by: Kever Yang --- .../dts/rk3588-orangepi-5-ultra-u-boot.dtsi | 20 +++++ board/rockchip/evb_rk3588/MAINTAINERS | 6 ++ board/xunlong/orangepi-5-ultra-rk3588/Kconfig | 12 +++ .../orangepi-5-ultra-rk3588/MAINTAINERS | 6 ++ configs/orangepi-5-ultra-rk3588_defconfig | 88 +++++++++++++++++++ doc/board/rockchip/rockchip.rst | 1 + 6 files changed, 133 insertions(+) create mode 100644 arch/arm/dts/rk3588-orangepi-5-ultra-u-boot.dtsi create mode 100644 board/xunlong/orangepi-5-ultra-rk3588/Kconfig create mode 100644 board/xunlong/orangepi-5-ultra-rk3588/MAINTAINERS create mode 100644 configs/orangepi-5-ultra-rk3588_defconfig diff --git a/arch/arm/dts/rk3588-orangepi-5-ultra-u-boot.dtsi b/arch/arm/dts/rk3588-orangepi-5-ultra-u-boot.dtsi new file mode 100644 index 00000000000..1ab31a4ec5a --- /dev/null +++ b/arch/arm/dts/rk3588-orangepi-5-ultra-u-boot.dtsi @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3588-u-boot.dtsi" + +&fspim1_pins { + bootph-pre-ram; + bootph-some-ram; +}; + +&sdhci { + cap-mmc-highspeed; + mmc-hs200-1_8v; +}; + +&sfc { + flash@0 { + bootph-pre-ram; + bootph-some-ram; + }; +}; diff --git a/board/rockchip/evb_rk3588/MAINTAINERS b/board/rockchip/evb_rk3588/MAINTAINERS index 1232f05a387..379c85f48a4 100644 --- a/board/rockchip/evb_rk3588/MAINTAINERS +++ b/board/rockchip/evb_rk3588/MAINTAINERS @@ -48,3 +48,9 @@ S: Maintained F: configs/orangepi-5-plus-rk3588_defconfig F: arch/arm/dts/rk3588-orangepi-5-plus.dts F: arch/arm/dts/rk3588-orangepi-5-plus-u-boot.dtsi + +ORANGEPI-5-RK3588-ULTRA +M: Niu Zhihong +S: Maintained +F: configs/orangepi-5-ultra-rk3588_defconfig +F: arch/arm/dts/rk3588-orangepi-5-ultra-u-boot.dtsi diff --git a/board/xunlong/orangepi-5-ultra-rk3588/Kconfig b/board/xunlong/orangepi-5-ultra-rk3588/Kconfig new file mode 100644 index 00000000000..43fc96b04c0 --- /dev/null +++ b/board/xunlong/orangepi-5-ultra-rk3588/Kconfig @@ -0,0 +1,12 @@ +if TARGET_ORANGEPI_5_ULTRA_RK3588 + +config SYS_BOARD + default "orangepi-5-ultra-rk3588" + +config SYS_VENDOR + default "xunlong" + +config SYS_CONFIG_NAME + default "evb_rk3588" + +endif diff --git a/board/xunlong/orangepi-5-ultra-rk3588/MAINTAINERS b/board/xunlong/orangepi-5-ultra-rk3588/MAINTAINERS new file mode 100644 index 00000000000..be9c93f6b9d --- /dev/null +++ b/board/xunlong/orangepi-5-ultra-rk3588/MAINTAINERS @@ -0,0 +1,6 @@ +ORANGEPI-5-RK3588-ULTRA +M: Niu Zhihong +S: Maintained +F: board/xunlong/orangepi-5-rk3588-ultra +F: configs/orangepi-5-ultra-rk3588_defconfig +F: arch/arm/dts/rk3588-orangepi-5-ultra.dts diff --git a/configs/orangepi-5-ultra-rk3588_defconfig b/configs/orangepi-5-ultra-rk3588_defconfig new file mode 100644 index 00000000000..f3274325922 --- /dev/null +++ b/configs/orangepi-5-ultra-rk3588_defconfig @@ -0,0 +1,88 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SF_DEFAULT_SPEED=80000000 +CONFIG_SF_DEFAULT_MODE=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588-orangepi-5-ultra" +CONFIG_ROCKCHIP_RK3588=y +CONFIG_ROCKCHIP_SPI_IMAGE=y +CONFIG_SPL_SERIAL=y +CONFIG_TARGET_EVB_RK3588=y +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_SF_DEFAULT_BUS=5 +CONFIG_DEBUG_UART_BASE=0xFEB50000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-orangepi-5-ultra.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_AHCI_PCI=y +CONFIG_DWC_AHCI=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_XMC=y +CONFIG_PHYLIB=y +CONFIG_RTL8169=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_PHY_ROCKCHIP_USBDP=y +CONFIG_SPL_PINCTRL=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_SCSI=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SFC=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_ERRNO_STR=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 1ac44ba0a52..de3aa79cb5c 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -164,6 +164,7 @@ List of mainline supported Rockchip boards: - Xunlong Orange Pi 5 (orangepi-5-rk3588s) - Xunlong Orange Pi 5 Max (orangepi-5-max-rk3588) - Xunlong Orange Pi 5 Plus (orangepi-5-plus-rk3588) + - Xunlong Orange Pi 5 Ultra (orangepi-5-ultra-rk3588) - Yanyi Tech CoolPi 4 Model B (coolpi-4b-rk3588s) - Yanyi Tech CoolPi CM5 EVB (coolpi-cm5-evb-rk3588) - Yanyi Tech CoolPi CM5 GenBook (coolpi-cm5-genbook-rk3588) From 0336e97b1187f7f54e11c6cb9f3fa938cc11204e Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Mon, 21 Jul 2025 22:07:10 +0000 Subject: [PATCH 41/50] phy: rockchip: usbdp: Fix Generic PHY reference counting Generic PHY reference counting helps ensure driver ops for init/exit and power on/off are called at correct state. For this to work the PHY driver must initialize PHY-id to a persistent value in of_xlate ops. The Rockchip USBDP PHY driver does not initialize the PHY-id field, this typically lead to use of unshared reference counting among different struct phy instances. Initialize the PHY-id in of_xlate ops to ensure use of shared reference counting among all struct phy instances. E.g. on a ROCK 5B following could be observed: => usb start starting USB... [...] Bus usb@fc400000: 2 USB Device(s) found scanning usb for storage devices... 1 Storage Device(s) found => usb reset resetting USB... [...] rockchip_udphy phy@fed90000: cmn ana lcpll lock timeout rockchip_udphy phy@fed90000: failed to init usbdp combophy rockchip_udphy phy@fed90000: PHY: Failed to init phy@fed90000: -110. Can't init PHY1 Bus usb@fc400000: probe failed, error -110 scanning usb for storage devices... 0 Storage Device(s) found With shared reference counting this is fixed: => usb reset resetting USB... [...] Bus usb@fc400000: 2 USB Device(s) found scanning usb for storage devices... 1 Storage Device(s) found Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- drivers/phy/rockchip/phy-rockchip-usbdp.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockchip/phy-rockchip-usbdp.c index ed0441842a1..c88eb0c1611 100644 --- a/drivers/phy/rockchip/phy-rockchip-usbdp.c +++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c @@ -587,12 +587,16 @@ static int udphy_power_off(struct rockchip_udphy *udphy, u8 mode) static int rockchip_u3phy_of_xlate(struct phy *phy, struct ofnode_phandle_args *args) { + struct rockchip_udphy *udphy = dev_get_priv(phy->dev); + if (args->args_count == 0) return -EINVAL; if (args->args[0] != PHY_TYPE_USB3) return -EINVAL; + phy->id = udphy->id; + return 0; } From 1e8370318f89b4a15d5ff9259363e44a852541b2 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Mon, 21 Jul 2025 22:07:11 +0000 Subject: [PATCH 42/50] phy: rockchip: usbdp: Simplify init ops With working shared reference counting for Generic PHY ops there is no need for the Rockchip USBDP PHY driver to keep its own status (reference counting) handling. Simplify the init ops now that shared reference counting is working. This also removes the unused mode_change handling as part of the simplication. No runtime change is expected with this simplication. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- drivers/phy/rockchip/phy-rockchip-usbdp.c | 71 +++-------------------- 1 file changed, 8 insertions(+), 63 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockchip/phy-rockchip-usbdp.c index c88eb0c1611..cca67dd3611 100644 --- a/drivers/phy/rockchip/phy-rockchip-usbdp.c +++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c @@ -96,9 +96,7 @@ struct rockchip_udphy { /* PHY status management */ bool flip; - bool mode_change; u8 mode; - u8 status; /* utilized for USB */ bool hs; /* flag for high-speed */ @@ -525,65 +523,6 @@ static int udphy_parse_dt(struct rockchip_udphy *udphy, struct udevice *dev) return 0; } -static int udphy_power_on(struct rockchip_udphy *udphy, u8 mode) -{ - int ret; - - if (!(udphy->mode & mode)) { - dev_info(udphy->dev, "mode 0x%02x is not support\n", mode); - return 0; - } - - if (udphy->status == UDPHY_MODE_NONE) { - udphy->mode_change = false; - ret = udphy_setup(udphy); - if (ret) - return ret; - - if (udphy->mode & UDPHY_MODE_USB) - udphy_u3_port_disable(udphy, false); - } else if (udphy->mode_change) { - udphy->mode_change = false; - udphy->status = UDPHY_MODE_NONE; - if (udphy->mode == UDPHY_MODE_DP) - udphy_u3_port_disable(udphy, true); - - ret = udphy_disable(udphy); - if (ret) - return ret; - ret = udphy_setup(udphy); - if (ret) - return ret; - } - - udphy->status |= mode; - - return 0; -} - -static int udphy_power_off(struct rockchip_udphy *udphy, u8 mode) -{ - int ret; - - if (!(udphy->mode & mode)) { - dev_info(udphy->dev, "mode 0x%02x is not supported\n", mode); - return 0; - } - - if (!udphy->status) - return 0; - - udphy->status &= ~mode; - - if (udphy->status == UDPHY_MODE_NONE) { - ret = udphy_disable(udphy); - if (ret) - return ret; - } - - return 0; -} - static int rockchip_u3phy_of_xlate(struct phy *phy, struct ofnode_phandle_args *args) { @@ -603,6 +542,7 @@ static int rockchip_u3phy_of_xlate(struct phy *phy, static int rockchip_u3phy_init(struct phy *phy) { struct rockchip_udphy *udphy = dev_get_priv(phy->dev); + int ret; /* DP only or high-speed, disable U3 port */ if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) { @@ -610,7 +550,12 @@ static int rockchip_u3phy_init(struct phy *phy) return 0; } - return udphy_power_on(udphy, UDPHY_MODE_USB); + ret = udphy_setup(udphy); + if (ret) + return ret; + + udphy_u3_port_disable(udphy, false); + return 0; } static int rockchip_u3phy_exit(struct phy *phy) @@ -621,7 +566,7 @@ static int rockchip_u3phy_exit(struct phy *phy) if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) return 0; - return udphy_power_off(udphy, UDPHY_MODE_USB); + return udphy_disable(udphy); } static const struct phy_ops rockchip_u3phy_ops = { From dfd2774cfc4434ef35b48febcd1dc1860a3dc8f8 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Mon, 21 Jul 2025 22:07:12 +0000 Subject: [PATCH 43/50] phy: rockchip: naneng-combphy: Fix Generic PHY reference counting Generic PHY reference counting helps ensure driver ops for init/exit and power on/off are called at correct state. For this to work the PHY driver must initialize PHY-id to a persistent value in of_xlate ops. The Rockchip COMBPHY driver does not initialize the PHY-id field, this typically lead to use of unshared reference counting among different struct phy instances. Initialize the PHY-id in of_xlate ops to ensure use of shared reference counting among all struct phy instances. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c index 6d8d10750b1..a66be0608d4 100644 --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c @@ -224,6 +224,7 @@ static int rockchip_combphy_xlate(struct phy *phy, struct ofnode_phandle_args *a return -EINVAL; } + phy->id = priv->id; priv->mode = args->args[0]; return 0; From 8a3d377d4ccd409b56b9a6eef20613472e4471fd Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Mon, 21 Jul 2025 22:07:13 +0000 Subject: [PATCH 44/50] phy: rockchip: naneng-combphy: Simplify init ops The init ops for Rockchip COMBPHY driver is more complex than it needs to be, e.g. declaring multiple init functions that only differ in the error message. Simplify the init ops based on code from the Linux mainline driver. This change also ensure that errors returned from combphy_cfg() and reset_deassert_bulk() is propertly propagated to the caller. No other runtime change is expected with this simplication. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- .../rockchip/phy-rockchip-naneng-combphy.c | 111 ++++-------------- 1 file changed, 24 insertions(+), 87 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c index a66be0608d4..9345378aa50 100644 --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c @@ -99,89 +99,6 @@ static int param_write(struct regmap *base, return regmap_write(base, reg->offset, val); } -static int rockchip_combphy_pcie_init(struct rockchip_combphy_priv *priv) -{ - int ret = 0; - - if (priv->cfg->combphy_cfg) { - ret = priv->cfg->combphy_cfg(priv); - if (ret) { - dev_err(priv->dev, "failed to init phy for pcie\n"); - return ret; - } - } - - return ret; -} - -static int rockchip_combphy_usb3_init(struct rockchip_combphy_priv *priv) -{ - int ret = 0; - - if (priv->cfg->combphy_cfg) { - ret = priv->cfg->combphy_cfg(priv); - if (ret) { - dev_err(priv->dev, "failed to init phy for usb3\n"); - return ret; - } - } - - return ret; -} - -static int rockchip_combphy_sata_init(struct rockchip_combphy_priv *priv) -{ - int ret = 0; - - if (priv->cfg->combphy_cfg) { - ret = priv->cfg->combphy_cfg(priv); - if (ret) { - dev_err(priv->dev, "failed to init phy for sata\n"); - return ret; - } - } - - return ret; -} - -static int rockchip_combphy_sgmii_init(struct rockchip_combphy_priv *priv) -{ - int ret = 0; - - if (priv->cfg->combphy_cfg) { - ret = priv->cfg->combphy_cfg(priv); - if (ret) { - dev_err(priv->dev, "failed to init phy for sgmii\n"); - return ret; - } - } - - return ret; -} - -static int rockchip_combphy_set_mode(struct rockchip_combphy_priv *priv) -{ - switch (priv->mode) { - case PHY_TYPE_PCIE: - rockchip_combphy_pcie_init(priv); - break; - case PHY_TYPE_USB3: - rockchip_combphy_usb3_init(priv); - break; - case PHY_TYPE_SATA: - rockchip_combphy_sata_init(priv); - break; - case PHY_TYPE_SGMII: - case PHY_TYPE_QSGMII: - return rockchip_combphy_sgmii_init(priv); - default: - dev_err(priv->dev, "incompatible PHY type\n"); - return -EINVAL; - } - - return 0; -} - static int rockchip_combphy_init(struct phy *phy) { struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev); @@ -191,12 +108,32 @@ static int rockchip_combphy_init(struct phy *phy) if (ret < 0 && ret != -ENOSYS) return ret; - ret = rockchip_combphy_set_mode(priv); + switch (priv->mode) { + case PHY_TYPE_PCIE: + case PHY_TYPE_USB3: + case PHY_TYPE_SATA: + case PHY_TYPE_SGMII: + case PHY_TYPE_QSGMII: + if (priv->cfg->combphy_cfg) + ret = priv->cfg->combphy_cfg(priv); + else + ret = 0; + break; + default: + dev_err(priv->dev, "incompatible PHY type\n"); + ret = -EINVAL; + break; + } + + if (ret) { + dev_err(priv->dev, "failed to init phy for phy type %x\n", priv->mode); + goto err_clk; + } + + ret = reset_deassert_bulk(&priv->phy_rsts); if (ret) goto err_clk; - reset_deassert_bulk(&priv->phy_rsts); - return 0; err_clk: @@ -306,7 +243,7 @@ static int rockchip_combphy_probe(struct udevice *udev) } priv->dev = udev; - priv->mode = PHY_TYPE_SATA; + priv->mode = PHY_NONE; priv->cfg = phy_cfg; return rockchip_combphy_parse_dt(udev, priv); From 12dd645914a4e5e65d92a4754d0dacbdbf1e4a55 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Mon, 21 Jul 2025 22:07:14 +0000 Subject: [PATCH 45/50] phy: rockchip: naneng-combphy: Use syscon_regmap_lookup_by_phandle Change to use syscon_regmap_lookup_by_phandle() helper instead of finding the syscon udevice and making a call to syscon_get_regmap(). No runtime change is expected with this simplication. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- .../phy/rockchip/phy-rockchip-naneng-combphy.c | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c index 9345378aa50..d602f965d6a 100644 --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c @@ -176,22 +176,19 @@ static const struct phy_ops rockchip_combphy_ops = { static int rockchip_combphy_parse_dt(struct udevice *dev, struct rockchip_combphy_priv *priv) { - struct udevice *syscon; int ret; - ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pipe-grf", &syscon); - if (ret) { - dev_err(dev, "failed to find peri_ctrl pipe-grf regmap"); - return ret; + priv->pipe_grf = syscon_regmap_lookup_by_phandle(dev, "rockchip,pipe-grf"); + if (IS_ERR(priv->pipe_grf)) { + dev_err(dev, "failed to find peri_ctrl pipe-grf regmap\n"); + return PTR_ERR(priv->pipe_grf); } - priv->pipe_grf = syscon_get_regmap(syscon); - ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pipe-phy-grf", &syscon); - if (ret) { + priv->phy_grf = syscon_regmap_lookup_by_phandle(dev, "rockchip,pipe-phy-grf"); + if (IS_ERR(priv->phy_grf)) { dev_err(dev, "failed to find peri_ctrl pipe-phy-grf regmap\n"); - return ret; + return PTR_ERR(priv->phy_grf); } - priv->phy_grf = syscon_get_regmap(syscon); ret = clk_get_by_index(dev, 0, &priv->ref_clk); if (ret) { From c8e6a7131d58511129cdec16f269600b51f0a45a Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Mon, 21 Jul 2025 22:07:15 +0000 Subject: [PATCH 46/50] phy: rockchip: inno-usb2: Fix improper use of UCLASS_PHY The Rockchip USB2PHY glue driver improperly present itself as a UCLASS_PHY driver, without ever implementing the required phy_ops. This is something that in special circumstances can lead to a NULL pointer dereference followed by a SError crash. Change the glue driver to use UCLASS_NOP to fix this. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c index 03fe1b38175..4ea6600ce7f 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c @@ -573,7 +573,7 @@ U_BOOT_DRIVER(rockchip_usb2phy_clock) = { U_BOOT_DRIVER(rockchip_usb2phy) = { .name = "rockchip_usb2phy", - .id = UCLASS_PHY, + .id = UCLASS_NOP, .of_match = rockchip_usb2phy_ids, .probe = rockchip_usb2phy_probe, .bind = rockchip_usb2phy_bind, From fca01a8792e6ed48a00e08124d55f4f74e47b11d Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Mon, 21 Jul 2025 22:07:16 +0000 Subject: [PATCH 47/50] phy: rockchip: typec: Fix improper use of UCLASS_PHY The Rockchip TypeC glue driver improperly present itself as a UCLASS_PHY driver, without ever implementing the required phy_ops. This is something that in special circumstances can lead to a NULL pointer dereference followed by a SError crash. Change the glue driver to use UCLASS_NOP to fix this. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- drivers/phy/rockchip/phy-rockchip-typec.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/phy/rockchip/phy-rockchip-typec.c b/drivers/phy/rockchip/phy-rockchip-typec.c index c48a5cd5267..66d1d32d25c 100644 --- a/drivers/phy/rockchip/phy-rockchip-typec.c +++ b/drivers/phy/rockchip/phy-rockchip-typec.c @@ -788,7 +788,7 @@ U_BOOT_DRIVER(rockchip_tcphy_usb3_port) = { U_BOOT_DRIVER(rockchip_typec_phy) = { .name = "rockchip_typec_phy", - .id = UCLASS_PHY, + .id = UCLASS_NOP, .of_match = rockchip_typec_phy_ids, .probe = rockchip_tcphy_probe, .bind = rockchip_tcphy_bind, From 9d39a56922878562b263e45f45523021cf5e7789 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Mon, 21 Jul 2025 22:07:17 +0000 Subject: [PATCH 48/50] rockchip: rk3588: Disable USB3OTG U3 ports early The RK3588 SoC comes with USB OTG support using a DWC3 controller with a USB2 PHY and a USB3 PHY (USBDP PHY). Some board designs may not use the USBDP PHY for USB3 purpose. For these board to use USB OTG the input clock source must change to use UTMI clk instead of PIPE clk. Change to always disable the USB3OTG U3 ports early and leave it to the USBDP PHY driver to re-enable the U3 port when a usb3-phy is described in the board device tree. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/rk3588/rk3588.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c b/arch/arm/mach-rockchip/rk3588/rk3588.c index e2278ff792b..c01a4002089 100644 --- a/arch/arm/mach-rockchip/rk3588/rk3588.c +++ b/arch/arm/mach-rockchip/rk3588/rk3588.c @@ -15,6 +15,10 @@ #include #include +#define USB_GRF_BASE 0xfd5ac000 +#define USB3OTG0_CON1 0x001c +#define USB3OTG1_CON1 0x0034 + #define FIREWALL_DDR_BASE 0xfe030000 #define FW_DDR_MST5_REG 0x54 #define FW_DDR_MST13_REG 0x74 @@ -184,6 +188,10 @@ int arch_cpu_init(void) /* Disable JTAG exposed on SDMMC */ rk_clrreg(&sys_grf->soc_con[6], SYS_GRF_FORCE_JTAG); #endif + + /* Disable USB3OTG U3 ports, later enabled by USBDP PHY driver */ + writel(0xffff0188, USB_GRF_BASE + USB3OTG0_CON1); + writel(0xffff0188, USB_GRF_BASE + USB3OTG1_CON1); #endif return 0; From be585d4916864387c53c82b4bde7f04093aac440 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Mon, 21 Jul 2025 22:07:18 +0000 Subject: [PATCH 49/50] rockchip: rk3576: Disable USB3OTG0 U3 port early The RK3576 SoC comes with USB OTG support using a DWC3 controller with a USB2 PHY and a USB3 PHY (USBDP PHY). Some board designs may not use the USBDP PHY for USB3 purpose. For these board to use USB OTG the input clock source must change to use UTMI clk instead of PIPE clk. Change to always disable the USB3OTG0 U3 port early and leave it to the USBDP PHY driver to re-enable the U3 port when a usb3-phy is described in the board device tree. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/rk3576/rk3576.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/mach-rockchip/rk3576/rk3576.c b/arch/arm/mach-rockchip/rk3576/rk3576.c index 2b1318f9532..a6c2fbdc484 100644 --- a/arch/arm/mach-rockchip/rk3576/rk3576.c +++ b/arch/arm/mach-rockchip/rk3576/rk3576.c @@ -33,6 +33,9 @@ #define SGRF_DOMAIN_CON4 0x10 #define SGRF_DOMAIN_CON5 0x14 +#define USB_GRF_BASE 0x2601E000 +#define USB3OTG0_CON1 0x0030 + const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { [BROM_BOOTSOURCE_EMMC] = "/soc/mmc@2a330000", [BROM_BOOTSOURCE_SD] = "/soc/mmc@2a310000", @@ -155,6 +158,9 @@ int arch_cpu_init(void) */ writel(0xffffff00, SYS_SGRF_BASE + SYS_SGRF_SOC_CON20); + /* Disable USB3OTG0 U3 port, later enabled by USBDP PHY driver */ + writel(0xffff0188, USB_GRF_BASE + USB3OTG0_CON1); + return 0; } From 0e68a93d7c220e37cf6ffe88ba47373e39fe5001 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Mon, 21 Jul 2025 22:07:19 +0000 Subject: [PATCH 50/50] rockchip: rk3588-generic: Move usb nodes to board dts After the commit 7a53abb18325 ("rockchip: rk3588: Remove USB3 DRD nodes in u-boot.dtsi") was merged for v2024.10 there is no reason to keep the usb nodes for the Generic RK3588 board in the board u-boot.dtsi. Move usb related nodes from board u-boot.dtsi to main board device tree. While at it, also drop use of the usb3-phy as we only want to enable the usb2-phy to be compatible with as many boards as possible. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rk3588-generic-u-boot.dtsi | 18 ------------------ arch/arm/dts/rk3588-generic.dts | 16 ++++++++++++++++ configs/generic-rk3588_defconfig | 1 - 3 files changed, 16 insertions(+), 19 deletions(-) diff --git a/arch/arm/dts/rk3588-generic-u-boot.dtsi b/arch/arm/dts/rk3588-generic-u-boot.dtsi index f67301d87a6..853ed58cfe5 100644 --- a/arch/arm/dts/rk3588-generic-u-boot.dtsi +++ b/arch/arm/dts/rk3588-generic-u-boot.dtsi @@ -1,21 +1,3 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) #include "rk3588s-u-boot.dtsi" - -&u2phy0 { - status = "okay"; -}; - -&u2phy0_otg { - status = "okay"; -}; - -&usbdp_phy0 { - status = "okay"; -}; - -&usb_host0_xhci { - dr_mode = "peripheral"; - maximum-speed = "high-speed"; - status = "okay"; -}; diff --git a/arch/arm/dts/rk3588-generic.dts b/arch/arm/dts/rk3588-generic.dts index 95d757676f1..6740f9866f1 100644 --- a/arch/arm/dts/rk3588-generic.dts +++ b/arch/arm/dts/rk3588-generic.dts @@ -39,7 +39,23 @@ status = "okay"; }; +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + &uart2 { pinctrl-0 = <&uart2m0_xfer>; status = "okay"; }; + +&usb_host0_xhci { + dr_mode = "peripheral"; + maximum-speed = "high-speed"; + phys = <&u2phy0_otg>; + phy-names = "usb2-phy"; + status = "okay"; +}; diff --git a/configs/generic-rk3588_defconfig b/configs/generic-rk3588_defconfig index ed2f936b324..dfa8efabe6b 100644 --- a/configs/generic-rk3588_defconfig +++ b/configs/generic-rk3588_defconfig @@ -53,7 +53,6 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y -CONFIG_PHY_ROCKCHIP_USBDP=y CONFIG_SPL_PINCTRL=y CONFIG_SPL_RAM=y CONFIG_BAUDRATE=1500000