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arm64: dts: renesas: Add Renesas R-Car X5H R8A78000 Ironhide board code
Add initial support for Renesas R-Car X5H R8A78000 Ironhide board. This consists mainly of DTs, Makefile and Kconfig entries and board specific configuration files. The DTs will be gradually switched over to Linux DTs via OF_UPSTREAM once Linux DTs become available upstream, as upstreaming progresses. Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
This commit is contained in:
Hai Pham
Marek Vasut
parent
b546189a4b
commit
cf71963778
@ -918,6 +918,13 @@ dtb-$(CONFIG_RZA1) += \
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r7s72100-genmai.dtb \
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r7s72100-gr-peach.dtb
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dtb-$(CONFIG_RCAR_GEN5) += \
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r8a78000-ironhide.dtb
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ifdef CONFIG_RCAR_GEN5
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DTC_FLAGS += -R 4 -p 0x1000
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endif
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dtb-$(CONFIG_TARGET_AT91SAM9261EK) += at91sam9261ek.dtb
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dtb-$(CONFIG_TARGET_PM9261) += at91sam9261ek.dtb
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8
arch/arm/dts/r8a78000-ironhide-u-boot.dtsi
Normal file
8
arch/arm/dts/r8a78000-ironhide-u-boot.dtsi
Normal file
@ -0,0 +1,8 @@
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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/*
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* Device Tree Source extras for U-Boot for the Ironhide board
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*
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* Copyright (C) 2025 Renesas Electronics Corp.
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*/
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#include "r8a78000-u-boot.dtsi"
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257
arch/arm/dts/r8a78000-ironhide.dts
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257
arch/arm/dts/r8a78000-ironhide.dts
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@ -0,0 +1,257 @@
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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/*
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* Device Tree Source for the Ironhide board
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*
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* Copyright (C) 2025 Renesas Electronics Corp.
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*/
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/dts-v1/;
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#include "r8a78000.dtsi"
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#include <dt-bindings/net/ti-dp83869.h>
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/ {
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model = "Renesas Ironhide board based on r8a78000";
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compatible = "renesas,ironhide", "renesas,r8a78000";
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aliases {
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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i2c3 = &i2c3;
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i2c4 = &i2c4;
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i2c5 = &i2c5;
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i2c6 = &i2c6;
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i2c7 = &i2c7;
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i2c8 = &i2c8;
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mmc0 = &mmc0;
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serial0 = &hscif0;
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};
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chosen {
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stdout-path = "serial0:1843200n8";
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};
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memory@40000000 {
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device_type = "memory";
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reg = <0x0 0x40000000 0x0 0x80000000>;
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};
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memory@1080000000 {
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device_type = "memory";
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reg = <0x10 0x80000000 0x0 0x80000000>;
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};
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memory@1200000000 {
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device_type = "memory";
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reg = <0x12 0x00000000 0x1 0x00000000>;
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};
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memory@1400000000 {
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device_type = "memory";
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reg = <0x14 0x00000000 0x1 0x00000000>;
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};
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memory@1600000000 {
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device_type = "memory";
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reg = <0x16 0x00000000 0x1 0x00000000>;
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};
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memory@1800000000 {
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device_type = "memory";
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reg = <0x18 0x00000000 0x1 0x00000000>;
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};
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memory@1a00000000 {
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device_type = "memory";
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reg = <0x1a 0x00000000 0x1 0x00000000>;
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};
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memory@1c00000000 {
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device_type = "memory";
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reg = <0x1c 0x00000000 0x1 0x00000000>;
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};
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memory@1e00000000 {
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device_type = "memory";
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reg = <0x1e 0x00000000 0x1 0x00000000>;
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};
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reg_1p8v: regulator-1p8v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-1.8V";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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reg_3p3v: regulator-3p3v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-3.3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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};
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&extal_clk {
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clock-frequency = <16666600>;
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};
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&extalr_clk {
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clock-frequency = <32768>;
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};
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&hscif0 {
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pinctrl-0 = <&hscif0_pins>;
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pinctrl-names = "default";
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uart-has-rtscts;
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status = "okay";
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};
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&i2c0 {
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pinctrl-0 = <&i2c0_pins>;
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pinctrl-names = "default";
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clock-frequency = <400000>;
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status = "okay";
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eeprom@50 {
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compatible = "rohm,br24g01", "atmel,24c01";
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reg = <0x50>;
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pagesize = <8>;
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};
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};
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&i2c1 {
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pinctrl-0 = <&i2c1_pins>;
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pinctrl-names = "default";
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clock-frequency = <400000>;
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status = "okay";
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};
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ð_pcs {
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phys = <&mp_phy 2 1>;
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status = "okay";
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};
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&mmc0 {
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pinctrl-0 = <&mmc0_pins>;
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pinctrl-1 = <&mmc0_pins>;
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pinctrl-names = "default", "state_uhs";
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bus-width = <8>;
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full-pwr-cycle-in-suspend;
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mmc-hs200-1_8v;
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mmc-hs400-1_8v;
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no-sd;
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no-sdio;
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non-removable;
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vmmc-supply = <®_3p3v>;
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vqmmc-supply = <®_1p8v>;
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status = "okay";
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};
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&ufs0 {
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status = "okay";
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};
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&ufs1 {
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status = "okay";
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};
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&mp_phy {
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status = "okay";
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};
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&pfc {
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pinctrl-0 = <&scif_clk_pins>;
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pinctrl-names = "default";
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eth25g2_pins: eth25g2 {
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groups = "eth25g2_mdio", "eth25g2_link", "eth25g2_phyint";
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function = "eth25g2";
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drive-strength = <24>;
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};
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ethes0_pins: ethes0 {
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groups = "ethes0_match", "ethes0_capture", "ethes0_pps";
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function = "ethes0";
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drive-strength = <24>;
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};
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hscif0_pins: hscif0 {
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groups = "hscif0_data", "hscif0_ctrl";
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function = "hscif0";
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};
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i2c0_pins: i2c0 {
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groups = "i2c0";
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function = "i2c0";
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};
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i2c1_pins: i2c1 {
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groups = "i2c1";
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function = "i2c1";
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};
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mmc0_pins: mmc0 {
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groups = "mmc0_data8", "mmc0_ctrl", "mmc0_ds";
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function = "mmc0";
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drive-strength = <24>;
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};
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rsw3_pins: rsw3 {
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groups = "rsw3_match", "rsw3_capture", "rsw3_pps";
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function = "rsw3";
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drive-strength = <24>;
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};
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scif_clk_pins: scif-clk {
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groups = "scif_clk";
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function = "scif_clk";
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};
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};
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&rswitch3 {
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pinctrl-0 = <&rsw3_pins>, <ð25g2_pins>, <ðes0_pins>;
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pinctrl-names = "default";
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status = "okay";
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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/*
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* NOTE: Only port@4 is configured for R-Car X5H board.
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* Other ports (0-3, 5-12) are currently unused or not
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* connected.
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*/
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port@4 {
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reg = <4>;
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renesas,connect_to_xpcs;
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phy-handle = <&dp83869_phy>;
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phy-mode = "sgmii";
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phys = <ð_pcs 5>;
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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dp83869_phy: ethernet-phy@2 {
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reg = <2>;
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ti,sgmii-interface;
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ti,max-output-impedance;
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ti,refclk-output-enable;
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ti,clk-output-sel = <DP83869_CLK_O_SEL_REF_CLK>;
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};
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};
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};
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};
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};
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&scif_clk {
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clock-frequency = <26000000>;
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};
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@ -9,4 +9,18 @@ config R8A78000
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endmenu
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choice
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prompt "Renesas ARM64 SoCs board select"
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optional
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config TARGET_IRONHIDE
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bool "Ironhide board"
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imply R8A78000
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help
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Support for Renesas R-Car Gen5 Ironhide platform
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endchoice
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source "board/renesas/ironhide/Kconfig"
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endif
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@ -43,6 +43,10 @@ else
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obj-y += gen4-common.o
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endif
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endif
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ifdef CONFIG_RCAR_GEN5
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obj-y += gen5-common.o
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endif
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endif
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endif
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75
board/renesas/common/gen5-common.c
Normal file
75
board/renesas/common/gen5-common.c
Normal file
@ -0,0 +1,75 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2025 Renesas Electronics Corp.
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*/
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#include <asm/arch/renesas.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm/mach-types.h>
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#include <asm/processor.h>
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#include <asm/system.h>
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#include <linux/errno.h>
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DECLARE_GLOBAL_DATA_PTR;
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static void init_generic_timer(void)
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{
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const u32 freq = CONFIG_SYS_CLK_FREQ;
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/* Update memory mapped and register based freqency */
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asm volatile ("msr cntfrq_el0, %0" :: "r" (freq));
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writel(freq, CNTFID0);
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/* Enable counter */
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setbits_le32(CNTCR_BASE, CNTCR_EN);
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}
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static void init_gic_v3(void)
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{
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/* GIC v3 power on */
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writel(BIT(1), GICR_LPI_PWRR);
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/* Wait till the WAKER_CA_BIT changes to 0 */
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clrbits_le32(GICR_LPI_WAKER, BIT(1));
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while (readl(GICR_LPI_WAKER) & BIT(2))
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;
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writel(0xffffffff, GICR_SGI_BASE + GICR_IGROUPR0);
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}
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void s_init(void)
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{
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if (current_el() == 3)
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init_generic_timer();
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}
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int board_early_init_f(void)
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{
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return 0;
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}
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int board_init(void)
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{
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/* Allow WDT reset */
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writel(RST_KCPROT_DIS, RST_RESKCPROT0);
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clrbits_le32(RST_WDTRSTCR, RST_WWDT_RSTMSK | RST_RWDT_RSTMSK);
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if (current_el() != 3)
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return 0;
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init_gic_v3();
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return 0;
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}
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void __weak reset_cpu(void)
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{
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writel(RST_KCPROT_DIS, RST_RESKCPROT0);
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writel(0x1, RST_SWSRES1A);
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}
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int ft_board_setup(void *blob, struct bd_info *bd)
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{
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return 0;
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}
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15
board/renesas/ironhide/Kconfig
Normal file
15
board/renesas/ironhide/Kconfig
Normal file
@ -0,0 +1,15 @@
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if TARGET_IRONHIDE
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config SYS_SOC
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default "renesas"
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config SYS_BOARD
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default "ironhide"
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config SYS_VENDOR
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default "renesas"
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config SYS_CONFIG_NAME
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default "ironhide"
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endif
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43
configs/r8a78000_ironhide_defconfig
Normal file
43
configs/r8a78000_ironhide_defconfig
Normal file
@ -0,0 +1,43 @@
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#include <configs/renesas_rcar5.config>
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CONFIG_ARM=y
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CONFIG_ARCH_RENESAS=y
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CONFIG_RCAR_GEN5=y
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CONFIG_TARGET_IRONHIDE=y
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# CONFIG_OF_UPSTREAM is not set
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CONFIG_ARMV8_PSCI=y
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CONFIG_ARM_SMCCC=y
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CONFIG_BAUDRATE=1843200
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CONFIG_BOOTCOMMAND="setexpr dloadaddr ${loadaddr} + 0x200000 && setexpr dloadaddr ${dloadaddr} \\\\& 0xffc00000 && setexpr kloadaddr ${dloadaddr} + 0x200000 && tftp ${dloadaddr} r8a78000-ironhide.dtb && tftp ${kloadaddr} Image && booti ${kloadaddr} - ${dloadaddr}"
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CONFIG_DEFAULT_DEVICE_TREE="r8a78000-ironhide"
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CONFIG_CLK_CCF=y
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CONFIG_CLK_COMPOSITE_CCF=y
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CONFIG_CLK_SCMI=y
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CONFIG_CMD_CLK=y
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CONFIG_CMD_MEMTEST=y
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CONFIG_CMD_SCMI=y
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CONFIG_CMD_UFS=y
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CONFIG_DM_MAILBOX=y
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CONFIG_DM_RESET=y
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CONFIG_ENV_IS_IN_MMC=y
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CONFIG_ENV_MMC_DEVICE_INDEX=0
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CONFIG_ENV_MMC_EMMC_HW_PARTITION=2
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CONFIG_ENV_OFFSET=0xFFFE0000
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CONFIG_ENV_SIZE=0x20000
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CONFIG_FIRMWARE=y
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CONFIG_NR_DRAM_BANKS=16
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CONFIG_POWER_DOMAIN=y
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CONFIG_RCAR_MFIS_MBOX=y
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CONFIG_RESET_SCMI=y
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CONFIG_SCMI_AGENT_MAILBOX=y
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CONFIG_SCMI_FIRMWARE=y
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CONFIG_SCMI_POWER_DOMAIN=y
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CONFIG_SCSI=y
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CONFIG_SYS_ALT_MEMTEST=y
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CONFIG_SYS_BARGSIZE=2048
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CONFIG_SYS_BOOT_GET_CMDLINE=y
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CONFIG_SYS_CBSIZE=2048
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CONFIG_SYS_CLK_FREQ=1066666667
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CONFIG_UFS=y
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CONFIG_UFS_RENESAS_GEN5=y
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23
configs/renesas_rcar5.config
Normal file
23
configs/renesas_rcar5.config
Normal file
@ -0,0 +1,23 @@
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#include <configs/renesas_rcar64.config>
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CONFIG_ARCH_CPU_INIT=y
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CONFIG_SYS_LOAD_ADDR=0x9E600000
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CONFIG_SYS_RELOC_GD_ENV_ADDR=y
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CONFIG_USE_BOOTARGS=y
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CONFIG_USE_BOOTCOMMAND=y
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CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
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CONFIG_CMD_MMC=y
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CONFIG_DM_ETH_PHY=y
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# CONFIG_MMC_HS200_SUPPORT is not set
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# CONFIG_MMC_IO_VOLTAGE is not set
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# CONFIG_MMC_UHS_SUPPORT is not set
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CONFIG_PHY_R8A78000_ETHERNET_PCS=y
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CONFIG_PHY_R8A78000_MP_PHY=y
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CONFIG_PHY_TI_DP83869=y
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# CONFIG_PSCI_RESET is not set
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CONFIG_RENESAS_ETHER_SWITCH=y
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CONFIG_RENESAS_SDHI=y
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CONFIG_SPI_FLASH_SPANSION=y
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# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
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CONFIG_SYS_I2C_RCAR_I2C=y
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11
include/configs/ironhide.h
Normal file
11
include/configs/ironhide.h
Normal file
@ -0,0 +1,11 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (C) 2025 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#ifndef __IRONHIDE_H
|
||||
#define __IRONHIDE_H
|
||||
|
||||
#include "rcar-gen5-common.h"
|
||||
|
||||
#endif /* __IRONHIDE_H */
|
||||
24
include/configs/rcar-gen5-common.h
Normal file
24
include/configs/rcar-gen5-common.h
Normal file
@ -0,0 +1,24 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (C) 2025 Renesas Electronics Corporation
|
||||
*/
|
||||
|
||||
#ifndef __RCAR_GEN5_COMMON_H
|
||||
#define __RCAR_GEN5_COMMON_H
|
||||
|
||||
#include <asm/arch/renesas.h>
|
||||
|
||||
/* Console */
|
||||
#define CFG_SYS_BAUDRATE_TABLE { 38400, 115200, 921600, 1843200, 3250000 }
|
||||
|
||||
/* Memory */
|
||||
#define DRAM_RSV_SIZE 0x08000000
|
||||
#define CFG_SYS_SDRAM_BASE (0x40000000 + DRAM_RSV_SIZE)
|
||||
#define CFG_SYS_SDRAM_SIZE (0x80000000u - DRAM_RSV_SIZE)
|
||||
#define CFG_MAX_MEM_MAPPED (0x80000000u - DRAM_RSV_SIZE)
|
||||
|
||||
/* Environment setting */
|
||||
#define CFG_EXTRA_ENV_SETTINGS \
|
||||
"bootm_size=0x10000000\0"
|
||||
|
||||
#endif /* __RCAR_GEN5_COMMON_H */
|
||||
Loading…
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Reference in New Issue
Block a user