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clk: mediatek: mt7622: convert to struct mtk_parent
Convert all parent clock arrays to use struct mtk_parent. This will allow us to simplify core code later by having only one possible data type for mux parent arrays. Reviewed-by: Macpaul Lin <macpaul.lin@mediatek.com> Reviewed-by: Julien Stephan <jstephan@baylibre.com> Link: https://patch.msgid.link/20260317-clk-mtk-unify-mux-parents-v3-1-a4760f5b0a80@baylibre.com Signed-off-by: David Lechner <dlechner@baylibre.com>
This commit is contained in:
David Lechner
parent
1ffc541eaf
commit
c4173429db
@ -159,231 +159,231 @@ static const struct mtk_fixed_factor top_fixed_divs[] = {
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FACTOR0(CLK_TOP_ETH_500M, CLK_APMIXED_ETH1PLL, 1, 1),
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};
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static const int axi_parents[] = {
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CLK_XTAL,
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CLK_TOP_SYSPLL1_D2,
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CLK_TOP_SYSPLL_D5,
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CLK_TOP_SYSPLL1_D4,
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CLK_TOP_UNIVPLL_D5,
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CLK_TOP_UNIVPLL2_D2,
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CLK_TOP_UNIVPLL_D7
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static const struct mtk_parent axi_parents[] = {
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XTAL_PARENT(CLK_XTAL),
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TOP_PARENT(CLK_TOP_SYSPLL1_D2),
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TOP_PARENT(CLK_TOP_SYSPLL_D5),
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TOP_PARENT(CLK_TOP_SYSPLL1_D4),
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TOP_PARENT(CLK_TOP_UNIVPLL_D5),
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TOP_PARENT(CLK_TOP_UNIVPLL2_D2),
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TOP_PARENT(CLK_TOP_UNIVPLL_D7),
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};
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static const int mem_parents[] = {
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CLK_XTAL,
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CLK_TOP_DMPLL
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static const struct mtk_parent mem_parents[] = {
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XTAL_PARENT(CLK_XTAL),
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TOP_PARENT(CLK_TOP_DMPLL),
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};
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static const int ddrphycfg_parents[] = {
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CLK_XTAL,
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CLK_TOP_SYSPLL1_D8
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static const struct mtk_parent ddrphycfg_parents[] = {
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XTAL_PARENT(CLK_XTAL),
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TOP_PARENT(CLK_TOP_SYSPLL1_D8),
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};
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static const int eth_parents[] = {
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CLK_XTAL,
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CLK_TOP_SYSPLL1_D2,
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CLK_TOP_UNIVPLL1_D2,
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CLK_TOP_SYSPLL1_D4,
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CLK_TOP_UNIVPLL_D5,
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-1,
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CLK_TOP_UNIVPLL_D7
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static const struct mtk_parent eth_parents[] = {
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XTAL_PARENT(CLK_XTAL),
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TOP_PARENT(CLK_TOP_SYSPLL1_D2),
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TOP_PARENT(CLK_TOP_UNIVPLL1_D2),
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TOP_PARENT(CLK_TOP_SYSPLL1_D4),
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TOP_PARENT(CLK_TOP_UNIVPLL_D5),
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VOID_PARENT,
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TOP_PARENT(CLK_TOP_UNIVPLL_D7),
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};
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static const int pwm_parents[] = {
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CLK_XTAL,
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CLK_TOP_UNIVPLL2_D4
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static const struct mtk_parent pwm_parents[] = {
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XTAL_PARENT(CLK_XTAL),
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TOP_PARENT(CLK_TOP_UNIVPLL2_D4),
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};
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static const int f10m_ref_parents[] = {
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CLK_XTAL,
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CLK_TOP_SYSPLL4_D16
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static const struct mtk_parent f10m_ref_parents[] = {
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XTAL_PARENT(CLK_XTAL),
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TOP_PARENT(CLK_TOP_SYSPLL4_D16),
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};
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static const int nfi_infra_parents[] = {
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CLK_XTAL,
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CLK_XTAL,
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CLK_XTAL,
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CLK_XTAL,
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CLK_XTAL,
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CLK_XTAL,
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CLK_XTAL,
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CLK_XTAL,
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CLK_TOP_UNIVPLL2_D8,
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CLK_TOP_SYSPLL1_D8,
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CLK_TOP_UNIVPLL1_D8,
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CLK_TOP_SYSPLL4_D2,
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CLK_TOP_UNIVPLL2_D4,
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CLK_TOP_UNIVPLL3_D2,
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CLK_TOP_SYSPLL1_D4
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static const struct mtk_parent nfi_infra_parents[] = {
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XTAL_PARENT(CLK_XTAL),
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XTAL_PARENT(CLK_XTAL),
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XTAL_PARENT(CLK_XTAL),
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XTAL_PARENT(CLK_XTAL),
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XTAL_PARENT(CLK_XTAL),
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XTAL_PARENT(CLK_XTAL),
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XTAL_PARENT(CLK_XTAL),
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XTAL_PARENT(CLK_XTAL),
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TOP_PARENT(CLK_TOP_UNIVPLL2_D8),
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TOP_PARENT(CLK_TOP_SYSPLL1_D8),
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TOP_PARENT(CLK_TOP_UNIVPLL1_D8),
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TOP_PARENT(CLK_TOP_SYSPLL4_D2),
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TOP_PARENT(CLK_TOP_UNIVPLL2_D4),
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TOP_PARENT(CLK_TOP_UNIVPLL3_D2),
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TOP_PARENT(CLK_TOP_SYSPLL1_D4),
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};
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static const int flash_parents[] = {
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CLK_XTAL,
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CLK_TOP_UNIVPLL_D80_D4,
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CLK_TOP_SYSPLL2_D8,
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CLK_TOP_SYSPLL3_D4,
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CLK_TOP_UNIVPLL3_D4,
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CLK_TOP_UNIVPLL1_D8,
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CLK_TOP_SYSPLL2_D4,
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CLK_TOP_UNIVPLL2_D4
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static const struct mtk_parent flash_parents[] = {
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XTAL_PARENT(CLK_XTAL),
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TOP_PARENT(CLK_TOP_UNIVPLL_D80_D4),
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TOP_PARENT(CLK_TOP_SYSPLL2_D8),
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TOP_PARENT(CLK_TOP_SYSPLL3_D4),
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TOP_PARENT(CLK_TOP_UNIVPLL3_D4),
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TOP_PARENT(CLK_TOP_UNIVPLL1_D8),
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TOP_PARENT(CLK_TOP_SYSPLL2_D4),
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TOP_PARENT(CLK_TOP_UNIVPLL2_D4),
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};
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static const int uart_parents[] = {
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CLK_XTAL,
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CLK_TOP_UNIVPLL2_D8
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static const struct mtk_parent uart_parents[] = {
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XTAL_PARENT(CLK_XTAL),
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TOP_PARENT(CLK_TOP_UNIVPLL2_D8),
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};
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static const int spi0_parents[] = {
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CLK_XTAL,
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CLK_TOP_SYSPLL3_D2,
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CLK_XTAL,
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CLK_TOP_SYSPLL2_D4,
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CLK_TOP_SYSPLL4_D2,
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CLK_TOP_UNIVPLL2_D4,
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CLK_TOP_UNIVPLL1_D8,
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CLK_XTAL
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static const struct mtk_parent spi0_parents[] = {
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XTAL_PARENT(CLK_XTAL),
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TOP_PARENT(CLK_TOP_SYSPLL3_D2),
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XTAL_PARENT(CLK_XTAL),
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TOP_PARENT(CLK_TOP_SYSPLL2_D4),
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TOP_PARENT(CLK_TOP_SYSPLL4_D2),
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TOP_PARENT(CLK_TOP_UNIVPLL2_D4),
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TOP_PARENT(CLK_TOP_UNIVPLL1_D8),
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XTAL_PARENT(CLK_XTAL),
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};
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static const int spi1_parents[] = {
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CLK_XTAL,
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CLK_TOP_SYSPLL3_D2,
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CLK_XTAL,
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CLK_TOP_SYSPLL4_D4,
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CLK_TOP_SYSPLL4_D2,
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CLK_TOP_UNIVPLL2_D4,
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CLK_TOP_UNIVPLL1_D8,
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CLK_XTAL
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static const struct mtk_parent spi1_parents[] = {
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XTAL_PARENT(CLK_XTAL),
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TOP_PARENT(CLK_TOP_SYSPLL3_D2),
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XTAL_PARENT(CLK_XTAL),
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TOP_PARENT(CLK_TOP_SYSPLL4_D4),
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TOP_PARENT(CLK_TOP_SYSPLL4_D2),
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TOP_PARENT(CLK_TOP_UNIVPLL2_D4),
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TOP_PARENT(CLK_TOP_UNIVPLL1_D8),
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XTAL_PARENT(CLK_XTAL),
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};
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static const int msdc30_0_parents[] = {
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CLK_XTAL,
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CLK_TOP_UNIVPLL2_D16,
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CLK_TOP_UNIV48M
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static const struct mtk_parent msdc30_0_parents[] = {
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XTAL_PARENT(CLK_XTAL),
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TOP_PARENT(CLK_TOP_UNIVPLL2_D16),
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TOP_PARENT(CLK_TOP_UNIV48M),
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};
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static const int a1sys_hp_parents[] = {
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CLK_XTAL,
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CLK_TOP_AUD1PLL,
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CLK_TOP_AUD2PLL,
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CLK_XTAL
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static const struct mtk_parent a1sys_hp_parents[] = {
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XTAL_PARENT(CLK_XTAL),
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TOP_PARENT(CLK_TOP_AUD1PLL),
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TOP_PARENT(CLK_TOP_AUD2PLL),
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XTAL_PARENT(CLK_XTAL),
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};
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static const int intdir_parents[] = {
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CLK_XTAL,
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CLK_TOP_SYSPLL1_D2,
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CLK_TOP_UNIVPLL_D2,
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CLK_TOP_SGMIIPLL
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static const struct mtk_parent intdir_parents[] = {
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XTAL_PARENT(CLK_XTAL),
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TOP_PARENT(CLK_TOP_SYSPLL1_D2),
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TOP_PARENT(CLK_TOP_UNIVPLL_D2),
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TOP_PARENT(CLK_TOP_SGMIIPLL),
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};
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static const int aud_intbus_parents[] = {
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CLK_XTAL,
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CLK_TOP_SYSPLL1_D4,
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CLK_TOP_SYSPLL4_D2,
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CLK_TOP_SYSPLL3_D2
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static const struct mtk_parent aud_intbus_parents[] = {
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XTAL_PARENT(CLK_XTAL),
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TOP_PARENT(CLK_TOP_SYSPLL1_D4),
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TOP_PARENT(CLK_TOP_SYSPLL4_D2),
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TOP_PARENT(CLK_TOP_SYSPLL3_D2),
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};
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static const int pmicspi_parents[] = {
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CLK_XTAL,
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-1,
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-1,
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-1,
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-1,
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CLK_TOP_UNIVPLL2_D16
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static const struct mtk_parent pmicspi_parents[] = {
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XTAL_PARENT(CLK_XTAL),
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VOID_PARENT,
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VOID_PARENT,
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VOID_PARENT,
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VOID_PARENT,
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TOP_PARENT(CLK_TOP_UNIVPLL2_D16),
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};
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static const int atb_parents[] = {
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CLK_XTAL,
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CLK_TOP_SYSPLL1_D2,
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CLK_TOP_SYSPLL_D5
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static const struct mtk_parent atb_parents[] = {
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XTAL_PARENT(CLK_XTAL),
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TOP_PARENT(CLK_TOP_SYSPLL1_D2),
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TOP_PARENT(CLK_TOP_SYSPLL_D5),
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};
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static const int audio_parents[] = {
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CLK_XTAL,
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CLK_TOP_SYSPLL3_D4,
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CLK_TOP_SYSPLL4_D4,
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CLK_TOP_UNIVPLL1_D16
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static const struct mtk_parent audio_parents[] = {
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XTAL_PARENT(CLK_XTAL),
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TOP_PARENT(CLK_TOP_SYSPLL3_D4),
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TOP_PARENT(CLK_TOP_SYSPLL4_D4),
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TOP_PARENT(CLK_TOP_UNIVPLL1_D16),
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};
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static const int usb20_parents[] = {
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CLK_XTAL,
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CLK_TOP_UNIVPLL3_D4,
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CLK_TOP_SYSPLL1_D8,
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CLK_XTAL
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static const struct mtk_parent usb20_parents[] = {
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XTAL_PARENT(CLK_XTAL),
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TOP_PARENT(CLK_TOP_UNIVPLL3_D4),
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TOP_PARENT(CLK_TOP_SYSPLL1_D8),
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XTAL_PARENT(CLK_XTAL),
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};
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static const int aud1_parents[] = {
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CLK_XTAL,
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CLK_TOP_AUD1PLL
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static const struct mtk_parent aud1_parents[] = {
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XTAL_PARENT(CLK_XTAL),
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TOP_PARENT(CLK_TOP_AUD1PLL),
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};
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static const int asm_l_parents[] = {
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CLK_XTAL,
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CLK_TOP_SYSPLL_D5,
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CLK_TOP_UNIVPLL2_D2,
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CLK_TOP_UNIVPLL2_D4
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static const struct mtk_parent asm_l_parents[] = {
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XTAL_PARENT(CLK_XTAL),
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TOP_PARENT(CLK_TOP_SYSPLL_D5),
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TOP_PARENT(CLK_TOP_UNIVPLL2_D2),
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TOP_PARENT(CLK_TOP_UNIVPLL2_D4),
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};
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static const int apll1_ck_parents[] = {
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CLK_TOP_AUD1_SEL,
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CLK_TOP_AUD2_SEL
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static const struct mtk_parent apll1_ck_parents[] = {
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TOP_PARENT(CLK_TOP_AUD1_SEL),
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TOP_PARENT(CLK_TOP_AUD2_SEL),
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};
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static const struct mtk_composite top_muxes[] = {
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/* CLK_CFG_0 */
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MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7),
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MUX_GATE(CLK_TOP_MEM_SEL, mem_parents, 0x40, 8, 1, 15),
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MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x40, 16, 1, 23),
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MUX_GATE(CLK_TOP_ETH_SEL, eth_parents, 0x40, 24, 3, 31),
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MUX_GATE_MIXED(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7),
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MUX_GATE_MIXED(CLK_TOP_MEM_SEL, mem_parents, 0x40, 8, 1, 15),
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MUX_GATE_MIXED(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x40, 16, 1, 23),
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MUX_GATE_MIXED(CLK_TOP_ETH_SEL, eth_parents, 0x40, 24, 3, 31),
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/* CLK_CFG_1 */
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MUX_GATE(CLK_TOP_PWM_SEL, pwm_parents, 0x50, 0, 2, 7),
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MUX_GATE(CLK_TOP_F10M_REF_SEL, f10m_ref_parents, 0x50, 8, 1, 15),
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MUX_GATE(CLK_TOP_NFI_INFRA_SEL, nfi_infra_parents, 0x50, 16, 4, 23),
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MUX_GATE(CLK_TOP_FLASH_SEL, flash_parents, 0x50, 24, 3, 31),
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MUX_GATE_MIXED(CLK_TOP_PWM_SEL, pwm_parents, 0x50, 0, 2, 7),
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MUX_GATE_MIXED(CLK_TOP_F10M_REF_SEL, f10m_ref_parents, 0x50, 8, 1, 15),
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MUX_GATE_MIXED(CLK_TOP_NFI_INFRA_SEL, nfi_infra_parents, 0x50, 16, 4, 23),
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MUX_GATE_MIXED(CLK_TOP_FLASH_SEL, flash_parents, 0x50, 24, 3, 31),
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/* CLK_CFG_2 */
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MUX_GATE(CLK_TOP_UART_SEL, uart_parents, 0x60, 0, 1, 7),
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MUX_GATE(CLK_TOP_SPI0_SEL, spi0_parents, 0x60, 8, 3, 15),
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MUX_GATE(CLK_TOP_SPI1_SEL, spi1_parents, 0x60, 16, 3, 23),
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MUX_GATE(CLK_TOP_MSDC50_0_SEL, uart_parents, 0x60, 24, 3, 31),
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MUX_GATE_MIXED(CLK_TOP_UART_SEL, uart_parents, 0x60, 0, 1, 7),
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MUX_GATE_MIXED(CLK_TOP_SPI0_SEL, spi0_parents, 0x60, 8, 3, 15),
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MUX_GATE_MIXED(CLK_TOP_SPI1_SEL, spi1_parents, 0x60, 16, 3, 23),
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MUX_GATE_MIXED(CLK_TOP_MSDC50_0_SEL, uart_parents, 0x60, 24, 3, 31),
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/* CLK_CFG_3 */
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MUX_GATE(CLK_TOP_MSDC30_0_SEL, msdc30_0_parents, 0x70, 0, 3, 7),
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MUX_GATE(CLK_TOP_MSDC30_1_SEL, msdc30_0_parents, 0x70, 8, 3, 15),
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MUX_GATE(CLK_TOP_A1SYS_HP_SEL, a1sys_hp_parents, 0x70, 16, 3, 23),
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MUX_GATE(CLK_TOP_A2SYS_HP_SEL, a1sys_hp_parents, 0x70, 24, 3, 31),
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MUX_GATE_MIXED(CLK_TOP_MSDC30_0_SEL, msdc30_0_parents, 0x70, 0, 3, 7),
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MUX_GATE_MIXED(CLK_TOP_MSDC30_1_SEL, msdc30_0_parents, 0x70, 8, 3, 15),
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MUX_GATE_MIXED(CLK_TOP_A1SYS_HP_SEL, a1sys_hp_parents, 0x70, 16, 3, 23),
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MUX_GATE_MIXED(CLK_TOP_A2SYS_HP_SEL, a1sys_hp_parents, 0x70, 24, 3, 31),
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/* CLK_CFG_4 */
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MUX_GATE(CLK_TOP_INTDIR_SEL, intdir_parents, 0x80, 0, 2, 7),
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MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, 0x80, 8, 2, 15),
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MUX_GATE(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x80, 16, 3, 23),
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MUX_GATE(CLK_TOP_SCP_SEL, ddrphycfg_parents, 0x80, 24, 2, 31),
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MUX_GATE_MIXED(CLK_TOP_INTDIR_SEL, intdir_parents, 0x80, 0, 2, 7),
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MUX_GATE_MIXED(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, 0x80, 8, 2, 15),
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MUX_GATE_MIXED(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x80, 16, 3, 23),
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MUX_GATE_MIXED(CLK_TOP_SCP_SEL, ddrphycfg_parents, 0x80, 24, 2, 31),
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/* CLK_CFG_5 */
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MUX_GATE(CLK_TOP_ATB_SEL, atb_parents, 0x90, 0, 2, 7),
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MUX_GATE_FLAGS(CLK_TOP_HIF_SEL, eth_parents, 0x90, 8, 3, 15,
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CLK_MUX_DOMAIN_SCPSYS),
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MUX_GATE(CLK_TOP_AUDIO_SEL, audio_parents, 0x90, 16, 2, 23),
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MUX_GATE(CLK_TOP_U2_SEL, usb20_parents, 0x90, 24, 2, 31),
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MUX_GATE_MIXED(CLK_TOP_ATB_SEL, atb_parents, 0x90, 0, 2, 7),
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MUX_GATE_MIXED_FLAGS(CLK_TOP_HIF_SEL, eth_parents, 0x90, 8, 3, 15,
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CLK_MUX_DOMAIN_SCPSYS),
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MUX_GATE_MIXED(CLK_TOP_AUDIO_SEL, audio_parents, 0x90, 16, 2, 23),
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MUX_GATE_MIXED(CLK_TOP_U2_SEL, usb20_parents, 0x90, 24, 2, 31),
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/* CLK_CFG_6 */
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MUX_GATE(CLK_TOP_AUD1_SEL, aud1_parents, 0xA0, 0, 1, 7),
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MUX_GATE(CLK_TOP_AUD2_SEL, aud1_parents, 0xA0, 8, 1, 15),
|
||||
MUX_GATE(CLK_TOP_IRRX_SEL, f10m_ref_parents, 0xA0, 16, 1, 23),
|
||||
MUX_GATE(CLK_TOP_IRTX_SEL, f10m_ref_parents, 0xA0, 24, 1, 31),
|
||||
MUX_GATE_MIXED(CLK_TOP_AUD1_SEL, aud1_parents, 0xA0, 0, 1, 7),
|
||||
MUX_GATE_MIXED(CLK_TOP_AUD2_SEL, aud1_parents, 0xA0, 8, 1, 15),
|
||||
MUX_GATE_MIXED(CLK_TOP_IRRX_SEL, f10m_ref_parents, 0xA0, 16, 1, 23),
|
||||
MUX_GATE_MIXED(CLK_TOP_IRTX_SEL, f10m_ref_parents, 0xA0, 24, 1, 31),
|
||||
|
||||
/* CLK_CFG_7 */
|
||||
MUX_GATE(CLK_TOP_ASM_L_SEL, asm_l_parents, 0xB0, 0, 2, 7),
|
||||
MUX_GATE(CLK_TOP_ASM_M_SEL, asm_l_parents, 0xB0, 8, 2, 15),
|
||||
MUX_GATE(CLK_TOP_ASM_H_SEL, asm_l_parents, 0xB0, 16, 2, 23),
|
||||
MUX_GATE_MIXED(CLK_TOP_ASM_L_SEL, asm_l_parents, 0xB0, 0, 2, 7),
|
||||
MUX_GATE_MIXED(CLK_TOP_ASM_M_SEL, asm_l_parents, 0xB0, 8, 2, 15),
|
||||
MUX_GATE_MIXED(CLK_TOP_ASM_H_SEL, asm_l_parents, 0xB0, 16, 2, 23),
|
||||
|
||||
/* CLK_AUDDIV_0 */
|
||||
MUX(CLK_TOP_APLL1_SEL, apll1_ck_parents, 0x120, 6, 1),
|
||||
MUX(CLK_TOP_APLL2_SEL, apll1_ck_parents, 0x120, 7, 1),
|
||||
MUX(CLK_TOP_I2S0_MCK_SEL, apll1_ck_parents, 0x120, 8, 1),
|
||||
MUX(CLK_TOP_I2S1_MCK_SEL, apll1_ck_parents, 0x120, 9, 1),
|
||||
MUX(CLK_TOP_I2S2_MCK_SEL, apll1_ck_parents, 0x120, 10, 1),
|
||||
MUX(CLK_TOP_I2S3_MCK_SEL, apll1_ck_parents, 0x120, 161, 1),
|
||||
MUX_MIXED(CLK_TOP_APLL1_SEL, apll1_ck_parents, 0x120, 6, 1),
|
||||
MUX_MIXED(CLK_TOP_APLL2_SEL, apll1_ck_parents, 0x120, 7, 1),
|
||||
MUX_MIXED(CLK_TOP_I2S0_MCK_SEL, apll1_ck_parents, 0x120, 8, 1),
|
||||
MUX_MIXED(CLK_TOP_I2S1_MCK_SEL, apll1_ck_parents, 0x120, 9, 1),
|
||||
MUX_MIXED(CLK_TOP_I2S2_MCK_SEL, apll1_ck_parents, 0x120, 10, 1),
|
||||
MUX_MIXED(CLK_TOP_I2S3_MCK_SEL, apll1_ck_parents, 0x120, 161, 1),
|
||||
};
|
||||
|
||||
/* infracfg */
|
||||
@ -423,16 +423,13 @@ static const struct mtk_gate infra_cgs[] = {
|
||||
};
|
||||
|
||||
/* pericfg */
|
||||
static const int peribus_ck_parents[] = {
|
||||
CLK_TOP_SYSPLL1_D8,
|
||||
CLK_TOP_SYSPLL1_D4,
|
||||
static const struct mtk_parent peribus_ck_parents[] = {
|
||||
TOP_PARENT(CLK_TOP_SYSPLL1_D8),
|
||||
TOP_PARENT(CLK_TOP_SYSPLL1_D4),
|
||||
};
|
||||
|
||||
#define PERI_MUX(_id, _parents, _reg, _shift, _width) \
|
||||
MUX_FLAGS(_id, _parents, _reg, _shift, _width, CLK_PARENT_TOPCKGEN)
|
||||
|
||||
static const struct mtk_composite peri_muxes[] = {
|
||||
PERI_MUX(CLK_PERIBUS_SEL, peribus_ck_parents, 0x05c, 0, 1),
|
||||
MUX_MIXED(CLK_PERIBUS_SEL, peribus_ck_parents, 0x05c, 0, 1),
|
||||
};
|
||||
|
||||
static const struct mtk_gate_regs peri0_cg_regs = {
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user