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Merge patch series "DDR configuration refactor and 16GB dual-rank support"

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Emanuele Ghidoli <ghidoliemanuele@gmail.com> says:

From: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>

This series refactors the DDR configuration handling for the
Toradex Aquila AM69 board and adds support for a 16GB dual-rank
memory configuration, while changing the HW_CFG pins value to
DDR configurations mapping.

Link: https://lore.kernel.org/r/20260309155342.145432-1-ghidoliemanuele@gmail.com
This commit is contained in:
Tom Rini 2026-03-23 09:19:00 -06:00
commit 1ffc541eaf
6 changed files with 88 additions and 30 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
board/toradex/aquila-am69/Makefile
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@ -6,4 +6,5 @@
obj-y += aquila-am69.o
obj-y += ddrs_patch.o
obj-y += aquila_ddrs_16GB.o
obj-y += aquila_ddrs_16GB_rank_2.o
obj-y += aquila_ddrs_8GB.o

26
board/toradex/aquila-am69/aquila-am69.c
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@ -17,26 +17,32 @@
#include <spl.h>
#include "../common/tdx-common.h"
#include "aquila_ddrs_16GB.h"
#include "aquila_ddrs_8GB.h"
#include "aquila_ddrs.h"
#include "ddrs_patch.h"
#define CTRL_MMR_CFG0_MCU_ADC1_CTRL 0x40F040B4
#define HW_CFG_MEM_SZ_32GB 0x00
#define HW_CFG_MEM_SZ_16GB 0x01
#define HW_CFG_MEM_SZ_16GB_RANK_2 0x01
#define HW_CFG_MEM_SZ_8GB 0x02
#define HW_CFG_MEM_SZ_16GB 0x03
#define HW_CFG_MEM_SZ_MASK 0x03
#define HW_CFG_MEM_CFG_MASK 0x03
DECLARE_GLOBAL_DATA_PTR;
static u8 hw_cfg;
static u8 aquila_am69_memory_cfg(void)
{
return hw_cfg & HW_CFG_MEM_CFG_MASK;
}
static u64 aquila_am69_memory_size(void)
{
switch (hw_cfg & HW_CFG_MEM_SZ_MASK) {
switch (aquila_am69_memory_cfg()) {
case HW_CFG_MEM_SZ_32GB:
return SZ_32G;
case HW_CFG_MEM_SZ_16GB_RANK_2:
case HW_CFG_MEM_SZ_16GB:
return SZ_16G;
case HW_CFG_MEM_SZ_8GB:
@ -79,12 +85,16 @@ static void update_ddr_timings(void)
int ret = 0;
void *fdt = (void *)gd->fdt_blob;
switch (aquila_am69_memory_size()) {
case SZ_8G:
switch (aquila_am69_memory_cfg()) {
case HW_CFG_MEM_SZ_8GB:
ret = aquila_am69_fdt_apply_ddr_patch(fdt, aquila_am69_ddrss_patch_8GB,
MULTI_DDR_CFG_INTRLV_SIZE_8GB);
break;
case SZ_16G:
case HW_CFG_MEM_SZ_16GB_RANK_2:
ret = aquila_am69_fdt_apply_ddr_patch(fdt, aquila_am69_ddrss_patch_16GB_rank_2,
MULTI_DDR_CFG_INTRLV_SIZE_16GB);
break;
case HW_CFG_MEM_SZ_16GB:
ret = aquila_am69_fdt_apply_ddr_patch(fdt, aquila_am69_ddrss_patch_16GB,
MULTI_DDR_CFG_INTRLV_SIZE_16GB);
break;

15
board/toradex/aquila-am69/aquila_ddrs.h Normal file
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@ -0,0 +1,15 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (c) Toradex - https://www.toradex.com/
*/
#ifndef __AQUILA_DDRS_H
#define __AQUILA_DDRS_H
#define MULTI_DDR_CFG_INTRLV_SIZE_8GB 9
#define MULTI_DDR_CFG_INTRLV_SIZE_16GB 11
extern struct ddrss_patch *aquila_am69_ddrss_patch_8GB[4];
extern struct ddrss_patch *aquila_am69_ddrss_patch_16GB[4];
extern struct ddrss_patch *aquila_am69_ddrss_patch_16GB_rank_2[4];
#endif // __AQUILA_DDRS_H

11
board/toradex/aquila-am69/aquila_ddrs_16GB.h
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@ -1,11 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2025 Toradex - https://www.toradex.com/
*/
#ifndef __AQUILA_DDRS_16GB_H
#define __AQUILA_DDRS_16GB_H
#define MULTI_DDR_CFG_INTRLV_SIZE_16GB 11
extern struct ddrss_patch *aquila_am69_ddrss_patch_16GB[4];
#endif // __AQUILA_DDRS_16GB_H

54
board/toradex/aquila-am69/aquila_ddrs_16GB_rank_2.c Normal file
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@ -0,0 +1,54 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) Toradex - https://www.toradex.com/
* This contains a diff against the 32GB register settings created from
* the 16GB dual rank tool output.
* The 16GB dtsi file was generated with the following tool revisions:
* - SysConfig: Revision 1.26.2+4477
* - Jacinto7_DDRSS_RegConfigTool: Revision 0.12.0
* This file was generated on Fri Mar 06 2026 10:39:50 GMT+0100 (Central European Standard Time)
*/
#include <asm/u-boot.h>
#include <linux/kernel.h>
#include "ddrs_patch.h"
#define DDRSS_PLL_FHS_CNT 3
#define DDRSS_CTL_268_DATA 0x01010000
#define DDRSS_CTL_270_DATA 0x00000FFF
#define DDRSS_CTL_271_DATA 0x1FFF1000
#define DDRSS_CTL_272_DATA 0x01FF0000
#define DDRSS_CTL_273_DATA 0x000101FF
#define DDRSS_PI_73_DATA 0x00080100
static struct ddr_reg_patch ctl_patch[] = {
{ 268, DDRSS_CTL_268_DATA},
{ 270, DDRSS_CTL_270_DATA},
{ 271, DDRSS_CTL_271_DATA},
{ 272, DDRSS_CTL_272_DATA},
{ 273, DDRSS_CTL_273_DATA}
};
static struct ddr_reg_patch pi_patch[] = {
{ 73, DDRSS_PI_73_DATA},
};
static struct ddrss_patch ddrss_ctrl_patch = {
.ddr_fhs_cnt = DDRSS_PLL_FHS_CNT,
.ctl_patch = ctl_patch,
.ctl_patch_num = ARRAY_SIZE(ctl_patch),
.pi_patch = pi_patch,
.pi_patch_num = ARRAY_SIZE(pi_patch),
.phy_patch = NULL,
.phy_patch_num = 0
};
struct ddrss_patch *aquila_am69_ddrss_patch_16GB_rank_2[4] = {
&ddrss_ctrl_patch,
&ddrss_ctrl_patch,
&ddrss_ctrl_patch,
&ddrss_ctrl_patch
};

11
board/toradex/aquila-am69/aquila_ddrs_8GB.h
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@ -1,11 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2025 Toradex - https://www.toradex.com/
*/
#ifndef __AQUILA_DDRS_8GB_H
#define __AQUILA_DDRS_8GB_H
#define MULTI_DDR_CFG_INTRLV_SIZE_8GB 9
extern struct ddrss_patch *aquila_am69_ddrss_patch_8GB[4];
#endif // __AQUILA_DDRS_8GB_H