Squashed 'dts/upstream/' changes from d08867ef8f12..4d52919c55f4

4d52919c55f4 Merge tag 'v6.17-dts-raw'
38fc28fcd6fe Merge tag 'i2c-for-6.17-rc8' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux
5df2896cdbcd Merge tag 'soc-fixes-6.17-3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
501d5fac4d3e Merge tag 'v6.17-rockchip-dtsfixes2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/fixes
388d0d237317 Merge tag 'sunxi-fixes-for-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/fixes
9c1a1aa76d6a dt-bindings: i2c: spacemit: extend and validate all properties
f88821c169f7 Merge tag 'hid-for-linus-2025092201' of git://git.kernel.org/pub/scm/linux/kernel/git/hid/hid
7bb1f59ee85e Merge tag 'v6.17-rc6-dts-raw'
785f4a41a7a7 Merge tag 'phy-fix-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy
b72de0ae4a0d Merge tag 'dmaengine-fix-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine
f1de2f274990 Merge tag 'tty-6.17-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty
8dd5e1884a5c Merge tag 'imx-fixes-6.17-2' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes
c0c7a4135951 Merge tag 'socfpga_dts_fix_for_v6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into arm/fixes
5f5117ff540a Merge tag 'mvebu-fixes-6.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into arm/fixes
affba3242b22 Merge commit '89c5214639294' into for-6.17/upstream-fixes
5c5133a89684 arm64: dts: marvell: cn9132-clearfog: fix multi-lane pci x2 and x4 ports
a30edc781685 arm64: dts: marvell: cn9132-clearfog: disable eMMC high-speed modes
4818551bb6d9 arm64: dts: marvell: cn913x-solidrun: fix sata ports status
e0499b5c331f ARM: dts: kirkwood: Fix sound DAI cells for OpenRD clients
b43e7c1e6d2d arm64: dts: imx8mp: Correct thermal sensor index
eaf6bab64a58 riscv: dts: allwinner: rename devterm i2c-gpio node to comply with binding
faf49552868d Merge tag 'v6.17-rc5-dts-raw'
b16ee588d71b arm64: dts: rockchip: Fix the headphone detection on the orangepi 5
e183eb884e5c arm64: dts: rockchip: Add vcc supply for SPI Flash on NanoPC-T6
d5396f16c37f ARM: dts: socfpga: sodia: Fix mdio bus probe and PHY address
ebd92f3a59b2 Merge tag 'spi-fix-v6.17-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
a526c9ef1b67 Merge tag 'soc-fixes-6.17-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
5d8ba326d104 Merge tag 'at91-fixes-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into arm/fixes
509dee1b7e66 ARM: dts: microchip: sama7d65: Force SDMMC Legacy mode
9e763cb3d1b4 Merge tag 'v6.17-rockchip-dtsfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/fixes
a41fd927377f arm64: dts: rockchip: fix second M.2 slot on ROCK 5T
18d0194799e5 dt-bindings: lpspi: Document support for S32G
c9fac75c65f2 arm64: dts: rockchip: fix USB on RADXA ROCK 5T
63ef95420b13 arm64: dts: axiado: Add missing UART aliases
b2a21e821e2c Merge tag 'imx-fixes-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes
58056a8dbfc9 Merge tag 'v6.17-rc4-dts-raw'
3e7b84751e93 Merge tag 'drm-fixes-2025-08-29' of https://gitlab.freedesktop.org/drm/kernel
ea89dcf2416c Merge tag 'drm-msm-fixes-2025-08-26' of https://gitlab.freedesktop.org/drm/msm into drm-fixes
6309b9b1efc4 arm64: dts: rockchip: Add vcc-supply to SPI flash on Pinephone Pro
e22da6a63ced Merge tag 'devicetree-fixes-for-6.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
f25e8f3f3e67 dt-bindings: display/msm: qcom,mdp5: drop lut clock
0b54cf7dc8d3 Merge tag 'v6.17-rc3-dts-raw'
0264ca32989f Merge tag 'mips-fixes_6.17_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux
302d05793211 arm64: dts: rockchip: fix es8388 address on rk3588s-roc-pc
0704a97d3469 arm64: dts: rockchip: Fix Bluetooth interrupts flag on Neardi LBA3368
f1a75d0e9267 arm64: dts: rockchip: correct network description on Sige5
4212fbb0acb5 arm64: dts: rockchip: Minor whitespace cleanup
a52498f55fed ARM: dts: rockchip: Minor whitespace cleanup
2b74ca5ff951 arm64: dts: rockchip: Add supplies for eMMC on rk3588-orangepi-5
5135047db7f2 arm64: dts: rockchip: Fix the headphone detection on the orangepi 5 plus
510af76983ed mips: lantiq: xway: sysctrl: rename the etop node
2ff76939eff1 mips: dts: lantiq: danube: add missing burst length property
5c17501f659d ARM64: dts: mcbin: fix SATA ports on Macchiatobin
6f440931507f ARM: dts: armada-370-db: Fix stereo audio input routing on Armada 370
140d6b3980c3 arm64: dts: imx95: Fix JPEG encoder node assigned clock
c384581e7d6f arm64: dts: imx95-19x19-evk: correct the phy setting for flexcan1/2
e2edf4aaafbf arm64: dts: imx8mp: Fix missing microSD slot vqmmc on Data Modul i.MX8M Plus eDM SBC
4ea5d96804b4 arm64: dts: imx8mp: Fix missing microSD slot vqmmc on DH electronics i.MX8M Plus DHCOM
2789604fc218 arm64: dts: imx8mp-tqma8mpql: remove virtual 3.3V regulator
a573a81d351e arm64: dts: imx8mp-tqma8mpql: fix LDO5 power off
e96897446ad9 Merge tag 'regulator-fix-v6.17-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator
694d45a2f761 dt-bindings: vendor-prefixes: add eswin
f16c7cbc671f ARM: dts: allwinner: Minor whitespace cleanup
9e29f1c5986c Merge tag 'v6.17-rc2-dts-raw'
43c415b40654 Merge tag 'net-6.17-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
e24d016dedd9 dt-bindings: serial: 8250: allow "main" and "uart" as clock names
93772d487e42 dt-bindings: serial: 8250: move a constraint
fa1b88e6663a dt-bindings: serial: brcm,bcm7271-uart: Constrain clocks
4982fdb2c306 dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Update pcie phy bindings
23a1689d9a68 dt-bindings: phy: marvell,comphy-cp110: Fix clock and child node constraints
d57c7d5cb3fe riscv: dts: thead: Add APB clocks for TH1520 GMACs
32097674787b dt-bindings: net: thead,th1520-gmac: Describe APB interface clock
25370078d056 regulator: dt-bindings: infineon,ir38060: Add Guenter as maintainer from IBM
5b650c7a3387 Merge tag 'v6.17-rc1-dts-raw'
f579ec5f89fe arm64: dts: rockchip: Add vcc-supply to SPI flash on rk3399-pinebook-pro
401adf630a1b arm64: dts: rockchip: mark eeprom as read-only for Radxa E52C
f6fe1e119a05 dt-bindings: dma: qcom: bam-dma: Add missing required properties
6eb6301028f5 Merge tag 'mailbox-v6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/jassibrar/mailbox
7beab77fbc66 Merge tag 'soc-fixes-6.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
9c15d4d232b9 Merge tag 'tegra-for-6.17-arm64-dt-v3' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/fixes
d818fcb1ce10 Merge tag 'net-6.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
c669bebbe274 Merge tag 'loongarch-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
d25371e88f49 Merge tag 'input-for-v6.17-rc0' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
b225444b125e dt-bindings: mailbox: Add ASPEED AST2700 series SoC
4022f68499d8 dt-bindings: mailbox: Drop consumers example DTS
08a32727c5e5 dt-bindings: mailbox: nvidia,tegra186-hsp: Use generic node name
3ed8929022ea dt-bindings: mailbox: Correct example indentation
08534e6d0a28 dt-bindings: mailbox: ti,secure-proxy: Add missing reg maxItems
c26f859e6afe dt-bindings: mailbox: amlogic,meson-gxbb-mhu: Add missing interrupts maxItems
a98189806d7f dt-bindings: mailbox: qcom-ipcc: document the Milos Inter-Processor Communication Controller
bcdf210f6039 dt-bindings: mailbox: Add support for bcm74110
7861e592add4 Merge branch 'next' into for-linus
e6595131966d Merge tag 'scsi-misc' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi
a317294a0141 dt-bindings: net: Replace bouncing Alexandru Tachici emails
9177d7f279b3 Input: add keycode for performance mode key
5bd774b49823 LoongArch: dts: Add eMMC/SDIO controller support to Loongson-2K2000
d2b50965e07c LoongArch: dts: Add SDIO controller support to Loongson-2K1000
20c7a872f5fd LoongArch: dts: Add SDIO controller support to Loongson-2K0500
65a3167b6e72 Merge tag 'i2c-for-6.17-rc1-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux
8deaba69701b Merge tag 'ib-mfd-gpio-input-pwm-v6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd into next
5927e9980011 Merge tag 'rtc-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux
9b82ded0a5a8 Merge tag 'i3c/for-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/i3c/linux
74cfe0883b3c Merge tag 'i2c-host-6.17-pt2' of git://git.kernel.org/pub/scm/linux/kernel/git/andi.shyti/linux into i2c/for-mergewindow
a29a05ff2d8d Merge tag 'pinctrl-v6.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
f43f3f8a2149 Merge tag 'rproc-v6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/remoteproc/linux
06484243d8ee Merge tag 'pci-v6.17-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci
38d94dc8574d Merge tag 'linux-watchdog-6.17-rc1' of git://www.linux-watchdog.org/linux-watchdog
81e6b5eb1307 Merge tag 'dmaengine-6.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine
912ad91d462a Merge tag 'phy-for-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy
fc1b311a55ee Merge tag 'sound-6.17-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound
f898700a53a9 Merge tag 'for-v6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/sre/linux-power-supply
19d393592c86 Merge branch 'pci/controller/sophgo'
522b974af253 Merge branch 'pci/controller/qcom'
b6336c96a490 Merge branch 'pci/controller/brcmstb'
eaddf7ef5e04 dt-bindings: PCI: qcom,pcie-sa8775p: Document 'link_down' reset
b61473b60b3f dt-bindings: PCI: Remove 83xx-512x-pci.txt
95e7dfd2b09c dt-bindings: PCI: Convert amazon,al-alpine-v[23]-pcie to DT schema
d855db32b1d6 dt-bindings: PCI: Convert marvell,armada-3700-pcie to DT schema
faa8038a538e dt-bindings: PCI: Convert apm,xgene-pcie to DT schema
b64147052a31 dt-bindings: PCI: Convert axis,artpec6-pcie to DT schema
89b27dfc989f dt-bindings: PCI: Convert st,spear1340-pcie to DT schema
761305253c7f Merge tag 'mtd/for-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux
7f4c60d44458 Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
d2166900176e Merge tag 'hwmon-for-v6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging
f654a4cffc8e Merge tag 'media/v6.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media
c68e5f5d8510 Merge tag 'leds-next-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/leds
5fa7da3742d2 Merge tag 'mfd-next-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd
d48c5718d931 Merge tag 'gnss-6.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/johan/gnss
f19dc807ef82 Merge tag 'mips_6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux
88ef88367045 Merge tag 'nand/for-6.17' into mtd/next
77ce7c807f31 Merge tag 'spi-nor/for-6.17' into mtd/next
617063dc7992 Merge tag 'v6.17-p1' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
fb35ad6772e3 arm64: tegra: Remove numa-node-id properties
5d5d47c2898d Merge branch 'clk-fixes' into clk-next
1810b29ee894 Merge tag 'drm-next-2025-07-30' of https://gitlab.freedesktop.org/drm/kernel
672251f07f5f Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm
1c4c35171c77 dt-bindings: i3c: Add Renesas I3C controller
acc6ad02daf0 Merge tag 'iommu-updates-v6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/iommu/linux
913a827d8026 Merge tag 'arm-soc/for-6.16/devicetree-fixes' of https://github.com/Broadcom/stblinux into for-next
ce735da13c91 Merge tag 'net-next-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next
23ad1dd8a0f2 mfd: dt-bindings: Convert TPS65910 to DT schema
ebcd01abab45 Merge tag 'powerpc-6.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux
fabc9eb3b96b dt-bindings: i2c: apple,i2c: Document Apple A7-A11, T2 compatibles
f08139dcfa69 Merge branches 'clk-rockchip', 'clk-thead', 'clk-microchip', 'clk-imx' and 'clk-qcom' into clk-next
fe77e800d26c Merge branches 'clk-renesas', 'clk-samsung', 'clk-spacemit', 'clk-allwinner' and 'clk-amlogic' into clk-next
f9a15ab8af76 Merge branches 'clk-bindings', 'clk-cleanup', 'clk-pwm', 'clk-hw-device', 'clk-xilinx' and 'clk-adi' into clk-next
84946f9433bb Merge tag 'irq-drivers-2025-07-27' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
11f0d2c420f3 Merge tag 'mmc-v6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc
7dff1db3c967 Merge tag 'pmdomain-v6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm
7a67b758e4c6 Merge tag 'i2c-for-6.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux
059f314983b4 Merge tag 'soc-newsoc-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
935ca70fe88a Merge tag 'soc-drivers-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
f210f652efaa Merge tag 'soc-dt-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
33c1d430f189 Merge tag 'devicetree-for-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
ca819c3ba978 Merge tag 'usb-6.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb
86157d6ef538 Merge tag 'tty-6.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty
638f234e9940 Merge tag 'char-misc-6.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc
206f073acf2c Merge tag 'kvmarm-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into HEAD
f1208bcf4c31 Merge tag 'pwm/for-6.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/ukleinek/linux
60c278df97a4 Merge tag 'spi-v6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
06e9819c6572 Merge tag 'regulator-v6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator
6094cd275fea Merge tag 'gpio-updates-for-v6.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux
fe3cebf87ff8 Merge tag 'sound-6.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound
ccd9a5c60b97 Merge tag 'thermal-6.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
1ed339a1dd9b Merge tag 'pm-6.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
dbfbda98c7fa dt-bindings: Correct indentation and style in DTS example
1c1a12439958 MIPS: mobileye: dts: eyeq5,eyeq6h: rename the emmc controller
2d80b8cff673 dt-bindings: hwmon: Replace bouncing Alexandru Tachici emails
a9536c4a533e dt-bindings: Add INA228 to ina2xx devicetree bindings
ba8204028427 dt-bindings: input: touchscreen: st1232: add touch-overlay example
1633cb20b256 dt-bindings: touchscreen: add touch-overlay property
06b06ef8f47d Input: Add and document BTN_GRIP*
59ae00fd8e64 dt-bindings: input: syna,rmi4: Document F1A function
cc47e10c64b0 dt-bindings: ieee802154: Convert at86rf230.txt yaml format
b966613384a2 Merge tag 'sunxi-fixes-for-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into soc/dt
3849b529499b dt-bindings: net: dsa: microchip: Add KSZ8463 switch support
6979cbfbf41e dt-bindings: net: altr,socfpga-stmmac: Add compatible string for Agilex5
6b627bb260fd Merge tag 'qcom-drivers-for-6.17-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers
233d517c1884 dt-bindings: i2c: i2c-rk3x: Allow use of a power-domain
7049499f9e5a dt-bindings: i2c: exynos5: add samsung,exynos2200-hsi2c compatible
fc7ae9ba5fb2 dt-bindings: net: dsa: b53: Document brcm,gpio-ctrl property
3c4710ce3e81 dt-bindings: display: mediatek,dp: Allow DisplayPort AUX bus
646525defa14 dt-bindings: fsl: convert fsl,vf610-mscm-ir.txt to yaml format
137ad9b12805 dt-bindings: interrupt-controller: Add fsl,icoll.yaml
648b651777b1 dt-bindings: interrupt-controller: Add missing Xilinx INTC binding
b41b883df97c scsi: arm64: dts: mediatek: mt8195: Add UFSHCI node
8523d45b2495 scsi: dt-bindings: mediatek,ufs: add MT8195 compatible and update clock nodes
3f060c24c171 scsi: dt-bindings: mediatek,ufs: Add ufs-disable-mcq flag for UFS host
711056c3ae41 Merge tag 'for-net-next-2025-07-23' of git://git.kernel.org/pub/scm/linux/kernel/git/bluetooth/bluetooth-next
dd1b4057dd88 Merge tag 'wireless-next-2025-07-24' of https://git.kernel.org/pub/scm/linux/kernel/git/wireless/wireless-next
155dc9a613a6 spi: sophgo: Add SPI NOR controller for SG2042
bb7c1194a99d Add RSPI support for RZ/V2H
50fd75a061ed dt-bindings: clock: convert lpc1850-cgu.txt to yaml format
24140d806f08 dt-bindings: clock: Convert qca,ath79-pll to DT schema
6e04ef32ef38 dt-bindings: clock: Convert nuvoton,npcm750-clk to DT schema
2db6f9a1da8f dt-bindings: clock: Convert moxa,moxart-clock to DT schema
001cac37e6e6 dt-bindings: clock: Convert microchip,pic32mzda-clk to DT schema
0cd4ab636909 dt-bindings: clock: Convert maxim,max9485 to DT schema
1c33570f5d22 support for amlogic the new SPI IP
a14fec537070 dt-bindings: clock: Convert qcom,krait-cc to DT schema
fa19909f10d5 dt-bindings: clock: qcom: Remove double colon from description
b039af46152a Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
a162ca77489e spi: dt-bindings: Document the RZ/V2H(P) RSPI
3d1aedbd9343 ASoC: dt-bindings: atmel,at91-ssc: add microchip,sam9x7-ssc
0bdf06c97664 spi: dt-bindings: Add binding document of Amlogic SPISG controller
4e1353cbd1b1 spi: dt-bindings: spi-sg2044-nor: Change SOPHGO SG2042
9707aa6ab611 Merge tag 'ib-mfd-gpio-power-soc-v6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd into gpio/for-next
8ee72356e984 dt-bindings: mfd: rk806: Allow to customize PMIC reset mode
28d9430f0964 dt-bindings: mfd: samsung,s2mps11: Add comment about interrupts properties
4563fdbc72d2 dt-bindings: mfd: fsl,imx8qxp-csr: Remove binding documentation
8f9f74c9d030 dt-bindings: mfd: Convert lpc1850-creg-clk, pc1850-dmamux and phy-lpc18xx-usb-otg to YAML format
75a11ccc6567 dt-bindings: mfd: convert mxs-lradc bindings to json-schema
8978eadc5578 Merge branches 'ib-mfd-gpio-input-pwm-6.17', 'ib-mfd-gpio-power-soc-6.17' and 'ib-mfd-misc-pinctrl-6.17' into ibs-for-mfd-merged
4e0a772975ea dt-bindings: gpio: rockchip: Allow use of a power-domain
f5cd2bf1e8fb dt-bindings: serial: snps-dw-apb-uart: Allow use of a power-domain
5d324bdff50d dt-bindings: serial: samsung: add samsung,exynos2200-uart compatible
0a9a83ae140d dt-bindings: mfd: Add Apple Mac System Management Controller
c7fa9a3843ab dt-bindings: power: reboot: Add Apple Mac SMC Reboot Controller
f4eddbec1946 dt-bindings: gpio: Add Apple Mac SMC GPIO block
09c00fdd331c Merge tag 'icc-6.17-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/djakov/icc into char-misc-next
ff8150e0b0f2 dt-bindings: i2c: nxp,pnx-i2c: allow clocks property
83fafeb193c6 dt-bindings: i2c: renesas,riic: Document RZ/T2H and RZ/N2H support
bd1edaf90e4d dt-bindings: i2c: renesas,riic: Move ref for i2c-controller.yaml to the end
4fb79a323ffa dt-bindings: rtc: amlogic,a4-rtc: Add compatible string for C3
6911acf4bf27 Merge tag 'riscv-dt-for-v6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt
d6c5bd06ba88 Merge tag 'samsung-drivers-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt
5335c6dec4f1 Merge tag 'arm-sophgo-dt-for-v6.17' of https://github.com/sophgo/linux into soc/newsoc
36beceecc031 Merge tag 'riscv-sophgo-dt-for-v6.17' of https://github.com/sophgo/linux into soc/dt
a94a0024593d dt-bindings: rtc: pcf85063: add binding for RV8063
355ece2bba05 dt-bindings: net: bluetooth: nxp: add support for supply and reset
c94c0ee603b8 dt-bindings: net: bluetooth: nxp: Add support for 4M baudrate
da422e2fd590 ASoC: dt-bindings: qcom,sm8250: Add Fairphone 4 sound card
d443d69fe59a ASoC: dt-bindings: qcom,q6afe: Document q6usb subnode
e1dc5fef731a dt-bindings: dma: fsl-mxs-dma: allow interrupt-names for fsl,imx23-dma-apbx
831ba7ce88cf dt-bindings: dma: Convert marvell,orion-xor to DT schema
d809488a383f dt-bindings: dma: Convert brcm,iproc-sba to DT schema
102be241c4b4 dt-bindings: dma: qcom,gpi: document the Milos GPI DMA Engine
57e8d0f51565 dt-bindings: pinctrl: mediatek: Add support for mt8189
143c71ae555f dt-bindings: net: wireless: rt2800: add SOC Wifi
3b69bcbd0f88 MIPS: dts: ralink: mt7620a: add wifi
b2e237f8d950 dt-bindings: power: rpmpd: Add Glymur power domains
ecb488880deb dt-bindings: leds: ncp5623: Add 0x39 as a valid I2C address
a4e266b64b63 dt-bindings: display: sprd,sharkl3-dsi-host: Fix missing clocks constraints
a4902ad760ba dt-bindings: display: sprd,sharkl3-dpu: Fix missing clocks constraints
9871ccfc7c82 dt-bindings: display: imx: convert fsl,dcu.txt to yaml format
cb3eab704df6 dt-bindings: timer: via,vt8500-timer: Convert to YAML
02bc5b47191f dt-bindings: net: Convert Marvell Armada NETA and BM to DT schema
d2cb17b16fcd arm64: dts: sophgo: Add Duo Module 01 Evaluation Board
e9a69b5764c5 arm64: dts: sophgo: Add Duo Module 01
d46c534cd1a4 arm64: dts: sophgo: Add initial SG2000 SoC device tree
ecee37b0c732 riscv: dts: sophgo: fix mdio node name for CV180X
edeb5fb8a57f riscv: dts: sophgo: sophgo-srd3-10: reserve uart0 device
39cea134a435 riscv: dts: sophgo: add Sophgo SG2042_EVB_V2.0 board device tree
3af1443caa87 riscv: dts: sophgo: add Sophgo SG2042_EVB_V1.X board device tree
d95438e9cc23 dt-bindings: riscv: add Sophgo SG2042_EVB_V1.X/V2.0 bindings
97ff3450b45b riscv: dts: sophgo: add ethernet GMAC device for sg2042
6523097f467e riscv: dts: sophgo: Enable ethernet device for Huashan Pi
9d7ba84277ac riscv: dts: sophgo: Add mdio multiplexer device for cv18xx
5ad41c12bb04 riscv: dts: sophgo: Add ethernet device for cv18xx
9c62ec1b061f riscv: dts: sophgo: sg2044: add pmu configuration
e204a42647dc riscv: dts: sophgo: sg2044: add ziccrse extension
e64ca04dfa1a riscv: dts: sophgo: add zfh for sg2042
af70f42b8563 riscv: dts: sophgo: add ziccrse for sg2042
341c9d72df4f riscv: dts: sophgo: Add xtheadvector to the sg2042 devicetree
867de304b18d riscv: dts: sophgo: sg2044: add PCIe device support for SG2044
084dbab95812 riscv: dts: sophgo: sg2044: add MSI device support for SG2044
f3f305412cd9 riscv: dts: sophgo: add reset configuration for Sophgo CV1800 series SoC
d4c78bf20a68 riscv: dts: sophgo: add reset generator for Sophgo CV1800 series SoC
ca25c70f2e20 dt-bindings: soc: sophgo: Move SoCs/boards from riscv into soc, add SG2000
b116c2ce6c9e riscv: dts: sophgo: sg2044: Add missing riscv,cbop-block-size property
a7465701ba1b riscv: dts: sophgo: add pwm controller for SG2044
2d4c469f3e0c riscv: dts: sophgo: add SG2044 SPI NOR controller driver
6ed1d5df4964 riscv: dts: sophgo: sg2044: Add pinctrl device
0e92ebbc7780 riscv: dts: sophgo: sg2044: Add ethernet control device
f20278d13b83 riscv: dts: sophgo: sophgo-srd3-10: add HWMON MCU device
1ab417f2c6d5 riscv: dts: sophgo: sg2044: Add MMC controller device
5234c1aec3a0 riscv: dts: sophgo: sg2044: add DMA controller device
72423eef988d riscv: dts: sophgo: sg2044: Add I2C device
a82a340b1d6b riscv: dts: sophgo: sg2044: Add GPIO device
733f28e2c1dc riscv: dts: sophgo: sg2044: Add clock controller device
8fa3d034a693 riscv: dts: sophgo: sg2044: Add system controller device
0adb6607aa87 riscv: dts: sophgo: cv18xx: Add RTCSYS device node
551dd312e065 Merge tag 'apple-soc-dt-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/sven/linux into soc/dt
0c7b9e2e286d Merge tag 'at91-dt-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into soc/dt
bd42c1ae49a9 Merge tag 'thead-dt-for-v6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/fustini/linux into soc/dt
773cec14b76e Merge tag 'v6.17-rockchip-dts64-2' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
6daf8e447699 ARM: dts: st: spear: Use generic "ethernet" as node name
515a597ed8c8 Merge tag 'qcom-drivers-for-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers
a7a24115ee9b Merge tag 'memory-controller-drv-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into soc/drivers
3c035ea894fb dt-bindings: riscv: cpus: Add AMD MicroBlaze V 64bit compatible
564f3f7a8a9d Merge tag 'tegra-for-6.17-memory' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/drivers
90505e583326 Merge branch 'newsoc/axiado' into soc/newsoc
d2c0ccccbebb arm64: dts: axiado: Add initial support for AX3000 SoC and eval board
676074106b8d dt-bindings: i3c: cdns: add Axiado AX3000 I3C controller
6ac4d3ce41ab dt-bindings: serial: cdns: add Axiado AX3000 UART controller
007d178e28db dt-bindings: gpio: cdns: add Axiado AX3000 GPIO variant
c2b4468d9adc dt-bindings: gpio: cdns: convert to YAML
5a5a1053ea3b dt-bindings: arm: axiado: add AX3000 EVK compatible strings
10f07517af93 dt-bindings: vendor-prefixes: Add Axiado Corporation
5583ebf434fb Merge tag 'mvebu-dt-6.17-1' of https://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into soc/dt
502759c762d2 Merge tag 'amlogic-arm64-dt-for-v6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into soc/dt
c839bab293d1 Merge tag 'qcom-arm64-for-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
3fccb04b054a Merge tag 'sunxi-dt-for-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into soc/dt
5507affeb4ce Merge tag 'ti-k3-dt-for-v6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into soc/dt
0390f8569044 Merge tag 'qcom-arm32-for-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
82b6193bcad3 Merge tag 'spacemit-dt-for-6.17-1' of https://github.com/spacemit-com/linux into soc/dt
048993d6cfca Merge tag 'imx-bindings-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt
16c8d6c0186c Merge tag 'imx-dt-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt
200442757655 Merge tag 'imx-dt64-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt
5dbe4280d749 Merge tag 'socfpga_dts_updates_for_v6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into soc/dt
df2b1b31d3ab Merge tag 'tegra-for-6.17-arm64-dt' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
92326a333c76 Merge tag 'tegra-for-6.17-arm-dt' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
2e35e6c04a0e Merge tag 'tegra-for-6.17-dt-bindings' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
0b4b59ce9c57 dt-bindings: qcom: geni-se: describe SA8255p
32ebdce75966 dt-bindings: serial: describe SA8255p
c5b78d58092e Merge branches 'pm-misc' and 'pm-tools'
cb4c9d49e8ae dt-bindings: phy: Convert brcm,sr-usb-combo-phy to DT schema
b71d5d92eed1 dt-bindings: phy: Convert ti,da830-usb-phy to DT schema
7113f012a446 dt-bindings: phy: marvell,mmp2-usb-phy: Drop status from the example
b8380346183a dt-bindings: phy: mixel, mipi-dsi-phy: Allow assigned-clock* properties
bc9f6c56ebf6 dt-bindings: phy: qcom,snps-eusb2: document the Milos Synopsys eUSB2 PHY
e8bf211ef002 dt-bindings: usb: qcom,snps-dwc3: Add Milos compatible
b1b5a102a159 dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Update pcie phy bindings for QCS615
4793916c4605 Merge branch 'icc-milos' into icc-next
ca79b1e41699 Merge tag 'ath-next-20250721' of git://git.kernel.org/pub/scm/linux/kernel/git/ath/ath into wireless-next
4a7813db0edd dt-bindings: thermal: tegra: Document Tegra210B01
647d14815aa7 dt-bindings: thermal: mediatek: Add fallback compatible string for MT7981 and MT8516
8cbb6e090113 dt-bindings: interconnect: document the RPMh Network-On-Chip Interconnect in Qualcomm Milos SoC
c75e65fa1a7a dt-bindings: serial: 8250: spacemit: set clocks property as required
3d801ddabd51 dt-bindings: serial: renesas: Document RZ/V2N SCIF
8004034be86b arm64: dts: apple: Add Apple SoC GPU
372bb0a9270c dt-bindings: gpu: Add Apple SoC GPU
0fd845e2039f arm64: dts: apple: t8012-j132: Include touchbar framebuffer node
def9acb229f9 arm64: dts: apple: Add bit offset to PMIC NVMEM node names
dc4bff407bcd Merge branch 'newsoc/cix-p1' into soc/newsoc
c9853b29c44c arm64: dts: cix: Add sky1 base dts initial support
566f7b29d383 dt-bindings: clock: cix: Add CIX sky1 scmi clock id
2d860dd2a924 dt-bindings: mailbox: add cix,sky1-mbox
4c129f674cb4 dt-bindings: arm: add CIX P1 (SKY1) SoC
ec61ee7dfba5 dt-bindings: vendor-prefixes: Add CIX Technology Group Co., Ltd.
7ebb5edbb224 Merge branch 'newsoc/andes' into soc/newsoc
629e67c23eef Merge tag 'mtk-dts64-for-v6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/dt
d845a9c7f436 Merge tag 'mtk-dts32-for-v6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/dt
8b47485f6798 Merge tag 'omap-for-v6.17/dt-signed' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap into soc/dt
866ff7150b56 Merge tag 'stm32-dt-for-v6.17-1' of https://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into soc/dt
ea5f4eb45cdb Merge tag 'v6.17-rockchip-dts64-1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
09a326b741de arm64: dts: nuvoton: npcm8xx: Drop the GIC "ppi-partitions" node
ca6ab3278201 Merge tag 'aspeed-6.17-devicetree-1' of https://git.kernel.org/pub/scm/linux/kernel/git/bmc/linux into soc/dt
12f66471cea2 Merge tag 'renesas-dts-for-v6.17-tag2' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
ce29d48849d5 Merge tag 'renesas-dt-bindings-for-v6.17-tag2' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
d5a3aec241ba Merge tag 'samsung-dt64-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt
61ffff1eadc1 Merge tag 'samsung-dt-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt
c241df52dbd4 Merge tag 'dt-vt8500-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt into soc/dt
5a97ca254d34 Merge tag 'arm-soc/for-6.17/drivers' of https://github.com/Broadcom/stblinux into soc/drivers
615e5dd1026f Merge tag 'v6.16-rc7' into tty-next
bfb15af09263 riscv: dts: andes: add Voyager board device tree
e75c75ca51e1 riscv: dts: andes: add QiLai SoC device tree
40e05487b65c dt-bindings: timer: add Andes machine timer
96e291cff48a dt-bindings: interrupt-controller: add Andes machine-level software interrupt controller
5a070b8aab00 dt-bindings: interrupt-controller: add Andes QiLai PLIC
23b07e5175ad dt-bindings: riscv: add Andes QiLai SoC and the Voyager board bindings
6f6f2755eb71 Merge tag 'reset-for-v6.17' of https://git.pengutronix.de/git/pza/linux into soc/drivers
d0eccdbd78de spidev: introduce trivial abb sensor device
e899273b9ee5 dt-bindings: trivial-devices: Document ABB sensors
39715dac45f4 PM: docs: Use my kernel.org address in ABI docs and DT bindings
9f70470351fe Merge tag 'v6.16-rc7' into usb-next
4d4776db387d dt-bindings: clock: Add support for i.MX94 LVDS/DISPLAY CSR
9a7abe6a0109 dt-bindings: hwmon: adt7475: Allow and recommend #pwm-cells = <3>
8e0e30e58cfa dt-bindings: trivial: Add tps53685 support
0ba69b597265 dt-bindings: hwmon: pmbus/adp1050: Add adp1051, adp1055 and ltp8800
5538f47fb83b dt-bindings: hwmon: pmbus: ti,ucd90320: Add missing compatibles
70a810c569f2 dt-bindings: hwmon: maxim,max20730: Add maxim,max20710 compatible
684ed1fcb89b dt-bindings: hwmon: lltc,ltc2978: Add lltc,ltc713 compatible
ceb2f4ae7231 dt-bindings: hwmon: ti,lm87: Add adi,adm1024 compatible
6fda8eb1d30f dt-bindings: hwmon: national,lm90: Add missing Dallas max6654 and onsemi nct72, nct214, and nct218
fec5aa716025 dt-bindings: hwmon: amc6821: Add cooling levels
2a3bb1bc029e dt-bindings: hwmon: (pmbus/isl68137) Add RAA229621 support
df9399258d45 dt-bindings: clock: qcom,sm4450-dispcc: Reference qcom,gcc.yaml
a21d5e131452 dt-bindings: clock: qcom,sm4450-camcc: Reference qcom,gcc.yaml
c26aa209d9af dt-bindings: clock: qcom,mmcc: Reference qcom,gcc.yaml
101385caa206 dt-bindings: clock: qcom,sm8150-camcc: Reference qcom,gcc.yaml
bf0ad3272a8d dt-bindings: clock: qcom: Remove double colon from description
5e0de7d92ba1 Merge tag 'iio-for-6.17a' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/jic23/iio into char-misc-next
ed2c0a3539b9 dt-bindings: interconnect: qcom,msm8998-bwmon: Allow 'nonposted-mmio'
16222f5add7f dt-bindings: interconnect: Add EPSS L3 compatible for QCS8300 SoC
26e8a1a26a63 dt-bindings: interconnect: qcom: Remove double colon from description
f3990f2988aa dt-bindings: gpio: Convert qca,ar7100-gpio to DT schema
f4169e8902ba dt-bindings: gpio: Convert maxim,max3191x to DT schema
cc96527c4361 dt-bindings: gpio: fsl,qoriq-gpio: Add missing mpc8xxx compatibles
234beb04554a dt-bindings: gpio: Create a trivial GPIO schema
d5b6bbdd5ea6 dt-bindings: gpio: Convert st,spear-spics-gpio to DT schema
57d91fffc5cb dt-bindings: gpio: Convert abilis,tb10x-gpio to DT schema
baf1be13c404 dt-bindings: gpio: Convert apm,xgene-gpio-sb to DT schema
bb01ffde4219 dt-bindings: gpio: Convert ti,twl4030-gpio to DT schema
7c869e945c1d dt-bindings: gpio: Convert lantiq,gpio-mm-lantiq to DT schema
2d351d673ed0 dt-bindings: gpio: Convert ti,keystone-dsp-gpio to DT schema
d1caee930967 dt-bindings: gpio: Convert altr,pio-1.0 to DT schema
f6b6f6538c88 dt-bindings: gpio: Convert cirrus,clps711x-mctrl-gpio to DT schema
f5b06d065b65 dt-bindings: gpio: Convert cavium,octeon-3860-gpio to DT schema
6ebb1a828301 dt-bindings: gpio: Convert exar,xra1403 to DT schema
2785b36e35cc dt-bindings: gpio: Convert microchip,pic32mzda-gpio to DT schema
b56e20fc40d7 dt-bindings: gpio: Convert lacie,netxbig-gpio-ext to DT schema
3ccc1ca7e0ba Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
8f379560c370 dt-bindings: trivial-devices: Add undocumented hwmon devices
39de5984956e dt-bindings: arm-smmu: Remove sdm845-cheza specific entry
a1ac450f3634 arm64: dts: rockchip: Add maskrom button to NanoPi R5S + R5C
af0325e129ae dt-bindings: thermal: qcom-tsens: document the Milos Temperature Sensor
49cc1296037b dt-bindings: clock: qcom: document the Milos Video Clock Controller
16340601924b dt-bindings: clock: qcom: document the Milos GPU Clock Controller
573f59c35a7e dt-bindings: clock: qcom: document the Milos Display Clock Controller
da3d8ec933a1 dt-bindings: clock: qcom: document the Milos Camera Clock Controller
108d90ed45b5 dt-bindings: clock: qcom: document the Milos Global Clock Controller
b1a99cb677d8 dt-bindings: clock: qcom,x1e80100-gcc: Add missing video resets
9e4ffed3ade8 dt-bindings: clock: qcom,sm8450-videocc: Document X1E80100 compatible
741514539768 dt-bindings: clock: qcom: document the Milos TCSR Clock Controller
97ec633f5480 dt-bindings: clock: qcom: Document the Milos RPMH Clock Controller
6d406a229797 dt-bindings: clock: Add Qualcomm QCS615 Video clock controller
8b50d3c9c410 dt-bindings: clock: Add Qualcomm QCS615 Graphics clock controller
d0090474f382 dt-bindings: clock: Add Qualcomm QCS615 Display clock controller
942ecba2c8f9 dt-bindings: clock: Add Qualcomm QCS615 Camera clock controller
82a322763a4f Merge branch '20250516-ipq5018-cmn-pll-v4-2-389a6b30e504@outlook.com' into clk-for-6.17
9eefab0dfdd5 dt-bindings: clock: qcom: Add CMN PLL support for IPQ5018 SoC
a1b9cfc98bd3 dt-bindings: soc: qcom: qcom,pmic-glink: document Milos compatible
d5da90eccdff dt-bindings: soc: qcom,aoss-qmp: document the Milos Always-On Subsystem side channel
34786aba9ba7 dt-bindings: firmware: qcom,scm: document Milos SCM Firmware Interface
6e113c99e893 dt-bindings: arm: qcom,ids: Add SoC IDs for SM7635 family
fd8cea27d9ae dt-bindings: net: cdns,macb: Add external REFCLK property
aec48256a2ff dt-bindings: thermal: rockchip: document otp thermal trim
328772974a15 dt-bindings: rockchip-thermal: Add RK3576 compatible
19f989a5bd1d MIPS: mobileye: eyeq5: add two GPIO bank nodes
6b4ac8add716 MIPS: mobileye: eyeq5: add evaluation board I2C temp sensor
4fd343c406b0 MIPS: mobileye: eyeq5: add 5 I2C controller nodes
e68a2aba902d dt-bindings: watchdog: nxp,pnx4008-wdt: allow clocks property
9c8255dc203b riscv: dts: starfive: jh7110-common: add status power led node
22723d632890 riscv: dts: starfive: jh7110-milkv-mars sort properties
e455f730d5b8 dt-bindings: nvmem: convert vf610-ocotp.txt to yaml format
5e169c37d95c dt-bindings: nvmem: mediatek: efuse: split MT8186/MT8188 from base version
7a10c41bf9e8 dt-bindings: nvmem: SID: Add binding for A523 SID controller
cbc42a476e75 dt-bindings: nvmem: convert lpc1857-eeprom.txt to yaml format
abc73f36bf9d dt-bindings: nvmem: fixed-layout: Allow optional bit positions
813b29da2d55 ASoC: dt-bindings: qcom,lpass-va-macro: Define clock-names in top-level
c33c7fb45109 dt-bindings: display: Add Sitronix ST7567 LCD Controller
c9198fbc442e dt-bindings: soc: samsung: exynos-sysreg: add hsi2 for ExynosAutov920
8cd3784e53b6 spi: dt-bindings: spi-mux: Drop "spi-max-frequency" as required
a08ba8cf59b0 dt-bindings: PCI: qcom: Move PHY & reset GPIO to Root Port node
8ab2a8849856 dt-bindings: PCI: qcom,pcie-sa8255p: Document ECAM compliant PCIe root complex
e7eea35f2725 arm64: dts: rockchip: Drop regulator-compatible property on rk3399
1fd0e3d44d5a arm64: dts: rockchip: Drop unneeded address+size-cells on px30
43cbc3eb401a arm64: dts: rockchip: Fix LCD panel port on rk3566-pinetab2
d654d06cfa41 arm64: dts: rockchip: Move mipi_out node on rk3399 haikou demo dtso
2e4252d482d0 arm64: dts: rockchip: Simplify mipi_out endpoint on rk3399 RP64 dtso
34b2c6e27343 arm64: dts: rockchip: Simplify edp endpoints on several rk3399 boards
c824fe70648a arm64: dts: rockchip: Simplify VOP port definition on rk3328
fa7552a02970 dt-bindings: usb: convert lpc32xx-udc.txt to yaml format
c80a7e0d3ea3 ARM: dts: broadcom: Fix bcm7445 memory controller compatible
1ef58d48a6ef dt-bindings: display: panel: samsung,atna30dw01: document ATNA30DW01
e77e4c64d3aa arm64: dts: allwinner: a523: enable Mali GPU for all boards
bf3f984838fb arm64: dts: allwinner: a523: add Mali GPU node
497e5ea363fe arm64: dts: allwinner: a523: Add power controller device nodes
9467e9442c85 Merge branch 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm into sunxi/dt-for-6.17
cc2d2d0d56f2 dt-bindings: mmc: sdhci-msm: document the Milos SDHCI Controller
b028e9e71dbc dt-bindings: power: Add A523 PPU and PCK600 power controllers
a266236fefcb arm64: dts: rockchip: Move dsi address+size-cells from SoC to rk3399 boards
ab7cf99a1f4a arm64: dts: rockchip: Move dsi address+size-cells from SoC to px30 boards
f8d95046048f dt-bindings: display: rockchip,dw-mipi-dsi: Drop address/size cells
597bb0d8411a dt-bindings: arm-smmu: document the support on Milos
ee596924f1a1 arm64: dts: rockchip: Fix UART DMA support for RK3528
01647aa1b636 arm64: dts: rockchip: Add reset button to NanoPi R5S
a74d4de252fd arm64: dts: rockchip: Add rtc0 alias for NanoPi R5S + R5C
46a8ca674cfa dt-bindings: interrupt-controller: Convert apm,xgene1-msi to DT schema
e07aac30910c dt-bindings: gpu: mali-bifrost: Add Allwinner A523 compatible
609204d3eec9 docs: dt: writing-schema: Document preferred order of properties
91dffad70433 docs: dt: writing-bindings: Document discouraged instance IDs
7d0a75ec87a1 docs: dt: writing-bindings: Document compatible and filename naming
ce2424aea4e8 docs: dt: submitting-patches: Avoid 'YAML' in the subject and add an example
cfcbcd138f50 dt-bindings: iio: proximity: Add Nicera D3-323-AA PIR sensor
1dc1537a1cfc dt-bindings: vendor-prefixes: Add Nicera
50d9d6206314 dt-bindings: iio: adc: Add support for MT7981
e3979d4e5a71 dt-bindings: iio: adc: Add AD4170-4
d56febcf05e4 dt-bindings: pinctrl: stm32: Introduce HDP
fad75c97710c Add RPMh regulator support for PM7550 & PMR735B
02ea21d540c3 ASoC: codec: Convert to GPIO descriptors for
89d0b8fce36f regulator: dt-bindings: qcom,rpmh: Add PMR735B compatible
c8bd9fcae9a0 regulator: dt-bindings: qcom,rpmh: Add PM7550 compatible
d4e6b1fb0783 dt-bindings: iio: adc: mt6359: Add MT6373 PMIC AuxADC
098202eec4e1 dt-bindings: iio: adc: mt6359: Add MT6363 PMIC AuxADC
1697eb314369 arm64: dts: imx8q: add camera ov5640 support for imx8qm-mek and imx8qxp-mek
28dbe992a899 arm64: dts: altera: socfpga_stratix10: update internal oscillators
df7e566fd9d3 arm64: dts: socfpga: swvp: remove phy-addr in the GMAC node
58018d66ed16 arm64: dts: socfpga: swvp: remove cpu1-start-addr
ed76c055b420 arm64: dts: socfpga: swvp: remove altr,modrst-offset
aec88103429c arm64: dts: socfpga: stratix10: fix dtbs_check for rstmgr
39d9a2cbc5e5 arm64: dts: socfpga: agilex: fix dtbs_check warning for f2s-free-clk
ef70c327c3f6 arm64: dts: allwinner: A523: Add SID controller node
752c7e4e2720 arm64: dts: allwinner: a133-liontron-h-a133l: Add Ethernet support
fae71aaf339e arm64: dts: allwinner: a100: Add EMAC support
b38274d492ca arm64: dts: allwinner: a100: Add pin definitions for RGMII/RMII
ed798b2f7978 media: dt-bindings: rockchip: Add RK3576 Video Decoder bindings
8a915333fc1e media: dt-bindings: rockchip: Document RK3588 Video Decoder bindings
9b65179d600c dt-bindings: pinctrl: document the Milos Top Level Mode Multiplexer
fb32a87d3875 dt-bindings: pinctrl: qcom,pmic-gpio: Add PM7550 support
9391657b90c6 dt-bindings: pinctrl: qcom,pmic-gpio: Add PMIV0104 support
d655238fffbd ARM: tegra: chagall: Add embedded controller node
8f97653e1318 ARM: tegra: Add device-tree for Asus Portable AiO P1801-T
800285ab20bb dt-bindings: arm: tegra: Add Asus Portable AiO P1801-T
2a2952b67a2e arm64: tegra: Add p3971-0089+p3834-0008 support
ce7e69af42ca arm64: tegra: Add memory controller on Tegra264
a81e86db62db arm64: tegra: Add Tegra264 support
a6689e2bd732 dt-bindings: arm: tegra: Add Asus VivoTab RT TF600T
776d06cf806e dt-bindings: Add Tegra264 clock and reset definitions
536f700e61e8 dt-bindings: tegra: Document P3971-0089+P3834-0008 Platform
c9998640b0fc dt-bindings: rtc: tegra: Document Tegra264 RTC
9aacfd76da1d dt-bindings: dma: Add Tegra264 compatible string
7def90ff5f38 dt-bindings: misc: Document Tegra264 APBMISC compatible
a59edbcea209 dt-bindings: firmware: Document Tegra264 BPMP
26008a3fa73f dt-bindings: mailbox: tegra-hsp: Properly sort compatible string list
ac67362457ac dt-bindings: mailbox: tegra-hsp: Bump number of shared interrupts
88181419846e dt-bindings: memory: tegra: Add Tegra264 support
80cb84e4d5a7 dt-bindings: tegra: pmc: Add Tegra264 compatible
44788ad15192 arm64: dts: rockchip: describe the OV8858 user camera on PinePhone Pro
f48d16bc01ed arm64: dts: rockchip: describe I2c Bus 1 and IMX258 world camera on PinePhone Pro
624791f8d74a arm64: dts: rockchip: Fix pinctrl node names for RK3528
2a7b4ab8ef90 arm64: dts: rockchip: Add FriendlyElec NanoPi M5 support
75ac9bbd660a dt-bindings: arm: rockchip: add FriendlyElec NanoPi M5 board
d9c568906be1 arm64: dts: rockchip: force PMIC reset behavior to restart PMU on RK3588 Tiger
8bd14566b75f arm64: dts: rockchip: force PMIC reset behavior to restart PMU on RK3588 Jaguar
0e417bfcbc38 arm64: dts: rockchip: add header for RK8XX PMIC constants
5cdc97a0faf8 arm64: dts: rockchip: add HDMI audio on ROCK 4D
d2defdc9b0c3 arm64: dts: rockchip: theoretically enable Wi-Fi on ROCK 4D
7200ec33cb56 arm64: dts: rockchip: complete USB nodes on ROCK 4D
ac5675c9dfae arm64: dts: rockchip: adjust dcin regulator on ROCK 4D
71bbd4df5a38 arm64: dts: Add DTS for Marvell PXA1908 and samsung,coreprimevelte
c3eb8bf27be6 dt-bindings: marvell: Document PXA1908 SoC and samsung,coreprimevelte
3dbe8d040691 dt-bindings: mmc: sdhci-pxa: restrict pinctrl to pxav1
256a25acb085 arm64: dts: freescale: imx8mp-toradex-smarc: remove gpio hog
4875356dd0d1 arm64: dts: freescale: imx8mp-toradex-smarc: fix lvds dsi mux gpio
7e16a47c774f arm64: dts: imx8mm-venice-gw7904: Increase HS400 USDHC clock speed
958eae2d29ea arm64: dts: imx8mm-venice-gw7903: Increase HS400 USDHC clock speed
3b94e93f86e6 arm64: dts: imx8mn-venice-gw7902: Increase HS400 USDHC clock speed
a81c22fbb48a arm64: dts: imx8mm-venice-gw7902: Increase HS400 USDHC clock speed
59d34e1fa7de arm64: dts: imx8mm-venice-gw7901: Increase HS400 USDHC clock speed
e1cf73b27bcb arm64: dts: imx8mp-venice-gw702x: Increase HS400 USDHC clock speed
0edd7bba0263 arm64: dts: imx8mm-venice-gw700x: Increase HS400 USDHC clock speed
9820a07342b0 arm64: dts: lx2160a-qds: add the two on-board RGMII PHYs
16382fa39594 arm64: dts: add imx95-libra-rdk-fpsc board
8a6f28dab39c arm64: dts: imx8q: add linux,cma node for imx8qm-mek and imx8qxp-mek
ba73343b8812 arm64: dts: imx8: add capture controller for i.MX8's img subsystem
ea6b32baf520 arm64: dts: imx95: add jpeg encode and decode nodes
2a4634dc728b arm64: dts: imx93-phyboard-nash: Add PEB-WLBT-07 overlay
c080e7b9ddda arm64: dts: imx93-phyboard-segin: Add PEB-WLBT-05 overlay
1f7892023ef4 arm64: dts: imx93-phyboard-segin: Add PEB-EVAL-01 overlay
faa5aade74a9 arm64: dts: imx93-phycore-som: Add RPMsg overlay
07780fa4aed1 arm64: dts: freescale: tqmls10xx: Add vdd-supply for spi-nor flash
8e3492338e8b arm64: dts: freescale: tqmls10xx-mbls10xxa: Add vdd-supply for i2c mux
271103d977c9 arm64: dts: tqmls1046a: Enable SFP interfaces
25f7bd3b4a47 arm64: dts: tqmls1043a: Enable SFP interface
54f5caa98df8 arm64: dts: tqmls10xxa: Move SFP cage definition to common place
e715bb94e263 arm64: dts: fsl-ls1088a: Remove superfluous address and size cells
c82c1751f804 arm64: dts: fsl-ls1046a: Remove superfluous address and size cells
ebcd19d6347a arm64: dts: fsl-ls1043a: Remove superfluous address and size cells
17c7cc47affb arm64: dts: imx94: add missing clock related properties to flexcan1
d60633ab78a3 arm64: dts: imx8mn: Configure DMA on UART2
7d4ebc6b315b arm64: dts: imx8mm: Configure DMA on UART2
6d1fccdc8f60 arm64: dts: fsl-ls1046a: Add missing DMA entries for I2C & LPUART
7495eeebbd34 arm64: dts: fsl-ls1043a: Add missing DMA entries for I2C & LPUART
e06f4e76e905 arm64: dts: freescale: imx93-phycore-som: Add watchdog ext-reset-output pin
d58bd9b4a79b arm64: dts: imx8mn-beacon: Fix HS400 USDHC clock speed
c694a7bc8cf3 arm64: dts: imx8mm-beacon: Fix HS400 USDHC clock speed
6743b8d488e1 arm64: dts: tqma8mpql-mba8mpxl-lvds: Rename overlay to include display name
a37af13d15c8 arm64: dts: imx8qm-mek: support revd board's wm8962 codec
7a3fbd740ca5 arm64: dts: imx8qxp-mek: support wcpu board's wm8962 codec
7e34086585b9 arm64: dts: imx8mp-evk: Use fsl-asoc-card to replace simple card
83f3bf720be9 arm64: dts: imx93: add edma error interrupt support
ebf5c781f77d arm64: dts: freescale: imx8mp-toradex-smarc: add fan cooling levels
181479b67e8a arm64: dts: imx8mp: Configure VPU clocks for overdrive
59f683a9ab68 arm64: dts: imx8mp-nominal: Explicitly configure nominal VPU clocks
8a232cb5a7fa arm64: dts: imx8mp: fix VPU_BUS clock setting
eb10431b8e66 arm64: dts: imx8mp: drop gpcv2 vpu power-domains and clocks
60e50a08da9b arm64: dts: freescale: imx8qxp/imx8qm: Add CAAM support
a248219a8875 ARM: dts: mediatek: add basic support for Lenovo A369i board
bfd569da9873 ARM: dts: mediatek: add basic support for JTY D101 board
2a4d4ef273b2 ARM: dts: mediatek: add basic support for MT6572 SoC
23404121bdd4 dt-bindings: arm: mediatek: add boards based on the MT6572 SoC
a4c8dd9520f6 dt-bindings: vendor-prefixes: add JTY
e0c23527ba98 dt-bindings: watchdog: mediatek,mtk-wdt: add MT6572
b2b61a2db095 dt-bindings: interrupt-controller: mediatek,mt6577-sysirq: add MT6572
804ab7c7d85d ARM: dts: imx6-gw: Replace license text comment with SPDX identifier
03bac12b32b2 ARM: dts: imx6ul-kontron-sl-common: Fix QSPI NAND node name
ad2593118243 ARM: dts: imx6ul-kontron-sl-common: Add SPI NOR partitions
4885f805e158 ARM: dts: imx6ul-kontron-bl-common: Fix RTS polarity for RS485 interface
d1b91e76690e dt-bindings: add imx95-libra-rdk-fpsc
a0409bf40ae5 arm64: dts: ti: k3-am69-sk: Add idle-states for remaining SERDES instances
673bf0fe91bc arm64: dts: ti: k3-am62a7-sk: add boot phase tags
0b61c356e6ad arm64: dts: ti: k3-am654-base-board: add boot phase tags
7d711c316bdb arm64: dts: ti: k3-am65: add boot phase tags
e177b1c9de01 dt-bindings: clock: ast2600: Add reset definitions for MAC1 and MAC2
1c5060689b34 dt-bindings: net: ftgmac100: Add resets property
5193dd5fa141 dt-bindings: net: sophgo,sg2044-dwmac: Add support for Sophgo SG2042 dwmac
5ce5f07b5508 dt-bindings: net: dsa: mediatek,mt7530: add internal mdio bus
583ebba08917 dt-bindings: net: dsa: mediatek,mt7530: add dsa-port definition for mt7988
0f557ac7ccfe dt-bindings: net: mediatek,net: add sram property
cffbaf9b81e2 dt-bindings: net: mediatek,net: allow irq names
a76ffe63b15c dt-bindings: net: mediatek,net: allow up to 8 IRQs
6bb228560999 dt-bindings: net: mediatek,net: update mac subnode pattern for mt7988
97de60cfbce0 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
b9da9213ade8 arm64: dts: st: remove empty line in stm32mp251.dtsi
64063fff5ffb arm64: dts: st: fix timer used for ticks
4c7a19b4cb33 regulator: Merge tps6594 driver changes
daad99af0822 dt-bindings: mfd: ti,tps6594: Add TI TPS652G1 PMIC
8386b729544f dt-bindings: media: cdns,csi2rx.yaml: Add optional interrupts for cdns-csi2rx
b29392c6d2f8 arm64: dts: rockchip: Enable HDMI receiver on RK3588 EVB1
d54023e2d503 arm64: dts: rockchip: fix PHY handling for ROCK 4D
a3f230874d3a arm64: dts: rockchip: Enable mipi dsi on rk3568-evb1-v10
cf9888548489 arm64: dts: rockchip: Add UFS support on the ROCK 4D
7903089bd476 arm64: dts: ti: k3-am69-sk: Add bootph-all property to enable Ethernet boot
24844a9efccd arm64: dts: ti: k3-j722s-evm: Add bootph-all property to enable Ethernet boot
f4fdd87dbb41 arm64: dts: ti: k3-am62p5-sk: Add bootph-all property to enable Ethernet boot
3939a611e8bc arm64: dts: ti: k3-am68-sk-base-board: Add bootph-all property to enable Ethernet boot
a3f5e9fa0441 arm64: dts: ti: Add support for AM62D2-EVM
7a38d687cc98 arm64: dts: ti: Add pinctrl entries for AM62D2 family of SoCs
f2166a890cbb dt-bindings: arm: ti: Add AM62D2 SoC and Boards
aa589db3ac8e arm64: dts: ti: Add bootph property to nodes at source for am62a
24acc0cda0ca dt-bindings: ethernet-phy: add MII-Lite phy interface type
de5faa29496a dt-bindings: dpll: Add support for Microchip Azurite chip family
be3edb0ba9c7 dt-bindings: dpll: Add DPLL device and pin
6951965726e3 dt-bindings: net: Add support for Sophgo CV1800 dwmac
57ec540c0009 dt-bindings: memory: renesas,rzg3e-xspi: Document RZ/V2H(P) and RZ/V2N support
397d62e38e6d dt-bindings: arm: sunxi: Combine board variants into enums
94f9ccddf8d2 ARM: tegra: Add device-tree for ASUS VivoTab RT TF600T
966adacf22f9 dt-bindings: serial: rsci: Update maintainer entry
311412a89e25 dt-bindings: serial: renesas,rsci: Add optional secondary clock input
107315cef7f1 dt-bindings: serial: sh-sci: Document r8a78000 bindings
49773b5da84b dt-bindings: power: qcom,rpmpd: document the Milos RPMh Power Domains
89e711f0ab70 arm64: dts: ti: k3-am62p-verdin: Adjust temperature trip points
6d8d2fd35d79 arm64: dts: ti: k3-am62p-j722s: Enable freq throttling on thermal alert
96816c0c1cda Merge tag 'pm-runtime-6.17-rc1' of https://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
4c2695cf19b3 arm64: dts: ti: k3-j784s4-j742s2-main-common: Add PBIST_14 node
8d9287a162e7 dt-bindings: soc: ti: bist: Add BIST for K3 devices
2708025daa67 arm64: dts: ti: k3-am62-main: Remove eMMC High Speed DDR support
3112e1658091 arm64: dts: ti: k3-am62*: Move eMMC pinmux to top level board file
6dfe3e70a454 arm64: dts: ti: k3-am62a7-sk: fix pinmux for main_uart1
b74625437e2b riscv: dts: spacemit: Move eMMC under storage-bus for K1
106a2d7182d9 riscv: dts: spacemit: Move UARTs under dma-bus for K1
37db9248d762 riscv: dts: spacemit: Add DMA translation buses for K1
d9accb54a587 riscv: dts: spacemit: add pwm14_1 pinctrl setting
0603708cb366 riscv: dts: spacemit: add PWM support for K1 SoC
23afee5fb806 arm64: dts: ti: k3-am62p-verdin: fix PWM_3_DSI GPIO direction
e05ddcb61514 arm64: dts: ti: k3-pinctrl: Enable Schmitt Trigger by default
d8f96fe1e4b5 dt-bindings: net: altr,socfpga-stmmac.yaml: add minItems to iommus
e38f508615bd net: dt-bindings: ixp4xx-ethernet: Support fixed links
75d68220cfff dt-bindings: interrupt-controller: Add Arm GICv5
33b7328bd67b Merge tag 'drm-msm-next-2025-07-05' of https://gitlab.freedesktop.org/drm/msm into drm-next
10794b789986 docs: dt: writing-bindings: Consistently use single-whitespace
86a9bf4c4443 docs: dt: writing-bindings: Express better expectations of "specific"
0c8f9e02cd3b docs: dt: writing-bindings: Rephrase typical fallback (superset) usage
0f6503d69ae6 arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable serial NOR FLASH
add55fc9ed19 arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Enable serial NOR FLASH
7cd8bb1dc1cc arm64: dts: renesas: r9a09g057: Add XSPI node
531f2d9725b7 arm64: dts: renesas: r9a09g056: Add XSPI node
84f1df18dc5f Merge tag 'renesas-r9a09g057-dt-binding-defs-tag4' into renesas-dts-for-v6.17
a4a0bc4dc3e9 arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Fix pinctrl node name for GBETH1
8b67347d881d arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Fix pinctrl node name for GBETH1
66af74e1aa4d arm64: dts: renesas: rzg3e-smarc-som: Enable eth{0-1} (GBETH) interfaces
c813a6ce829d arm64: dts: renesas: r9a09g047e57-smarc: Add gpio keys
eb1e7e4e9e6e dt-bindings: rtc: nxp,lpc1788-rtc: add compatible string nxp,lpc1850-rtc
d9c9432709dc dt-bindings: rtc: move nxp,lpc3220-rtc to separated file from trivial-rtc.yaml
f7e641cf0882 dt-bindings: Move sophgo,cv1800b-rtc to rtc directory
c2ccc8724b7a arm: dts: ti: omap: Fixup pinheader typo
e6a0b772cb05 ARM: dts: am335x-pdu001: Fix RS-485 transceiver switching
40e9787d1816 ASoC: soc-dapm: cleanups
01c983755f54 ARM: dts: marvell: kirkwood: use recent scl/sda gpio bindings
75df38d090a6 arm64: dts: mediatek: mt8395-genio-1200-evk: Add MT6359 PMIC key support
3a6357e27ba7 arm64: dts: mediatek: mt8390-genio-common: Add Home MT6359 PMIC key support
6a3deb51c9b5 arm64: dts: mediatek: mt7988a-bpi-r4: add gpio leds
c7292550d3ab ARM: dts: imx6-karo: Replace license text comment with SPDX identifier
c134c3be2c58 arm64: dts: s32g: Add USB device tree information for s32g2/s32g3
8faccf139224 dt-bindings: usb: Add compatible strings for s32g2/s32g3
32caa97af9bf dt-bindings: gpio: pca95xx: add TI TCA6418
7158638bb3cd arm64: dts: mediatek: mt7988a-bpi-r4: drop unused pins
a2a08c044349 arm64: dts: mediatek: mt7988a-bpi-r4: add proc-supply for cci
240182754e31 arm64: dts: mediatek: mt7988: add cci node
6e93e2385a19 dt-bindings: interconnect: add mt7988-cci compatible
74844cb5275e arm64: dts: airoha: en7581: Add ethernet nodes to EN7581 SoC evaluation board
8289107f1c92 arm64: dts: mediatek: mt8192-asurada-spherion: Mark trackpads as fail-needs-probe
e4519cc918c5 arm64: dts: mediatek: mt8186: Add Squirtle Chromebooks
f8de516be111 arm64: dts: mediatek: mt8186: Merge Voltorb device trees
034615aac7eb arm64: dts: mediatek: mt8186-steelix: Mark second source components for probing
b0b73c2d7ae7 dt-bindings: arm: mediatek: Add MT8186 Squirtle Chromebooks
6b59c9ae290e dt-bindings: arm: mediatek: Merge MT8186 Voltorb entries
ae2638c7d641 Merge tag 'pm-runtime-6.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm into gpio/for-next
bc9b5bf851b3 dt-bindings: pwm: Convert lpc32xx-pwm.txt to yaml format
56458f97f58d dt-bindings: pwm: argon40,fan-hat: Document Argon40 Fan HAT
5ec6557630fd dt-bindings: vendor-prefixes: Document Argon40
71c5a4bb4e89 dt-bindings: pwm: mediatek,mt2712-pwm: Add support for MT6991/MT8196
6240e06fc3e5 dt-bindings: pwm: convert lpc1850-sct-pwm.txt to yaml format
b535e7088d2f dt-bindings: pwm: adi,axi-pwmgen: Update documentation link
69d7e2a442d2 dt-bindings: pwm: sophgo: Add pwm controller for SG2044
af64f85f74b4 riscv: dts: sifive: unleashed/unmatched: Remove PWM controlled LED's active-low properties
e0be156f6035 dt-bindings: pwm: marvell,pxa-pwm: Add SpacemiT K1 PWM support
e49654c2f279 Merge tag 'pm-runtime-6.17-rc1'
b24aeebf87a0 arm64: dts: allwinner: t527: Add OrangePi 4A board
7f5a1f6e1eb9 arm64: dts: allwinner: a523: Add UART1 pins
952f9cbd7af1 arm64: dts: allwinner: a523: Move rgmii0 pins to correct location
ad8576fad7d4 arm64: dts: allwinner: a523: Move mmc nodes to correct position
15e4d9212ce3 dt-bindings: arm: sunxi: Add Xunlong OrangePi 4A board
12336bf96c72 dt-bindings: iio: adc: nxp,lpc3220-adc: allow clocks property
e65cbadc0548 dt-bindings: iio: adc: ad4851: add spi-3wire
4d9c51edc9b9 arm64: dts: exynos7870-j6lte: reduce memory ranges to base amount
e086fd8876f5 arm64: dts: exynos7870-on7xelte: reduce memory ranges to base amount
9d9c6611c451 arm64: dts: exynos7870: add quirk to disable USB2 LPM in gadget mode
208cce5857c4 ARM: dts: microchip: sama7g5: Add cache configuration for cpu node
509b99826913 ARM: dts: microchip: sama7d65: Add cache configuration for cpu node
f3d0e33299fd ARM: dts: microchip: sama5d4: Update the cache configuration for CPU
8941fbf6ba5b ARM: dts: microchip: sama5d3: Update the cache configuration for CPU
2eff3303da8d ARM: dts: microchip: sama5d2: Update the cache configuration for CPU
e7b18d4c2364 Merge merge point of tag 'usb-6.16-rc5' into usb-next
c38da1ad3c4f dt-bindings: opp: adreno: Update regex of OPP entry
677b04f5438a dt-bindings: power: qcom,rpmpd: add Turbo L5 corner
e31a0e2df6d3 arm64: dts: amlogic: Enable the npu node for Alta and VIM3
607ef22a465f dts: arm64: amlogic: add S6 pinctrl node
9211f8207ece dts: arm64: amlogic: add S7D pinctrl node
ab5a66e09833 dts: arm64: amlogic: add S7 pinctrl node
15aac295b6bc arm64: dts: amlogic: Add Ugoos AM3
79c971501356 dt-bindings: arm: amlogic: Add Ugoos AM3
a6dec074934f arm64: dts: amlogic: Align wifi node name with bindings
a21c94e943cb dt-bindings: display/msm: qcom,sm8750-mdss: Add SM8750
109b054c5d62 dt-bindings: display/msm: qcom,sm8650-dpu: Add SM8750
d58d7037c611 dt-bindings: display/msm: dp-controller: Add SM8750
79c555201895 dt-bindings: display/msm: dsi-controller-main: Add SM8750
02e87e911953 dt-bindings: display/msm: dsi-phy-7nm: Add SM8750
792e2ba64bb0 ARM: dts: stm32: add stm32mp157f-dk2 board support
69778818ec62 dt-bindings: arm: stm32: add STM32MP157F-DK2 board compatible
7643ccce963f ARM: dts: stm32: optee async notif interrupt for MP15 scmi variants
5b0e91604398 ARM: dts: stm32: use internal regulators bindings for MP15 scmi variants
bf70ebd8ffe1 dt-bindings: regulator: Add STM32MP15 SCMI regulator identifiers
c76df445d8e2 ARM: dts: stm32: use 'typec' generic name for stusb1600 on stm32mp15xx-dkx
475d705400c1 ARM: dts: stm32: fullfill diversity with OPP for STM32M15xF SOCs
4bb10d43e4dc ARM: dts: stm32: add system-clock-direction-out on stm32mp15xx-dkx
b0cec331ce90 arm64: dts: st: add timer nodes on stm32mp257f-ev1
3784048145a5 arm64: dts: st: add timer pins for stm32mp257f-ev1
2030d965c281 arm64: dts: st: add timer nodes on stm32mp251
5e0382c920e9 ARM: dts: stm32: Add nvmem-cells to ethernet nodes for constant mac-addresses
7f41efee603f Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
1210620aaa38 arm64: dts: ti: k3-am62p-verdin: add SD_1 CD pull-up
49fb938f2aa0 ARM: dts: aspeed: yosemite4: add gpio name for uart mux sel
f80c1ece0727 ARM: dts: aspeed: santabarbara: Add Meta Santabarbara BMC
5739123deb47 dt-bindings: arm: aspeed: add Meta Santabarbara board
17e841eb8a01 ARM: dts: aspeed: bletchley: enable USB PD negotiation
6c20b3c5da78 ARM: dts: aspeed: lanyang: Fix 'lable' typo in LED nodes
ac274dd83da4 ARM: dts: aspeed: harma: add mmc health
5f776e456b95 ARM: dts: aspeed: Harma: revise gpio bride pin for battery
285c16da7d59 ARM: dts: aspeed: harma: add ADC128D818 for voltage monitoring
707670385616 ARM: dts: aspeed: harma: add fan board I/O expander
5cdab6370fb5 ARM: dts: aspeed: harma: add E1.S power monitor
4ac3caeab4d6 ARM: dts: aspeed: catalina: Enable MCTP for frontend NIC management
4acc31107f44 Merge tag 'drm-misc-next-2025-07-03' of https://gitlab.freedesktop.org/drm/misc/kernel into drm-next
3dfcfb15f3a4 riscv: dts: spacemit: add reset support for the K1 SoC
b1de41ddb12c Merge tag 'spacemit-reset-binding-for-6.17-1' of https://github.com/spacemit-com/linux
990c4c25e751 dt-bindings: pinctrl: stm32: Add missing blank lines
e6da1f46eb46 dt-bindings: pinctrl: convert nxp,lpc1850-scu.txt to yaml format
bfffde04584b arm64: dts: qcom: sm8150: Drop unrelated clocks from PCIe hosts
bccba5ad2d5e arm64: dts: qcom: sc8180x: Drop unrelated clocks from PCIe hosts
7d4d5736e895 dt-bindings: watchdog: fsl-imx-wdt: add compatible string fsl,ls1046a-wdt
3bd76858e231 Merge tag 'arm-soc/for-6.17/devicetree-arm64' of https://github.com/Broadcom/stblinux into soc/dt
e5d755023dc6 ARM: dts: lpc32xx: Add #pwm-cells property to the two SoC PWMs
5c1cfc4da7e7 Merge tag 'arm-soc/for-6.17/devicetree' of https://github.com/Broadcom/stblinux into soc/dt
376d0636861a dt-bindings: mtd: jedec,spi-nor: Add atmel,at26* compatible string
fe2b22926763 Merge tag 'renesas-dts-for-v6.17-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
5aaa6a166e8d Merge tag 'renesas-dt-bindings-for-v6.17-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
7a374a9fc8f9 arm64: dts: cavium: thunder2: Add missing PL011 "uartclk"
9b8b632ab773 arm64: dts: lg: Add missing PL011 "uartclk"
1840478bd82c arm64: dts: lg: Refactor common LG1312 and LG1313 parts
da6dbfcc7301 dt-bindings: soc: spacemit: define spacemit,k1-ccu resets
bb90348d29a9 dt-bindings: mmc: Add sdhci compatible for qcs8300
0414ba944436 spi: dt-bindings: Convert marvell,orion-spi to DT schema
a56bc205230f dt-bindings: mmc: loongson,ls2k0500-mmc: Add compatible for Loongson-2K2000
3cc034e85df9 dt-bindings: mmc: Add Loongson-2K SD/SDIO/eMMC controller binding
dcdc40b6d229 mips: dts: qca: add wmac support
c66d6090a834 MIPS: mobileye: dts: eyeq5: add the emmc controller
cec254c8523d MIPS: mobileye: dts: eyeq6h: add the emmc controller
611c15d5e513 dt-bindings: mmc: renesas,sdhi: Document RZ/T2H and RZ/N2H support
c824773bddb3 dt-bindings: reset: Convert snps,dw-reset to DT schema
86485ac1b19d dt-bindings: media: qcom,x1e80100-camss: Fix isp unit address
728f8edb14ff dt-bindings: media: qcom,x1e80100-camss: Remove clock-lanes port property
7a573d543274 dt-bindings: media: qcom,x1e80100-camss: Add optional bus-type property
775c0a28cdd1 dt-bindings: media: qcom,x1e80100-camss: Tighten the property regex pattern
e73fc4fe22c1 Merge tag 'ib-mfd-gpio-input-pwm-v6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd into gpio/for-next
2cdc59469372 dt-bindings: net: Convert socfpga-dwmac bindings to yaml
03396f2ec6d3 arm64: dts: renesas: Add CN15 eMMC and SD overlays for RZ/V2H and RZ/V2N EVKs
b581622620e9 arm64: dts: renesas: r8a779h2: Add Gray Hawk Single support
8c9f5b0429a2 arm64: dts: renesas: Add Renesas R8A779H2 SoC support
2b6093a18f87 arm64: dts: renesas: Factor out Gray Hawk Single board support
c8fc0b439820 dt-bindings: soc: renesas: Document R-Car V4M-7 Gray Hawk Single
ec22ed6659ed Merge tag 'renesas-r9a09g057-dt-binding-defs-tag4' into renesas-clk-for-v6.17
64c19295dba9 Merge tag 'renesas-r9a09g087-dt-binding-defs-tag2' into renesas-clk-for-v6.17
8fef4f6b3495 dt-bindings: clock: renesas,r9a09g077/87: Add SDHI_CLKHS clock ID
0f1bcc2d243a dt-bindings: clock: renesas,r9a09g056/57-cpg: Add XSPI core clock
4380d39a0bfd ARM: dts: sun8i: v3: Add RGB666 LCD PD pins definition
d4241e745089 ARM: dts: sun8i: v3s: Add RGB666 LCD PE pins definition
6b354c7e0cba mips: dts: realtek: Add gpio block
c0d0aedd3de9 mips: dts: realtek: Add watchdog
dae2bc5616a8 mips: dts: realtek: Add switch interrupts
38394a11dfec mips: dts: cameo-rtl9302c: Add switch block
e4d0f8f0b485 MIPS: dts: ralink: gardena_smart_gateway_mt7688: Fix power LED
53804508fc88 MIPS: dts: ralink: mt7628a: Update watchdog node according to bindings
96b1d8882b30 MIPS: dts: ralink: mt7628a: Fix sysc's compatible property for MT7688
3a5d39e27fb7 dt-bindings: clock: mediatek,mtmips-sysc: Adapt compatible for MT7688 boards
e2714b69d705 ASoC: dt-bindings: qcom,sm8250: Add QCS8275 sound card
93001f7dcb85 ARM: dts: imx6ul: support Engicam MicroGEA GTW board
9ea985f294fc ARM: dts: imx6ul: support Engicam MicroGEA RMM board
b0e34d5a967c ARM: dts: imx6ul: support Engicam MicroGEA BMM board
acf9f66533f6 ARM: dts: imx6ul: support Engicam MicroGEA-MX6UL SoM
d23e9ea1eaac dt-bindings: arm: fsl: support Engicam MicroGEA GTW board
e50303295b76 dt-bindings: arm: fsl: support Engicam MicroGEA RMM board
aec517ade0f4 dt-bindings: arm: fsl: support Engicam MicroGEA BMM board
98ba73c32158 dt-bindings: net: convert nxp,lpc1850-dwmac.txt to yaml format
0f4043ab479c iio: adc: ad7173: add SPI offload support
d7b8723e5cc9 dt-bindings: trigger-source: add ADI Util Sigma-Delta SPI
84d8f9c362fd dt-bindings: mfd: adp5585: document reset gpio
362f91ed9a71 dt-bindings: mfd: adp5585: add properties for input events
a8629f7b1c76 dt-bindings: mfd: adp5585: document adp5589 I/O expander
56126147cf7f dt-bindings: mfd: adp5585: ease on the required properties
e89612b694cf dt-bindings: input: touchscreen: edt-ft5x06: Document FT8716 support
fcb3290cc9aa dt-bindings: input: touchscreen: convert tsc2007.txt to yaml format
2aa354161f52 dt-bindings: dsp: fsl,dsp: document 'access-controllers' property
6e293da49ad9 dt-bindings: bus: document the IMX AIPSTZ bridge
56370e58513a arm64: dts: imx93-11x11-evk: remove the duplicated pinctrl_lpi2c3 node
b2cf0ac6473f arm64: dts: imx93-11x11-evk: reduce the driving strength of net RXC/TXC
1f8f5eb35b99 arm64: dts: imx93-11x11-evk: disable all realtek ethernet phy CLKOUT
3f439f3e0847 arm64: dts: imx93-qsb/evk: add usdhc3 and lpuart5
c288a6c72f58 arm64: dts: imx93: remove eee-broken-1000t for eqos node
28a0f520481d arm64: dts: imx93-9x9-qsb: add IMU sensor support
bdbdeea06674 arm64: dts: freescale: imx8mp-var-som: Add EQoS support with MaxLinear PHY
fef47da29940 arm64: dts: imx8qm: add system controller watchdog support
43a9c5204a71 arm64: dts: imx95-19x19-evk: add GPIO reset for ethphy0
cfbae9c05739 arm64: dts: imx95-19x19-evk: adjust pinctrl settings for usdhc2
2d2d317cda64 arm64: dts: imx95-evk: add USB3 PHY tuning properties
e2984acda327 arm64: dts: imx95-19x19-evk: add adc0 flexcan[1,2] i2c[2,3] uart5 spi3 and tpm3
1b516b64f709 arm64: dts: freescale: imx93-var-som: update eqos support for MaxLinear PHY
236b3b5fa844 arm64: dts: imx8mp-venice-gw74xx: update name of M2SKT_WDIS2# gpio
ee2949900e0f arm64: dts: freescale: imx93-tqma9352: add memory node
a8cfb47ba83a arm64: dts: freescale: imx93-phyboard-nash: Move ADC vref to SoM
b4ab5602f093 dt-bindings: arm: fsl: add i.MX28 Amarula rmm board
58732bd8328b ARM: dts: mxs: support i.MX28 Amarula rmm board
54dad17c1416 ARM: dts: imx28: add pwm7 muxing options
7826f7be97d7 dt-bindings: serial: mediatek,uart: add MT6572
a6870cdf2262 dt-bindings: interrupt-controller: Convert fsl,mpic-msi to YAML
a39baf2874e1 riscv: dts: thead: Add PVT node
59dcbcb5dbe8 riscv: dts: thead: th1520: Add GPU clkgen reset to AON node
b7064204c34a arm: dts: omap: Add support for BeagleBone Green Eco board
97e7316298d4 dt-bindings: omap: Add Seeed BeagleBone Green Eco
1fc23c040c64 arm: dts: omap: am335x-bone-common: Rename tps to generic pmic node
d6a683de0144 dt-bindings: display: panel: Make reset-gpio as optional for Raydium RM67200
c7b79f4c60ea dt-bindings: display: panel: Add Himax HX83112B
287b9ff3a30a dt-bindings: vendor-prefixes: document Shenzhen DJN Optronics Technology
5b00d9d7cef3 arm64: dts: rockchip: Enable eMMC HS200 mode on Radxa E20C
f493d4244fb4 arm64: dts: rockchip: Add bluetooth support to ArmSoM Sige7
2c6901d159a6 arm64: dts: rockchip: enable PCIe on ROCK 4D
c3fcd8d33101 arm64: dts: rockchip: Enable HDMI receiver on CM3588
c0c64cb2bea6 arm64: dts: rockchip: Add HDMI PHY PLL clock source to VOP2 on rk3576
271c1ecee280 arm64: dts: rockchip: Enable HDMI PHY clk provider on rk3576
b347f6353796 dt-bindings: display: vop2: Add optional PLL clock property for rk3576
0ec19b976d2f dt-bindings: media: imx258: inherit video-interface-devices properties
32656f2dd7f7 dt-bindings: media: ov8858: inherit video-interface-devices properties
0a479200fad0 media: dt-bindings: mt9m114: Add slew-rate DT-binding
afcd87416700 media: dt-bindings: sony,imx214: Deprecate property clock-frequency
8c02f74a820d media: dt-bindings: mipi-ccs: Refer to video-interface-devices.yaml
21dd16fda6ae arm64: dts: exynos: gs101: switch to gs101 specific reboot
692223514aae arm64: dts: exynos: gs101-pixel-common: add main PMIC node
92a8f685b654 arm64: dts: exynos: gs101: ufs: add dma-coherent property
221da32f58b1 Merge 6.16-rc4 into tty-next
c0f052a89615 arm64: dts: imx95: add SMMU support for NETC
b5ed179c47d0 arm64: dts: imx943-evk: Add PDM microphone sound card support
bd71324d2afc arm64: dts: imx943-evk: add bt-sco sound card support
e22973f9644c arm64: dts: imx943-evk: add sound-wm8962 support
ba65c43c3568 arm64: dts: imx943-evk: add i2c io expander support
2364aebb71bb arm64: dts: imx943-evk: add lpi2c support
0b36a8496df3 arm64: dts: imx94: Add micfil and mqs device nodes
47f22e04693c dt-bindings: serial: 8250: allow clock 'uartclk' and 'reg' for nxp,lpc1850-uart
bb6fa1f5823a dt-bindings: usb: genesys,gl850g: add downstream facing ports
fe67c5983537 dt-bindings: usb: genesys,gl850g: use usb-hub.yaml
9d866d360be9 dt-bindings: input: touchscreen: convert lpc32xx-tsc.txt to yaml format
d9e86831c9e7 ARM: dts: Fix up wrv54g device tree
c88d144e4ee0 dt-bindings: dsa: Rewrite Micrel KS8995 in schema
721733928299 dt-bindings: net: sun8i-emac: Add A100 EMAC compatible
26d787d538c0 dt-bindings: net/nfc: ti,trf7970a: Add ti,rx-gain-reduction-db option
c4e889a39fbe dt-bindings: net: convert lpc-eth.txt yaml format
9d619f67ea06 dt-bindings: reset: sophgo: Add CV1800B support
390a51a896e0 dt-bindings: reset: renesas,rzv2h-usb2phy: Document RZ/V2N SoC support
1ab195547189 dt-bindings: reset: convert nxp,lpc1850-rgu.txt to yaml format
74f427003123 dt-bindings: reset: add support for canaan,k230-rst
bdfa6cf09cc8 dt-bindings: leds: lp50xx: Document child reg, fix example
0481e0a9c242 arm64: dts: exynos: gs101: add dm-verity-device-corrupted syscon-reboot-mode
d358bcfbc85a arm64: dts: exynos: gs101-pixel-common: add nvmem-reboot-mode
3b48424bb12d arm64: dts: exynos: gs101-pixel-common: add Maxim MAX77759 PMIC
1067406bccda dt-bindings: net: Document support for Airoha AN7583 MDIO Controller
5d19097df3ab dt-bindings: memory-controller: Define fallback compatible
3a12dc8d7019 dt-bindings: interrupt-controller: Add arm,armv7m-nvic and fix #interrupt-cells
977be08b2098 dt-bindings: trivial-devices: add compatible string nxp,isp1301 from isp1301.txt
faae60a9136d dt-bindings: net: Rename renesas,r9a09g057-gbeth.yaml
acc53bb0cab4 Merge tag 'drm-misc-next-2025-06-26' of https://gitlab.freedesktop.org/drm/misc/kernel into drm-next
253782c324ed dt-bindings: phy: qcom,snps-eusb2-repeater: Remove default tuning values
0ba1a407aad6 dt-bindings: phy: apm,xgene-phy: Remove trailing whitespace
29f6bd159cad spi: dt-bindings: add nxp,lpc3220-spi.yaml
563a067ae378 dt-bindings: net: wireless: ath11k-pci: describe firmware-name property
3dafddbf2214 dt-bindings: net: wireless: ath9k: add WIFI bindings
5a46d78c27c7 arm64: dts: qcom: x1-asus-zenbook: support sound
4820d1a59ead arm64: dts: qcom: x1-asus-zenbook: fixup GPU nodes
17d54e8cff64 dt-bindings: iio: adc: ad7768-1: add trigger-sources property
f1a36c705c57 dt-bindings: iio: adc: ad7768-1: Document GPIO controller
6d62b06711b2 dt-bindings: iio: adc: ad7768-1: document regulator provider property
f94145ede4c6 dt-bindings: trigger-source: add generic GPIO trigger source
b5103f279f65 dt-bindings: iio: adc: add ad7405
72d91eb75105 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
4a0d83820fdf arm64: dts: renesas: r9a09g047: Add GBETH nodes
3485db855114 arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Rename fixed regulator node names
66a9960e5871 arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Add RAA215300 PMIC
062f9e2c026a arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Add RAA215300 PMIC
3cfe736f1e40 dt-bindings: interrupt-controller: Add MIPS P8700 aclint-sswi
3cd935575bee dt-bindings: net: ti: k3-am654-cpsw-nuss: update phy-mode in example
669d2c02c393 dt-bindings: display: ti: Add schema for AM625 OLDI Transmitter
7b4c77851db5 dt-bindings: display: ti,am65x-dss: Re-indent the example
7fe4a35ce8ca arm64: dts: ti: k3-j784s4-j742s2-main-common: Add ACSPCIE1 node
c6a9ae83e762 arm64: dts: ti: k3-j722s-evm: Fix USB gpio-hog level for Type-C
a0ad301286a9 arm64: dts: qcom: sm6115: add debug UART pins
2c030b5460a9 dt-bindings: trivial-devices: Add Analog Devices ADT7411
34cb86fcdff2 Add few updates to the STM32 SPI driver
d16f0509fbae ARM: dts: microchip: sam9x7: Add LVDS controller
dc59315540b6 ASoC: Standardize ASoC menu
717b4dc30bb3 arm64: dts: exynos5433: Align i2c-gpio node names with dtschema
0d47606fb8d9 ARM: dts: s5pv210: Align i2c-gpio node names with dtschema
ae5dcb68953b ARM: dts: exynos: Align i2c-gpio node names with dtschema
fc41e79c8d7c dt-bindings: reset: sun55i-a523-r-ccu: Add missing PPU0 reset
97166fd1f53d dt-bindings: firmware: thead,th1520: Add resets for GPU clkgen
9c5a0a7d84d4 dt-bindings: net: cdns,macb: add sama7d65 ethernet interface
989c7d86c01f spi: dt-bindings: stm32: deprecate `st,spi-midi-ns` property
65f0c52f9155 spi: dt-bindings: stm32: update bindings with SPI Rx DMA-MDMA chaining
3b18f58612bb dt-bindings: usb: dwc2: rename sophgo usb compatible string
37b9182375b9 dt-bindings: gnss: u-blox: add u-blox,neo-9m compatible
aeb89b24ad7e dt-bindings: mmc: cdns: add Mobileye EyeQ MMC/SDHCI controller
eb7dca9a7276 dt-bindings: mmc: mxs-mmc: change ref to mmc-controller-common.yaml from mmc-controller.yaml
d3ef944175aa dt-bindings: pse: tps23881: Clarify channels property description
54965f2a3351 dt-bindings: soc: renesas: Document RZ/T2H Evaluation Board part number
4e1c8311bf0d ARM: dts: microchip: sama5d2_icp: rename spi-cs-setup-ns property to spi-cs-setup-delay-ns
f6e4727e66e0 ARM: dts: microchip: sama5d27_wlsom1: rename spi-cs-setup-ns property to spi-cs-setup-delay-ns
1025e2432dc1 ARM: dts: microchip: sama5d27_som1: rename spi-cs-setup-ns property to spi-cs-setup-delay-ns
346177955338 ARM: dts: microchip: sam9x60ek: rename spi-cs-setup-ns property to spi-cs-setup-delay-ns
040ecf520251 dt-bindings: net: convert qca,qca7000.txt yaml format
da41efa1472c Revert "ARM: dts: Update pcie ranges for dra7"
86e3aa4733ed ARM: dts: omap: am335x: Use non-deprecated rts-gpios
dcc259a92bf1 spi: microchip-core-qspi: Add regular transfers
689d9094a731 dt-bindings: net: qca,ar803x: Add IPQ5018 Internal GE PHY support
795bfa427a40 regulator: dvfsrc: Add support for MT8196 and
0c92dc5fb726 dt-bindings: regulator: mediatek-dvfsrc: Add MT8196 support
40062b24de96 dt-bindings: regulator: mediatek-dvfsrc: Add MT6893 support
3ea17e80490b dt-bindings: PCI: brcm,stb-pcie: Add num-lanes property
1a3a8073faf0 dt-bindings: PCI: qcom,pcie-sm8150: Drop unrelated clocks from PCIe hosts
ead3a65c4352 dt-bindings: PCI: qcom,pcie-sc8180x: Drop unrelated clocks from PCIe hosts
23ba48ce4f3d dt-bindings: crypto: Convert ti,omap4-des to DT schema
f3dc660ef7dd dt-bindings: crypto: Convert ti,omap2-aes to DT schema
b339218b8279 dt-bindings: rng: atmel,at91-trng: add sama7d65 TRNG
ff643bb28541 dt-bindings: crypto: add sama7d65 in Atmel TDES
0f0c72dc98dc dt-bindings: crypto: add sama7d65 in Atmel SHA
8462bd595120 dt-bindings: crypto: add sama7d65 in Atmel AES
76b9ac22e92f dt-bindings: crypto: fsl,sec-v4.0: Add power domains for iMX8QM and iMX8QXP
8639cd6d493b powerpc/microwatt: Correct ISA version number in device tree
5a69b5d0f9d4 ARM: dts: at91-sama5d27_wlsom1: Improve the Wifi compatible
b38f516e544a ARM: dts: microchip: gardena-smart-gateway: Fix power LED
a7efef227924 ARM: dts: microchip: sam9x7: Add clock name property
0c5aec276273 ARM: dts: microchip: sama7d65: Add clock name property
6fe4b2852827 ARM: dts: microchip: sama7g5: Adjust clock xtal phandle
3f1852d5065d ARM: dts: microchip: sam9x7: Add HLCD controller
5e5f78f26a1c ARM: dts: microchip: sama7d65: Enable CAN bus
9f891644a466 ARM: dts: microchip: sama7d65: Clean up extra space
e458631c8156 ARM: dts: microchip: sama7d65: Add CAN bus support
a2d173f4f06a ARM: dts: microchip: sama7d65: Add PWM support
e8cb36704dcf ARM: dts: microchip: sama7d65: Add crypto support
fad2776b7baf ARM: dts: microchip: use recent scl/sda gpio bindings
cfa530559e94 dt-bindings: power: supply: Drop redundant monitored-battery ref
4a278ae395fb dt-bindings: power: supply: summit,smb347: Add missing power-supply ref
1b193da31601 dt-bindings: power: supply: richtek,rt5033: Add missing power-supply ref
5b64ac18febc dt-bindings: power: supply: qcom,pmi8998: Add missing power-supply ref
f09e89e71f18 dt-bindings: power: supply: bq256xx: Add missing power-supply ref
561c50eeff1b dt-bindings: power: supply: bq2515x: Add missing power-supply ref
1c2a6f716763 arm64: dts: rockchip: add DTs for Firefly ROC-RK3588S-PC
6e8c6721786a dt-bindings: arm: rockchip: Add Firefly ROC-RK3588S-PC
d788cdf18afe arm64: dts: rockchip: Enable GPU on Radxa E20C
16d867f13e38 arm64: dts: rockchip: Add GPU node for RK3528
c3a10091d51d arm64: dts: ti: k3-am642-evm-pcie0-ep: Add boot phase tag to "pcie0_ep"
a2ef24e102ed arm64: dts: ti: k3-j722s-main: Add audio-refclk0 node
1d53c6646d99 arm64: dts: ti: k3-am62p-j722s: fix pinctrl-single size
307b8ee66245 arm64: dts: ti: k3-am62a7-sk: Describe the SPI NAND
e0da88bbe5dc arm64: dts: ti: k3-j721s2-main: Add McASP nodes
f72c8b39a660 arm64: dts: ti: k3-am62p-verdin: Enable pull-ups on I2C_3_HDMI
4228071de8ea arm64: dts: ti: k3-am62-verdin: Enable pull-ups on I2C buses
9f3a0581be0a arm64: dts: ti: k3-am642-phyboard-electra: Fix PRU-ICSSG Ethernet ports
0067f17cbb71 arm64: dts: mediatek: mt8370: Enable gpu support
fd8a8a611df3 dt-bindings: gpu: mali-bifrost: Add compatible for MT8370 SoC
8a87dd54887f media: dt-bindings: nxp,imx8-jpeg: Add compatible strings for IMX95 JPEG
a811534390f1 dt-bindings: media: convert fsl-vdoa.txt to yaml format
7c1831c97562 arm64: dts: rockchip: support camera module on Haikou Video Demo on PX30 Ringneck
e65d94e8c6e4 arm64: dts: rockchip: add label to first port of ISP on px30
49bd59bda613 arm64: dts: rockchip: fix endpoint dtc warning for PX30 ISP
8f0855aaa6a1 dt-bindings: dma: qcom,gpi: Document the sc8280xp GPI DMA engine
de8e8cacccbf arm64: dts: s32g: add RTC node
2eff8e3eb821 arm64: dts: Add DSPI entries for S32G platforms
527d37438b73 arm64: dts: freescale: imx93-phyboard-segin: Set ethernet1 alias
e9c4ed1380e5 arm64: dts: freescale: imx93-phycore-som: Move ethernet0 alias to SoM
19fc892ae830 arm64: dts: tqma8mpql: Add EASRC support
10d58add28d4 arm64: dts: tqma8mnql: Add EASRC support
9684884f9cc2 arm64: dts: freescale: Add the BOE av123z7m-n17 variant of the Moduline Display
36d39a81979d arm64: dts: freescale: Add the BOE av101hdt-a10 variant of the Moduline Display
0ab9cec49c0a arm64: dts: freescale: Add the GOcontroll Moduline Display baseboard
96478662ba59 arm64: dts: freescale: add Ka-Ro Electronics tx8p-ml81 COM
a54ff893e9e6 arm64: dts: imx8mp: Add pinctrl config definitions
b0356e47aa51 arm64: dts: rockchip: Add power controller for RK3528
fa630610e626 arm64: dts: rockchip: enable USB on Sige5
32d30cc2bfc3 arm64: dts: rockchip: add overlay for the WiFi/BT module on Sige5 v1.2
c7f61653a73d arm64: dts: rockchip: add version-independent WiFi/BT nodes on Sige5
d5edb6dfb78c arm64: dts: rockchip: add SDIO controller on RK3576
a22bac5ead32 arm64: dts: rockchip: Enable gpu on rk3576-evb1-v10
4e9c9ee05c23 dt-bindings: clock: convert lpc1850-ccu.txt to yaml format
5dab6d0666f8 arm64: dts: rockchip: Update the PinePhone Pro panel description
eaa75b56dcfb Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
64842d8e059f Merge tag 'renesas-r9a09g087-dt-binding-defs-tag1' into renesas-clk-for-v6.17
07f1f3844c5d Merge tag 'renesas-r9a09g077-dt-binding-defs-tag2' into renesas-clk-for-v6.17
e0ebadb2045d dt-bindings: clock: renesas,cpg-mssr: Document RZ/N2H support
949d0cfc7c44 dt-bindings: soc: renesas: Document RZ/N2H (R9A09G087) SoC
51071ab402e3 dt-bindings: clock: renesas,r9a09g077: Add PCLKL core clock ID
3ec018584fa1 arm64: dts: renesas: rcar-gen3: Add bootph-all to sysinfo EEPROMs
fc5f0def788b arm64: dts: renesas: sparrow-hawk: Describe split PCIe clock
3a8905aac211 arm64: dts: renesas: r8a779g0: Describe PCIe root ports
6887bc8543b4 arm64: dts: renesas: ebisu: Add CAN0 support
fd8b44404cb0 ARM: dts: renesas: r9a06g032: Add second clock input to RTC
2371c2df77ea arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Enable USB2.0 support
b1400fa1ae46 arm64: dts: renesas: r9a09g056: Add USB2.0 support
1e6055b1bfba arm64: dts: renesas: r8a779g3-sparrow-hawk: Sort DTS
e46668c89ed4 ARM: dts: renesas: r9a06g032-rzn1d400-db: Describe debug LEDs
b65d84ca5033 arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable USB2.0 support
5105a55fda27 dt-bindings: serial: renesas,rsci: Document RZ/N2H support
717942ab9fdf dt-bindings: usb: renesas,usbhs: Add RZ/V2N SoC support
51e5237dc82f ARM: dts: vf: vf610-zii-cfu1: rename node name *-gpio to *-gpios
39b627463c2b ARM: dts: vf: vf-colibri-eval-v3: add power-supply for edt,et057090dhu
fd302676921b ARM: dts: vf: rename io-expander@20 to pinctrl@20
9bea7c6d261c ARM: dts: vf: remove redundant layer under iomux
e139807952b1 ARM: dts: vf: remove redundant pinctrl-names
d2e638640e96 ARM: dts: vf: remove reg property for arm pmu
8f8e41560419 ARM: dts: vfxxx: Correctly use two tuples for timer address
f98b63e7e4d4 dt-bindings: arm: fsl: Add GOcontroll Moduline Display
2c61daf98d93 arm64: dts: add ngpios for vf610 compatible gpio controllers
063fd6175ada ARM: dts: add ngpios for vf610 compatible gpio controllers
19c622072a55 dt-bindings: net: pse-pd: ti,tps23881: Add interrupt description
a956323691dc dt-bindings: net: pse-pd: microchip,pd692x0: Add manager regulator supply
49faac7c9fd8 dt-bindings: clock: Convert alphascale,asm9260-clock-controller to DT schema
2d92d14e9eef dt-bindings: clock: Convert marvell,armada-370-corediv-clock to DT schema
d2ce3c47d404 dt-bindings: clock: Convert marvell,armada-3700-periph-clock to DT schema
e37e069f8b0f dt-bindings: clock: Convert marvell,mvebu-core-clock to DT schema
9cf6d0ba0fdf dt-bindings: clock: Convert marvell,berlin2-clk to DT schema
bb06131b2ecc dt-bindings: clock: Convert marvell,dove-divider-clock to DT schema
1fd176774ea2 dt-bindings: clock: Convert marvell,armada-3700-tbg-clock to DT schema
a06036f72ced dt-bindings: clock: Convert marvell-armada-370-gating-clock to DT schema
45f94b0de650 dt-bindings: clock: Convert marvell,armada-xp-cpu-clock to DT schema
5a9f538c0e6b dt-bindings: clock: Convert TI-NSPIRE clocks to DT schema
5a62a028d23b dt-bindings: clock: Convert lsi,axm5516-clks to DT schema
bb7d222956f9 dt-bindings: clock: Convert img,pistachio-clk to DT schema
763873a48189 dt-bindings: clock: Convert brcm,bcm2835-cprman to DT schema
cee9659816b4 dt-bindings: clock: Convert cirrus,ep7209-clk to DT schema
f10c6670b7e2 dt-bindings: clock: Convert APM XGene clocks to DT schema
bff50be25ecd dt-bindings: clock: Convert axis,artpec6-clkctrl to DT schema
7debe9917c80 dt-bindings: clock: Convert brcm,bcm53573-ilp to DT schema
37248ce61324 Merge branch '20250610-qcom_ipq5424_cmnpll-v3-1-ceada8165645@quicinc.com' into clk-for-6.17
945db09189dc dt-bindings: clock: qcom: Add CMN PLL support for IPQ5424 SoC
71f2de4a034f arm64: dts: qcom: sm8650: add iris DT node
d496cf29098a arm64: dts: qcom: msm8976-longcheer-l9360: Add initial device tree
ab1f53f63414 arm64: dts: qcom: msm8976: Add sdc2 GPIOs
b003f5c6b91d dt-bindings: arm: qcom: Add MSM8976 BQ Aquaris X5 Plus
a260177d0411 arm64: dts: qcom: msm8976: Make blsp_dma controlled-remotely
6de07b6f15ca ASoC: dt-bindings: cirrus,cs42xx8: add 'port' property
fb3447bb3b35 arm64: dts: qcom: sa8775p: Correct the interrupt for remoteproc
3058275a342c dt-bindings: rockchip: pmu: Add compatible for RK3528
50db66235f2b dt-bindings: power: rockchip: Add support for RK3528
33ceeabccc61 dt-bindings: pinctrl: eswin: Document for EIC7700 SoC
64e88c0fed96 arm64: dts: exynos: gs101: Add 'local-timer-stop' to cpuidle nodes
b10142d10119 dt-bindings: gpio: arm,pl061: Drop interrupt properties as required
469d40ff1fc6 arm64: dts: exynosautov920: Add DT node for all SPI ports
d6e199e49db3 dt-bindings: pinctrl: stm32: Add RSVD mux function
fcd55a37ae62 dt-bindings: mtd: convert nxp-spifi.txt to yaml format
b88ae50b4a3f media: dt-bindings: nxp,imx8mq-mipi-csi2: Add i.MX8QM(QXP) compatible strings
5ea6161f602d media: dt-bindings: Add binding doc for i.MX8QXP and i.MX8QM ISI
12f918ab5174 arm64: dts: qcom: sm8550: Add support for camss
3b8507884db9 arm64: dts: qcom: qcs615: disable the CTI device of the camera block
f605900d6de0 arm64: dts: qcom: qcs615-ride: enable remoteprocs
8093aa08d5a7 arm64: dts: qcom: qcs615: add ADSP and CDSP nodes
cff0cbfd4ffc arm64: dts: qcom: qcs615: Add IMEM and PIL info region
1454cb2395b1 arm64: dts: qcom: qcs615: Add mproc node for SEMP2P
d41393450043 arm64: dts: qcom: Add support for X1-based Asus Zenbook A14
455400158e35 arm64: dts: qcom: sc7180: Expand IMEM region
b73a5a409b33 arm64: dts: qcom: sdm845: Expand IMEM region
ed819d4948e0 dt-bindings: sram: qcom,imem: Add a number of missing compatibles
46d41941b590 arm64: dts: qcom: qcs615: fix a crash issue caused by infinite loop for Coresight
bcd405d4605c arm64: dts: qcom: sm6350: add APR and some audio-related services
cf84790a7bc1 arm64: dts: qcom: qcm2290: Add CAMSS node
71de0b13f5f4 arm64: dts: qcom: sa8775p-ride: enable video
f3c905ddb143 arm64: dts: qcom: sa8775p: add support for video node
2ea4d1a862e7 arm64: dts: qcom: sa8775p: Add CPU OPP tables to scale DDR/L3
f57f90da02fd arm64: dts: qcom: sa8775p: add EPSS l3 interconnect provider
484acd85064e arm64: dts: qcom: sm8750: Add UFS nodes for SM8750 QRD board
08d016ce62b5 arm64: dts: qcom: sm8750: Add UFS nodes for SM8750 MTP
21f3bb719d06 arm64: dts: qcom: sm8750: Add UFS nodes for SM8750 SoC
a4f170b96c2b arm64: dts: qcom: apq8016-sbc-d3-camera: Convert to DT overlay
96ffdf9514de arm64: dts: qcom: x1e80100-dell-xps-9345: Add WiFi/BT pwrseq
81e24b484d8f Merge tag 'drm-misc-next-2025-06-12' of https://gitlab.freedesktop.org/drm/misc/kernel into drm-next
7c6c4e986b5e dt-bindings: arm: cpus: Add Kryo 470 CPUs
c3e977592183 dt-bindings: sram: qcom,imem: Add the SM7150 compatible
ff4ba6b971ae dt-bindings: soc: qcom: aoss-qmp: Add the SM7150 compatible
3b86b00b2868 dt-bindings: soc: qcom,dcc: Add the SM7150 compatible
47cee050ea05 dt-bindings: soc: qcom: add qcom,qcs615-imem compatible
73bee717137b dt-bindings: PCI: pci-ep: Extend max-link-speed to PCIe Gen5/Gen6
6ad7e7635ff2 dt-bindings: PCI: qcom,pcie-sa8775p: Document QCS8300
fe9760407d9e dt-bindings: PCI: qcom,pcie-sm8150: Document QCS615
279926cf824c arm64: dts: qcom: Add QMP handle for qcom_stats
33b6b81327b2 arm64: dts: qcom: qrb5165-rb5-vision-mezzanine: remove camcc status property
4dcdeb9e373b arm64: dts: qcom: sm8250: enable camcc clock controller by default
986337f7125b dt-bindings: remoteproc: qcom,sa8775p-pas: Correct the interrupt number
87d25536e261 dt-bindings: gpio: gpio-xilinx: Mark clocks as required property
7d9619784d4c dt-bindings: dmaengine: Add dma multiplexer for CV18XX/SG200X series SoC
949eaeb96a7b dt-bindings: clock: Add RaspberryPi RP1 clock bindings
d37ab6d3737b media: dt-bindings: media: renesas,vsp1: Document RZ/V2N SoC
c999498941a3 media: dt-bindings: media: renesas,fcp: Document RZ/V2N SoC
17e3b9892493 dt-bindings: phy: Add the M31 based eUSB2 PHY bindings
bc371e92d06e dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: Add SM8750 to QMP PHY
335d8d9ff6e9 dt-bindings: phy: renesas,usb2-phy: Document RZ/V2N SoC support
b6272058c2ee dt-bindings: phy: Convert Marvell MVEBU PHYs to DT schema
3e6965af3886 dt-bindings: phy: Convert marvell,armada-380-comphy to DT schema
87f3979709df dt-bindings: phy: Convert ti,keystone-usbphy to DT schema
09d69b51d927 dt-bindings: phy: Convert ti,dm816x-usb-phy to DT schema
844acf2c998f dt-bindings: phy: Convert st,spear1310-miphy to DT schema
4bce5936846a dt-bindings: phy: Convert qca,ar7100-usb-phy to DT schema
ac5ef382d934 dt-bindings: phy: Convert motorola,mapphone-mdm6600 to DT schema
85e480d5fc84 dt-bindings: phy: Convert motorola,cpcap-usb-phy to DT schema
fe17837b8d9b dt-bindings: phy: Convert marvell,mmp2-usb-phy to DT schema
b126307f27dc dt-bindings: phy: Convert marvell,comphy-cp110 to DT schema
9bcbff3bd9d7 dt-bindings: phy: Convert marvell,berlin2-usb-phy to DT schema
0c82a7e3b08d dt-bindings: phy: Convert marvell,berlin2-sata-phy to DT schema
dc17572110df dt-bindings: phy: Convert lantiq,ase-usb2-phy to DT schema
b10685a3371a dt-bindings: phy: Convert img,pistachio-usb-phy to DT schema
408705e5a1ad dt-bindings: phy: Convert hisilicon,inno-usb2-phy to DT schema
727e67e12857 dt-bindings: phy: Convert hisilicon,hi6220-usb-phy to DT schema
1723ae98c198 dt-bindings: phy: Convert hisilicon,hix5hd2-sata-phy to DT schema
1dc8e1978b35 dt-bindings: phy: Convert brcm,sr-pcie-phy to DT schema
7cff50883378 dt-bindings: phy: Convert brcm,ns2-drd-phy to DT schema
93a177a9b1e9 dt-bindings: phy: Convert apm,xgene-phy to DT schema
55252481b031 dt-bindings: phy: samsung,mipi-video-phy: document exynos7870 MIPI phy
2b521ba242d3 dt-bindings: phy: samsung,usb3-drd-phy: Add exynos990 compatible
249194d3dfb7 dt-bindings: pci: Add Sophgo SG2044 PCIe host
88df97c059e6 arm64: dts: freescale: imx93-tqma9352: Remove unneeded GPIO hog
a73858b8f497 arm64: dts: freescale: imx93-tqma9352: Limit BUCK2 to 600mV
74609a3fb4f4 dt-bindings: net: renesas-gbeth: Add support for RZ/G3E (R9A09G047) SoC
ecbe9ffa03ea ARM: dts: imx7s-warp: Improve the Wifi description
b3cead4032a5 ARM: dts: imx7s-warp: Improve the Bluetooth description
d826170f23a8 arm64: dts: exynosautov920: add CMU_HSI2 clock DT nodes
892f6f8d54b1 dt-bindings: clock: exynosautov920: add hsi2 clock definitions
fc73efed87ea dt-bindings: clock: exynosautov920: sort clock definitions
a698889e0340 ARM: dts: vt8500: Add L2 cache controller on WM8850/WM8950
cc0cd2f62fba ARM: dts: vt8500: Fix the unit address of the VT8500 LCD controller
ba6b8fbd8f10 ARM: dts: vt8500: Use generic node name for the SD/MMC controller
4c2bee5a57aa ARM: dts: vt8500: Move memory nodes to board dts and fix addr/size
618840988c7d ARM: dts: vt8500: Add node address and reg in CPU nodes
638f4396159a arm64: dts: exynos: add initial support for Samsung Galaxy S22+
cda58ddae028 arm64: dts: exynos: add initial support for exynos2200 SoC
ba78ccfb85f1 dt-bindings: arm: samsung: document g0s board binding
928cf7b4db3d ASoC: dt-bindings: mt8192-afe-pcm: Allow specifying reserved memory region
7f82922e67a2 ASoC: dt-bindings: mt8186-afe-pcm: Allow specifying reserved memory region
7b4cfbf9cb43 ASoC: dt-bindings: mt8173-afe-pcm: Allow specifying reserved memory region
76cd57f4055e ASoC: dt-bindings: mt8173-afe-pcm: Add power domain
e8ba4d8d36e5 ASoC: dt-bindings: Convert MT8173 AFE binding to dt-schema
f9ab470b7216 ARM: dts: qcom: msm8974-sony-xperia-rhine: Add alias for mmc0 & mmc1
9a441a5e784a ARM: dts: qcom: msm8974-hammerhead: Add alias for mmc0
ab2a3af6930a ARM: dts: qcom: msm8974-oneplus-bacon: Add alias for mmc0
13bab98ae230 ARM: dts: qcom: Add initial support for Sony Xperia Z Ultra (togari)
830c3bb76487 dt-bindings: arm: qcom: Add Sony Xperia Z Ultra (togari)
65ca47d47e86 ARM: dts: qcom: msm8974-sony-xperia-rhine: Move camera buttons to amami & honami
658cf0eaccff ARM: dts: qcom: msm8974-sony-xperia-rhine: Enable USB charging
23712e8754a3 arm64: dts: qcom: x1p42100: Fix thermal sensor configuration
aa97b937223a arm64: dts: qcom: sm8650: remove unused reg
822ac62b57ee arm64: dts: qcom: sm8750-qrd: Add sound (speakers, headset codec, dmics)
6a7ae2443826 arm64: dts: qcom: sm8750-mtp: Add sound (speakers, headset codec, dmics)
6f4d1bf469a1 arm64: dts: qcom: sm8750: Add Soundwire nodes
dd1d6dea4bb1 arm64: dts: qcom: x1e80100-hp-x14: amend order of nodes
9eeffdf93012 arm64: dts: qcom: x1e80100-hp-x14: remove unused i2c buses
87e775221157 arm64: dts: qcom: x1e80100-hp-x14: add usb-1-ss1-sbu-mux
22c3ee0b6723 dt-bindings: clock: Convert brcm,bcm63xx-clocks to DT schema
5959214b449a dt-bindings: clock: ti: add ti,autoidle.yaml reference
be74285c8495 dt-bindings: clock: ti: Convert fixed-factor-clock to yaml
795aeb632bcf dt-bindings: clock: ti: Convert autoidle binding to yaml
81cf11f33bdc ARM: dts: qcom: msm8960: use macros for interrupts
b8acdc312e48 spi: dt-bindings: mediatek,spi-mt65xx: Add support for MT6991/MT8196 SPI
b27e030826ed arm64: dts: mediatek: mt8395-genio-1200-evk: Enable Audio DSP and sound card
f1bdce636304 arm64: dts: mediatek: mt8192-asurada: Reserve memory for audio frontend
4c6cbd4937e7 arm64: dts: mediatek: mt8186-corsola: Reserve memory for audio frontend
0bbc5f383e6f arm64: dts: mediatek: mt8183-kukui: Reserve memory for audio frontend
459a4687b473 arm64: dts: mediatek: mt8173: Reserve memory for audio frontend
bcfa2c4f812f arm64: dts: imx8mp: Enable gpu passive throttling
4bee3e87ff2b arm64: dts: imx95: correct i3c node in imx95
f4253a424db7 Merge drm/drm-next into drm-misc-next
67be89b70d90 ARM: dts: aspeed: Add device tree for Nvidia's GB200NVL BMC
b38511e07580 dt-bindings: arm: aspeed: add Nvidia's GB200NVL BMC
c9ef33bddfd0 ARM: dts: aspeed: catalina: Enable MCTP support for NIC management
5bea70972e95 ARM: dts: aspeed: catalina: Update CBC FRU EEPROM I2C bus and address
5340d8724879 ARM: dts: aspeed: catalina: Enable multi-master on additional I2C buses
917b91ebae04 ARM: dts: aspeed: catalina: Remove INA238 and INA230 nodes
0872eae37927 ARM: dts: aspeed: catalina: Add second source HSC node support
30621d6376f4 ARM: dts: aspeed: catalina: Add second source fan controller support
23a5060692bc ARM: dts: aspeed: catalina: Add fan controller support
c9680d1b9907 ARM: dts: aspeed: catalina: Add MP5990 power sensor node
43d4786d6d8d ARM: dts: aspeed: catalina: Add Front IO board remote thermal sensor
084d47454493 ARM: dts: aspeed: catalina: Add IO Mezz board thermal sensor nodes
5038976dd89a ARM: dts: aspeed: system1: Disable gpio pull down
a50225982fba ARM: dts: aspeed: system1: Mark GPIO line high/low
50fd31ea857a ARM: dts: aspeed: system1: Remove VRs max8952
907d0214bef2 ARM: dts: aspeed: system1: Update LED gpio name
7a218d1c5197 ARM: dts: aspeed: system1: Reduce sgpio speed
9d816c14e2c1 ARM: dts: aspeed: system1: Add GPIO line name
b78c314eda75 ARM: dts: aspeed: system1: Add IPMB device
4dbb7162e72d dt-bindings: ipmi: Add binding for IPMB device
58cf50957126 ARM: dts: aspeed: bletchley: remove unused ethernet-phy node
e2d77b735d13 ARM: dts: aspeed: Align GPIO hog name with bindings
7827afbe3914 ARM: dts: aspeed: Remove swift machine
a888a5efe1c2 dt-bindings: remoteproc: qcom,sm8150-pas: Document QCS615 remoteproc
69d13fabcaaf arm64: dts: qcom: Add camera clock controller for sc8180x
a9d6cb6c0fbe Merge branch '20250512-sc8180x-camcc-support-v4-2-8fb1d3265f52@quicinc.com' into arm64-for-6.17
531ad909582b Merge branch '20250512-sc8180x-camcc-support-v4-2-8fb1d3265f52@quicinc.com' into clk-for-6.17
db7047b5c166 dt-bindings: clock: Add Qualcomm SC8180X Camera clock controller
85694e07d677 dt-bindings: clock: qcom: Add missing bindings on gcc-sc8180x
0b4116099b60 arm64: dts: qcom: sm6350: Add video clock controller
c685c753be9d arm64: dts: qcom: qcs8300-ride: enable video
b80f475be983 arm64: dts: qcom: qcs8300: add video node
e08e7b76aa1e dt-bindings: clock: qcom,sm8450-camcc: Move sc8280xp camcc to sa8775p camcc
4d05467482c8 dt-bindings: clock: qcom,sm8450-camcc: Allow to specify two power domains
895f435e10e9 dt-bindings: clock: qcom,sm8450-videocc: Add MXC power domain
bc791dcd8483 arm64: dts: qcom: sa8775p-ride: add anx7625 DSI to DP bridge nodes
4098c5a2bf59 arm64: dts: qcom: sa8775p: add Display Serial Interface device nodes
0e31d061c9c0 arm64: dts: broadcom: northstar2: Drop GIC V2M "interrupt-parent"
ea1885c9fd30 arm64: dts: qcom: x1e80100: Add missing 'global' PCIe interrupt
14ad59d4559f arm64: dts: qcom: sar2130p: Add 'global' PCIe interrupt
0a47f45ad43a arm64: dts: qcom: sc8180x: Add 'global' PCIe interrupt
94ff2d21c06d arm64: dts: qcom: ipq6018: Add missing MSI and 'global' IRQs
420964cc89e0 arm64: dts: qcom: ipq8074: Add missing MSI and 'global' IRQs
6d1521f0fc17 arm64: dts: qcom: msm8998: Add missing MSI and 'global' IRQs
9da0fdcbce25 arm64: dts: qcom: msm8996: Add missing MSI SPI interrupts
275a1383fcdf arm64: dts: qcom: sdm845: Add missing MSI and 'global' IRQs
22e63cea7b60 arm64: dts: qcom: sc7280: Add 'global' PCIe interrupt
28bef8454e3d arm64: dts: qcom: sa8775p: Add 'global' PCIe interrupt
c18c33f1c365 arm64: dts: qcom: sm8350: Add 'global' PCIe interrupt
30dd461fe360 arm64: dts: qcom: sm8250: Add 'global' PCIe interrupt
5c8dac48ba74 arm64: dts: qcom: sm8150: Add 'global' PCIe interrupt
bb38e4d566a8 ARM: dts: qcom: Align wifi node name with bindings
0b05f902b191 dt-bindings: pinctrl: rockchip: increase max amount of device functions
e09ea8c6b2f4 dt-bindings: ili9881c: Document 7" Raspberry Pi 720x1280
d8786b38477d dt-bindings: pinctl: amlogic,pinctrl-a4: Add compatible string for S7/S7D/S6
ac3bc668fd07 dt-bindings: display: st7701: Add Winstar wf40eswaa6mnn0 panel
998a197154ea dt-bindings: display: visionox-rm69299: document new compatible string
8f0d68ed872a arm64: dts: rockchip: convert rk3562 to their dt-binding constants
509e0c2fabe8 arm64: dts: rockchip: Add Luckfox Omni3576 Board support
28cf288916a0 dt-bindings: arm: rockchip: Add Luckfox Omni3576 and Core3576 bindings
9c61e9d15269 dt-bindings: vendor-prefixes: Add luckfox prefix
2ab598cbc1ba arm64: dts: rockchip: Remove workaround that prevented Turing RK1 GPU power regulator control
68888e37d9fb arm64: dts: rockchip: add overlay for RockPro64 screen
f1ab980e061c Revert "dt-bindings: clock: renesas,rzg2l-cpg: Update #power-domain-cells = <1> for RZ/G3S"
d5b5838ba286 dt-bindings: clock: rzg2l: Drop power domain IDs
eb2482bd3a71 Merge tag 'renesas-r9a09g077-dt-binding-defs-tag' into renesas-clk-for-v6.17
c80e0b36f0b1 dt-bindings: memory-controllers: convert arm,pl172.txt to yaml format
6cf75590b12d dt-bindings: soc: samsung: exynos-pmu: Constrain google,pmu-intr-gen-syscon
9505fc5dd862 dt-bindings: gpio: convert nxp,lpc1850-gpio.txt to yaml format
54fb0929cc99 dt-bindings: gpio: convert gpio-74xx-mmio.txt to yaml format
a3e905523cd5 dt-bindings: gpio: convert gpio-pisosr.txt to yaml format
1040128bb18a arm64: dts: renesas: r9a09g057: Add USB2.0 support
a2a9c525081e arm64: dts: renesas: r9a09g047e57-smarc: Enable CRU, CSI support
21b5186a7f3e arm64: dts: renesas: renesas-smarc2: Enable I2C0 node
313bfdd58194 arm64: dts: renesas: r9a09g047e57-smarc: Add I2C0 pincontrol
c4a0b4786c56 arm64: dts: renesas: r9a09g047: Add CRU, CSI2 nodes
942d44d91446 arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Enable Mali-G31 GPU
df4a18da3850 arm64: dts: renesas: r9a09g056: Add Mali-G31 GPU node
97126d793150 arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Enable WDT1
aa49b82d292a arm64: dts: renesas: r9a09g056: Add WDT0-WDT3 nodes
0fd2a920a15b arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Enable RIIC controllers
a9e1b1c51a2e arm64: dts: renesas: r9a09g056: Add RIIC controllers
8620f503d15b arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Enable OSTM timers on RZ/V2N EVK
7edd14aa50b6 arm64: dts: renesas: r9a09g056: Add OSTM0-OSTM7 nodes
694ebe54d549 arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Enable GBETH
4b6db87a7c10 arm64: dts: renesas: r9a09g056: Add GBETH nodes
46869466a047 arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable GBETH
7fd2951fbfb5 arm64: dts: renesas: r9a09g057: Add GBETH nodes
d2a7f6061328 arm64: dts: renesas: rzg3e-smarc-som: Enable serial NOR FLASH
ca067cd873d2 arm64: dts: renesas: r9a09g047: Add XSPI node
6afb981042a9 dt-bindings: soc: renesas: Document RZ/V2H EVK board part number
47e339df4236 arm64: dts: qcom: sdm850-lenovo-yoga-c630: enable sensors DSP
3eb07ee1199c arm64: dts: qcom: x1e80100-dell-xps13-9345: Enable fingerprint sensor
2369c0a8d811 spi: spi-fsl-dspi: DSPI support for NXP S32G
519d961ebee1 ARM: dts: bcm958625-meraki-mx6x: Use #pwm-cells = <3>
364569526281 ARM: dts: bcm63178: Add BCMBCA peripherals
a8aa7adbe86e ARM: dts: bcm63148: Add BCMBCA peripherals
72b55d5589da ARM: dts: bcm63138: Add BCMBCA peripherals
40f65eebdc16 ARM: dts: bcm6878: Add BCMBCA peripherals
4db474ab76b1 ARM: dts: bcm6855: Add BCMBCA peripherals
c1fa2261ce24 ARM: dts: bcm6846: Add interrupt to RNG
cfb95bca76c8 dt-bindings: rng: r200: Add interrupt property
8f5c0556e851 ARM: dts: bcm6878: Correct UART0 IRQ number
756cdb1f3650 arm64: dts: broadcom: Add overlay for RP1 device
f3e865c8518c arm64: dts: broadcom: Add board DTS for Rpi5 which includes RP1 node
f07526de4e4d arm64: dts: bcm2712: Add external clock for RP1 chipset on Rpi5
82e6696b5c5c arm64: dts: rp1: Add support for RaspberryPi's RP1 device
e4470510ff94 dt-bindings: misc: Add device specific bindings for RaspberryPi RP1
36ec48d1dd05 dt-bindings: pinctrl: Add RaspberryPi RP1 gpio/pinctrl/pinmux bindings
5bae359ddb89 dt-bindings: clock: Add RaspberryPi RP1 clock bindings
7311a83b9240 ARM64: dts: bcm63158: Add BCMBCA peripherals
c820a00e2552 ARM64: dts: bcm6858: Add BCMBCA peripherals
2a6681b31935 ARM64: dts: bcm6856: Add BCMBCA peripherals
f6d523dc2308 ARM64: dts: bcm4908: Add BCMBCA peripherals
cfb6a63d41fe riscv: dts: spacemit: enable eMMC for K1 SoC
274a9a682e34 dt-bindings: display: convert himax,hx8357d.txt to yaml format
99b29e7ccd61 dt-bindings: display: arm,pl11x: Allow resets property
e13ecc320126 dt-bindings: display: convert sitronix,st7586 to YAML
1e04213799d5 dt-bindings: lcdif: add lcd panel related property for imx28
11b1b6e24edd dt-bindings: soc: Add fsl,imx23-digctl.yaml for i.MX23 and i.MX28
9c5a32bcb7b7 ASoC: Add Richtek RTQ9124 support
d57db601e6b0 ASoC: tas571x: add support for tas5753
caa03026f5ef ASoC: codecs: wcd93xx: Few simplifications of code and
baa572592b2c regulator: dt-bindings: rpi-panel: Add regulator for 7" Raspberry Pi 720x1280
504cdf1cd54f ASoC: dt-bindings: rt9123: Append RTQ9124 description
3174278d792f arm64: dts: rockchip: drop touch panel display from rockpro64
873fbebb9c18 arm64: dts: rockchip: Use standard PHY reset properties for RK3576 ArmSoM Sige5
1222a7f24b9f arm64: dts: rockchip: add ROCK 5T device tree
0f79e5a028f1 arm64: dts: rockchip: move common ROCK 5B/+ nodes into own tree
0562055bfc3a arm64: dts: rockchip: rename rk3588-rock-5b.dtsi
9c200495868c dt-bindings: arm: rockchip: add RADXA ROCK 5T
7bcc6969adbc arm64: dts: rockchip: Add spi nodes for RK3528
45b18dd32d6a arm64: dts: rockchip: add DTs for Sakura Pi RK3308B
bfca6dc90f2b dt-bindings: arm: rockchip: Add Sakura Pi RK3308B
6d2e9d5b069d dt-bindings: vendor-prefixes: Add SakuraPi prefix
99295ef16891 arm64: dts: rockchip: Fix cover detection on PineNote
c13e5de9b3a4 arm64: dts: rockchip: Document unused device on i2c1
718ca7a2529e arm64: dts: rockchip: support Ethernet Switch adapter for RK3588 Jaguar
f6310c860d5d arm64: dts: rockchip: Add DSI panel support for gameforce-ace
e53018a1ec5b dt-bindings: iio: adc: adi,ad7606: add gain calibration support
14dc2df77a84 dt-bindings: iio: gyroscope: invensense,itg3200: add binding
2f573d87f578 dt-bindings: iio: adc: st,spear600-adc: txt to yaml format conversion.
ed7d4c99dbc3 dt-bindings: iio: adc: add ad4080
61b12aa8b66f dt-bindings: iio: adc: add ad408x axi variant
05db8b79a0b6 arm64: dts: qcom: sm8750: Trivial stray lines removal
1576a89b79e8 spi: dt-bindings: mxs-spi: allow clocks properpty
feffdd266d46 dt-bindings: spi: dspi: Add S32G support
d87d1c2d9447 dt-bindings: regulator: add pca9450: Add regulator-allowed-modes
fa5cfb1fe890 ASoC: dt-bindings: covert mxs-audio-sgtl5000.txt to yaml format
1a0738c10fdd ASoC: dt-bindings: tas57xx: add tas5753 compatibility
90f889cf60f4 ASoC: dt-bindings: qcom,wcd939x: Document missing VDD_PX supply
36269efd9ee8 dt-bindings: display: himax-hx8394: Add Huiling hl055fhav028c
8cd51ffc1367 dt-bindings: vendor-prefixes: Add prefix for Huiling
534b0f65825d dt-bindings: display: simple: add AUO P238HAN01 panel
158a6f7c3376 Merge drm-next-2025-05-28 into drm-misc-next
af3871ba3627 dt-bindings: allwinner: add H616 DE33 mixer binding
2124a6a99b66 dt-bindings: clock: renesas,cpg-mssr: Document RZ/T2H support
f5efe4f4902d dt-bindings: display: renesas,rzg2l-du: Add support for RZ/V2H(P) SoC
c625b4924743 dt-bindings: display: panel: Document Renesas R69328 based DSI panel
36ea865fae13 dt-bindings: display: panel: Document Renesas R61307 based DSI panel
0d28beee9809 dt-bindings: display: ti,am65x-dss: Add support for AM62L DSS
a0e2388af079 dt-bindings: gpu: mali-utgard: Add Rockchip RK3528 compatible
ac5d1cdc0275 dt-bindings: display: imx: Add i.MX8qxp Display Controller
963333f8371f dt-bindings: interrupt-controller: Add i.MX8qxp Display Controller interrupt controller
2889c661fb91 dt-bindings: display: imx: Add i.MX8qxp Display Controller command sequencer
57051a9f0a4c dt-bindings: display: imx: Add i.MX8qxp Display Controller AXI performance counter
cf04f0c00267 dt-bindings: display: imx: Add i.MX8qxp Display Controller pixel engine
0940d6bd8421 dt-bindings: display: imx: Add i.MX8qxp Display Controller display engine
6454e207cfe6 dt-bindings: display: imx: Add i.MX8qxp Display Controller blit engine
8300a1f4ca66 dt-bindings: display: imx: Add i.MX8qxp Display Controller processing units

git-subtree-dir: dts/upstream
git-subtree-split: 4d52919c55f45d027062baf25ebe1c24730699bd

Bindings/arm/amlogic.yaml

@@ -135,6 +135,7 @@ properties:
               - minix,neo-u9h
               - nexbox,a1
               - tronsmart,vega-s96
+              - ugoos,am3
               - videostrong,gxm-kiii-pro
               - wetek,core2
           - const: amlogic,s912

Bindings/arm/arm,trace-buffer-extension.yaml

@@ -41,10 +41,10 @@ additionalProperties: false
 examples:
 
   - |
-   #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
 
-   trbe {
-     compatible = "arm,trace-buffer-extension";
-     interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
-   };
+    trbe {
+        compatible = "arm,trace-buffer-extension";
+        interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
+    };
 ...

Bindings/arm/aspeed/aspeed.yaml

@@ -87,6 +87,7 @@ properties:
               - facebook,greatlakes-bmc
               - facebook,harma-bmc
               - facebook,minerva-cmc
+              - facebook,santabarbara-bmc
               - facebook,yosemite4-bmc
               - ibm,blueridge-bmc
               - ibm,everest-bmc
@@ -98,6 +99,7 @@ properties:
               - inventec,starscream-bmc
               - inventec,transformer-bmc
               - jabil,rbp-bmc
+              - nvidia,gb200nvl-bmc
               - qcom,dc-scm-v1-bmc
               - quanta,s6q-bmc
               - ufispace,ncplite-bmc

Bindings/arm/axiado.yaml

@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/axiado.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Axiado Platforms
+
+maintainers:
+  - Harshit Shah <hshah@axiado.com>
+
+properties:
+  $nodename:
+    const: '/'
+  compatible:
+    oneOf:
+      - description: AX3000 based boards
+        items:
+          - enum:
+              - axiado,ax3000-evk       # Axiado AX3000 Evaluation Board
+          - const: axiado,ax3000       # Axiado AX3000 SoC
+
+additionalProperties: true

Bindings/arm/cix.yaml

@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/cix.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: CIX platforms
+
+maintainers:
+  - Peter Chen <peter.chen@cixtech.com>
+  - Fugang Duan <fugang.duan@cixtech.com>
+
+properties:
+  $nodename:
+    const: '/'
+  compatible:
+    oneOf:
+
+      - description: Radxa Orion O6
+        items:
+          - const: radxa,orion-o6
+          - const: cix,sky1
+
+additionalProperties: true
+
+...

Bindings/arm/cpus.yaml

@@ -200,6 +200,7 @@ properties:
       - qcom,kryo385
       - qcom,kryo465
       - qcom,kryo468
+      - qcom,kryo470
       - qcom,kryo485
       - qcom,kryo560
       - qcom,kryo570

Bindings/arm/freescale/fsl,vf610-mscm-ir.txt

@@ -1,30 +0,0 @@
-Freescale Vybrid Miscellaneous System Control - Interrupt Router
-
-The MSCM IP contains multiple sub modules, this binding describes the second
-block of registers which control the interrupt router. The interrupt router
-allows to configure the recipient of each peripheral interrupt. Furthermore
-it controls the directed processor interrupts. The module is available in all
-Vybrid SoC's but is only really useful in dual core configurations (VF6xx
-which comes with a Cortex-A5/Cortex-M4 combination).
-
-Required properties:
-- compatible:		"fsl,vf610-mscm-ir"
-- reg:			the register range of the MSCM Interrupt Router
-- fsl,cpucfg:		The handle to the MSCM CPU configuration node, required
-			to get the current CPU ID
-- interrupt-controller:	Identifies the node as an interrupt controller
-- #interrupt-cells:	Two cells, interrupt number and cells.
-			The hardware interrupt number according to interrupt
-			assignment of the interrupt router is required.
-			Flags get passed only when using GIC as parent. Flags
-			encoding as documented by the GIC bindings.
-
-Example:
-	mscm_ir: interrupt-controller@40001800 {
-		compatible = "fsl,vf610-mscm-ir";
-		reg = <0x40001800 0x400>;
-		fsl,cpucfg = <&mscm_cpucfg>;
-		interrupt-controller;
-		#interrupt-cells = <2>;
-		interrupt-parent = <&intc>;
-	}

Bindings/arm/fsl.yaml

@@ -89,6 +89,7 @@ properties:
       - description: i.MX28 based Boards
         items:
           - enum:
+              - amarula,imx28-rmm
               - armadeus,imx28-apf28      # APF28 SoM
               - bluegiga,apx4devkit       # Bluegiga APx4 SoM on dev board
               - crystalfontz,cfa10036     # Crystalfontz CFA-10036 SoM
@@ -769,6 +770,15 @@ properties:
           - const: dh,imx6ull-dhcor-som
           - const: fsl,imx6ull
 
+      - description: i.MX6ULL Engicam MicroGEA SoM based boards
+        items:
+          - enum:
+              - engicam,microgea-imx6ull-bmm       # i.MX6ULL Engicam MicroGEA BMM Board
+              - engicam,microgea-imx6ull-gtw       # i.MX6ULL Engicam MicroGEA GTW Board
+              - engicam,microgea-imx6ull-rmm       # i.MX6ULL Engicam MicroGEA RMM Board
+          - const: engicam,microgea-imx6ull        # i.MX6ULL Engicam MicroGEA SoM
+          - const: fsl,imx6ull
+
       - description: i.MX6ULL PHYTEC phyBOARD-Segin
         items:
           - enum:
@@ -1095,6 +1105,7 @@ properties:
               - gateworks,imx8mp-gw74xx   # i.MX8MP Gateworks Board
               - gateworks,imx8mp-gw75xx-2x # i.MX8MP Gateworks Board
               - gateworks,imx8mp-gw82xx-2x # i.MX8MP Gateworks Board
+              - gocontroll,moduline-display # GOcontroll Moduline Display controller
               - skov,imx8mp-skov-basic # SKOV i.MX8MP baseboard without frontplate
               - skov,imx8mp-skov-revb-hdmi # SKOV i.MX8MP climate control without panel
               - skov,imx8mp-skov-revb-lt6 # SKOV i.MX8MP climate control with 7” panel
@@ -1395,6 +1406,13 @@ properties:
               - fsl,imx95-19x19-evk       # i.MX95 19x19 EVK Board
           - const: fsl,imx95
 
+      - description: PHYTEC i.MX 95 FPSC based Boards
+        items:
+          - enum:
+              - phytec,imx95-libra-rdk-fpsc   # Libra-i.MX 95 FPSC
+          - const: phytec,imx95-phycore-fpsc  # phyCORE-i.MX 95 FPSC
+          - const: fsl,imx95
+
       - description: i.MXRT1050 based Boards
         items:
           - enum:

Bindings/arm/mediatek.yaml

@@ -27,6 +27,11 @@ properties:
           - enum:
               - mediatek,mt2712-evb
           - const: mediatek,mt2712
+      - items:
+          - enum:
+              - jty,d101
+              - lenovo,a369i
+          - const: mediatek,mt6572
       - items:
           - enum:
               - mediatek,mt6580-evbp1
@@ -302,6 +307,10 @@ properties:
           - const: google,steelix-sku196608
           - const: google,steelix
           - const: mediatek,mt8186
+      - description: Google Squirtle (Acer Chromebook Spin 311 (R724T)
+        items:
+          - const: google,squirtle
+          - const: mediatek,mt8186
       - description: Google Starmie (ASUS Chromebook Enterprise CM30 (CM3001))
         items:
           - const: google,starmie-sku0
@@ -350,9 +359,6 @@ properties:
           - const: mediatek,mt8186
       - description: Google Voltorb (Acer Chromebook 311 C723/C732T)
         items:
-          - enum:
-              - google,voltorb-sku589824
-              - google,voltorb-sku589825
           - const: google,voltorb
           - const: mediatek,mt8186
       - items:

Bindings/arm/mrvl/mrvl.yaml

@@ -35,6 +35,11 @@ properties:
           - enum:
               - dell,wyse-ariel
           - const: marvell,mmp3
+      - description: PXA1908 based boards
+        items:
+          - enum:
+              - samsung,coreprimevelte
+          - const: marvell,pxa1908
 
 additionalProperties: true
 

Bindings/arm/qcom.yaml

@@ -209,6 +209,7 @@ properties:
               - samsung,hlte
               - sony,xperia-amami
               - sony,xperia-honami
+              - sony,xperia-togari
           - const: qcom,msm8974
 
       - items:
@@ -230,6 +231,11 @@ properties:
           - const: qcom,msm8974pro
           - const: qcom,msm8974
 
+      - items:
+          - enum:
+              - longcheer,l9360
+          - const: qcom,msm8976
+
       - items:
           - enum:
               - acer,a1-724

Bindings/arm/rockchip.yaml

@@ -258,6 +258,11 @@ properties:
           - const: firefly,rk3566-roc-pc
           - const: rockchip,rk3566
 
+      - description: Firefly Station M3
+        items:
+          - const: firefly,rk3588s-roc-pc
+          - const: rockchip,rk3588s
+
       - description: Firefly Station P2
         items:
           - const: firefly,rk3568-roc-pc
@@ -295,6 +300,12 @@ properties:
               - friendlyarm,nanopi-r4s-enterprise
           - const: rockchip,rk3399
 
+      - description: FriendlyElec NanoPi M5 series boards
+        items:
+          - enum:
+              - friendlyarm,nanopi-m5
+          - const: rockchip,rk3576
+
       - description: FriendlyElec NanoPi R5 series boards
         items:
           - enum:
@@ -715,6 +726,13 @@ properties:
           - const: lckfb,tspi-rk3566
           - const: rockchip,rk3566
 
+      - description: Luckfox Core3576 Module based boards
+        items:
+          - enum:
+              - luckfox,omni3576
+          - const: luckfox,core3576
+          - const: rockchip,rk3576
+
       - description: Lunzn FastRhino R66S / R68S
         items:
           - enum:
@@ -961,6 +979,11 @@ properties:
           - const: radxa,rock-s0
           - const: rockchip,rk3308
 
+      - description: Radxa ROCK 5T
+        items:
+          - const: radxa,rock-5t
+          - const: rockchip,rk3588
+
       - description: Radxa ZERO 3W/3E
         items:
           - enum:
@@ -1109,6 +1132,11 @@ properties:
           - const: rockchip,rk3588-toybrick-x0
           - const: rockchip,rk3588
 
+      - description: Sakura Pi RK3308B
+        items:
+          - const: sakurapi,rk3308-sakurapi-rk3308b
+          - const: rockchip,rk3308
+
       - description: Sinovoip RK3308 Banana Pi P2 Pro
         items:
           - const: sinovoip,rk3308-bpi-p2pro

Bindings/arm/rockchip/pmu.yaml

@@ -25,6 +25,7 @@ select:
           - rockchip,rk3288-pmu
           - rockchip,rk3368-pmu
           - rockchip,rk3399-pmu
+          - rockchip,rk3528-pmu
           - rockchip,rk3562-pmu
           - rockchip,rk3568-pmu
           - rockchip,rk3576-pmu
@@ -44,6 +45,7 @@ properties:
           - rockchip,rk3288-pmu
           - rockchip,rk3368-pmu
           - rockchip,rk3399-pmu
+          - rockchip,rk3528-pmu
           - rockchip,rk3562-pmu
           - rockchip,rk3568-pmu
           - rockchip,rk3576-pmu

Bindings/arm/samsung/samsung-boards.yaml

@@ -45,6 +45,12 @@ properties:
           - const: samsung,aries
           - const: samsung,s5pv210
 
+      - description: Exynos2200 based boards
+        items:
+          - enum:
+              - samsung,g0s                     # Samsung Galaxy S22+ (SM-S906B)
+          - const: samsung,exynos2200
+
       - description: Exynos3250 based boards
         items:
           - enum:

Bindings/arm/stm32/st,mlahb.yaml

@@ -55,17 +55,17 @@ unevaluatedProperties: false
 examples:
   - |
     ahb {
-      compatible = "st,mlahb", "simple-bus";
-      #address-cells = <1>;
-      #size-cells = <1>;
-      ranges;
-      dma-ranges = <0x00000000 0x38000000 0x10000>,
-                   <0x10000000 0x10000000 0x60000>,
-                   <0x30000000 0x30000000 0x60000>;
+        compatible = "st,mlahb", "simple-bus";
+        #address-cells = <1>;
+        #size-cells = <1>;
+        ranges;
+        dma-ranges = <0x00000000 0x38000000 0x10000>,
+                     <0x10000000 0x10000000 0x60000>,
+                     <0x30000000 0x30000000 0x60000>;
 
-      m4_rproc: m4@10000000 {
-       reg = <0x10000000 0x40000>;
-      };
+        m4_rproc: m4@10000000 {
+            reg = <0x10000000 0x40000>;
+        };
     };
 
 ...

Bindings/arm/stm32/stm32.yaml

@@ -121,6 +121,7 @@ properties:
               - st,stm32mp157a-dk1-scmi
               - st,stm32mp157c-dk2
               - st,stm32mp157c-dk2-scmi
+              - st,stm32mp157f-dk2
           - const: st,stm32mp157
 
       - items:

Bindings/arm/sunxi.yaml

@@ -341,15 +341,11 @@ properties:
           - const: allwinner,i12-tvbox
           - const: allwinner,sun7i-a20
 
-      - description: ICnova A20 ADB4006
+      - description: ICnova A20
         items:
-          - const: incircuit,icnova-a20-adb4006
-          - const: incircuit,icnova-a20
-          - const: allwinner,sun7i-a20
-
-      - description: ICNova A20 SWAC
-        items:
-          - const: incircuit,icnova-a20-swac
+          - enum:
+              - incircuit,icnova-a20-adb4006
+              - incircuit,icnova-a20-swac
           - const: incircuit,icnova-a20
           - const: allwinner,sun7i-a20
 
@@ -760,21 +756,12 @@ properties:
           - const: pine64,pinebook
           - const: allwinner,sun50i-a64
 
-      - description: Pine64 PinePhone Developer Batch (1.0)
+      - description: Pine64 PinePhone
         items:
-          - const: pine64,pinephone-1.0
-          - const: pine64,pinephone
-          - const: allwinner,sun50i-a64
-
-      - description: Pine64 PinePhone Braveheart (1.1)
-        items:
-          - const: pine64,pinephone-1.1
-          - const: pine64,pinephone
-          - const: allwinner,sun50i-a64
-
-      - description: Pine64 PinePhone (1.2)
-        items:
-          - const: pine64,pinephone-1.2
+          - enum:
+              - pine64,pinephone-1.0 # Developer Batch (1.0)
+              - pine64,pinephone-1.1 # Braveheart (1.1)
+              - pine64,pinephone-1.2
           - const: pine64,pinephone
           - const: allwinner,sun50i-a64
 
@@ -996,6 +983,11 @@ properties:
           - const: xunlong,orangepi-3
           - const: allwinner,sun50i-h6
 
+      - description: Xunlong OrangePi 4A
+        items:
+          - const: xunlong,orangepi-4a
+          - const: allwinner,sun55i-t527
+
       - description: Xunlong OrangePi Lite
         items:
           - const: xunlong,orangepi-lite

Bindings/arm/tegra.yaml

@@ -52,6 +52,10 @@ properties:
               - nvidia,cardhu-a04
           - const: nvidia,cardhu
           - const: nvidia,tegra30
+      - description: ASUS Portable AiO P1801-T
+        items:
+          - const: asus,p1801-t
+          - const: nvidia,tegra30
       - description: ASUS Transformers Device family
         items:
           - enum:
@@ -61,6 +65,10 @@ properties:
               - asus,tf300tl
               - asus,tf700t
           - const: nvidia,tegra30
+      - description: Asus VivoTab RT
+        items:
+          - const: asus,tf600t
+          - const: nvidia,tegra30
       - description: LG Optimus 4X P880
         items:
           - const: lg,p880
@@ -242,5 +250,10 @@ properties:
           - const: nvidia,p3768-0000+p3767-0005
           - const: nvidia,p3767-0005
           - const: nvidia,tegra234
+      - description: NVIDIA P3971-0089+P3834-0008 Engineering Reference Platform
+        items:
+          - const: nvidia,p3971-0089+p3834-0008
+          - const: nvidia,p3834-0008
+          - const: nvidia,tegra264
 
 additionalProperties: true

Bindings/arm/tegra/nvidia,tegra186-pmc.yaml

@@ -16,6 +16,7 @@ properties:
       - nvidia,tegra186-pmc
       - nvidia,tegra194-pmc
       - nvidia,tegra234-pmc
+      - nvidia,tegra264-pmc
 
   reg:
     minItems: 4

Bindings/arm/ti/k3.yaml

@@ -25,6 +25,12 @@ properties:
               - ti,am62a7-sk
           - const: ti,am62a7
 
+      - description: K3 AM62D2 SoC and Boards
+        items:
+          - enum:
+              - ti,am62d2-evm
+          - const: ti,am62d2
+
       - description: K3 AM62A7 SoC PHYTEC phyBOARD-Lyra
         items:
           - const: phytec,am62a7-phyboard-lyra-rdk

Bindings/arm/ti/omap.yaml

@@ -107,6 +107,7 @@ properties:
               - compulab,cm-t335
               - moxa,uc-8100-me-t
               - novatech,am335x-lxm
+              - seeed,am335x-bone-green-eco
               - ti,am335x-bone
               - ti,am335x-evm
               - ti,am3359-icev2

Bindings/bus/fsl,imx8mp-aipstz.yaml

@@ -0,0 +1,104 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bus/fsl,imx8mp-aipstz.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Secure AHB to IP Slave bus (AIPSTZ) bridge
+
+description:
+  The secure AIPS bridge (AIPSTZ) acts as a bridge for AHB masters issuing
+  transactions to IP Slave peripherals. Additionally, this module offers access
+  control configurations meant to restrict which peripherals a master can
+  access.
+
+maintainers:
+  - Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
+
+properties:
+  compatible:
+    const: fsl,imx8mp-aipstz
+
+  reg:
+    maxItems: 1
+
+  power-domains:
+    maxItems: 1
+
+  "#address-cells":
+    const: 1
+
+  "#size-cells":
+    const: 1
+
+  "#access-controller-cells":
+    const: 3
+    description:
+      First cell - consumer ID
+      Second cell - consumer type (master or peripheral)
+      Third cell - configuration value
+
+  ranges: true
+
+# borrowed from simple-bus.yaml, no additional requirements for children
+patternProperties:
+  "@(0|[1-9a-f][0-9a-f]*)$":
+    type: object
+    additionalProperties: true
+    properties:
+      reg:
+        items:
+          minItems: 2
+          maxItems: 4
+        minItems: 1
+        maxItems: 1024
+      ranges:
+        oneOf:
+          - items:
+              minItems: 3
+              maxItems: 7
+            minItems: 1
+            maxItems: 1024
+          - $ref: /schemas/types.yaml#/definitions/flag
+    anyOf:
+      - required:
+          - reg
+      - required:
+          - ranges
+
+required:
+  - compatible
+  - reg
+  - power-domains
+  - "#address-cells"
+  - "#size-cells"
+  - "#access-controller-cells"
+  - ranges
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/imx8mp-clock.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    bus@30df0000 {
+        compatible = "fsl,imx8mp-aipstz";
+        reg = <0x30df0000 0x10000>;
+        ranges = <0x30c00000 0x30c00000 0x400000>;
+        power-domains = <&pgc_audio>;
+        #address-cells = <1>;
+        #size-cells = <1>;
+        #access-controller-cells = <3>;
+
+        dma-controller@30e00000 {
+            compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
+            reg = <0x30e00000 0x10000>;
+            #dma-cells = <3>;
+            clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT>,
+                     <&clk IMX8MP_CLK_AUDIO_ROOT>;
+            clock-names = "ipg", "ahb";
+            interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+            fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
+        };
+    };

Bindings/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml

@@ -103,11 +103,14 @@ examples:
         clock-names = "msi", "ahb";
         power-domains = <&pd IMX_SC_R_DC_0>;
 
-        syscon@56221000 {
-            compatible = "fsl,imx8qxp-mipi-lvds-csr", "syscon", "simple-mfd";
+        bus@56221000 {
+            compatible = "simple-pm-bus", "syscon";
             reg = <0x56221000 0x1000>;
             clocks = <&mipi_lvds_0_di_mipi_lvds_regs_lpcg IMX_LPCG_CLK_4>;
             clock-names = "ipg";
+            #address-cells = <1>;
+            #size-cells = <1>;
+            ranges;
 
             pxl2dpi {
                 compatible = "fsl,imx8qxp-pxl2dpi";

Bindings/clock/alphascale,acc.txt

@@ -1,114 +0,0 @@
-Alphascale Clock Controller
-
-The ACC (Alphascale Clock Controller) is responsible for choosing proper
-clock source, setting dividers and clock gates.
-
-Required properties for the ACC node:
- - compatible: must be "alphascale,asm9260-clock-controller"
- - reg: must contain the ACC register base and size
- - #clock-cells : shall be set to 1.
-
-Simple one-cell clock specifier format is used, where the only cell is used
-as an index of the clock inside the provider.
-It is encouraged to use dt-binding for clock index definitions. SoC specific
-dt-binding should be included to the device tree descriptor. For example
-Alphascale ASM9260:
-#include <dt-bindings/clock/alphascale,asm9260.h>
-
-This binding contains two types of clock providers:
- _AHB_ - AHB gate;
- _SYS_ - adjustable clock source. Not all peripheral have _SYS_ clock provider.
-All clock specific details can be found in the SoC documentation.
-CLKID_AHB_ROM		0
-CLKID_AHB_RAM		1
-CLKID_AHB_GPIO		2
-CLKID_AHB_MAC		3
-CLKID_AHB_EMI		4
-CLKID_AHB_USB0		5
-CLKID_AHB_USB1		6
-CLKID_AHB_DMA0		7
-CLKID_AHB_DMA1		8
-CLKID_AHB_UART0		9
-CLKID_AHB_UART1		10
-CLKID_AHB_UART2		11
-CLKID_AHB_UART3		12
-CLKID_AHB_UART4		13
-CLKID_AHB_UART5		14
-CLKID_AHB_UART6		15
-CLKID_AHB_UART7		16
-CLKID_AHB_UART8		17
-CLKID_AHB_UART9		18
-CLKID_AHB_I2S0		19
-CLKID_AHB_I2C0		20
-CLKID_AHB_I2C1		21
-CLKID_AHB_SSP0		22
-CLKID_AHB_IOCONFIG	23
-CLKID_AHB_WDT		24
-CLKID_AHB_CAN0		25
-CLKID_AHB_CAN1		26
-CLKID_AHB_MPWM		27
-CLKID_AHB_SPI0		28
-CLKID_AHB_SPI1		29
-CLKID_AHB_QEI		30
-CLKID_AHB_QUADSPI0	31
-CLKID_AHB_CAMIF		32
-CLKID_AHB_LCDIF		33
-CLKID_AHB_TIMER0	34
-CLKID_AHB_TIMER1	35
-CLKID_AHB_TIMER2	36
-CLKID_AHB_TIMER3	37
-CLKID_AHB_IRQ		38
-CLKID_AHB_RTC		39
-CLKID_AHB_NAND		40
-CLKID_AHB_ADC0		41
-CLKID_AHB_LED		42
-CLKID_AHB_DAC0		43
-CLKID_AHB_LCD		44
-CLKID_AHB_I2S1		45
-CLKID_AHB_MAC1		46
-
-CLKID_SYS_CPU		47
-CLKID_SYS_AHB		48
-CLKID_SYS_I2S0M		49
-CLKID_SYS_I2S0S		50
-CLKID_SYS_I2S1M		51
-CLKID_SYS_I2S1S		52
-CLKID_SYS_UART0		53
-CLKID_SYS_UART1		54
-CLKID_SYS_UART2		55
-CLKID_SYS_UART3		56
-CLKID_SYS_UART4		56
-CLKID_SYS_UART5		57
-CLKID_SYS_UART6		58
-CLKID_SYS_UART7		59
-CLKID_SYS_UART8		60
-CLKID_SYS_UART9		61
-CLKID_SYS_SPI0		62
-CLKID_SYS_SPI1		63
-CLKID_SYS_QUADSPI	64
-CLKID_SYS_SSP0		65
-CLKID_SYS_NAND		66
-CLKID_SYS_TRACE		67
-CLKID_SYS_CAMM		68
-CLKID_SYS_WDT		69
-CLKID_SYS_CLKOUT	70
-CLKID_SYS_MAC		71
-CLKID_SYS_LCD		72
-CLKID_SYS_ADCANA	73
-
-Example of clock consumer with _SYS_ and _AHB_ sinks.
-uart4: serial@80010000 {
-	compatible = "alphascale,asm9260-uart";
-	reg = <0x80010000 0x4000>;
-	clocks = <&acc CLKID_SYS_UART4>, <&acc CLKID_AHB_UART4>;
-	interrupts = <19>;
-};
-
-Clock consumer with only one, _AHB_ sink.
-timer0: timer@80088000 {
-	compatible = "alphascale,asm9260-timer";
-	reg = <0x80088000 0x4000>;
-	clocks = <&acc CLKID_AHB_TIMER0>;
-	interrupts = <29>;
-};
-

Bindings/clock/alphascale,asm9260-clock-controller.yaml

@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/alphascale,asm9260-clock-controller.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Alphascale Clock Controller
+
+maintainers:
+  - Oleksij Rempel <linux@rempel-privat.de>
+
+description: |
+  The ACC (Alphascale Clock Controller) is responsible for choosing proper
+  clock source, setting dividers and clock gates.
+
+  Simple one-cell clock specifier format is used, where the only cell is used
+  as an index of the clock inside the provider.
+  It is encouraged to use dt-binding for clock index definitions. SoC specific
+  dt-binding should be included to the device tree descriptor. For example
+  Alphascale ASM9260:
+
+  #include <dt-bindings/clock/alphascale,asm9260.h>
+
+  This binding contains two types of clock providers:
+
+    _AHB_ - AHB gate;
+    _SYS_ - adjustable clock source. Not all peripheral have _SYS_ clock provider.
+
+  All clock specific details can be found in the SoC documentation.
+
+properties:
+  compatible:
+    const: alphascale,asm9260-clock-controller
+
+  reg:
+    maxItems: 1
+
+  '#clock-cells':
+    const: 1
+
+  clocks:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - '#clock-cells'
+
+additionalProperties: false

Bindings/clock/apm,xgene-device-clock.yaml

@@ -0,0 +1,80 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/apm,xgene-device-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: APM X-Gene SoC device clocks
+
+maintainers:
+  - Khuong Dinh <khuong@os.amperecomputing.com>
+
+properties:
+  compatible:
+    const: apm,xgene-device-clock
+
+  reg:
+    minItems: 1
+    maxItems: 2
+
+  reg-names:
+    items:
+      - enum: [ csr-reg, div-reg ]
+      - const: div-reg
+    minItems: 1
+
+  clocks:
+    maxItems: 1
+
+  "#clock-cells":
+    const: 1
+
+  clock-output-names:
+    maxItems: 1
+
+  clock-names:
+    maxItems: 1
+
+  csr-offset:
+    description: Offset to the CSR reset register
+    $ref: /schemas/types.yaml#/definitions/uint32
+    default: 0
+
+  csr-mask:
+    description: CSR reset mask bit
+    $ref: /schemas/types.yaml#/definitions/uint32
+    default: 0xf
+
+  enable-offset:
+    description: Offset to the enable register
+    $ref: /schemas/types.yaml#/definitions/uint32
+    default: 8
+
+  enable-mask:
+    description: CSR enable mask bit
+    $ref: /schemas/types.yaml#/definitions/uint32
+    default: 0xf
+
+  divider-offset:
+    description: Offset to the divider register
+    $ref: /schemas/types.yaml#/definitions/uint32
+    default: 0
+
+  divider-width:
+    description: Width of the divider register
+    $ref: /schemas/types.yaml#/definitions/uint32
+    default: 0
+
+  divider-shift:
+    description: Bit shift of the divider register
+    $ref: /schemas/types.yaml#/definitions/uint32
+    default: 0
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - '#clock-cells'
+  - clock-output-names
+
+additionalProperties: false

Bindings/clock/apm,xgene-socpll-clock.yaml

@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/apm,xgene-socpll-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: APM X-Gene SoC PLL, PCPPLL, and PMD clocks
+
+maintainers:
+  - Khuong Dinh <khuong@os.amperecomputing.com>
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - apm,xgene-pcppll-clock
+          - apm,xgene-pcppll-v2-clock
+          - apm,xgene-pmd-clock
+          - apm,xgene-socpll-clock
+          - apm,xgene-socpll-v2-clock
+
+  reg:
+    maxItems: 1
+
+  reg-names:
+    items:
+      - enum: [ csr-reg, div-reg ]
+      - const: div-reg
+    minItems: 1
+
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    enum: [ pcppll, socpll ]
+
+  "#clock-cells":
+    const: 1
+
+  clock-output-names:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - '#clock-cells'
+  - clock-output-names
+
+additionalProperties: false

Bindings/clock/armada3700-periph-clock.txt

@@ -1,71 +0,0 @@
-* Peripheral Clock bindings for Marvell Armada 37xx SoCs
-
-Marvell Armada 37xx SoCs provide peripheral clocks which are
-used as clock source for the peripheral of the SoC.
-
-There are two different blocks associated to north bridge and south
-bridge.
-
-The peripheral clock consumer should specify the desired clock by
-having the clock ID in its "clocks" phandle cell.
-
-The following is a list of provided IDs for Armada 3700 North bridge clocks:
-ID	Clock name	Description
------------------------------------
-0	mmc		MMC controller
-1	sata_host	Sata Host
-2	sec_at		Security AT
-3	sac_dap		Security DAP
-4	tsecm		Security Engine
-5	setm_tmx	Serial Embedded Trace Module
-6	avs		Adaptive Voltage Scaling
-7	sqf		SPI
-8	pwm		PWM
-9	i2c_2		I2C 2
-10	i2c_1		I2C 1
-11	ddr_phy		DDR PHY
-12	ddr_fclk	DDR F clock
-13	trace		Trace
-14	counter		Counter
-15	eip97		EIP 97
-16	cpu		CPU
-
-The following is a list of provided IDs for Armada 3700 South bridge clocks:
-ID	Clock name	Description
------------------------------------
-0	gbe-50		50 MHz parent clock for Gigabit Ethernet
-1	gbe-core	parent clock for Gigabit Ethernet core
-2	gbe-125		125 MHz parent clock for Gigabit Ethernet
-3	gbe1-50		50 MHz clock for Gigabit Ethernet port 1
-4	gbe0-50		50 MHz clock for Gigabit Ethernet port 0
-5	gbe1-125	125 MHz clock for Gigabit Ethernet port 1
-6	gbe0-125	125 MHz clock for Gigabit Ethernet port 0
-7	gbe1-core	Gigabit Ethernet core port 1
-8	gbe0-core	Gigabit Ethernet core port 0
-9	gbe-bm		Gigabit Ethernet Buffer Manager
-10	sdio		SDIO
-11	usb32-sub2-sys	USB 2 clock
-12	usb32-ss-sys	USB 3 clock
-13	pcie		PCIe controller
-
-Required properties:
-
-- compatible : shall be "marvell,armada-3700-periph-clock-nb" for the
-  north bridge block, or
-  "marvell,armada-3700-periph-clock-sb" for the south bridge block
-- reg : must be the register address of North/South Bridge Clock register
-- #clock-cells : from common clock binding; shall be set to 1
-
-- clocks : list of the parent clock phandle in the following order:
-  TBG-A P, TBG-B P, TBG-A S, TBG-B S and finally the xtal clock.
-
-
-Example:
-
-nb_perih_clk: nb-periph-clk@13000{
-	compatible = "marvell,armada-3700-periph-clock-nb";
-	reg = <0x13000 0x1000>;
-	clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
-	<&tbg 3>, <&xtalclk>;
-	#clock-cells = <1>;
-};

Bindings/clock/armada3700-tbg-clock.txt

@@ -1,27 +0,0 @@
-* Time Base Generator Clock bindings for Marvell Armada 37xx SoCs
-
-Marvell Armada 37xx SoCs provide Time Base Generator clocks which are
-used as parent clocks for the peripheral clocks.
-
-The TBG clock consumer should specify the desired clock by having the
-clock ID in its "clocks" phandle cell.
-
-The following is a list of provided IDs and clock names on Armada 3700:
- 0 = TBG A P
- 1 = TBG B P
- 2 = TBG A S
- 3 = TBG B S
-
-Required properties:
-- compatible : shall be "marvell,armada-3700-tbg-clock"
-- reg : must be the register address of North Bridge PLL register
-- #clock-cells : from common clock binding; shall be set to 1
-
-Example:
-
-tbg: tbg@13200 {
-	compatible = "marvell,armada-3700-tbg-clock";
-	reg = <0x13200 0x1000>;
-	clocks = <&xtalclk>;
-	#clock-cells = <1>;
-};

Bindings/clock/artpec6.txt

@@ -1,41 +0,0 @@
-* Clock bindings for Axis ARTPEC-6 chip
-
-The bindings are based on the clock provider binding in
-Documentation/devicetree/bindings/clock/clock-bindings.txt
-
-External clocks:
-----------------
-
-There are two external inputs to the main clock controller which should be
-provided using the common clock bindings.
-- "sys_refclk": External 50 Mhz oscillator (required)
-- "i2s_refclk": Alternate audio reference clock (optional).
-
-Main clock controller
----------------------
-
-Required properties:
-- #clock-cells: Should be <1>
-  See dt-bindings/clock/axis,artpec6-clkctrl.h for the list of valid identifiers.
-- compatible: Should be "axis,artpec6-clkctrl"
-- reg: Must contain the base address and length of the system controller
-- clocks:  Must contain a phandle entry for each clock in clock-names
-- clock-names: Must include the external oscillator ("sys_refclk"). Optional
-  ones are the audio reference clock ("i2s_refclk") and the audio fractional
-  dividers ("frac_clk0" and "frac_clk1").
-
-Examples:
-
-ext_clk: ext_clk {
-	#clock-cells = <0>;
-	compatible = "fixed-clock";
-	clock-frequency = <50000000>;
-};
-
-clkctrl: clkctrl@f8000000 {
-	#clock-cells = <1>;
-	compatible = "axis,artpec6-clkctrl";
-	reg = <0xf8000000 0x48>;
-	clocks = <&ext_clk>;
-	clock-names = "sys_refclk";
-};

Bindings/clock/axis,artpec6-clkctrl.yaml

@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/axis,artpec6-clkctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Axis ARTPEC-6 clock controller
+
+maintainers:
+  - Lars Persson <lars.persson@axis.com>
+
+properties:
+  compatible:
+    const: axis,artpec6-clkctrl
+
+  reg:
+    maxItems: 1
+
+  "#clock-cells":
+    const: 1
+
+  clocks:
+    minItems: 1
+    items:
+      - description: external 50 MHz oscillator.
+      - description: optional audio reference clock.
+      - description: fractional audio clock divider 0.
+      - description: fractional audio clock divider 1.
+
+  clock-names:
+    minItems: 1
+    items:
+      - const: sys_refclk
+      - const: i2s_refclk
+      - const: frac_clk0
+      - const: frac_clk1
+
+required:
+  - compatible
+  - reg
+  - "#clock-cells"
+  - clocks
+  - clock-names
+
+additionalProperties: false
+
+examples:
+  - |
+    clock-controller@f8000000 {
+        compatible = "axis,artpec6-clkctrl";
+        reg = <0xf8000000 0x48>;
+        #clock-cells = <1>;
+        clocks = <&ext_clk>;
+        clock-names = "sys_refclk";
+    };

Bindings/clock/brcm,bcm2835-cprman.txt

@@ -1,60 +0,0 @@
-Broadcom BCM2835 CPRMAN clocks
-
-This binding uses the common clock binding:
-    Documentation/devicetree/bindings/clock/clock-bindings.txt
-
-The CPRMAN clock controller generates clocks in the audio power domain
-of the BCM2835.  There is a level of PLLs deriving from an external
-oscillator, a level of PLL dividers that produce channels off of the
-few PLLs, and a level of mostly-generic clock generators sourcing from
-the PLL channels.  Most other hardware components source from the
-clock generators, but a few (like the ARM or HDMI) will source from
-the PLL dividers directly.
-
-Required properties:
-- compatible:	should be one of the following,
-	"brcm,bcm2711-cprman"
-	"brcm,bcm2835-cprman"
-- #clock-cells:	Should be <1>. The permitted clock-specifier values can be
-		  found in include/dt-bindings/clock/bcm2835.h
-- reg:		Specifies base physical address and size of the registers
-- clocks:	phandles to the parent clocks used as input to the module, in
-		  the following order:
-
-		  - External oscillator
-		  - DSI0 byte clock
-		  - DSI0 DDR2 clock
-		  - DSI0 DDR clock
-		  - DSI1 byte clock
-		  - DSI1 DDR2 clock
-		  - DSI1 DDR clock
-
-		  Only external oscillator is required.  The DSI clocks may
-		  not be present, in which case their children will be
-		  unusable.
-
-Example:
-
-	clk_osc: clock@3 {
-		compatible = "fixed-clock";
-		reg = <3>;
-		#clock-cells = <0>;
-		clock-output-names = "osc";
-		clock-frequency = <19200000>;
-	};
-
-	clocks: cprman@7e101000 {
-		compatible = "brcm,bcm2835-cprman";
-		#clock-cells = <1>;
-		reg = <0x7e101000 0x2000>;
-		clocks = <&clk_osc>;
-	};
-
-	i2c0: i2c@7e205000 {
-		compatible = "brcm,bcm2835-i2c";
-		reg = <0x7e205000 0x1000>;
-		interrupts = <2 21>;
-		clocks = <&clocks BCM2835_CLOCK_VPU>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-	};

Bindings/clock/brcm,bcm2835-cprman.yaml

@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/brcm,bcm2835-cprman.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom BCM2835 CPRMAN clocks
+
+maintainers:
+  - Stefan Wahren <wahrenst@gmx.net>
+  - Raspberry Pi Kernel Maintenance <kernel-list@raspberrypi.com>
+
+description:
+  The CPRMAN clock controller generates clocks in the audio power domain of the
+  BCM2835.  There is a level of PLLs deriving from an external oscillator, a
+  level of PLL dividers that produce channels off of the few PLLs, and a level
+  of mostly-generic clock generators sourcing from the PLL channels.  Most other
+  hardware components source from the clock generators, but a few (like the ARM
+  or HDMI) will source from the PLL dividers directly.
+
+properties:
+  compatible:
+    enum:
+      - brcm,bcm2711-cprman
+      - brcm,bcm2835-cprman
+
+  reg:
+    maxItems: 1
+
+  '#clock-cells':
+    const: 1
+
+  clocks:
+    minItems: 1
+    items:
+      - description: External oscillator clock.
+      - description: DSI0 byte clock.
+      - description: DSI0 DDR2 clock.
+      - description: DSI0 DDR clock.
+      - description: DSI1 byte clock.
+      - description: DSI1 DDR2 clock.
+      - description: DSI1 DDR clock.
+
+additionalProperties: false
+
+required:
+  - compatible
+  - '#clock-cells'
+  - reg
+  - clocks
+
+examples:
+  - |
+    clock-controller@7e101000 {
+        compatible = "brcm,bcm2835-cprman";
+        reg = <0x7e101000 0x2000>;
+        #clock-cells = <1>;
+        clocks = <&clk_osc>;
+    };

Bindings/clock/brcm,bcm53573-ilp.txt

@@ -1,36 +0,0 @@
-Broadcom BCM53573 ILP clock
-===========================
-
-This binding uses the common clock binding:
-    Documentation/devicetree/bindings/clock/clock-bindings.txt
-
-This binding is used for ILP clock (sometimes referred as "slow clock")
-on Broadcom BCM53573 devices using Cortex-A7 CPU.
-
-ILP's rate has to be calculated on runtime and it depends on ALP clock
-which has to be referenced.
-
-This clock is part of PMU (Power Management Unit), a Broadcom's device
-handing power-related aspects. Its node must be sub-node of the PMU
-device.
-
-Required properties:
-- compatible: "brcm,bcm53573-ilp"
-- clocks: has to reference an ALP clock
-- #clock-cells: should be <0>
-- clock-output-names: from common clock bindings, should contain clock
-		      name
-
-Example:
-
-pmu@18012000 {
-	compatible = "simple-mfd", "syscon";
-	reg = <0x18012000 0x00001000>;
-
-	ilp {
-		compatible = "brcm,bcm53573-ilp";
-		clocks = <&alp>;
-		#clock-cells = <0>;
-		clock-output-names = "ilp";
-	};
-};

Bindings/clock/brcm,bcm53573-ilp.yaml

@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/brcm,bcm53573-ilp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom BCM53573 ILP clock
+
+maintainers:
+  - Rafał Miłecki <rafal@milecki.pl>
+
+description: >
+  ILP clock (sometimes referred as "slow clock") on Broadcom BCM53573 devices
+  using Cortex-A7 CPU.
+
+  ILP's rate has to be calculated on runtime and it depends on ALP clock which
+  has to be referenced.
+
+  This clock is part of PMU (Power Management Unit), a Broadcom device handling
+  power-related aspects. Its node must be sub-node of the PMU device.
+
+properties:
+  compatible:
+    items:
+      - const: brcm,bcm53573-ilp
+
+  clocks:
+    maxItems: 1
+
+  '#clock-cells':
+    const: 0
+
+  clock-output-names:
+    items:
+      - const: ilp
+
+additionalProperties: false
+
+examples:
+  - |
+    ilp {
+        compatible = "brcm,bcm53573-ilp";
+        clocks = <&alp>;
+        #clock-cells = <0>;
+        clock-output-names = "ilp";
+    };

Bindings/clock/brcm,bcm63xx-clocks.txt

@@ -1,24 +0,0 @@
-Gated Clock Controller Bindings for MIPS based BCM63XX SoCs
-
-Required properties:
-- compatible: must be one of:
-	 "brcm,bcm3368-clocks"
-	 "brcm,bcm6318-clocks"
-	 "brcm,bcm6318-ubus-clocks"
-	 "brcm,bcm6328-clocks"
-	 "brcm,bcm6358-clocks"
-	 "brcm,bcm6362-clocks"
-	 "brcm,bcm6368-clocks"
-	 "brcm,bcm63268-clocks"
-
-- reg: Address and length of the register set
-- #clock-cells: must be <1>
-
-
-Example:
-
-clkctl: clock-controller@10000004 {
-	compatible = "brcm,bcm6328-clocks";
-	reg = <0x10000004 0x4>;
-	#clock-cells = <1>;
-};

Bindings/clock/brcm,bcm63xx-clocks.yaml

@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/brcm,bcm63xx-clocks.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MIPS based BCM63XX SoCs Gated Clock Controller
+
+maintainers:
+  - Álvaro Fernández Rojas <noltari@gmail.com>
+  - Jonas Gorski <jonas.gorski@gmail.com>
+
+properties:
+  compatible:
+    enum:
+      - brcm,bcm3368-clocks
+      - brcm,bcm6318-clocks
+      - brcm,bcm6318-ubus-clocks
+      - brcm,bcm6328-clocks
+      - brcm,bcm6358-clocks
+      - brcm,bcm6362-clocks
+      - brcm,bcm6368-clocks
+      - brcm,bcm63268-clocks
+
+  reg:
+    maxItems: 1
+
+  '#clock-cells':
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    clock-controller@10000004 {
+        compatible = "brcm,bcm6328-clocks";
+        reg = <0x10000004 0x4>;
+        #clock-cells = <1>;
+    };

Bindings/clock/cirrus,ep7209-clk.yaml

@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/cirrus,ep7209-clk.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cirrus Logic CLPS711X Clock Controller
+
+maintainers:
+  - Alexander Shiyan <shc_work@mail.ru>
+
+description:
+  See include/dt-bindings/clock/clps711x-clock.h for the full list of CLPS711X
+  clock IDs.
+
+properties:
+  compatible:
+    items:
+      - const: cirrus,ep7312-clk
+      - const: cirrus,ep7209-clk
+
+  reg:
+    maxItems: 1
+
+  startup-frequency:
+    description: Factory set CPU startup frequency in HZ.
+    $ref: /schemas/types.yaml#/definitions/uint32
+
+  "#clock-cells":
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - startup-frequency
+  - "#clock-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    clock-controller@80000000 {
+        compatible = "cirrus,ep7312-clk", "cirrus,ep7209-clk";
+        reg = <0x80000000 0xc000>;
+        #clock-cells = <1>;
+        startup-frequency = <73728000>;
+    };

Bindings/clock/clps711x-clock.txt

@@ -1,19 +0,0 @@
-* Clock bindings for the Cirrus Logic CLPS711X CPUs
-
-Required properties:
-- compatible       : Shall contain "cirrus,ep7209-clk".
-- reg              : Address of the internal register set.
-- startup-frequency: Factory set CPU startup frequency in HZ.
-- #clock-cells     : Should be <1>.
-
-The clock consumer should specify the desired clock by having the clock
-ID in its "clocks" phandle cell. See include/dt-bindings/clock/clps711x-clock.h
-for the full list of CLPS711X clock IDs.
-
-Example:
-	clks: clks@80000000 {
-		#clock-cells = <1>;
-		compatible = "cirrus,ep7312-clk", "cirrus,ep7209-clk";
-		reg = <0x80000000 0xc000>;
-		startup-frequency = <73728000>;
-	};

Bindings/clock/dove-divider-clock.txt

@@ -1,28 +0,0 @@
-PLL divider based Dove clocks
-
-Marvell Dove has a 2GHz PLL, which feeds into a set of dividers to provide
-high speed clocks for a number of peripherals.  These dividers are part of
-the PMU, and thus this node should be a child of the PMU node.
-
-The following clocks are provided:
-
-ID	Clock
--------------
-0	AXI bus clock
-1	GPU clock
-2	VMeta clock
-3	LCD clock
-
-Required properties:
-- compatible : shall be "marvell,dove-divider-clock"
-- reg : shall be the register address of the Core PLL and Clock Divider
-   Control 0 register.  This will cover that register, as well as the
-   Core PLL and Clock Divider Control 1 register.  Thus, it will have
-   a size of 8.
-- #clock-cells : from common clock binding; shall be set to 1
-
-divider_clk: core-clock@64 {
-	compatible = "marvell,dove-divider-clock";
-	reg = <0x0064 0x8>;
-	#clock-cells = <1>;
-};

Bindings/clock/img,pistachio-clk.yaml

@@ -0,0 +1,136 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/img,pistachio-clk.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Imagination Technologies Pistachio SoC clock controllers
+
+maintainers:
+  - Andrew Bresticker <abrestic@chromium.org>
+
+description: |
+  Pistachio has four clock controllers (core clock, peripheral clock, peripheral
+  general control, and top general control) which are instantiated individually
+  from the device-tree.
+
+  Core clock controller:
+
+  The core clock controller generates clocks for the CPU, RPU (WiFi + BT
+  co-processor), audio, and several peripherals.
+
+  Peripheral clock controller:
+
+  The peripheral clock controller generates clocks for the DDR, ROM, and other
+  peripherals. The peripheral system clock ("periph_sys") generated by the core
+  clock controller is the input clock to the peripheral clock controller.
+
+  Peripheral general control:
+
+  The peripheral general control block generates system interface clocks and
+  resets for various peripherals. It also contains miscellaneous peripheral
+  control registers.
+
+  Top-level general control:
+
+  The top-level general control block contains miscellaneous control registers
+  and gates for the external clocks "audio_clk_in" and "enet_clk_in".
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - img,pistachio-clk
+          - img,pistachio-clk-periph
+          - img,pistachio-cr-periph
+          - img,pistachio-cr-top
+
+  reg:
+    maxItems: 1
+
+  '#clock-cells':
+    const: 1
+
+  clocks:
+    minItems: 1
+    maxItems: 3
+
+  clock-names:
+    minItems: 1
+    maxItems: 3
+
+required:
+  - compatible
+  - reg
+  - '#clock-cells'
+  - clocks
+  - clock-names
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: img,pistachio-clk
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External 52Mhz oscillator
+            - description: Alternate audio reference clock
+            - description: Alternate ethernet PHY clock
+
+        clock-names:
+          items:
+            - const: xtal
+            - const: audio_refclk_ext_gate
+            - const: ext_enet_in_gate
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: img,pistachio-clk-periph
+    then:
+      properties:
+        clocks:
+          items:
+            - description: Peripheral system clock
+
+        clock-names:
+          items:
+            - const: periph_sys_core
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: img,pistachio-cr-periph
+    then:
+      properties:
+        clocks:
+          items:
+            - description: System interface clock
+
+        clock-names:
+          items:
+            - const: sys
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: img,pistachio-cr-top
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External audio reference clock
+            - description: External ethernet PHY clock
+
+        clock-names:
+          items:
+            - const: audio_clk_in
+            - const: enet_clk_in
+
+additionalProperties: false

Bindings/clock/lpc1850-ccu.txt

@@ -1,77 +0,0 @@
-* NXP LPC1850 Clock Control Unit (CCU)
-
-Each CGU base clock has several clock branches which can be turned on
-or off independently by the Clock Control Units CCU1 or CCU2. The
-branch clocks are distributed between CCU1 and CCU2.
-
- - Above text taken from NXP LPC1850 User Manual.
-
-This binding uses the common clock binding:
-    Documentation/devicetree/bindings/clock/clock-bindings.txt
-
-Required properties:
-- compatible:
-	Should be "nxp,lpc1850-ccu"
-- reg:
-	Shall define the base and range of the address space
-	containing clock control registers
-- #clock-cells:
-	Shall have value <1>.  The permitted clock-specifier values
-	are the branch clock names defined in table below.
-- clocks:
-	Shall contain a list of phandles for the base clocks routed
-	from the CGU to the specific CCU. See mapping of base clocks
-	and CCU in table below.
-- clock-names:
-	Shall contain a list of names for the base clock routed
-	from the CGU to the specific CCU. Valid CCU clock names:
-	"base_usb0_clk",  "base_periph_clk", "base_usb1_clk",
-	"base_cpu_clk",   "base_spifi_clk",  "base_spi_clk",
-	"base_apb1_clk",  "base_apb3_clk",   "base_adchs_clk",
-	"base_sdio_clk",  "base_ssp0_clk",   "base_ssp1_clk",
-	"base_uart0_clk", "base_uart1_clk",  "base_uart2_clk",
-	"base_uart3_clk", "base_audio_clk"
-
-Which branch clocks that are available on the CCU depends on the
-specific LPC part. Check the user manual for your specific part.
-
-A list of CCU clocks can be found in dt-bindings/clock/lpc18xx-ccu.h.
-
-Example board file:
-
-soc {
-	ccu1: clock-controller@40051000 {
-		compatible = "nxp,lpc1850-ccu";
-		reg = <0x40051000 0x1000>;
-		#clock-cells = <1>;
-		clocks = <&cgu BASE_APB3_CLK>,   <&cgu BASE_APB1_CLK>,
-			 <&cgu BASE_SPIFI_CLK>,  <&cgu BASE_CPU_CLK>,
-			 <&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>,
-			 <&cgu BASE_USB1_CLK>,   <&cgu BASE_SPI_CLK>;
-		clock-names = "base_apb3_clk",   "base_apb1_clk",
-			      "base_spifi_clk",  "base_cpu_clk",
-			      "base_periph_clk", "base_usb0_clk",
-			      "base_usb1_clk",   "base_spi_clk";
-	};
-
-	ccu2: clock-controller@40052000 {
-		compatible = "nxp,lpc1850-ccu";
-		reg = <0x40052000 0x1000>;
-		#clock-cells = <1>;
-		clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>,
-			 <&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>,
-			 <&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>,
-			 <&cgu BASE_SSP0_CLK>,  <&cgu BASE_SDIO_CLK>;
-		clock-names = "base_audio_clk", "base_uart3_clk",
-			      "base_uart2_clk", "base_uart1_clk",
-			      "base_uart0_clk", "base_ssp1_clk",
-			      "base_ssp0_clk",  "base_sdio_clk";
-	};
-
-	/* A user of CCU branch clocks */
-	uart1: serial@40082000 {
-		...
-		clocks = <&ccu2 CLK_APB0_UART1>, <&ccu1 CLK_CPU_UART1>;
-		...
-	};
-};

Bindings/clock/lpc1850-cgu.txt

@@ -1,131 +0,0 @@
-* NXP LPC1850 Clock Generation Unit (CGU)
-
-The CGU generates multiple independent clocks for the core and the
-peripheral blocks of the LPC18xx. Each independent clock is called
-a base clock and itself is one of the inputs to the two Clock
-Control Units (CCUs) which control the branch clocks to the
-individual peripherals.
-
-The CGU selects the inputs to the clock generators from multiple
-clock sources, controls the clock generation, and routes the outputs
-of the clock generators through the clock source bus to the output
-stages. Each output stage provides an independent clock source and
-corresponds to one of the base clocks for the LPC18xx.
-
- - Above text taken from NXP LPC1850 User Manual.
-
-
-This binding uses the common clock binding:
-    Documentation/devicetree/bindings/clock/clock-bindings.txt
-
-Required properties:
-- compatible:
-	Should be "nxp,lpc1850-cgu"
-- reg:
-	Shall define the base and range of the address space
-	containing clock control registers
-- #clock-cells:
-	Shall have value <1>.  The permitted clock-specifier values
-	are the base clock numbers defined below.
-- clocks:
-	Shall contain a list of phandles for the external input
-	sources to the CGU. The list shall be in the following
-	order: xtal, 32khz, enet_rx_clk, enet_tx_clk, gp_clkin.
-- clock-indices:
-	Shall be an ordered list of numbers defining the base clock
-	number provided by the CGU.
-- clock-output-names:
-	Shall be an ordered list of strings defining the names of
-	the clocks provided by the CGU.
-
-Which base clocks that are available on the CGU depends on the
-specific LPC part. Base clocks are numbered from 0 to 27.
-
-Number:		Name:			Description:
- 0		BASE_SAFE_CLK		Base safe clock (always on) for WWDT
- 1		BASE_USB0_CLK		Base clock for USB0
- 2		BASE_PERIPH_CLK		Base clock for Cortex-M0SUB subsystem,
-					SPI, and SGPIO
- 3		BASE_USB1_CLK		Base clock for USB1
- 4		BASE_CPU_CLK		System base clock for ARM Cortex-M core
-					and APB peripheral blocks #0 and #2
- 5		BASE_SPIFI_CLK		Base clock for SPIFI
- 6		BASE_SPI_CLK		Base clock for SPI
- 7		BASE_PHY_RX_CLK		Base clock for Ethernet PHY Receive clock
- 8		BASE_PHY_TX_CLK		Base clock for Ethernet PHY Transmit clock
- 9		BASE_APB1_CLK		Base clock for APB peripheral block # 1
-10		BASE_APB3_CLK		Base clock for APB peripheral block # 3
-11		BASE_LCD_CLK		Base clock for LCD
-12		BASE_ADCHS_CLK		Base clock for ADCHS
-13		BASE_SDIO_CLK		Base clock for SD/MMC
-14		BASE_SSP0_CLK		Base clock for SSP0
-15		BASE_SSP1_CLK		Base clock for SSP1
-16		BASE_UART0_CLK		Base clock for UART0
-17		BASE_UART1_CLK		Base clock for UART1
-18		BASE_UART2_CLK		Base clock for UART2
-19		BASE_UART3_CLK		Base clock for UART3
-20		BASE_OUT_CLK		Base clock for CLKOUT pin
-24-21		-			Reserved
-25		BASE_AUDIO_CLK		Base clock for audio system (I2S)
-26 		BASE_CGU_OUT0_CLK	Base clock for CGU_OUT0 clock output
-27 		BASE_CGU_OUT1_CLK	Base clock for CGU_OUT1 clock output
-
-BASE_PERIPH_CLK and BASE_SPI_CLK is only available on LPC43xx.
-BASE_ADCHS_CLK is only available on LPC4370.
-
-
-Example board file:
-
-/ {
-	clocks {
-		xtal: xtal {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <12000000>;
-		};
-
-		xtal32: xtal32 {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <32768>;
-		};
-
-		enet_rx_clk: enet_rx_clk {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <0>;
-			clock-output-names = "enet_rx_clk";
-		};
-
-		enet_tx_clk: enet_tx_clk {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <0>;
-			clock-output-names = "enet_tx_clk";
-		};
-
-		gp_clkin: gp_clkin {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <0>;
-			clock-output-names = "gp_clkin";
-		};
-	};
-
-	soc {
-		cgu: clock-controller@40050000 {
-			compatible = "nxp,lpc1850-cgu";
-			reg = <0x40050000 0x1000>;
-			#clock-cells = <1>;
-			clocks = <&xtal>, <&creg_clk 1>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>;
-		};
-
-		/* A CGU and CCU clock consumer */
-		lcdc: lcdc@40008000 {
-			...
-			clocks = <&cgu BASE_LCD_CLK>, <&ccu1 CLK_CPU_LCD>;
-			clock-names = "clcdclk", "apb_pclk";
-			...
-		};
-	};
-};

Bindings/clock/lpc1850-creg-clk.txt

@@ -1,52 +0,0 @@
-* NXP LPC1850 CREG clocks
-
-The NXP LPC18xx/43xx CREG (Configuration Registers) block contains
-control registers for two low speed clocks. One of the clocks is a
-32 kHz oscillator driver with power up/down and clock gating. Next
-is a fixed divider that creates a 1 kHz clock from the 32 kHz osc.
-
-These clocks are used by the RTC and the Event Router peripherals.
-The 32 kHz can also be routed to other peripherals to enable low
-power modes.
-
-This binding uses the common clock binding:
-    Documentation/devicetree/bindings/clock/clock-bindings.txt
-
-Required properties:
-- compatible:
-	Should be "nxp,lpc1850-creg-clk"
-- #clock-cells:
-	Shall have value <1>.
-- clocks:
-	Shall contain a phandle to the fixed 32 kHz crystal.
-
-The creg-clk node must be a child of the creg syscon node.
-
-The following clocks are available from the clock node.
-
-Clock ID	Name
-   0		 1 kHz clock
-   1		32 kHz Oscillator
-
-Example:
-soc {
-	creg: syscon@40043000 {
-		compatible = "nxp,lpc1850-creg", "syscon", "simple-mfd";
-		reg = <0x40043000 0x1000>;
-
-		creg_clk: clock-controller {
-			compatible = "nxp,lpc1850-creg-clk";
-			clocks = <&xtal32>;
-			#clock-cells = <1>;
-		};
-
-		...
-	};
-
-	rtc: rtc@40046000 {
-		...
-		clocks = <&creg_clk 0>, <&ccu1 CLK_CPU_BUS>;
-		clock-names = "rtc", "reg";
-		...
-	};
-};

Bindings/clock/lsi,axm5516-clks.txt

@@ -1,29 +0,0 @@
-AXM5516 clock driver bindings
------------------------------
-
-Required properties :
-- compatible : shall contain "lsi,axm5516-clks"
-- reg : shall contain base register location and length
-- #clock-cells : shall contain 1
-
-The consumer specifies the desired clock by having the clock ID in its "clocks"
-phandle cell. See <dt-bindings/clock/lsi,axxia-clock.h> for the list of
-supported clock IDs.
-
-Example:
-
-	clks: clock-controller@2010020000 {
-		compatible = "lsi,axm5516-clks";
-		#clock-cells = <1>;
-		reg = <0x20 0x10020000 0 0x20000>;
-	};
-
-	serial0: uart@2010080000 {
-		compatible = "arm,pl011", "arm,primecell";
-		reg = <0x20 0x10080000 0 0x1000>;
-		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&clks AXXIA_CLK_PER>;
-		clock-names = "apb_pclk";
-	};
-																																};
-

Bindings/clock/lsi,axm5516-clks.yaml

@@ -0,0 +1,43 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright 2025 LSI
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/lsi,axm5516-clks.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: LSI AXM5516 Clock Controller
+
+maintainers:
+  - Anders Berg <anders.berg@lsi.com>
+
+description:
+  See <dt-bindings/clock/lsi,axxia-clock.h> for the list of supported clock IDs.
+
+properties:
+  compatible:
+    const: lsi,axm5516-clks
+
+  reg:
+    maxItems: 1
+
+  '#clock-cells':
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    bus {
+        #address-cells = <2>;
+        #size-cells = <1>;
+        clock-controller@2010020000 {
+            compatible = "lsi,axm5516-clks";
+            #clock-cells = <1>;
+            reg = <0x20 0x10020000 0x20000>;
+        };
+    };

Bindings/clock/lsi,nspire-cx-clock.yaml

@@ -0,0 +1,33 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/lsi,nspire-cx-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI-NSPIRE Clocks
+
+maintainers:
+  - Daniel Tang <dt.tangr@gmail.com>
+
+properties:
+  compatible:
+    enum:
+      - lsi,nspire-cx-ahb-divider
+      - lsi,nspire-classic-ahb-divider
+      - lsi,nspire-cx-clock
+      - lsi,nspire-classic-clock
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  '#clock-cells':
+    const: 0
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg

Bindings/clock/marvell,armada-370-corediv-clock.yaml

@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/marvell,armada-370-corediv-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Marvell MVEBU Core Divider Clock
+
+maintainers:
+  - Andrew Lunn <andrew@lunn.ch>
+  - Gregory Clement <gregory.clement@bootlin.com>
+
+properties:
+  compatible:
+    oneOf:
+      - enum:
+          - marvell,armada-370-corediv-clock
+          - marvell,armada-375-corediv-clock
+          - marvell,armada-380-corediv-clock
+          - marvell,mv98dx3236-corediv-clock
+      - items:
+          - const: marvell,armada-390-corediv-clock
+          - const: marvell,armada-380-corediv-clock
+
+  reg:
+    maxItems: 1
+
+  "#clock-cells":
+    const: 1
+
+  clocks:
+    maxItems: 1
+
+  clock-output-names:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - "#clock-cells"
+  - clocks
+
+additionalProperties: false
+
+examples:
+  - |
+    clock-controller@18740 {
+        compatible = "marvell,armada-370-corediv-clock";
+        reg = <0x18740 0xc>;
+        #clock-cells = <1>;
+        clocks = <&pll>;
+    };

Bindings/clock/marvell,armada-3700-periph-clock.yaml

@@ -0,0 +1,96 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/marvell,armada-3700-periph-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Marvell Armada 37xx SoCs Peripheral Clocks
+
+maintainers:
+  - Andrew Lunn <andrew@lunn.ch>
+  - Gregory Clement <gregory.clement@bootlin.com>
+
+description: >
+  Marvell Armada 37xx SoCs provide peripheral clocks which are used as clock
+  source for the peripheral of the SoC.
+
+  There are two different blocks associated to north bridge and south bridge.
+
+  The following is a list of provided IDs for Armada 3700 North bridge clocks:
+
+    ID	Clock name	Description
+    -----------------------------------
+    0	mmc		MMC controller
+    1	sata_host	Sata Host
+    2	sec_at		Security AT
+    3	sac_dap		Security DAP
+    4	tsecm		Security Engine
+    5	setm_tmx	Serial Embedded Trace Module
+    6	avs		Adaptive Voltage Scaling
+    7	sqf		SPI
+    8	pwm		PWM
+    9	i2c_2		I2C 2
+    10	i2c_1		I2C 1
+    11	ddr_phy		DDR PHY
+    12	ddr_fclk	DDR F clock
+    13	trace		Trace
+    14	counter		Counter
+    15	eip97		EIP 97
+    16	cpu		CPU
+
+  The following is a list of provided IDs for Armada 3700 South bridge clocks:
+
+    ID	Clock name	Description
+    -----------------------------------
+    0	gbe-50		50 MHz parent clock for Gigabit Ethernet
+    1	gbe-core	parent clock for Gigabit Ethernet core
+    2	gbe-125		125 MHz parent clock for Gigabit Ethernet
+    3	gbe1-50		50 MHz clock for Gigabit Ethernet port 1
+    4	gbe0-50		50 MHz clock for Gigabit Ethernet port 0
+    5	gbe1-125	125 MHz clock for Gigabit Ethernet port 1
+    6	gbe0-125	125 MHz clock for Gigabit Ethernet port 0
+    7	gbe1-core	Gigabit Ethernet core port 1
+    8	gbe0-core	Gigabit Ethernet core port 0
+    9	gbe-bm		Gigabit Ethernet Buffer Manager
+    10	sdio		SDIO
+    11	usb32-sub2-sys	USB 2 clock
+    12	usb32-ss-sys	USB 3 clock
+    13	pcie		PCIe controller
+
+properties:
+  compatible:
+    oneOf:
+      - const: marvell,armada-3700-periph-clock-sb
+      - items:
+          - const: marvell,armada-3700-periph-clock-nb
+          - const: syscon
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: TBG-A P clock and specifier
+      - description: TBG-B P clock and specifier
+      - description: TBG-A S clock and specifier
+      - description: TBG-B S clock and specifier
+      - description: Xtal clock and specifier
+
+  '#clock-cells':
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    clock-controller@13000{
+        compatible = "marvell,armada-3700-periph-clock-sb";
+        reg = <0x13000 0x1000>;
+        clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, <&tbg 3>, <&xtalclk>;
+        #clock-cells = <1>;
+    };

Bindings/clock/marvell,armada-3700-tbg-clock.yaml

@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/marvell,armada-3700-tbg-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Marvell Armada 3700 Time Base Generator Clock
+
+maintainers:
+  - Andrew Lunn <andrew@lunn.ch>
+  - Gregory Clement <gregory.clement@bootlin.com>
+
+description: >
+  Marvell Armada 37xx SoCs provide Time Base Generator clocks which are used as
+  parent clocks for the peripheral clocks.
+
+  The TBG clock consumer should specify the desired clock by having the clock ID
+  in its "clocks" phandle cell.
+
+  The following is a list of provided IDs and clock names on Armada 3700:
+
+    0 = TBG A P
+    1 = TBG B P
+    2 = TBG A S
+    3 = TBG B S
+
+properties:
+  compatible:
+    const: marvell,armada-3700-tbg-clock
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  '#clock-cells':
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    clock-controller@13200 {
+        compatible = "marvell,armada-3700-tbg-clock";
+        reg = <0x13200 0x1000>;
+        clocks = <&xtalclk>;
+        #clock-cells = <1>;
+    };

Bindings/clock/marvell,armada-xp-cpu-clock.yaml

@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+---
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+$id: http://devicetree.org/schemas/clock/marvell,armada-xp-cpu-clock.yaml#
+
+title: Marvell EBU CPU Clock
+
+maintainers:
+  - Andrew Lunn <andrew@lunn.ch>
+  - Gregory Clement <gregory.clement@bootlin.com>
+
+properties:
+  compatible:
+    enum:
+      - marvell,armada-xp-cpu-clock
+      - marvell,mv98dx3236-cpu-clock
+
+  reg:
+    items:
+      - description: Clock complex registers
+      - description: PMU DFS registers
+
+  '#clock-cells':
+    const: 1
+
+  clocks:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - '#clock-cells'
+  - clocks
+
+additionalProperties: false
+
+examples:
+  - |
+    clock-controller@d0018700 {
+        #clock-cells = <1>;
+        compatible = "marvell,armada-xp-cpu-clock";
+        reg = <0xd0018700 0xa0>, <0x1c054 0x10>;
+        clocks = <&coreclk 1>;
+    };

Bindings/clock/marvell,berlin.txt

@@ -1,31 +0,0 @@
-Device Tree Clock bindings for Marvell Berlin
-
-This binding uses the common clock binding[1].
-
-[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-
-Clock related registers are spread among the chip control registers. Berlin
-clock node should be a sub-node of the chip controller node. Marvell Berlin2
-(BG2, BG2CD, BG2Q) SoCs share the same IP for PLLs and clocks, with some
-minor differences in features and register layout.
-
-Required properties:
-- compatible: must be "marvell,berlin2-clk" or "marvell,berlin2q-clk"
-- #clock-cells: must be 1
-- clocks: must be the input parent clock phandle
-- clock-names: name of the input parent clock
-	Allowed clock-names for the reference clocks are
-	"refclk" for the SoCs oscillator input on all SoCs,
-	and SoC-specific input clocks for
-	BG2/BG2CD: "video_ext0" for the external video clock input
-
-
-Example:
-
-chip_clk: clock {
-	compatible = "marvell,berlin2q-clk";
-
-	#clock-cells = <1>;
-	clocks = <&refclk>;
-	clock-names = "refclk";
-};

Bindings/clock/marvell,berlin2-clk.yaml

@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/marvell,berlin2-clk.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Marvell Berlin Clock Controller
+
+maintainers:
+  - Jisheng Zhang <jszhang@kernel.org>
+
+description:
+  Clock related registers are spread among the chip control registers. Berlin
+  clock node should be a sub-node of the chip controller node. Marvell Berlin2
+  (BG2, BG2CD, BG2Q) SoCs share the same IP for PLLs and clocks, with some minor
+  differences in features and register layout.
+
+properties:
+  compatible:
+    enum:
+      - marvell,berlin2-clk
+      - marvell,berlin2q-clk
+
+  '#clock-cells':
+    const: 1
+
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    items:
+      - enum:
+          - refclk
+          - video_ext0
+
+required:
+  - compatible
+  - '#clock-cells'
+  - clocks
+  - clock-names
+
+additionalProperties: false
+
+examples:
+  - |
+    clock-controller {
+        compatible = "marvell,berlin2q-clk";
+        #clock-cells = <1>;
+        clocks = <&refclk>;
+        clock-names = "refclk";
+    };

Bindings/clock/marvell,dove-divider-clock.yaml

@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/marvell,dove-divider-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Marvell Dove PLL Divider Clock
+
+maintainers:
+  - Andrew Lunn <andrew@lunn.ch>
+  - Gregory Clement <gregory.clement@bootlin.com>
+
+description: >
+  Marvell Dove has a 2GHz PLL, which feeds into a set of dividers to provide
+  high speed clocks for a number of peripherals.  These dividers are part of the
+  PMU, and thus this node should be a child of the PMU node.
+
+  The following clocks are provided:
+
+    ID	Clock
+    -------------
+    0	AXI bus clock
+    1	GPU clock
+    2	VMeta clock
+    3	LCD clock
+
+properties:
+  compatible:
+    const: marvell,dove-divider-clock
+
+  reg:
+    maxItems: 1
+
+  '#clock-cells':
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    clock-controller@64 {
+        compatible = "marvell,dove-divider-clock";
+        reg = <0x0064 0x8>;
+        #clock-cells = <1>;
+    };

Bindings/clock/marvell,mvebu-core-clock.yaml

@@ -0,0 +1,94 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/marvell,mvebu-core-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Marvell MVEBU SoC core clock
+
+maintainers:
+  - Andrew Lunn <andrew@lunn.ch>
+  - Gregory Clement <gregory.clement@bootlin.com>
+
+description: >
+  Marvell MVEBU SoCs usually allow to determine core clock frequencies by
+  reading the Sample-At-Reset (SAR) register. The core clock consumer should
+  specify the desired clock by having the clock ID in its "clocks" phandle cell.
+
+  The following is a list of provided IDs and clock names on Armada 370/XP:
+   0 = tclk    (Internal Bus clock)
+   1 = cpuclk  (CPU clock)
+   2 = nbclk   (L2 Cache clock)
+   3 = hclk    (DRAM control clock)
+   4 = dramclk (DDR clock)
+
+  The following is a list of provided IDs and clock names on Armada 375:
+   0 = tclk    (Internal Bus clock)
+   1 = cpuclk  (CPU clock)
+   2 = l2clk   (L2 Cache clock)
+   3 = ddrclk  (DDR clock)
+
+  The following is a list of provided IDs and clock names on Armada 380/385:
+   0 = tclk    (Internal Bus clock)
+   1 = cpuclk  (CPU clock)
+   2 = l2clk   (L2 Cache clock)
+   3 = ddrclk  (DDR clock)
+
+  The following is a list of provided IDs and clock names on Armada 39x:
+   0 = tclk    (Internal Bus clock)
+   1 = cpuclk  (CPU clock)
+   2 = nbclk   (Coherent Fabric clock)
+   3 = hclk    (SDRAM Controller Internal Clock)
+   4 = dclk    (SDRAM Interface Clock)
+   5 = refclk  (Reference Clock)
+
+  The following is a list of provided IDs and clock names on 98dx3236:
+   0 = tclk    (Internal Bus clock)
+   1 = cpuclk  (CPU clock)
+   2 = ddrclk  (DDR clock)
+   3 = mpll    (MPLL Clock)
+
+  The following is a list of provided IDs and clock names on Kirkwood and Dove:
+   0 = tclk   (Internal Bus clock)
+   1 = cpuclk (CPU0 clock)
+   2 = l2clk  (L2 Cache clock derived from CPU0 clock)
+   3 = ddrclk (DDR controller clock derived from CPU0 clock)
+
+  The following is a list of provided IDs and clock names on Orion5x:
+   0 = tclk   (Internal Bus clock)
+   1 = cpuclk (CPU0 clock)
+   2 = ddrclk (DDR controller clock derived from CPU0 clock)
+
+properties:
+  compatible:
+    enum:
+      - marvell,armada-370-core-clock
+      - marvell,armada-375-core-clock
+      - marvell,armada-380-core-clock
+      - marvell,armada-390-core-clock
+      - marvell,armada-xp-core-clock
+      - marvell,dove-core-clock
+      - marvell,kirkwood-core-clock
+      - marvell,mv88f5181-core-clock
+      - marvell,mv88f5182-core-clock
+      - marvell,mv88f5281-core-clock
+      - marvell,mv88f6180-core-clock
+      - marvell,mv88f6183-core-clock
+      - marvell,mv98dx1135-core-clock
+      - marvell,mv98dx3236-core-clock
+
+  reg:
+    maxItems: 1
+
+  '#clock-cells':
+    const: 1
+
+  clock-output-names:
+    description: Overwrite default clock output names.
+
+required:
+  - compatible
+  - reg
+  - '#clock-cells'
+
+additionalProperties: false

Bindings/clock/marvell-armada-370-gating-clock.yaml

@@ -0,0 +1,227 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+---
+$id: http://devicetree.org/schemas/clock/marvell-armada-370-gating-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Marvell EBU SoC gating-clock
+
+maintainers:
+  - Andrew Lunn <andrew@lunn.ch>
+  - Gregory Clement <gregory.clement@bootlin.com>
+
+description: >
+  Marvell Armada 370/375/380/385/39x/XP, Dove and Kirkwood allow some peripheral
+  clocks to be gated to save some power. The clock ID is directly mapped to the
+  corresponding clock gating control bit in HW to ease manual clock lookup in
+  datasheet.
+
+  The following is a list of provided IDs for Armada 370:
+
+    ID    Clock    Peripheral
+    -----------------------------------
+    0     Audio    AC97 Cntrl
+    1     pex0_en  PCIe 0 Clock out
+    2     pex1_en  PCIe 1 Clock out
+    3     ge1      Gigabit Ethernet 1
+    4     ge0      Gigabit Ethernet 0
+    5     pex0     PCIe Cntrl 0
+    9     pex1     PCIe Cntrl 1
+    15    sata0    SATA Host 0
+    17    sdio     SDHCI Host
+    23    crypto   CESA (crypto engine)
+    25    tdm      Time Division Mplx
+    28    ddr      DDR Cntrl
+    30    sata1   SATA Host 0
+
+  The following is a list of provided IDs for Armada 375:
+
+    ID    Clock           Peripheral
+    -----------------------------------
+    2     mu              Management Unit
+    3     pp              Packet Processor
+    4     ptp             PTP
+    5     pex0            PCIe 0 Clock out
+    6     pex1            PCIe 1 Clock out
+    8     audio           Audio Cntrl
+    11    nd_clk          Nand Flash Cntrl
+    14    sata0_link      SATA 0 Link
+    15    sata0_core      SATA 0 Core
+    16    usb3            USB3 Host
+    17    sdio            SDHCI Host
+    18    usb             USB Host
+    19    gop             Gigabit Ethernet MAC
+    20    sata1_link      SATA 1 Link
+    21    sata1_core      SATA 1 Core
+    22    xor0            XOR DMA 0
+    23    xor1            XOR DMA 0
+    24    copro           Coprocessor
+    25    tdm             Time Division Mplx
+    28    crypto0_enc     Cryptographic Unit Port 0 Encryption
+    29    crypto0_core    Cryptographic Unit Port 0 Core
+    30    crypto1_enc     Cryptographic Unit Port 1 Encryption
+    31    crypto1_core    Cryptographic Unit Port 1 Core
+
+  The following is a list of provided IDs for Armada 380/385:
+
+    ID    Clock           Peripheral
+    -----------------------------------
+    0     audio           Audio
+    2     ge2             Gigabit Ethernet 2
+    3     ge1             Gigabit Ethernet 1
+    4     ge0             Gigabit Ethernet 0
+    5     pex1            PCIe 1
+    6     pex2            PCIe 2
+    7     pex3            PCIe 3
+    8     pex0            PCIe 0
+    9     usb3h0          USB3 Host 0
+    10    usb3h1          USB3 Host 1
+    11    usb3d           USB3 Device
+    13    bm              Buffer Management
+    14    crypto0z        Cryptographic 0 Z
+    15    sata0           SATA 0
+    16    crypto1z        Cryptographic 1 Z
+    17    sdio            SDIO
+    18    usb2            USB 2
+    21    crypto1         Cryptographic 1
+    22    xor0            XOR 0
+    23    crypto0         Cryptographic 0
+    25    tdm             Time Division Multiplexing
+    28    xor1            XOR 1
+    30    sata1           SATA 1
+
+  The following is a list of provided IDs for Armada 39x:
+
+    ID    Clock           Peripheral
+    -----------------------------------
+    5     pex1            PCIe 1
+    6     pex2            PCIe 2
+    7     pex3            PCIe 3
+    8     pex0            PCIe 0
+    9     usb3h0          USB3 Host 0
+    10    usb3h1          USB3 Host 1
+    15    sata0           SATA 0
+    17    sdio            SDIO
+    22    xor0            XOR 0
+    28    xor1            XOR 1
+
+  The following is a list of provided IDs for Armada XP:
+
+    ID    Clock           Peripheral
+    -----------------------------------
+    0     audio           Audio Cntrl
+    1     ge3             Gigabit Ethernet 3
+    2     ge2             Gigabit Ethernet 2
+    3     ge1             Gigabit Ethernet 1
+    4     ge0             Gigabit Ethernet 0
+    5     pex0            PCIe Cntrl 0
+    6     pex1            PCIe Cntrl 1
+    7     pex2            PCIe Cntrl 2
+    8     pex3            PCIe Cntrl 3
+    13    bp
+    14    sata0lnk
+    15    sata0           SATA Host 0
+    16    lcd             LCD Cntrl
+    17    sdio            SDHCI Host
+    18    usb0            USB Host 0
+    19    usb1            USB Host 1
+    20    usb2            USB Host 2
+    22    xor0            XOR DMA 0
+    23    crypto          CESA engine
+    25    tdm             Time Division Mplx
+    28    xor1            XOR DMA 1
+    29    sata1lnk
+    30    sata1           SATA Host 1
+
+  The following is a list of provided IDs for 98dx3236:
+
+    ID    Clock           Peripheral
+    -----------------------------------
+    3     ge1             Gigabit Ethernet 1
+    4     ge0             Gigabit Ethernet 0
+    5     pex0            PCIe Cntrl 0
+    17    sdio            SDHCI Host
+    18    usb0            USB Host 0
+    22    xor0            XOR DMA 0
+
+  The following is a list of provided IDs for Dove:
+
+  ID    Clock           Peripheral
+  -----------------------------------
+    0     usb0            USB Host 0
+    1     usb1            USB Host 1
+    2     ge              Gigabit Ethernet
+    3     sata            SATA Host
+    4     pex0            PCIe Cntrl 0
+    5     pex1            PCIe Cntrl 1
+    8     sdio0           SDHCI Host 0
+    9     sdio1           SDHCI Host 1
+    10    nand            NAND Cntrl
+    11    camera          Camera Cntrl
+    12    i2s0            I2S Cntrl 0
+    13    i2s1            I2S Cntrl 1
+    15    crypto          CESA engine
+    21    ac97            AC97 Cntrl
+    22    pdma            Peripheral DMA
+    23    xor0            XOR DMA 0
+    24    xor1            XOR DMA 1
+    30    gephy           Gigabit Ethernet PHY
+    Note: gephy(30) is implemented as a parent clock of ge(2)
+
+  The following is a list of provided IDs for Kirkwood:
+
+    ID    Clock           Peripheral
+    -----------------------------------
+    0     ge0             Gigabit Ethernet 0
+    2     pex0            PCIe Cntrl 0
+    3     usb0            USB Host 0
+    4     sdio            SDIO Cntrl
+    5     tsu             Transp. Stream Unit
+    6     dunit           SDRAM Cntrl
+    7     runit           Runit
+    8     xor0            XOR DMA 0
+    9     audio           I2S Cntrl 0
+    14    sata0           SATA Host 0
+    15    sata1           SATA Host 1
+    16    xor1            XOR DMA 1
+    17    crypto          CESA engine
+    18    pex1            PCIe Cntrl 1
+    19    ge1             Gigabit Ethernet 1
+    20    tdm             Time Division Mplx
+
+properties:
+  compatible:
+    enum:
+      - marvell,armada-370-gating-clock
+      - marvell,armada-375-gating-clock
+      - marvell,armada-380-gating-clock
+      - marvell,armada-390-gating-clock
+      - marvell,armada-xp-gating-clock
+      - marvell,mv98dx3236-gating-clock
+      - marvell,dove-gating-clock
+      - marvell,kirkwood-gating-clock
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  '#clock-cells':
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    clock-controller@d0038 {
+        compatible = "marvell,dove-gating-clock";
+        reg = <0xd0038 0x4>;
+        /* default parent clock is tclk */
+        clocks = <&core_clk 0>;
+        #clock-cells = <1>;
+    };

Bindings/clock/maxim,max9485.txt

@@ -1,59 +0,0 @@
-Devicetree bindings for Maxim MAX9485 Programmable Audio Clock Generator
-
-This device exposes 4 clocks in total:
-
-- MAX9485_MCLKOUT: 	A gated, buffered output of the input clock of 27 MHz
-- MAX9485_CLKOUT:	A PLL that can be configured to 16 different discrete
-			frequencies
-- MAX9485_CLKOUT[1,2]:	Two gated outputs for MAX9485_CLKOUT
-
-MAX9485_CLKOUT[1,2] are children of MAX9485_CLKOUT which upchain all rate set
-requests.
-
-Required properties:
-- compatible:	"maxim,max9485"
-- clocks:	Input clock, must provide 27.000 MHz
-- clock-names:	Must be set to "xclk"
-- #clock-cells: From common clock binding; shall be set to 1
-
-Optional properties:
-- reset-gpios:		GPIO descriptor connected to the #RESET input pin
-- vdd-supply:		A regulator node for Vdd
-- clock-output-names:	Name of output clocks, as defined in common clock
-			bindings
-
-If not explicitly set, the output names are "mclkout", "clkout", "clkout1"
-and "clkout2".
-
-Clocks are defined as preprocessor macros in the dt-binding header.
-
-Example:
-
-	#include <dt-bindings/clock/maxim,max9485.h>
-
-	xo-27mhz: xo-27mhz {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <27000000>;
-	};
-
-	&i2c0 {
-		max9485: audio-clock@63 {
-			reg = <0x63>;
-			compatible = "maxim,max9485";
-			clock-names = "xclk";
-			clocks = <&xo-27mhz>;
-			reset-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
-			vdd-supply = <&3v3-reg>;
-			#clock-cells = <1>;
-		};
-	};
-
-	// Clock consumer node
-
-	foo@0 {
-		compatible = "bar,foo";
-		/* ... */
-		clock-names = "foo-input-clk";
-		clocks = <&max9485 MAX9485_CLKOUT1>;
-	};

Bindings/clock/maxim,max9485.yaml

@@ -0,0 +1,82 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/maxim,max9485.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Maxim MAX9485 Programmable Audio Clock Generator
+
+maintainers:
+  - Daniel Mack <daniel@zonque.org>
+
+description: >
+  Maxim MAX9485 Programmable Audio Clock Generator exposes 4 clocks in total:
+
+    - MAX9485_MCLKOUT:  A gated, buffered output of the input clock of 27 MHz
+    - MAX9485_CLKOUT:   A PLL that can be configured to 16 different discrete
+                        frequencies
+    - MAX9485_CLKOUT[1,2]:  Two gated outputs for MAX9485_CLKOUT
+
+  MAX9485_CLKOUT[1,2] are children of MAX9485_CLKOUT which upchain all rate set
+  requests.
+
+properties:
+  compatible:
+    const: maxim,max9485
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    description: Input clock. Must provide 27 MHz
+    maxItems: 1
+
+  clock-names:
+    items:
+      - const: xclk
+
+  '#clock-cells':
+    const: 1
+
+  reset-gpios:
+    description: >
+      GPIO descriptor connected to the #RESET input pin
+
+  vdd-supply:
+    description: A regulator node for Vdd
+
+  clock-output-names:
+    description: Name of output clocks, as defined in common clock bindings
+    items:
+      - const: mclkout
+      - const: clkout
+      - const: clkout1
+      - const: clkout2
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/gpio/gpio.h>
+
+    i2c {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        clock-controller@63 {
+            compatible = "maxim,max9485";
+            reg = <0x63>;
+            #clock-cells = <1>;
+            clock-names = "xclk";
+            clocks = <&xo_27mhz>;
+            reset-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
+            vdd-supply = <&reg_3v3>;
+        };
+    };

Bindings/clock/mediatek,mtmips-sysc.yaml

@@ -26,18 +26,22 @@ description: |
 
 properties:
   compatible:
-    items:
-      - enum:
-          - ralink,mt7620-sysc
-          - ralink,mt7628-sysc
-          - ralink,mt7688-sysc
-          - ralink,rt2880-sysc
-          - ralink,rt3050-sysc
-          - ralink,rt3052-sysc
-          - ralink,rt3352-sysc
-          - ralink,rt3883-sysc
-          - ralink,rt5350-sysc
-      - const: syscon
+    oneOf:
+      - items:
+          - enum:
+              - ralink,mt7620-sysc
+              - ralink,mt7688-sysc
+              - ralink,rt2880-sysc
+              - ralink,rt3050-sysc
+              - ralink,rt3052-sysc
+              - ralink,rt3352-sysc
+              - ralink,rt3883-sysc
+              - ralink,rt5350-sysc
+          - const: syscon
+      - items:
+          - const: ralink,mt7628-sysc
+          - const: ralink,mt7688-sysc
+          - const: syscon
 
   reg:
     maxItems: 1

Bindings/clock/microchip,pic32.txt

@@ -1,39 +0,0 @@
-Microchip PIC32 Clock Controller Binding
-----------------------------------------
-Microchip clock controller is consists of few oscillators, PLL, multiplexer
-and few divider modules.
-
-This binding uses common clock bindings.
-[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-
-Required properties:
-- compatible: shall be "microchip,pic32mzda-clk".
-- reg: shall contain base address and length of clock registers.
-- #clock-cells: shall be 1.
-
-Optional properties:
-- microchip,pic32mzda-sosc: shall be added only if platform has
-  secondary oscillator connected.
-
-Example:
-	rootclk: clock-controller@1f801200 {
-		compatible = "microchip,pic32mzda-clk";
-		reg = <0x1f801200 0x200>;
-		#clock-cells = <1>;
-		/* optional */
-		microchip,pic32mzda-sosc;
-	};
-
-
-The clock consumer shall specify the desired clock-output of the clock
-controller (as defined in [2]) by specifying output-id in its "clock"
-phandle cell.
-[2] include/dt-bindings/clock/microchip,pic32-clock.h
-
-For example for UART2:
-uart2: serial@2 {
-	compatible = "microchip,pic32mzda-uart";
-	reg = <>;
-	interrupts = <>;
-	clocks = <&rootclk PB2CLK>;
-};

Bindings/clock/microchip,pic32mzda-clk.yaml

@@ -0,0 +1,45 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/microchip,pic32mzda-clk.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip PIC32MZDA Clock Controller
+
+maintainers:
+  - Purna Chandra Mandal <purna.mandal@microchip.com>
+
+description:
+  Microchip clock controller consists of a few oscillators, PLL, multiplexer
+  and divider modules.
+
+properties:
+  compatible:
+    const: microchip,pic32mzda-clk
+
+  reg:
+    maxItems: 1
+
+  '#clock-cells':
+    const: 1
+
+  microchip,pic32mzda-sosc:
+    description: Presence of secondary oscillator.
+    type: boolean
+
+required:
+  - compatible
+  - reg
+  - "#clock-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    clock-controller@1f801200 {
+        compatible = "microchip,pic32mzda-clk";
+        reg = <0x1f801200 0x200>;
+        #clock-cells = <1>;
+        /* optional */
+        microchip,pic32mzda-sosc;
+    };

Bindings/clock/moxa,moxart-clock.txt

@@ -1,48 +0,0 @@
-Device Tree Clock bindings for arch-moxart
-
-This binding uses the common clock binding[1].
-
-[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-
-MOXA ART SoCs allow to determine PLL output and APB frequencies
-by reading registers holding multiplier and divisor information.
-
-
-PLL:
-
-Required properties:
-- compatible : Must be "moxa,moxart-pll-clock"
-- #clock-cells : Should be 0
-- reg : Should contain registers location and length
-- clocks : Should contain phandle + clock-specifier for the parent clock
-
-Optional properties:
-- clock-output-names : Should contain clock name
-
-
-APB:
-
-Required properties:
-- compatible : Must be "moxa,moxart-apb-clock"
-- #clock-cells : Should be 0
-- reg : Should contain registers location and length
-- clocks : Should contain phandle + clock-specifier for the parent clock
-
-Optional properties:
-- clock-output-names : Should contain clock name
-
-
-For example:
-
-	clk_pll: clk_pll@98100000 {
-		compatible = "moxa,moxart-pll-clock";
-		#clock-cells = <0>;
-		reg = <0x98100000 0x34>;
-	};
-
-	clk_apb: clk_apb@98100000 {
-		compatible = "moxa,moxart-apb-clock";
-		#clock-cells = <0>;
-		reg = <0x98100000 0x34>;
-		clocks = <&clk_pll>;
-	};

Bindings/clock/moxa,moxart-clock.yaml

@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/moxa,moxart-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MOXA ART Clock Controllers
+
+maintainers:
+  - Krzysztof Kozlowski <krzk@kernel.org>
+
+description:
+  MOXA ART SoCs allow to determine PLL output and APB frequencies by reading
+  registers holding multiplier and divisor information.
+
+properties:
+  compatible:
+    enum:
+      - moxa,moxart-apb-clock
+      - moxa,moxart-pll-clock
+
+  "#clock-cells":
+    const: 0
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  clock-output-names: true
+
+additionalProperties: false
+
+required:
+  - compatible
+  - "#clock-cells"
+  - reg

Bindings/clock/mvebu-core-clock.txt

@@ -1,87 +0,0 @@
-* Core Clock bindings for Marvell MVEBU SoCs
-
-Marvell MVEBU SoCs usually allow to determine core clock frequencies by
-reading the Sample-At-Reset (SAR) register. The core clock consumer should
-specify the desired clock by having the clock ID in its "clocks" phandle cell.
-
-The following is a list of provided IDs and clock names on Armada 370/XP:
- 0 = tclk    (Internal Bus clock)
- 1 = cpuclk  (CPU clock)
- 2 = nbclk   (L2 Cache clock)
- 3 = hclk    (DRAM control clock)
- 4 = dramclk (DDR clock)
-
-The following is a list of provided IDs and clock names on Armada 375:
- 0 = tclk    (Internal Bus clock)
- 1 = cpuclk  (CPU clock)
- 2 = l2clk   (L2 Cache clock)
- 3 = ddrclk  (DDR clock)
-
-The following is a list of provided IDs and clock names on Armada 380/385:
- 0 = tclk    (Internal Bus clock)
- 1 = cpuclk  (CPU clock)
- 2 = l2clk   (L2 Cache clock)
- 3 = ddrclk  (DDR clock)
-
-The following is a list of provided IDs and clock names on Armada 39x:
- 0 = tclk    (Internal Bus clock)
- 1 = cpuclk  (CPU clock)
- 2 = nbclk   (Coherent Fabric clock)
- 3 = hclk    (SDRAM Controller Internal Clock)
- 4 = dclk    (SDRAM Interface Clock)
- 5 = refclk  (Reference Clock)
-
-The following is a list of provided IDs and clock names on 98dx3236:
- 0 = tclk    (Internal Bus clock)
- 1 = cpuclk  (CPU clock)
- 2 = ddrclk   (DDR clock)
- 3 = mpll    (MPLL Clock)
-
-The following is a list of provided IDs and clock names on Kirkwood and Dove:
- 0 = tclk   (Internal Bus clock)
- 1 = cpuclk (CPU0 clock)
- 2 = l2clk  (L2 Cache clock derived from CPU0 clock)
- 3 = ddrclk (DDR controller clock derived from CPU0 clock)
-
-The following is a list of provided IDs and clock names on Orion5x:
- 0 = tclk   (Internal Bus clock)
- 1 = cpuclk (CPU0 clock)
- 2 = ddrclk (DDR controller clock derived from CPU0 clock)
-
-Required properties:
-- compatible : shall be one of the following:
-	"marvell,armada-370-core-clock" - For Armada 370 SoC core clocks
-	"marvell,armada-375-core-clock" - For Armada 375 SoC core clocks
-	"marvell,armada-380-core-clock" - For Armada 380/385 SoC core clocks
-	"marvell,armada-390-core-clock" - For Armada 39x SoC core clocks
-	"marvell,armada-xp-core-clock" - For Armada XP SoC core clocks
-	"marvell,mv98dx3236-core-clock" - For 98dx3236 family SoC core clocks
-	"marvell,dove-core-clock" - for Dove SoC core clocks
-	"marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180)
-	"marvell,mv88f6180-core-clock" - for Kirkwood MV88f6180 SoC
-	"marvell,mv98dx1135-core-clock" - for Kirkwood 98dx1135 SoC
-	"marvell,mv88f5181-core-clock" - for Orion MV88F5181 SoC
-	"marvell,mv88f5182-core-clock" - for Orion MV88F5182 SoC
-	"marvell,mv88f5281-core-clock" - for Orion MV88F5281 SoC
-	"marvell,mv88f6183-core-clock" - for Orion MV88F6183 SoC
-- reg : shall be the register address of the Sample-At-Reset (SAR) register
-- #clock-cells : from common clock binding; shall be set to 1
-
-Optional properties:
-- clock-output-names : from common clock binding; allows overwrite default clock
-	output names ("tclk", "cpuclk", "l2clk", "ddrclk")
-
-Example:
-
-core_clk: core-clocks@d0214 {
-	compatible = "marvell,dove-core-clock";
-	reg = <0xd0214 0x4>;
-	#clock-cells = <1>;
-};
-
-spi0: spi@10600 {
-	compatible = "marvell,orion-spi";
-	/* ... */
-	/* get tclk from core clock provider */
-	clocks = <&core_clk 0>;
-};

Bindings/clock/mvebu-corediv-clock.txt

@@ -1,23 +0,0 @@
-* Core Divider Clock bindings for Marvell MVEBU SoCs
-
-The following is a list of provided IDs and clock names on Armada 370/XP:
- 0 = nand (NAND clock)
-
-Required properties:
-- compatible : must be "marvell,armada-370-corediv-clock",
-		       "marvell,armada-375-corediv-clock",
-		       "marvell,armada-380-corediv-clock",
-                       "marvell,mv98dx3236-corediv-clock",
-
-- reg : must be the register address of Core Divider control register
-- #clock-cells : from common clock binding; shall be set to 1
-- clocks : must be set to the parent's phandle
-
-Example:
-
-corediv_clk: corediv-clocks@18740 {
-	compatible = "marvell,armada-370-corediv-clock";
-	reg = <0x18740 0xc>;
-	#clock-cells = <1>;
-	clocks = <&pll>;
-};

Bindings/clock/mvebu-cpu-clock.txt

@@ -1,23 +0,0 @@
-Device Tree Clock bindings for cpu clock of Marvell EBU platforms
-
-Required properties:
-- compatible : shall be one of the following:
-	"marvell,armada-xp-cpu-clock" - cpu clocks for Armada XP
-	"marvell,mv98dx3236-cpu-clock" - cpu clocks for 98DX3236 SoC
-- reg : Address and length of the clock complex register set, followed
-        by address and length of the PMU DFS registers
-- #clock-cells : should be set to 1.
-- clocks : shall be the input parent clock phandle for the clock.
-
-cpuclk: clock-complex@d0018700 {
-	#clock-cells = <1>;
-	compatible = "marvell,armada-xp-cpu-clock";
-	reg = <0xd0018700 0xA0>, <0x1c054 0x10>;
-	clocks = <&coreclk 1>;
-}
-
-cpu@0 {
-	compatible = "marvell,sheeva-v7";
-	reg = <0>;
-	clocks = <&cpuclk 0>;
-};

Bindings/clock/mvebu-gated-clock.txt

@@ -1,205 +0,0 @@
-* Gated Clock bindings for Marvell EBU SoCs
-
-Marvell Armada 370/375/380/385/39x/XP, Dove and Kirkwood allow some
-peripheral clocks to be gated to save some power. The clock consumer
-should specify the desired clock by having the clock ID in its
-"clocks" phandle cell. The clock ID is directly mapped to the
-corresponding clock gating control bit in HW to ease manual clock
-lookup in datasheet.
-
-The following is a list of provided IDs for Armada 370:
-ID	Clock	Peripheral
------------------------------------
-0	Audio	AC97 Cntrl
-1	pex0_en	PCIe 0 Clock out
-2	pex1_en	PCIe 1 Clock out
-3	ge1	Gigabit Ethernet 1
-4	ge0	Gigabit Ethernet 0
-5	pex0	PCIe Cntrl 0
-9	pex1	PCIe Cntrl 1
-15	sata0	SATA Host 0
-17	sdio	SDHCI Host
-23	crypto	CESA (crypto engine)
-25	tdm	Time Division Mplx
-28	ddr	DDR Cntrl
-30	sata1	SATA Host 0
-
-The following is a list of provided IDs for Armada 375:
-ID	Clock		Peripheral
------------------------------------
-2	mu		Management Unit
-3	pp		Packet Processor
-4	ptp		PTP
-5	pex0		PCIe 0 Clock out
-6	pex1		PCIe 1 Clock out
-8	audio		Audio Cntrl
-11	nd_clk		Nand Flash Cntrl
-14	sata0_link	SATA 0 Link
-15	sata0_core	SATA 0 Core
-16	usb3		USB3 Host
-17	sdio		SDHCI Host
-18	usb		USB Host
-19	gop		Gigabit Ethernet MAC
-20	sata1_link	SATA 1 Link
-21	sata1_core	SATA 1 Core
-22	xor0		XOR DMA 0
-23	xor1		XOR DMA 0
-24	copro		Coprocessor
-25	tdm		Time Division Mplx
-28	crypto0_enc	Cryptographic Unit Port 0 Encryption
-29	crypto0_core	Cryptographic Unit Port 0 Core
-30	crypto1_enc	Cryptographic Unit Port 1 Encryption
-31	crypto1_core	Cryptographic Unit Port 1 Core
-
-The following is a list of provided IDs for Armada 380/385:
-ID	Clock		Peripheral
------------------------------------
-0	audio		Audio
-2	ge2		Gigabit Ethernet 2
-3	ge1		Gigabit Ethernet 1
-4	ge0		Gigabit Ethernet 0
-5	pex1		PCIe 1
-6	pex2		PCIe 2
-7	pex3		PCIe 3
-8	pex0		PCIe 0
-9	usb3h0		USB3 Host 0
-10	usb3h1		USB3 Host 1
-11	usb3d		USB3 Device
-13	bm		Buffer Management
-14	crypto0z	Cryptographic 0 Z
-15	sata0		SATA 0
-16	crypto1z	Cryptographic 1 Z
-17	sdio		SDIO
-18	usb2		USB 2
-21	crypto1		Cryptographic 1
-22	xor0		XOR 0
-23	crypto0		Cryptographic 0
-25	tdm		Time Division Multiplexing
-28	xor1		XOR 1
-30	sata1		SATA 1
-
-The following is a list of provided IDs for Armada 39x:
-ID	Clock		Peripheral
------------------------------------
-5	pex1		PCIe 1
-6	pex2		PCIe 2
-7	pex3		PCIe 3
-8	pex0		PCIe 0
-9	usb3h0		USB3 Host 0
-10	usb3h1		USB3 Host 1
-15	sata0		SATA 0
-17	sdio		SDIO
-22	xor0		XOR 0
-28	xor1		XOR 1
-
-The following is a list of provided IDs for Armada XP:
-ID	Clock	Peripheral
------------------------------------
-0	audio	Audio Cntrl
-1	ge3	Gigabit Ethernet 3
-2	ge2	Gigabit Ethernet 2
-3	ge1	Gigabit Ethernet 1
-4	ge0	Gigabit Ethernet 0
-5	pex0	PCIe Cntrl 0
-6	pex1	PCIe Cntrl 1
-7	pex2	PCIe Cntrl 2
-8	pex3	PCIe Cntrl 3
-13	bp
-14	sata0lnk
-15	sata0	SATA Host 0
-16	lcd	LCD Cntrl
-17	sdio	SDHCI Host
-18	usb0	USB Host 0
-19	usb1	USB Host 1
-20	usb2	USB Host 2
-22	xor0	XOR DMA 0
-23	crypto	CESA engine
-25	tdm	Time Division Mplx
-28	xor1	XOR DMA 1
-29	sata1lnk
-30	sata1	SATA Host 1
-
-The following is a list of provided IDs for 98dx3236:
-ID	Clock	Peripheral
------------------------------------
-3	ge1	Gigabit Ethernet 1
-4	ge0	Gigabit Ethernet 0
-5	pex0	PCIe Cntrl 0
-17	sdio	SDHCI Host
-18	usb0	USB Host 0
-22	xor0	XOR DMA 0
-
-The following is a list of provided IDs for Dove:
-ID	Clock	Peripheral
------------------------------------
-0	usb0	USB Host 0
-1	usb1	USB Host 1
-2	ge	Gigabit Ethernet
-3	sata	SATA Host
-4	pex0	PCIe Cntrl 0
-5	pex1	PCIe Cntrl 1
-8	sdio0	SDHCI Host 0
-9	sdio1	SDHCI Host 1
-10	nand	NAND Cntrl
-11	camera	Camera Cntrl
-12	i2s0	I2S Cntrl 0
-13	i2s1	I2S Cntrl 1
-15	crypto	CESA engine
-21	ac97	AC97 Cntrl
-22	pdma	Peripheral DMA
-23	xor0	XOR DMA 0
-24	xor1	XOR DMA 1
-30	gephy	Gigabit Ethernel PHY
-Note: gephy(30) is implemented as a parent clock of ge(2)
-
-The following is a list of provided IDs for Kirkwood:
-ID	Clock	Peripheral
------------------------------------
-0	ge0	Gigabit Ethernet 0
-2	pex0	PCIe Cntrl 0
-3	usb0	USB Host 0
-4	sdio	SDIO Cntrl
-5	tsu	Transp. Stream Unit
-6	dunit	SDRAM Cntrl
-7	runit	Runit
-8	xor0	XOR DMA 0
-9	audio	I2S Cntrl 0
-14	sata0	SATA Host 0
-15	sata1	SATA Host 1
-16	xor1	XOR DMA 1
-17	crypto	CESA engine
-18	pex1	PCIe Cntrl 1
-19	ge1	Gigabit Ethernet 1
-20	tdm	Time Division Mplx
-
-Required properties:
-- compatible : shall be one of the following:
-	"marvell,armada-370-gating-clock" - for Armada 370 SoC clock gating
-	"marvell,armada-375-gating-clock" - for Armada 375 SoC clock gating
-	"marvell,armada-380-gating-clock" - for Armada 380/385 SoC clock gating
-	"marvell,armada-390-gating-clock" - for Armada 39x SoC clock gating
-	"marvell,armada-xp-gating-clock" - for Armada XP SoC clock gating
-	"marvell,mv98dx3236-gating-clock" - for 98dx3236 SoC clock gating
-	"marvell,dove-gating-clock" - for Dove SoC clock gating
-	"marvell,kirkwood-gating-clock" - for Kirkwood SoC clock gating
-- reg : shall be the register address of the Clock Gating Control register
-- #clock-cells : from common clock binding; shall be set to 1
-
-Optional properties:
-- clocks : default parent clock phandle (e.g. tclk)
-
-Example:
-
-gate_clk: clock-gating-control@d0038 {
-	compatible = "marvell,dove-gating-clock";
-	reg = <0xd0038 0x4>;
-	/* default parent clock is tclk */
-	clocks = <&core_clk 0>;
-	#clock-cells = <1>;
-};
-
-sdio0: sdio@92000 {
-	compatible = "marvell,dove-sdhci";
-	/* get clk gate bit 8 (sdio0) */
-	clocks = <&gate_clk 8>;
-};

Bindings/clock/nspire-clock.txt

@@ -1,24 +0,0 @@
-TI-NSPIRE Clocks
-
-Required properties:
-- compatible: Valid compatible properties include:
-	"lsi,nspire-cx-ahb-divider" for the AHB divider in the CX model
-	"lsi,nspire-classic-ahb-divider" for the AHB divider in the older model
-	"lsi,nspire-cx-clock" for the base clock in the CX model
-	"lsi,nspire-classic-clock" for the base clock in the older model
-
-- reg: Physical base address of the controller and length of memory mapped
-	region.
-
-Optional:
-- clocks: For the "nspire-*-ahb-divider" compatible clocks, this is the parent
-	clock where it divides the rate from.
-
-Example:
-
-ahb_clk {
-	#clock-cells = <0>;
-	compatible = "lsi,nspire-cx-clock";
-	reg = <0x900B0000 0x4>;
-	clocks = <&base_clk>;
-};

Bindings/clock/nuvoton,npcm750-clk.txt

@@ -1,100 +0,0 @@
-* Nuvoton NPCM7XX Clock Controller
-
-Nuvoton Poleg BMC NPCM7XX contains an integrated clock controller, which
-generates and supplies clocks to all modules within the BMC.
-
-External clocks:
-
-There are six fixed clocks that are generated outside the BMC. All clocks are of
-a known fixed value that cannot be changed. clk_refclk, clk_mcbypck and
-clk_sysbypck are inputs to the clock controller.
-clk_rg1refck, clk_rg2refck and clk_xin are external clocks suppling the
-network. They are set on the device tree, but not used by the clock module. The
-network devices use them directly.
-Example can be found below.
-
-All available clocks are defined as preprocessor macros in:
-dt-bindings/clock/nuvoton,npcm7xx-clock.h
-and can be reused as DT sources.
-
-Required Properties of clock controller:
-
-	- compatible: "nuvoton,npcm750-clk" : for clock controller of Nuvoton
-		  Poleg BMC NPCM750
-
-	- reg: physical base address of the clock controller and length of
-		memory mapped region.
-
-	- #clock-cells: should be 1.
-
-Example: Clock controller node:
-
-	clk: clock-controller@f0801000 {
-		compatible = "nuvoton,npcm750-clk";
-		#clock-cells = <1>;
-		reg = <0xf0801000 0x1000>;
-		clock-names = "refclk", "sysbypck", "mcbypck";
-		clocks = <&clk_refclk>, <&clk_sysbypck>, <&clk_mcbypck>;
-	};
-
-Example: Required external clocks for network:
-
-	/* external reference clock */
-	clk_refclk: clk-refclk {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <25000000>;
-		clock-output-names = "refclk";
-	};
-
-	/* external reference clock for cpu. float in normal operation */
-	clk_sysbypck: clk-sysbypck {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <800000000>;
-		clock-output-names = "sysbypck";
-	};
-
-	/* external reference clock for MC. float in normal operation */
-	clk_mcbypck: clk-mcbypck {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <800000000>;
-		clock-output-names = "mcbypck";
-	};
-
-	 /* external clock signal rg1refck, supplied by the phy */
-	clk_rg1refck: clk-rg1refck {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <125000000>;
-		clock-output-names = "clk_rg1refck";
-	};
-
-	 /* external clock signal rg2refck, supplied by the phy */
-	clk_rg2refck: clk-rg2refck {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <125000000>;
-		clock-output-names = "clk_rg2refck";
-	};
-
-	clk_xin: clk-xin {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <50000000>;
-		clock-output-names = "clk_xin";
-	};
-
-
-Example: GMAC controller node that consumes two clocks: a generated clk by the
-clock controller and a fixed clock from DT (clk_rg1refck).
-
-	ethernet0: ethernet@f0802000 {
-		compatible = "snps,dwmac";
-		reg = <0xf0802000 0x2000>;
-		interrupts = <0 14 4>;
-		interrupt-names = "macirq";
-		clocks	= <&clk_rg1refck>, <&clk NPCM7XX_CLK_AHB>;
-		clock-names = "stmmaceth", "clk_gmac";
-	};

Bindings/clock/nuvoton,npcm750-clk.yaml

@@ -0,0 +1,66 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/nuvoton,npcm750-clk.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Nuvoton NPCM7XX Clock Controller
+
+maintainers:
+  - Tali Perry <tali.perry1@gmail.com>
+
+description: >
+  Nuvoton Poleg BMC NPCM7XX contains an integrated clock controller, which
+  generates and supplies clocks to all modules within the BMC.
+
+  External clocks:
+
+  There are six fixed clocks that are generated outside the BMC. All clocks are of
+  a known fixed value that cannot be changed. clk_refclk, clk_mcbypck and
+  clk_sysbypck are inputs to the clock controller.
+  clk_rg1refck, clk_rg2refck and clk_xin are external clocks suppling the
+  network. They are set on the device tree, but not used by the clock module. The
+  network devices use them directly.
+
+  All available clocks are defined as preprocessor macros in:
+  dt-bindings/clock/nuvoton,npcm7xx-clock.h
+  and can be reused as DT sources.
+
+properties:
+  compatible:
+    const: nuvoton,npcm750-clk
+
+  reg:
+    maxItems: 1
+
+  '#clock-cells':
+    const: 1
+
+  clock-names:
+    items:
+      - const: refclk
+      - const: sysbypck
+      - const: mcbypck
+
+  clocks:
+    items:
+      - description: refclk
+      - description: sysbypck
+      - description: mcbypck
+
+required:
+  - compatible
+  - reg
+  - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    clock-controller@f0801000 {
+        compatible = "nuvoton,npcm750-clk";
+        #clock-cells = <1>;
+        reg = <0xf0801000 0x1000>;
+        clock-names = "refclk", "sysbypck", "mcbypck";
+        clocks = <&clk_refclk>, <&clk_sysbypck>, <&clk_mcbypck>;
+    };

Bindings/clock/nxp,imx95-blk-ctl.yaml

@@ -13,6 +13,8 @@ properties:
   compatible:
     items:
       - enum:
+          - nxp,imx94-display-csr
+          - nxp,imx94-lvds-csr
           - nxp,imx95-camera-csr
           - nxp,imx95-display-csr
           - nxp,imx95-hsio-blk-ctl

Bindings/clock/nxp,lpc1850-ccu.yaml

@@ -0,0 +1,104 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/nxp,lpc1850-ccu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP LPC1850 Clock Control Unit (CCU)
+
+description:
+  Each CGU base clock has several clock branches which can be turned on
+  or off independently by the Clock Control Units CCU1 or CCU2. The
+  branch clocks are distributed between CCU1 and CCU2.
+
+  Above text taken from NXP LPC1850 User Manual
+
+maintainers:
+  - Frank Li <Frank.Li@nxp.com>
+
+properties:
+  compatible:
+    const: nxp,lpc1850-ccu
+
+  reg:
+    maxItems: 1
+
+  '#clock-cells':
+    const: 1
+
+  clocks:
+    minItems: 1
+    maxItems: 8
+
+  clock-names:
+    minItems: 1
+    maxItems: 8
+    items:
+      enum:
+        - base_usb0_clk
+        - base_periph_clk
+        - base_usb1_clk
+        - base_cpu_clk
+        - base_spifi_clk
+        - base_spi_clk
+        - base_apb1_clk
+        - base_apb3_clk
+        - base_adchs_clk
+        - base_sdio_clk
+        - base_ssp0_clk
+        - base_ssp1_clk
+        - base_uart0_clk
+        - base_uart1_clk
+        - base_uart2_clk
+        - base_uart3_clk
+        - base_audio_clk
+    description:
+      Which branch clocks that are available on the CCU depends on the
+      specific LPC part. Check the user manual for your specific part.
+
+      A list of CCU clocks can be found in dt-bindings/clock/lpc18xx-ccu.h.
+
+required:
+  - compatible
+  - reg
+  - '#clock-cells'
+  - clocks
+  - clock-names
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/lpc18xx-cgu.h>
+
+    clock-controller@40051000 {
+        compatible = "nxp,lpc1850-ccu";
+        reg = <0x40051000 0x1000>;
+        #clock-cells = <1>;
+        clocks = <&cgu BASE_APB3_CLK>, <&cgu BASE_APB1_CLK>,
+                 <&cgu BASE_SPIFI_CLK>, <&cgu BASE_CPU_CLK>,
+                 <&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>,
+                 <&cgu BASE_USB1_CLK>, <&cgu BASE_SPI_CLK>;
+        clock-names = "base_apb3_clk",   "base_apb1_clk",
+                      "base_spifi_clk",  "base_cpu_clk",
+                      "base_periph_clk", "base_usb0_clk",
+                      "base_usb1_clk",   "base_spi_clk";
+    };
+
+  - |
+    #include <dt-bindings/clock/lpc18xx-cgu.h>
+
+    clock-controller@40052000 {
+        compatible = "nxp,lpc1850-ccu";
+        reg = <0x40052000 0x1000>;
+        #clock-cells = <1>;
+        clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>,
+                 <&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>,
+                 <&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>,
+                 <&cgu BASE_SSP0_CLK>,  <&cgu BASE_SDIO_CLK>;
+        clock-names = "base_audio_clk", "base_uart3_clk",
+                      "base_uart2_clk", "base_uart1_clk",
+                      "base_uart0_clk", "base_ssp1_clk",
+                      "base_ssp0_clk",  "base_sdio_clk";
+    };
+

Bindings/clock/nxp,lpc1850-cgu.yaml

@@ -0,0 +1,99 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/nxp,lpc1850-cgu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP LPC1850 Clock Generation Unit (CGU)
+
+description: >
+  The CGU generates multiple independent clocks for the core and the
+  peripheral blocks of the LPC18xx. Each independent clock is called
+  a base clock and itself is one of the inputs to the two Clock
+  Control Units (CCUs) which control the branch clocks to the
+  individual peripherals.
+
+  The CGU selects the inputs to the clock generators from multiple
+  clock sources, controls the clock generation, and routes the outputs
+  of the clock generators through the clock source bus to the output
+  stages. Each output stage provides an independent clock source and
+  corresponds to one of the base clocks for the LPC18xx.
+
+  Above text taken from NXP LPC1850 User Manual.
+
+maintainers:
+  - Frank Li <Frank.Li@nxp.com>
+
+properties:
+  compatible:
+    const: nxp,lpc1850-cgu
+
+  reg:
+    maxItems: 1
+
+  '#clock-cells':
+    const: 1
+    description: |
+      Which base clocks that are available on the CGU depends on the
+      specific LPC part. Base clocks are numbered from 0 to 27.
+
+      Number:         Name:                   Description:
+       0              BASE_SAFE_CLK           Base safe clock (always on) for WWDT
+       1              BASE_USB0_CLK           Base clock for USB0
+       2              BASE_PERIPH_CLK         Base clock for Cortex-M0SUB subsystem,
+                                        SPI, and SGPIO
+       3              BASE_USB1_CLK           Base clock for USB1
+       4              BASE_CPU_CLK            System base clock for ARM Cortex-M core
+                                        and APB peripheral blocks #0 and #2
+       5              BASE_SPIFI_CLK          Base clock for SPIFI
+       6              BASE_SPI_CLK            Base clock for SPI
+       7              BASE_PHY_RX_CLK         Base clock for Ethernet PHY Receive clock
+       8              BASE_PHY_TX_CLK         Base clock for Ethernet PHY Transmit clock
+       9              BASE_APB1_CLK           Base clock for APB peripheral block # 1
+      10              BASE_APB3_CLK           Base clock for APB peripheral block # 3
+      11              BASE_LCD_CLK            Base clock for LCD
+      12              BASE_ADCHS_CLK          Base clock for ADCHS
+      13              BASE_SDIO_CLK           Base clock for SD/MMC
+      14              BASE_SSP0_CLK           Base clock for SSP0
+      15              BASE_SSP1_CLK           Base clock for SSP1
+      16              BASE_UART0_CLK          Base clock for UART0
+      17              BASE_UART1_CLK          Base clock for UART1
+      18              BASE_UART2_CLK          Base clock for UART2
+      19              BASE_UART3_CLK          Base clock for UART3
+      20              BASE_OUT_CLK            Base clock for CLKOUT pin
+      24-21           -                       Reserved
+      25              BASE_AUDIO_CLK          Base clock for audio system (I2S)
+      26              BASE_CGU_OUT0_CLK       Base clock for CGU_OUT0 clock output
+      27              BASE_CGU_OUT1_CLK       Base clock for CGU_OUT1 clock output
+
+      BASE_PERIPH_CLK and BASE_SPI_CLK is only available on LPC43xx.
+      BASE_ADCHS_CLK is only available on LPC4370.
+
+  clocks:
+    maxItems: 5
+
+  clock-indices:
+    minItems: 1
+    maxItems: 28
+
+  clock-output-names:
+    minItems: 1
+    maxItems: 28
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    clock-controller@40050000 {
+        compatible = "nxp,lpc1850-cgu";
+        reg = <0x40050000 0x1000>;
+        #clock-cells = <1>;
+        clocks = <&xtal>, <&creg_clk 1>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>;
+    };
+

Bindings/clock/pistachio-clock.txt

@@ -1,123 +0,0 @@
-Imagination Technologies Pistachio SoC clock controllers
-========================================================
-
-Pistachio has four clock controllers (core clock, peripheral clock, peripheral
-general control, and top general control) which are instantiated individually
-from the device-tree.
-
-External clocks:
-----------------
-
-There are three external inputs to the clock controllers which should be
-defined with the following clock-output-names:
-- "xtal": External 52Mhz oscillator (required)
-- "audio_clk_in": Alternate audio reference clock (optional)
-- "enet_clk_in": Alternate ethernet PHY clock (optional)
-
-Core clock controller:
-----------------------
-
-The core clock controller generates clocks for the CPU, RPU (WiFi + BT
-co-processor), audio, and several peripherals.
-
-Required properties:
-- compatible: Must be "img,pistachio-clk".
-- reg: Must contain the base address and length of the core clock controller.
-- #clock-cells: Must be 1.  The single cell is the clock identifier.
-  See dt-bindings/clock/pistachio-clk.h for the list of valid identifiers.
-- clocks: Must contain an entry for each clock in clock-names.
-- clock-names: Must include "xtal" (see "External clocks") and
-  "audio_clk_in_gate", "enet_clk_in_gate" which are generated by the
-  top-level general control.
-
-Example:
-	clk_core: clock-controller@18144000 {
-		compatible = "img,pistachio-clk";
-		reg = <0x18144000 0x800>;
-		clocks = <&xtal>, <&cr_top EXT_CLK_AUDIO_IN>,
-			 <&cr_top EXT_CLK_ENET_IN>;
-		clock-names = "xtal", "audio_clk_in_gate", "enet_clk_in_gate";
-
-		#clock-cells = <1>;
-	};
-
-Peripheral clock controller:
-----------------------------
-
-The peripheral clock controller generates clocks for the DDR, ROM, and other
-peripherals.  The peripheral system clock ("periph_sys") generated by the core
-clock controller is the input clock to the peripheral clock controller.
-
-Required properties:
-- compatible: Must be "img,pistachio-periph-clk".
-- reg: Must contain the base address and length of the peripheral clock
-  controller.
-- #clock-cells: Must be 1.  The single cell is the clock identifier.
-  See dt-bindings/clock/pistachio-clk.h for the list of valid identifiers.
-- clocks: Must contain an entry for each clock in clock-names.
-- clock-names: Must include "periph_sys", the peripheral system clock generated
-  by the core clock controller.
-
-Example:
-	clk_periph: clock-controller@18144800 {
-		compatible = "img,pistachio-clk-periph";
-		reg = <0x18144800 0x800>;
-		clocks = <&clk_core CLK_PERIPH_SYS>;
-		clock-names = "periph_sys";
-
-		#clock-cells = <1>;
-	};
-
-Peripheral general control:
----------------------------
-
-The peripheral general control block generates system interface clocks and
-resets for various peripherals.  It also contains miscellaneous peripheral
-control registers.  The system clock ("sys") generated by the peripheral clock
-controller is the input clock to the system clock controller.
-
-Required properties:
-- compatible: Must include "img,pistachio-periph-cr" and "syscon".
-- reg: Must contain the base address and length of the peripheral general
-  control registers.
-- #clock-cells: Must be 1.  The single cell is the clock identifier.
-  See dt-bindings/clock/pistachio-clk.h for the list of valid identifiers.
-- clocks: Must contain an entry for each clock in clock-names.
-- clock-names: Must include "sys", the system clock generated by the peripheral
-  clock controller.
-
-Example:
-	cr_periph: syscon@18144800 {
-		compatible = "img,pistachio-cr-periph", "syscon";
-		reg = <0x18148000 0x1000>;
-		clocks = <&clock_periph PERIPH_CLK_PERIPH_SYS>;
-		clock-names = "sys";
-
-		#clock-cells = <1>;
-	};
-
-Top-level general control:
---------------------------
-
-The top-level general control block contains miscellaneous control registers and
-gates for the external clocks "audio_clk_in" and "enet_clk_in".
-
-Required properties:
-- compatible: Must include "img,pistachio-cr-top" and "syscon".
-- reg: Must contain the base address and length of the top-level
-  control registers.
-- clocks: Must contain an entry for each clock in clock-names.
-- clock-names: Two optional clocks, "audio_clk_in" and "enet_clk_in" (see
-  "External clocks").
-- #clock-cells: Must be 1.  The single cell is the clock identifier.
-  See dt-bindings/clock/pistachio-clk.h for the list of valid identifiers.
-
-Example:
-	cr_top: syscon@18144800 {
-		compatible = "img,pistachio-cr-top", "syscon";
-		reg = <0x18149000 0x200>;
-		clocks = <&audio_refclk>, <&ext_enet_in>;
-		clock-names = "audio_clk_in", "enet_clk_in";
-
-		#clock-cells = <1>;
-	};

Bindings/clock/qca,ath79-pll.txt

@@ -1,33 +0,0 @@
-Binding for Qualcomm Atheros AR7xxx/AR9XXX PLL controller
-
-The PPL controller provides the 3 main clocks of the SoC: CPU, DDR and AHB.
-
-Required Properties:
-- compatible: has to be "qca,<soctype>-pll" and one of the following
-  fallbacks:
-  - "qca,ar7100-pll"
-  - "qca,ar7240-pll"
-  - "qca,ar9130-pll"
-  - "qca,ar9330-pll"
-  - "qca,ar9340-pll"
-  - "qca,qca9550-pll"
-- reg: Base address and size of the controllers memory area
-- clock-names: Name of the input clock, has to be "ref"
-- clocks: phandle of the external reference clock
-- #clock-cells: has to be one
-
-Optional properties:
-- clock-output-names: should be "cpu", "ddr", "ahb"
-
-Example:
-
-	pll-controller@18050000 {
-		compatible = "qca,ar9132-pll", "qca,ar9130-pll";
-		reg = <0x18050000 0x20>;
-
-		clock-names = "ref";
-		clocks = <&extosc>;
-
-		#clock-cells = <1>;
-		clock-output-names = "cpu", "ddr", "ahb";
-	};

Bindings/clock/qca,ath79-pll.yaml

@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qca,ath79-pll.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Atheros ATH79 PLL controller
+
+maintainers:
+  - Alban Bedel <albeu@free.fr>
+  - Antony Pavlov <antonynpavlov@gmail.com>
+
+description: >
+  The PLL controller provides the 3 main clocks of the SoC: CPU, DDR and AHB.
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - const: qca,ar9132-pll
+          - const: qca,ar9130-pll
+      - items:
+          - enum:
+              - qca,ar7100-pll
+              - qca,ar7240-pll
+              - qca,ar9130-pll
+              - qca,ar9330-pll
+              - qca,ar9340-pll
+              - qca,qca9530-pll
+              - qca,qca9550-pll
+              - qca,qca9560-pll
+
+  reg:
+    maxItems: 1
+
+  clock-names:
+    items:
+      - const: ref
+
+  clocks:
+    maxItems: 1
+
+  '#clock-cells':
+    const: 1
+
+  clock-output-names:
+    items:
+      - const: cpu
+      - const: ddr
+      - const: ahb
+
+required:
+  - compatible
+  - reg
+  - clock-names
+  - clocks
+  - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    clock-controller@18050000 {
+        compatible = "qca,ar9132-pll", "qca,ar9130-pll";
+        reg = <0x18050000 0x20>;
+        clock-names = "ref";
+        clocks = <&extosc>;
+        #clock-cells = <1>;
+        clock-output-names = "cpu", "ddr", "ahb";
+    };

Bindings/clock/qcom,camcc-sm8250.yaml

@@ -13,7 +13,7 @@ description: |
   Qualcomm camera clock control module provides the clocks, resets and
   power domains on SM8250.
 
-  See also:: include/dt-bindings/clock/qcom,camcc-sm8250.h
+  See also: include/dt-bindings/clock/qcom,camcc-sm8250.h
 
 allOf:
   - $ref: qcom,gcc.yaml#

Bindings/clock/qcom,dispcc-sm6125.yaml

@@ -13,7 +13,7 @@ description: |
   Qualcomm display clock control module provides the clocks and power domains
   on SM6125.
 
-  See also:: include/dt-bindings/clock/qcom,dispcc-sm6125.h
+  See also: include/dt-bindings/clock/qcom,dispcc-sm6125.h
 
 properties:
   compatible:

Bindings/clock/qcom,dispcc-sm6350.yaml

@@ -13,7 +13,7 @@ description: |
   Qualcomm display clock control module provides the clocks, resets and power
   domains on SM6350.
 
-  See also:: include/dt-bindings/clock/qcom,dispcc-sm6350.h
+  See also: include/dt-bindings/clock/qcom,dispcc-sm6350.h
 
 properties:
   compatible:

Bindings/clock/qcom,gcc-ipq4019.yaml

@@ -15,7 +15,7 @@ description: |
   Qualcomm global clock control module provides the clocks, resets and power
   domains on IPQ4019.
 
-  See also:: include/dt-bindings/clock/qcom,gcc-ipq4019.h
+  See also: include/dt-bindings/clock/qcom,gcc-ipq4019.h
 
 allOf:
   - $ref: qcom,gcc.yaml#

Bindings/clock/qcom,gcc-ipq8074.yaml

@@ -14,7 +14,7 @@ description: |
   Qualcomm global clock control module provides the clocks, resets and power
   domains on IPQ8074.
 
-  See also:: include/dt-bindings/clock/qcom,gcc-ipq8074.h
+  See also: include/dt-bindings/clock/qcom,gcc-ipq8074.h
 
 allOf:
   - $ref: qcom,gcc.yaml#

Bindings/clock/qcom,gcc-msm8976.yaml

@@ -14,7 +14,7 @@ description: |
   Qualcomm global clock control module provides the clocks, resets and power
   domains on MSM8976.
 
-  See also:: include/dt-bindings/clock/qcom,gcc-msm8976.h
+  See also: include/dt-bindings/clock/qcom,gcc-msm8976.h
 
 properties:
   compatible:

Bindings/clock/qcom,gcc-msm8994.yaml

@@ -13,7 +13,7 @@ description: |
   Qualcomm global clock control module provides the clocks, resets and power
   domains on MSM8994 and MSM8992.
 
-  See also:: include/dt-bindings/clock/qcom,gcc-msm8994.h
+  See also: include/dt-bindings/clock/qcom,gcc-msm8994.h
 
 properties:
   compatible:

Bindings/clock/qcom,gcc-msm8996.yaml

@@ -14,7 +14,7 @@ description: |
   Qualcomm global clock control module which provides the clocks, resets and
   power domains on MSM8996.
 
-  See also:: include/dt-bindings/clock/qcom,gcc-msm8996.h
+  See also: include/dt-bindings/clock/qcom,gcc-msm8996.h
 
 properties:
   compatible:

Bindings/clock/qcom,gcc-msm8998.yaml

@@ -14,7 +14,7 @@ description: |
   Qualcomm global clock control module provides the clocks, resets and power
   domains on MSM8998.
 
-  See also:: include/dt-bindings/clock/qcom,gcc-msm8998.h
+  See also: include/dt-bindings/clock/qcom,gcc-msm8998.h
 
 properties:
   compatible:

Bindings/clock/qcom,gcc-qcm2290.yaml

@@ -13,7 +13,7 @@ description: |
   Qualcomm global clock control module provides the clocks, resets and power
   domains on QCM2290.
 
-  See also:: include/dt-bindings/clock/qcom,gcc-qcm2290.h
+  See also: include/dt-bindings/clock/qcom,gcc-qcm2290.h
 
 properties:
   compatible:

Bindings/clock/qcom,gcc-qcs404.yaml

@@ -14,7 +14,7 @@ description: |
   Qualcomm global clock control module provides the clocks, resets and power
   domains on QCS404.
 
-  See also:: include/dt-bindings/clock/qcom,gcc-qcs404.h
+  See also: include/dt-bindings/clock/qcom,gcc-qcs404.h
 
 properties:
   compatible:

Bindings/clock/qcom,gcc-sc7180.yaml

@@ -14,7 +14,7 @@ description: |
   Qualcomm global clock control module provides the clocks, resets and power
   domains on SC7180.
 
-  See also:: include/dt-bindings/clock/qcom,gcc-sc7180.h
+  See also: include/dt-bindings/clock/qcom,gcc-sc7180.h
 
 properties:
   compatible:

Bindings/clock/qcom,gcc-sc7280.yaml

@@ -13,7 +13,7 @@ description: |
   Qualcomm global clock control module provides the clocks, resets and power
   domains on SC7280.
 
-  See also:: include/dt-bindings/clock/qcom,gcc-sc7280.h
+  See also: include/dt-bindings/clock/qcom,gcc-sc7280.h
 
 properties:
   compatible:

Bindings/clock/qcom,gcc-sc8180x.yaml

@@ -13,7 +13,7 @@ description: |
   Qualcomm global clock control module provides the clocks, resets and power
   domains on SC8180x.
 
-  See also:: include/dt-bindings/clock/qcom,gcc-sc8180x.h
+  See also: include/dt-bindings/clock/qcom,gcc-sc8180x.h
 
 properties:
   compatible:

Bindings/clock/qcom,gcc-sc8280xp.yaml

@@ -13,7 +13,7 @@ description: |
   Qualcomm global clock control module provides the clocks, resets and
   power domains on SC8280xp.
 
-  See also:: include/dt-bindings/clock/qcom,gcc-sc8280xp.h
+  See also: include/dt-bindings/clock/qcom,gcc-sc8280xp.h
 
 properties:
   compatible:

Bindings/clock/qcom,gcc-sdm845.yaml

@@ -14,7 +14,7 @@ description: |
   Qualcomm global clock control module provides the clocks, resets and power
   domains on SDM670 and SDM845
 
-  See also:: include/dt-bindings/clock/qcom,gcc-sdm845.h
+  See also: include/dt-bindings/clock/qcom,gcc-sdm845.h
 
 properties:
   compatible:

Bindings/clock/qcom,gcc-sdx55.yaml

@@ -14,7 +14,7 @@ description: |
   Qualcomm global clock control module provides the clocks, resets and
   power domains on SDX55
 
-  See also:: include/dt-bindings/clock/qcom,gcc-sdx55.h
+  See also: include/dt-bindings/clock/qcom,gcc-sdx55.h
 
 properties:
   compatible:

Bindings/clock/qcom,gcc-sdx65.yaml

@@ -13,7 +13,7 @@ description: |
   Qualcomm global clock control module provides the clocks, resets and power
   domains on SDX65
 
-  See also:: include/dt-bindings/clock/qcom,gcc-sdx65.h
+  See also: include/dt-bindings/clock/qcom,gcc-sdx65.h
 
 properties:
   compatible:

Bindings/clock/qcom,gcc-sm6115.yaml

@@ -13,7 +13,7 @@ description: |
   Qualcomm global clock control module provides the clocks, resets and power
   domains on SM4250/6115.
 
-  See also:: include/dt-bindings/clock/qcom,gcc-sm6115.h
+  See also: include/dt-bindings/clock/qcom,gcc-sm6115.h
 
 properties:
   compatible:

Bindings/clock/qcom,gcc-sm6125.yaml

@@ -13,7 +13,7 @@ description: |
   Qualcomm global clock control module provides the clocks, resets and power
   domains on SM6125.
 
-  See also:: include/dt-bindings/clock/qcom,gcc-sm6125.h
+  See also: include/dt-bindings/clock/qcom,gcc-sm6125.h
 
 properties:
   compatible:

Bindings/clock/qcom,gcc-sm6350.yaml

@@ -13,7 +13,7 @@ description: |
   Qualcomm global clock control module provides the clocks, resets and power
   domains on SM6350.
 
-  See also:: include/dt-bindings/clock/qcom,gcc-sm6350.h
+  See also: include/dt-bindings/clock/qcom,gcc-sm6350.h
 
 properties:
   compatible:

Bindings/clock/qcom,gcc-sm8150.yaml

@@ -14,7 +14,7 @@ description: |
   Qualcomm global clock control module provides the clocks, resets and power
   domains on SM8150.
 
-  See also:: include/dt-bindings/clock/qcom,gcc-sm8150.h
+  See also: include/dt-bindings/clock/qcom,gcc-sm8150.h
 
 properties:
   compatible:

Bindings/clock/qcom,gcc-sm8250.yaml

@@ -14,7 +14,7 @@ description: |
   Qualcomm global clock control module provides the clocks, resets and power
   domains on SM8250.
 
-  See also:: include/dt-bindings/clock/qcom,gcc-sm8250.h
+  See also: include/dt-bindings/clock/qcom,gcc-sm8250.h
 
 properties:
   compatible:

Bindings/clock/qcom,gcc-sm8350.yaml

@@ -13,7 +13,7 @@ description: |
   Qualcomm global clock control module provides the clocks, resets and power
   domains on SM8350.
 
-  See also:: include/dt-bindings/clock/qcom,gcc-sm8350.h
+  See also: include/dt-bindings/clock/qcom,gcc-sm8350.h
 
 properties:
   compatible: