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https://source.denx.de/u-boot/u-boot.git
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usb: dwc2: Clean up with bitfield macros
Use FIELD_PREP, FIELD_GET, BIT, and GENMASK macros to standardize bit manipulation across the DWC2 code, improving readability and maintainability without altering functionality. Signed-off-by: Kongyang Liu <seashell11234455@gmail.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com> Tested-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech> Link: https://lore.kernel.org/r/20250110-dwc2-dev-v4-4-987f4fd6f8b2@pigmoral.tech Signed-off-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
This commit is contained in:
Kongyang Liu
Mattijs Korpershoek
parent
bd6ef5097d
commit
a5699130f4
@ -29,6 +29,7 @@
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#include <linux/delay.h>
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#include <linux/printk.h>
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#include <linux/bitfield.h>
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#include <linux/errno.h>
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#include <linux/list.h>
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@ -526,8 +527,8 @@ static void reconfig_usbd(struct dwc2_udc *dev)
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}
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/* 8. Unmask EPO interrupts*/
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writel(((1 << EP0_CON) << DAINT_OUT_BIT)
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| (1 << EP0_CON), ®->device_regs.daintmsk);
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writel(FIELD_PREP(DAINT_OUTEP_MASK, BIT(EP0_CON)) |
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FIELD_PREP(DAINT_INEP_MASK, BIT(EP0_CON)), ®->device_regs.daintmsk);
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/* 9. Unmask device OUT EP common interrupts*/
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writel(DOEPMSK_INIT, ®->device_regs.doepmsk);
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@ -32,7 +32,7 @@ struct dwc2_usbotg_phy {
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#define VB_VALOEN BIT(2)
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/* DWC2_UDC_OTG_GOTINT */
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#define GOTGINT_SES_END_DET (1<<2)
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#define GOTGINT_SES_END_DET BIT(2)
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/* DWC2_UDC_OTG_GAHBCFG */
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#define PTXFE_HALF (0 << 8)
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@ -50,27 +50,26 @@ struct dwc2_usbotg_phy {
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#define GBL_INT_MASK (0 << 0)
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/* DWC2_UDC_OTG_GRSTCTL */
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#define AHB_MASTER_IDLE (1u<<31)
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#define CORE_SOFT_RESET (0x1<<0)
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#define AHB_MASTER_IDLE BIT(31)
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#define CORE_SOFT_RESET BIT(0)
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/* DWC2_UDC_OTG_GINTSTS/DWC2_UDC_OTG_GINTMSK core interrupt register */
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#define INT_RESUME (1u<<31)
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#define INT_DISCONN (0x1<<29)
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#define INT_CONN_ID_STS_CNG (0x1<<28)
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#define INT_OUT_EP (0x1<<19)
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#define INT_IN_EP (0x1<<18)
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#define INT_ENUMDONE (0x1<<13)
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#define INT_RESET (0x1<<12)
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#define INT_SUSPEND (0x1<<11)
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#define INT_EARLY_SUSPEND (0x1<<10)
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#define INT_NP_TX_FIFO_EMPTY (0x1<<5)
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#define INT_RX_FIFO_NOT_EMPTY (0x1<<4)
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#define INT_SOF (0x1<<3)
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#define INT_OTG (0x1<<2)
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#define INT_DEV_MODE (0x0<<0)
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#define INT_HOST_MODE (0x1<<1)
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#define INT_GOUTNakEff (0x01<<7)
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#define INT_GINNakEff (0x01<<6)
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#define INT_RESUME BIT(31)
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#define INT_DISCONN BIT(29)
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#define INT_CONN_ID_STS_CNG BIT(28)
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#define INT_OUT_EP BIT(19)
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#define INT_IN_EP BIT(18)
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#define INT_ENUMDONE BIT(13)
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#define INT_RESET BIT(12)
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#define INT_SUSPEND BIT(11)
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#define INT_EARLY_SUSPEND BIT(10)
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#define INT_GOUTNakEff BIT(7)
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#define INT_GINNakEff BIT(6)
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#define INT_NP_TX_FIFO_EMPTY BIT(5)
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#define INT_RX_FIFO_NOT_EMPTY BIT(4)
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#define INT_SOF BIT(3)
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#define INT_OTG BIT(2)
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#define INT_HOST_MODE BIT(1)
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#define FULL_SPEED_CONTROL_PKT_SIZE 8
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#define FULL_SPEED_BULK_PKT_SIZE 64
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@ -78,9 +77,9 @@ struct dwc2_usbotg_phy {
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#define HIGH_SPEED_CONTROL_PKT_SIZE 64
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#define HIGH_SPEED_BULK_PKT_SIZE 512
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#define RX_FIFO_SIZE (1024)
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#define NPTX_FIFO_SIZE (1024)
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#define PTX_FIFO_SIZE (384)
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#define RX_FIFO_SIZE 1024
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#define NPTX_FIFO_SIZE 1024
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#define PTX_FIFO_SIZE 384
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#define DEPCTL_TXFNUM_0 (0x0 << 22)
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#define DEPCTL_TXFNUM_1 (0x1 << 22)
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@ -102,32 +101,30 @@ struct dwc2_usbotg_phy {
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#define GLOBAL_OUT_NAK (0x1 << 17)
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/* DWC2_UDC_OTG_DCTL device control register */
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#define NORMAL_OPERATION (0x1<<0)
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#define SOFT_DISCONNECT (0x1<<1)
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#define NORMAL_OPERATION BIT(0)
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#define SOFT_DISCONNECT BIT(1)
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/* DWC2_UDC_OTG_DAINT device all endpoint interrupt register */
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#define DAINT_OUT_BIT (16)
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#define DAINT_MASK (0xFFFF)
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#define DAINT_OUTEP_MASK GENMASK(31, 16)
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#define DAINT_INEP_MASK GENMASK(15, 0)
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/* DWC2_UDC_OTG_DIEPCTL0/DOEPCTL0 device
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control IN/OUT endpoint 0 control register */
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#define DEPCTL_EPENA (0x1<<31)
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#define DEPCTL_EPDIS (0x1<<30)
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#define DEPCTL_SETD1PID (0x1<<29)
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#define DEPCTL_SETD0PID (0x1<<28)
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#define DEPCTL_SNAK (0x1<<27)
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#define DEPCTL_CNAK (0x1<<26)
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#define DEPCTL_STALL (0x1<<21)
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#define DEPCTL_TYPE_BIT (18)
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#define DEPCTL_TYPE_MASK (0x3<<18)
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#define DEPCTL_EPENA BIT(31)
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#define DEPCTL_EPDIS BIT(30)
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#define DEPCTL_SETD1PID BIT(29)
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#define DEPCTL_SETD0PID BIT(28)
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#define DEPCTL_SNAK BIT(27)
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#define DEPCTL_CNAK BIT(26)
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#define DEPCTL_STALL BIT(21)
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#define DEPCTL_TYPE_MASK GENMASK(19, 18)
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#define DEPCTL_CTRL_TYPE (0x0 << 18)
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#define DEPCTL_ISO_TYPE (0x1 << 18)
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#define DEPCTL_BULK_TYPE (0x2 << 18)
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#define DEPCTL_INTR_TYPE (0x3 << 18)
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#define DEPCTL_USBACTEP (0x1<<15)
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#define DEPCTL_NEXT_EP_BIT (11)
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#define DEPCTL_MPS_BIT (0)
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#define DEPCTL_MPS_MASK (0x7FF)
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#define DEPCTL_USBACTEP BIT(15)
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#define DEPCTL_NEXT_EP_MASK GENMASK(14, 11)
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#define DEPCTL_MPS_MASK GENMASK(10, 0)
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#define DEPCTL0_MPS_64 (0x0 << 0)
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#define DEPCTL0_MPS_32 (0x1 << 0)
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@ -141,40 +138,40 @@ struct dwc2_usbotg_phy {
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/* DWC2_UDC_OTG_DIEPMSK/DOEPMSK device IN/OUT endpoint
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common interrupt mask register */
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/* DWC2_UDC_OTG_DIEPINTn/DOEPINTn device IN/OUT endpoint interrupt register */
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#define BACK2BACK_SETUP_RECEIVED (0x1<<6)
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#define INTKNEPMIS (0x1<<5)
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#define INTKN_TXFEMP (0x1<<4)
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#define NON_ISO_IN_EP_TIMEOUT (0x1<<3)
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#define CTRL_OUT_EP_SETUP_PHASE_DONE (0x1<<3)
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#define AHB_ERROR (0x1<<2)
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#define EPDISBLD (0x1<<1)
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#define TRANSFER_DONE (0x1<<0)
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#define BACK2BACK_SETUP_RECEIVED BIT(6)
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#define INTKNEPMIS BIT(5)
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#define INTKN_TXFEMP BIT(4)
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#define NON_ISO_IN_EP_TIMEOUT BIT(3)
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#define CTRL_OUT_EP_SETUP_PHASE_DONE BIT(3)
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#define AHB_ERROR BIT(2)
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#define EPDISBLD BIT(1)
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#define TRANSFER_DONE BIT(0)
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#define USB_PHY_CTRL_EN0 (0x1 << 0)
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#define USB_PHY_CTRL_EN0 BIT(0)
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/* OPHYPWR */
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#define PHY_0_SLEEP (0x1 << 5)
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#define OTG_DISABLE_0 (0x1 << 4)
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#define ANALOG_PWRDOWN (0x1 << 3)
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#define FORCE_SUSPEND_0 (0x1 << 0)
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#define PHY_0_SLEEP BIT(5)
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#define OTG_DISABLE_0 BIT(4)
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#define ANALOG_PWRDOWN BIT(3)
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#define FORCE_SUSPEND_0 BIT(0)
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/* URSTCON */
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#define HOST_SW_RST (0x1 << 4)
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#define PHY_SW_RST1 (0x1 << 3)
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#define PHYLNK_SW_RST (0x1 << 2)
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#define LINK_SW_RST (0x1 << 1)
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#define PHY_SW_RST0 (0x1 << 0)
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#define HOST_SW_RST BIT(4)
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#define PHY_SW_RST1 BIT(3)
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#define PHYLNK_SW_RST BIT(2)
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#define LINK_SW_RST BIT(1)
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#define PHY_SW_RST0 BIT(0)
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/* OPHYCLK */
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#define COMMON_ON_N1 (0x1 << 7)
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#define COMMON_ON_N0 (0x1 << 4)
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#define ID_PULLUP0 (0x1 << 2)
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#define COMMON_ON_N1 BIT(7)
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#define COMMON_ON_N0 BIT(4)
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#define ID_PULLUP0 BIT(2)
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#define CLK_SEL_24MHZ (0x3 << 0)
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#define CLK_SEL_12MHZ (0x2 << 0)
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#define CLK_SEL_48MHZ (0x0 << 0)
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#define EXYNOS4X12_ID_PULLUP0 (0x01 << 3)
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#define EXYNOS4X12_COMMON_ON_N0 (0x01 << 4)
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#define EXYNOS4X12_ID_PULLUP0 BIT(3)
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#define EXYNOS4X12_COMMON_ON_N0 BIT(4)
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#define EXYNOS4X12_CLK_SEL_12MHZ (0x02 << 0)
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#define EXYNOS4X12_CLK_SEL_24MHZ (0x05 << 0)
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@ -183,13 +180,13 @@ struct dwc2_usbotg_phy {
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#define DEV_SPEED_FULL_SPEED_20 (0x1 << 0)
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#define DEV_SPEED_LOW_SPEED_11 (0x2 << 0)
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#define DEV_SPEED_FULL_SPEED_11 (0x3 << 0)
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#define EP_MISS_CNT(x) (x << 18)
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#define DEVICE_ADDRESS(x) (x << 4)
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#define EP_MISS_CNT(x) ((x) << 18)
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#define DEVICE_ADDRESS(x) ((x) << 4)
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/* Core Reset Register (GRSTCTL) */
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#define TX_FIFO_FLUSH (0x1 << 5)
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#define RX_FIFO_FLUSH (0x1 << 4)
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#define TX_FIFO_NUMBER(x) (x << 6)
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#define TX_FIFO_FLUSH BIT(5)
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#define RX_FIFO_FLUSH BIT(4)
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#define TX_FIFO_NUMBER(x) ((x) << 6)
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#define TX_FIFO_FLUSH_ALL TX_FIFO_NUMBER(0x10)
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/* Masks definitions */
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@ -201,22 +198,21 @@ struct dwc2_usbotg_phy {
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| GBL_INT_UNMASK)
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/* Device Endpoint X Transfer Size Register (DIEPTSIZX) */
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#define DIEPT_SIZ_PKT_CNT(x) (x << 19)
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#define DIEPT_SIZ_XFER_SIZE(x) (x << 0)
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#define DIEPT_SIZ_PKT_CNT(x) ((x) << 19)
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#define DIEPT_SIZ_XFER_SIZE(x) ((x) << 0)
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/* Device OUT Endpoint X Transfer Size Register (DOEPTSIZX) */
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#define DOEPT_SIZ_PKT_CNT(x) (x << 19)
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#define DOEPT_SIZ_XFER_SIZE(x) (x << 0)
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#define DOEPT_SIZ_PKT_CNT(x) ((x) << 19)
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#define DOEPT_SIZ_XFER_SIZE(x) ((x) << 0)
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#define DOEPT_SIZ_XFER_SIZE_MAX_EP0 (0x7F << 0)
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#define DOEPT_SIZ_XFER_SIZE_MAX_EP (0x7FFF << 0)
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/* Device Endpoint-N Control Register (DIEPCTLn/DOEPCTLn) */
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#define DIEPCTL_TX_FIFO_NUM(x) (x << 22)
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#define DIEPCTL_TX_FIFO_NUM_MASK (~DIEPCTL_TX_FIFO_NUM(0xF))
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#define DIEPCTL_TX_FIFO_NUM_MASK GENMASK(25, 22)
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/* Device ALL Endpoints Interrupt Register (DAINT) */
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#define DAINT_IN_EP_INT(x) (x << 0)
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#define DAINT_OUT_EP_INT(x) (x << 16)
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#define DAINT_IN_EP_INT(x) ((x) << 0)
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#define DAINT_OUT_EP_INT(x) ((x) << 16)
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/* User HW Config4 */
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#define GHWCFG4_NUM_IN_EPS_MASK (0xf << 26)
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@ -19,6 +19,7 @@
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#include <cpu_func.h>
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#include <log.h>
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#include <linux/bitfield.h>
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#include <linux/bug.h>
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static u8 clear_feature_num;
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@ -174,11 +175,11 @@ static int setdma_tx(struct dwc2_ep *ep, struct dwc2_request *req)
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ctrl = readl(®->device_regs.in_endp[ep_num].diepctl);
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/* Write the FIFO number to be used for this endpoint */
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ctrl &= DIEPCTL_TX_FIFO_NUM_MASK;
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ctrl |= DIEPCTL_TX_FIFO_NUM(ep->fifo_num);
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ctrl &= ~DIEPCTL_TX_FIFO_NUM_MASK;
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ctrl |= FIELD_PREP(DIEPCTL_TX_FIFO_NUM_MASK, ep->fifo_num);
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/* Clear reserved (Next EP) bits */
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ctrl = (ctrl&~(EP_MASK<<DEPCTL_NEXT_EP_BIT));
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ctrl &= ~DEPCTL_NEXT_EP_MASK;
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writel(DEPCTL_EPENA | DEPCTL_CNAK | ctrl, ®->device_regs.in_endp[ep_num].diepctl);
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@ -380,7 +381,7 @@ static void process_ep_in_intr(struct dwc2_udc *dev)
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debug_cond(DEBUG_IN_EP,
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"*** %s: EP In interrupt : DAINT = 0x%x\n", __func__, ep_intr);
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ep_intr &= DAINT_MASK;
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ep_intr = FIELD_GET(DAINT_INEP_MASK, ep_intr);
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while (ep_intr) {
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if (ep_intr & DAINT_IN_EP_INT(1)) {
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@ -431,10 +432,10 @@ static void process_ep_out_intr(struct dwc2_udc *dev)
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"*** %s: EP OUT interrupt : DAINT = 0x%x\n",
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__func__, ep_intr);
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ep_intr = (ep_intr >> DAINT_OUT_BIT) & DAINT_MASK;
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ep_intr = FIELD_GET(DAINT_OUTEP_MASK, ep_intr);
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while (ep_intr) {
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if (ep_intr & 0x1) {
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if (ep_intr & BIT(EP0_CON)) {
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ep_intr_status = readl(®->device_regs.out_endp[ep_num].doepint);
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debug_cond(DEBUG_OUT_EP != 0,
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"\tEP%d-OUT : DOEPINT = 0x%x\n",
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@ -1114,10 +1115,10 @@ static void dwc2_udc_ep_activate(struct dwc2_ep *ep)
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/* Read DEPCTLn register */
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if (ep_is_in(ep)) {
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ep_ctrl = readl(®->device_regs.in_endp[ep_num].diepctl);
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daintmsk = 1 << ep_num;
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daintmsk = FIELD_PREP(DAINT_INEP_MASK, BIT(ep_num));
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} else {
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ep_ctrl = readl(®->device_regs.out_endp[ep_num].doepctl);
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daintmsk = (1 << ep_num) << DAINT_OUT_BIT;
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daintmsk = FIELD_PREP(DAINT_OUTEP_MASK, BIT(ep_num));
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}
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debug("%s: EPCTRL%d = 0x%x, ep_is_in = %d\n",
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@ -1127,9 +1128,9 @@ static void dwc2_udc_ep_activate(struct dwc2_ep *ep)
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* register. */
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if (!(ep_ctrl & DEPCTL_USBACTEP)) {
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ep_ctrl = (ep_ctrl & ~DEPCTL_TYPE_MASK) |
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(ep->bmAttributes << DEPCTL_TYPE_BIT);
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FIELD_PREP(DEPCTL_TYPE_MASK, ep->bmAttributes);
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ep_ctrl = (ep_ctrl & ~DEPCTL_MPS_MASK) |
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(ep->ep.maxpacket << DEPCTL_MPS_BIT);
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FIELD_PREP(DEPCTL_MPS_MASK, ep->ep.maxpacket);
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ep_ctrl |= (DEPCTL_SETD0PID | DEPCTL_USBACTEP | DEPCTL_SNAK);
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if (ep_is_in(ep)) {
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@ -19,6 +19,7 @@
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#include <asm/cache.h>
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#include <asm/io.h>
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#include <dm/device_compat.h>
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#include <linux/bitfield.h>
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#include <linux/delay.h>
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#include <linux/usb/otg.h>
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#include <power/regulator.h>
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@ -95,10 +96,8 @@ static void init_fslspclksel(struct dwc2_core_regs *regs)
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#ifdef DWC2_ULPI_FS_LS
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uint32_t hwcfg2 = readl(®s->global_regs.ghwcfg2);
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uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
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DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
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uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
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DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
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uint32_t hval = FIELD_GET(GHWCFG2_HS_PHY_TYPE_MASK, ghwcfg2);
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uint32_t fval = FIELD_GET(GHWCFG2_FS_PHY_TYPE_MASK, ghwcfg2);
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if (hval == 2 && fval == 1)
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phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */
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@ -106,7 +105,7 @@ static void init_fslspclksel(struct dwc2_core_regs *regs)
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|
||||
clrsetbits_le32(®s->host_regs.hcfg,
|
||||
DWC2_HCFG_FSLSPCLKSEL_MASK,
|
||||
phyclk << DWC2_HCFG_FSLSPCLKSEL_OFFSET);
|
||||
FIELD_PREP(DWC2_HCFG_FSLSPCLKSEL_MASK, phyclk));
|
||||
}
|
||||
|
||||
/*
|
||||
@ -120,7 +119,7 @@ static void dwc_otg_flush_tx_fifo(struct udevice *dev,
|
||||
{
|
||||
int ret;
|
||||
|
||||
writel(DWC2_GRSTCTL_TXFFLSH | (num << DWC2_GRSTCTL_TXFNUM_OFFSET),
|
||||
writel(DWC2_GRSTCTL_TXFFLSH | FIELD_PREP(DWC2_GRSTCTL_TXFNUM_MASK, num),
|
||||
®s->global_regs.grstctl);
|
||||
ret = wait_for_bit_le32(®s->global_regs.grstctl, DWC2_GRSTCTL_TXFFLSH,
|
||||
false, 1000, false);
|
||||
@ -266,18 +265,14 @@ static void dwc_otg_core_host_init(struct udevice *dev,
|
||||
writel(DWC2_HOST_RX_FIFO_SIZE, ®s->global_regs.grxfsiz);
|
||||
|
||||
/* Non-periodic Tx FIFO */
|
||||
nptxfifosize |= DWC2_HOST_NPERIO_TX_FIFO_SIZE <<
|
||||
DWC2_FIFOSIZE_DEPTH_OFFSET;
|
||||
nptxfifosize |= DWC2_HOST_RX_FIFO_SIZE <<
|
||||
DWC2_FIFOSIZE_STARTADDR_OFFSET;
|
||||
nptxfifosize |= FIELD_PREP(DWC2_FIFOSIZE_DEPTH_MASK, DWC2_HOST_NPERIO_TX_FIFO_SIZE);
|
||||
nptxfifosize |= FIELD_PREP(DWC2_FIFOSIZE_STARTADDR_MASK, DWC2_HOST_RX_FIFO_SIZE);
|
||||
writel(nptxfifosize, ®s->global_regs.gnptxfsiz);
|
||||
|
||||
/* Periodic Tx FIFO */
|
||||
ptxfifosize |= DWC2_HOST_PERIO_TX_FIFO_SIZE <<
|
||||
DWC2_FIFOSIZE_DEPTH_OFFSET;
|
||||
ptxfifosize |= (DWC2_HOST_RX_FIFO_SIZE +
|
||||
DWC2_HOST_NPERIO_TX_FIFO_SIZE) <<
|
||||
DWC2_FIFOSIZE_STARTADDR_OFFSET;
|
||||
ptxfifosize |= FIELD_PREP(DWC2_FIFOSIZE_DEPTH_MASK, DWC2_HOST_PERIO_TX_FIFO_SIZE);
|
||||
ptxfifosize |= FIELD_PREP(DWC2_FIFOSIZE_STARTADDR_MASK, DWC2_HOST_RX_FIFO_SIZE +
|
||||
DWC2_HOST_NPERIO_TX_FIFO_SIZE);
|
||||
writel(ptxfifosize, ®s->global_regs.hptxfsiz);
|
||||
}
|
||||
#endif
|
||||
@ -290,10 +285,8 @@ static void dwc_otg_core_host_init(struct udevice *dev,
|
||||
dwc_otg_flush_rx_fifo(dev, regs);
|
||||
|
||||
/* Flush out any leftover queued requests. */
|
||||
num_channels = readl(®s->global_regs.ghwcfg2);
|
||||
num_channels &= DWC2_HWCFG2_NUM_HOST_CHAN_MASK;
|
||||
num_channels >>= DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET;
|
||||
num_channels += 1;
|
||||
num_channels = FIELD_GET(DWC2_HWCFG2_NUM_HOST_CHAN_MASK,
|
||||
readl(®s->global_regs.ghwcfg2)) + 1;
|
||||
|
||||
for (i = 0; i < num_channels; i++)
|
||||
clrsetbits_le32(®s->host_regs.hc[i].hcchar,
|
||||
@ -390,7 +383,7 @@ static void dwc_otg_core_init(struct udevice *dev)
|
||||
/* Program GI2CCTL.I2CEn */
|
||||
clrsetbits_le32(®s->global_regs.gi2cctl, DWC2_GI2CCTL_I2CEN |
|
||||
DWC2_GI2CCTL_I2CDEVADDR_MASK,
|
||||
1 << DWC2_GI2CCTL_I2CDEVADDR_OFFSET);
|
||||
FIELD_PREP(DWC2_GI2CCTL_I2CDEVADDR_MASK, 1));
|
||||
setbits_le32(®s->global_regs.gi2cctl, DWC2_GI2CCTL_I2CEN);
|
||||
#endif
|
||||
|
||||
@ -429,10 +422,8 @@ static void dwc_otg_core_init(struct udevice *dev)
|
||||
usbcfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M);
|
||||
#ifdef DWC2_ULPI_FS_LS
|
||||
uint32_t hwcfg2 = readl(®s->global_regs.ghwcfg2);
|
||||
uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
|
||||
DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
|
||||
uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
|
||||
DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
|
||||
uint32_t hval = FIELD_GET(DWC2_HWCFG2_HS_PHY_TYPE_MASK, ghwcfg2);
|
||||
uint32_t fval = FIELD_GET(DWC2_HWCFG2_FS_PHY_TYPE_MASK, ghwcfg2);
|
||||
if (hval == 2 && fval == 1) {
|
||||
usbcfg |= DWC2_GUSBCFG_ULPI_FSLS;
|
||||
usbcfg |= DWC2_GUSBCFG_ULPI_CLK_SUS_M;
|
||||
@ -444,12 +435,11 @@ static void dwc_otg_core_init(struct udevice *dev)
|
||||
writel(usbcfg, ®s->global_regs.gusbcfg);
|
||||
|
||||
/* Program the GAHBCFG Register. */
|
||||
switch (readl(®s->global_regs.ghwcfg2) & DWC2_HWCFG2_ARCHITECTURE_MASK) {
|
||||
switch (FIELD_GET(DWC2_HWCFG2_ARCHITECTURE_MASK, readl(®s->global_regs.ghwcfg2))) {
|
||||
case DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY:
|
||||
break;
|
||||
case DWC2_HWCFG2_ARCHITECTURE_EXT_DMA:
|
||||
ahbcfg |= (LOG2(brst_sz >> 1) << DWC2_GAHBCFG_HBURSTLEN_OFFSET) &
|
||||
DWC2_GAHBCFG_HBURSTLEN_MASK;
|
||||
ahbcfg |= FIELD_PREP(DWC2_GAHBCFG_HBURSTLEN_MASK, LOG2(brst_sz >> 1));
|
||||
|
||||
#ifdef DWC2_DMA_ENABLE
|
||||
ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
|
||||
@ -492,11 +482,11 @@ static void dwc_otg_hc_init(struct dwc2_core_regs *regs, uint8_t hc_num,
|
||||
uint8_t ep_is_in, uint8_t ep_type, uint16_t max_packet)
|
||||
{
|
||||
struct dwc2_hc_regs *hc_regs = ®s->host_regs.hc[hc_num];
|
||||
uint32_t hcchar = (dev_addr << DWC2_HCCHAR_DEVADDR_OFFSET) |
|
||||
(ep_num << DWC2_HCCHAR_EPNUM_OFFSET) |
|
||||
(ep_is_in << DWC2_HCCHAR_EPDIR_OFFSET) |
|
||||
(ep_type << DWC2_HCCHAR_EPTYPE_OFFSET) |
|
||||
(max_packet << DWC2_HCCHAR_MPS_OFFSET);
|
||||
u32 hcchar = FIELD_PREP(DWC2_HCCHAR_DEVADDR_MASK, dev_addr) |
|
||||
FIELD_PREP(DWC2_HCCHAR_EPNUM_MASK, ep_num) |
|
||||
FIELD_PREP(DWC2_HCCHAR_EPDIR, ep_is_in) |
|
||||
FIELD_PREP(DWC2_HCCHAR_EPTYPE_MASK, ep_type) |
|
||||
FIELD_PREP(DWC2_HCCHAR_MPS_MASK, max_packet);
|
||||
|
||||
if (dev->speed == USB_SPEED_LOW)
|
||||
hcchar |= DWC2_HCCHAR_LSPDDEV;
|
||||
@ -517,8 +507,8 @@ static void dwc_otg_hc_init_split(struct dwc2_hc_regs *hc_regs,
|
||||
uint32_t hcsplt = 0;
|
||||
|
||||
hcsplt = DWC2_HCSPLT_SPLTENA;
|
||||
hcsplt |= hub_devnum << DWC2_HCSPLT_HUBADDR_OFFSET;
|
||||
hcsplt |= hub_port << DWC2_HCSPLT_PRTADDR_OFFSET;
|
||||
hcsplt |= FIELD_PREP(DWC2_HCSPLT_HUBADDR_MASK, hub_devnum);
|
||||
hcsplt |= FIELD_PREP(DWC2_HCSPLT_PRTADDR_MASK, hub_port);
|
||||
|
||||
/* Program the HCSPLIT register for SPLITs */
|
||||
writel(hcsplt, &hc_regs->hcsplt);
|
||||
@ -567,11 +557,14 @@ static int dwc_otg_submit_rh_msg_in_status(struct dwc2_core_regs *regs,
|
||||
if (hprt0 & DWC2_HPRT0_PRTPWR)
|
||||
port_status |= USB_PORT_STAT_POWER;
|
||||
|
||||
if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == DWC2_HPRT0_PRTSPD_LOW)
|
||||
switch (FIELD_GET(DWC2_HPRT0_PRTSPD_MASK, hprt0)) {
|
||||
case DWC2_HPRT0_PRTSPD_LOW:
|
||||
port_status |= USB_PORT_STAT_LOW_SPEED;
|
||||
else if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
|
||||
DWC2_HPRT0_PRTSPD_HIGH)
|
||||
break;
|
||||
case DWC2_HPRT0_PRTSPD_HIGH:
|
||||
port_status |= USB_PORT_STAT_HIGH_SPEED;
|
||||
break;
|
||||
}
|
||||
|
||||
if (hprt0 & DWC2_HPRT0_PRTENCHNG)
|
||||
port_change |= USB_PORT_STAT_C_ENABLE;
|
||||
@ -822,9 +815,8 @@ int wait_for_chhltd(struct dwc2_hc_regs *hc_regs, uint32_t *sub, u8 *toggle)
|
||||
|
||||
hcint = readl(&hc_regs->hcint);
|
||||
hctsiz = readl(&hc_regs->hctsiz);
|
||||
*sub = (hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK) >>
|
||||
DWC2_HCTSIZ_XFERSIZE_OFFSET;
|
||||
*toggle = (hctsiz & DWC2_HCTSIZ_PID_MASK) >> DWC2_HCTSIZ_PID_OFFSET;
|
||||
*sub = FIELD_GET(DWC2_HCTSIZ_XFERSIZE_MASK, hctsiz);
|
||||
*toggle = FIELD_GET(DWC2_HCTSIZ_PID_MASK, hctsiz);
|
||||
|
||||
debug("%s: HCINT=%08x sub=%u toggle=%d\n", __func__, hcint, *sub,
|
||||
*toggle);
|
||||
@ -856,9 +848,9 @@ static int transfer_chunk(struct dwc2_hc_regs *hc_regs, void *aligned_buffer,
|
||||
debug("%s: chunk: pid %d xfer_len %u pkts %u\n", __func__,
|
||||
*pid, xfer_len, num_packets);
|
||||
|
||||
writel((xfer_len << DWC2_HCTSIZ_XFERSIZE_OFFSET) |
|
||||
(num_packets << DWC2_HCTSIZ_PKTCNT_OFFSET) |
|
||||
(*pid << DWC2_HCTSIZ_PID_OFFSET),
|
||||
writel(FIELD_PREP(DWC2_HCTSIZ_XFERSIZE_MASK, xfer_len) |
|
||||
FIELD_PREP(DWC2_HCTSIZ_PKTCNT_MASK, num_packets) |
|
||||
FIELD_PREP(DWC2_HCTSIZ_PID_MASK, *pid),
|
||||
&hc_regs->hctsiz);
|
||||
|
||||
if (xfer_len) {
|
||||
@ -885,8 +877,8 @@ static int transfer_chunk(struct dwc2_hc_regs *hc_regs, void *aligned_buffer,
|
||||
clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
|
||||
DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS |
|
||||
DWC2_HCCHAR_ODDFRM,
|
||||
(1 << DWC2_HCCHAR_MULTICNT_OFFSET) |
|
||||
(odd_frame << DWC2_HCCHAR_ODDFRM_OFFSET) |
|
||||
FIELD_PREP(DWC2_HCCHAR_MULTICNT_MASK, 1) |
|
||||
FIELD_PREP(DWC2_HCCHAR_ODDFRM, odd_frame) |
|
||||
DWC2_HCCHAR_CHEN);
|
||||
|
||||
ret = wait_for_chhltd(hc_regs, &sub, pid);
|
||||
@ -950,8 +942,7 @@ int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev,
|
||||
uint8_t hub_port;
|
||||
uint32_t hprt0 = readl(®s->host_regs.hprt0);
|
||||
|
||||
if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
|
||||
DWC2_HPRT0_PRTSPD_HIGH) {
|
||||
if (FIELD_GET(DWC2_HPRT0_PRTSPD_MASK, hprt0) == DWC2_HPRT0_PRTSPD_HIGH) {
|
||||
usb_find_usb2_hub_address_port(dev, &hub_addr,
|
||||
&hub_port);
|
||||
dwc_otg_hc_init_split(hc_regs, hub_addr, hub_port);
|
||||
@ -995,17 +986,17 @@ int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev,
|
||||
stop_transfer = 0;
|
||||
if (hcint & DWC2_HCINT_NYET) {
|
||||
ret = 0;
|
||||
int frame_num = DWC2_HFNUM_MAX_FRNUM &
|
||||
readl(&host_regs->hfnum);
|
||||
if (((frame_num - ssplit_frame_num) &
|
||||
DWC2_HFNUM_MAX_FRNUM) > 4)
|
||||
int frame_num = FIELD_GET(DWC2_HFNUM_FRNUM_MASK,
|
||||
readl(&host_regs->hfnum));
|
||||
|
||||
if (((frame_num - ssplit_frame_num) & DWC2_HFNUM_FRNUM_MASK) > 4)
|
||||
ret = -EAGAIN;
|
||||
} else
|
||||
complete_split = 0;
|
||||
} else if (do_split) {
|
||||
if (hcint & DWC2_HCINT_ACK) {
|
||||
ssplit_frame_num = DWC2_HFNUM_MAX_FRNUM &
|
||||
readl(&host_regs->hfnum);
|
||||
ssplit_frame_num = FIELD_GET(DWC2_HFNUM_FRNUM_MASK,
|
||||
readl(&host_regs->hfnum));
|
||||
ret = 0;
|
||||
complete_split = 1;
|
||||
}
|
||||
@ -1183,8 +1174,8 @@ static int dwc2_init_common(struct udevice *dev, struct dwc2_priv *priv)
|
||||
dev_info(dev, "Core Release: %x.%03x\n",
|
||||
snpsid >> 12 & 0xf, snpsid & 0xfff);
|
||||
|
||||
if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx &&
|
||||
(snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_3xx) {
|
||||
if (FIELD_GET(DWC2_SNPSID_DEVID_MASK, snpsid) != DWC2_SNPSID_DEVID_VER_2xx &&
|
||||
FIELD_GET(DWC2_SNPSID_DEVID_MASK, snpsid) != DWC2_SNPSID_DEVID_VER_3xx) {
|
||||
dev_info(dev, "SNPSID invalid (not DWC2 OTG device): %08x\n",
|
||||
snpsid);
|
||||
return -ENODEV;
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
Loading…
x
Reference in New Issue
Block a user