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a5699130f4
Use FIELD_PREP, FIELD_GET, BIT, and GENMASK macros to standardize bit manipulation across the DWC2 code, improving readability and maintainability without altering functionality. Signed-off-by: Kongyang Liu <seashell11234455@gmail.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com> Tested-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech> Link: https://lore.kernel.org/r/20250110-dwc2-dev-v4-4-987f4fd6f8b2@pigmoral.tech Signed-off-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
412 lines
17 KiB
C
412 lines
17 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2014 Marek Vasut <marex@denx.de>
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*/
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#ifndef __DWC2_H__
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#define __DWC2_H__
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#include <linux/bitops.h>
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#define DWC2_GOTGCTL_SESREQSCS BIT(0)
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#define DWC2_GOTGCTL_SESREQ BIT(1)
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#define DWC2_GOTGCTL_HSTNEGSCS BIT(8)
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#define DWC2_GOTGCTL_HNPREQ BIT(9)
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#define DWC2_GOTGCTL_HSTSETHNPEN BIT(10)
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#define DWC2_GOTGCTL_DEVHNPEN BIT(11)
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#define DWC2_GOTGCTL_CONIDSTS BIT(16)
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#define DWC2_GOTGCTL_DBNCTIME BIT(17)
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#define DWC2_GOTGCTL_ASESVLD BIT(18)
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#define DWC2_GOTGCTL_BSESVLD BIT(19)
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#define DWC2_GOTGCTL_OTGVER BIT(20)
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#define DWC2_GOTGINT_SESENDDET BIT(2)
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#define DWC2_GOTGINT_SESREQSUCSTSCHNG BIT(8)
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#define DWC2_GOTGINT_HSTNEGSUCSTSCHNG BIT(9)
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#define DWC2_GOTGINT_RESERVER10_16_MASK GENMASK(16, 10)
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#define DWC2_GOTGINT_HSTNEGDET BIT(17)
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#define DWC2_GOTGINT_ADEVTOUTCHNG BIT(18)
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#define DWC2_GOTGINT_DEBDONE BIT(19)
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#define DWC2_GAHBCFG_GLBLINTRMSK BIT(0)
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#define DWC2_GAHBCFG_HBURSTLEN_SINGLE (0 << 1)
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#define DWC2_GAHBCFG_HBURSTLEN_INCR (1 << 1)
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#define DWC2_GAHBCFG_HBURSTLEN_INCR4 (3 << 1)
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#define DWC2_GAHBCFG_HBURSTLEN_INCR8 (5 << 1)
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#define DWC2_GAHBCFG_HBURSTLEN_INCR16 (7 << 1)
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#define DWC2_GAHBCFG_HBURSTLEN_MASK GENMASK(4, 1)
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#define DWC2_GAHBCFG_DMAENABLE BIT(5)
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#define DWC2_GAHBCFG_NPTXFEMPLVL_TXFEMPLVL BIT(7)
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#define DWC2_GAHBCFG_PTXFEMPLVL BIT(8)
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#define DWC2_GUSBCFG_TOUTCAL_MASK GENMASK(2, 0)
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#define DWC2_GUSBCFG_PHYIF BIT(3)
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#define DWC2_GUSBCFG_ULPI_UTMI_SEL BIT(4)
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#define DWC2_GUSBCFG_FSINTF BIT(5)
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#define DWC2_GUSBCFG_PHYSEL BIT(6)
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#define DWC2_GUSBCFG_DDRSEL BIT(7)
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#define DWC2_GUSBCFG_SRPCAP BIT(8)
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#define DWC2_GUSBCFG_HNPCAP BIT(9)
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#define DWC2_GUSBCFG_USBTRDTIM_MASK GENMASK(13, 10)
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#define DWC2_GUSBCFG_NPTXFRWNDEN BIT(14)
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#define DWC2_GUSBCFG_PHYLPWRCLKSEL BIT(15)
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#define DWC2_GUSBCFG_OTGUTMIFSSEL BIT(16)
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#define DWC2_GUSBCFG_ULPI_FSLS BIT(17)
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#define DWC2_GUSBCFG_ULPI_AUTO_RES BIT(18)
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#define DWC2_GUSBCFG_ULPI_CLK_SUS_M BIT(19)
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#define DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV BIT(20)
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#define DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR BIT(21)
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#define DWC2_GUSBCFG_TERM_SEL_DL_PULSE BIT(22)
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#define DWC2_GUSBCFG_INDICATOR_PASSTHROUGH BIT(24)
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#define DWC2_GUSBCFG_IC_USB_CAP BIT(26)
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#define DWC2_GUSBCFG_IC_TRAFFIC_PULL_REMOVE BIT(27)
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#define DWC2_GUSBCFG_TX_END_DELAY BIT(28)
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#define DWC2_GUSBCFG_FORCEHOSTMODE BIT(29)
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#define DWC2_GUSBCFG_FORCEDEVMODE BIT(30)
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#define DWC2_GLPMCTL_LPM_CAP_EN BIT(0)
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#define DWC2_GLPMCTL_APPL_RESP BIT(1)
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#define DWC2_GLPMCTL_HIRD_MASK GENMASK(5, 2)
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#define DWC2_GLPMCTL_REM_WKUP_EN BIT(6)
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#define DWC2_GLPMCTL_EN_UTMI_SLEEP BIT(7)
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#define DWC2_GLPMCTL_HIRD_THRES_MASK GENMASK(12, 8)
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#define DWC2_GLPMCTL_LPM_RESP_MASK GENMASK(14, 13)
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#define DWC2_GLPMCTL_PRT_SLEEP_STS BIT(15)
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#define DWC2_GLPMCTL_SLEEP_STATE_RESUMEOK BIT(16)
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#define DWC2_GLPMCTL_LPM_CHAN_INDEX_MASK GENMASK(20, 17)
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#define DWC2_GLPMCTL_RETRY_COUNT_MASK GENMASK(23, 21)
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#define DWC2_GLPMCTL_SEND_LPM BIT(24)
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#define DWC2_GLPMCTL_RETRY_COUNT_STS_MASK GENMASK(27, 25)
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#define DWC2_GLPMCTL_HSIC_CONNECT BIT(30)
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#define DWC2_GLPMCTL_INV_SEL_HSIC BIT(31)
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#define DWC2_GRSTCTL_CSFTRST BIT(0)
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#define DWC2_GRSTCTL_HSFTRST BIT(1)
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#define DWC2_GRSTCTL_HSTFRM BIT(2)
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#define DWC2_GRSTCTL_INTKNQFLSH BIT(3)
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#define DWC2_GRSTCTL_RXFFLSH BIT(4)
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#define DWC2_GRSTCTL_TXFFLSH BIT(5)
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#define DWC2_GRSTCTL_TXFNUM_MASK GENMASK(10, 6)
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#define DWC2_GRSTCTL_DMAREQ BIT(30)
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#define DWC2_GRSTCTL_AHBIDLE BIT(31)
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#define DWC2_GINTMSK_MODEMISMATCH BIT(1)
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#define DWC2_GINTMSK_OTGINTR BIT(2)
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#define DWC2_GINTMSK_SOFINTR BIT(3)
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#define DWC2_GINTMSK_RXSTSQLVL BIT(4)
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#define DWC2_GINTMSK_NPTXFEMPTY BIT(5)
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#define DWC2_GINTMSK_GINNAKEFF BIT(6)
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#define DWC2_GINTMSK_GOUTNAKEFF BIT(7)
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#define DWC2_GINTMSK_I2CINTR BIT(9)
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#define DWC2_GINTMSK_ERLYSUSPEND BIT(10)
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#define DWC2_GINTMSK_USBSUSPEND BIT(11)
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#define DWC2_GINTMSK_USBRESET BIT(12)
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#define DWC2_GINTMSK_ENUMDONE BIT(13)
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#define DWC2_GINTMSK_ISOOUTDROP BIT(14)
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#define DWC2_GINTMSK_EOPFRAME BIT(15)
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#define DWC2_GINTMSK_EPMISMATCH BIT(17)
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#define DWC2_GINTMSK_INEPINTR BIT(18)
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#define DWC2_GINTMSK_OUTEPINTR BIT(19)
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#define DWC2_GINTMSK_INCOMPLISOIN BIT(20)
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#define DWC2_GINTMSK_INCOMPLISOOUT BIT(21)
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#define DWC2_GINTMSK_PORTINTR BIT(24)
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#define DWC2_GINTMSK_HCINTR BIT(25)
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#define DWC2_GINTMSK_PTXFEMPTY BIT(26)
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#define DWC2_GINTMSK_LPMTRANRCVD BIT(27)
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#define DWC2_GINTMSK_CONIDSTSCHNG BIT(28)
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#define DWC2_GINTMSK_DISCONNECT BIT(29)
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#define DWC2_GINTMSK_SESSREQINTR BIT(30)
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#define DWC2_GINTMSK_WKUPINTR BIT(31)
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#define DWC2_GINTSTS_CURMODE_HOST BIT(0)
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#define DWC2_GINTSTS_MODEMISMATCH BIT(1)
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#define DWC2_GINTSTS_OTGINTR BIT(2)
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#define DWC2_GINTSTS_SOFINTR BIT(3)
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#define DWC2_GINTSTS_RXSTSQLVL BIT(4)
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#define DWC2_GINTSTS_NPTXFEMPTY BIT(5)
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#define DWC2_GINTSTS_GINNAKEFF BIT(6)
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#define DWC2_GINTSTS_GOUTNAKEFF BIT(7)
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#define DWC2_GINTSTS_I2CINTR BIT(9)
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#define DWC2_GINTSTS_ERLYSUSPEND BIT(10)
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#define DWC2_GINTSTS_USBSUSPEND BIT(11)
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#define DWC2_GINTSTS_USBRESET BIT(12)
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#define DWC2_GINTSTS_ENUMDONE BIT(13)
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#define DWC2_GINTSTS_ISOOUTDROP BIT(14)
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#define DWC2_GINTSTS_EOPFRAME BIT(15)
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#define DWC2_GINTSTS_INTOKENRX BIT(16)
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#define DWC2_GINTSTS_EPMISMATCH BIT(17)
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#define DWC2_GINTSTS_INEPINT BIT(18)
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#define DWC2_GINTSTS_OUTEPINTR BIT(19)
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#define DWC2_GINTSTS_INCOMPLISOIN BIT(20)
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#define DWC2_GINTSTS_INCOMPLISOOUT BIT(21)
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#define DWC2_GINTSTS_PORTINTR BIT(24)
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#define DWC2_GINTSTS_HCINTR BIT(25)
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#define DWC2_GINTSTS_PTXFEMPTY BIT(26)
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#define DWC2_GINTSTS_LPMTRANRCVD BIT(27)
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#define DWC2_GINTSTS_CONIDSTSCHNG BIT(28)
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#define DWC2_GINTSTS_DISCONNECT BIT(29)
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#define DWC2_GINTSTS_SESSREQINTR BIT(30)
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#define DWC2_GINTSTS_WKUPINTR BIT(31)
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#define DWC2_GRXSTS_EPNUM_MASK GENMASK(3, 0)
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#define DWC2_GRXSTS_BCNT_MASK GENMASK(14, 4)
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#define DWC2_GRXSTS_DPID_MASK GENMASK(16, 15)
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#define DWC2_GRXSTS_PKTSTS_MASK GENMASK(20, 17)
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#define DWC2_GRXSTS_FN_MASK GENMASK(24, 21)
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#define DWC2_FIFOSIZE_STARTADDR_MASK GENMASK(15, 0)
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#define DWC2_FIFOSIZE_DEPTH_MASK GENMASK(31, 16)
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#define DWC2_GNPTXSTS_NPTXFSPCAVAIL_MASK GENMASK(15, 0)
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#define DWC2_GNPTXSTS_NPTXQSPCAVAIL_MASK GENMASK(23, 16)
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#define DWC2_GNPTXSTS_NPTXQTOP_TERMINATE BIT(24)
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#define DWC2_GNPTXSTS_NPTXQTOP_TOKEN_MASK GENMASK(26, 25)
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#define DWC2_GNPTXSTS_NPTXQTOP_CHNEP_MASK GENMASK(30, 27)
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#define DWC2_DTXFSTS_TXFSPCAVAIL_MASK GENMASK(15, 0)
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#define DWC2_GI2CCTL_RWDATA_MASK GENMASK(7, 0)
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#define DWC2_GI2CCTL_REGADDR_MASK GENMASK(15, 8)
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#define DWC2_GI2CCTL_ADDR_MASK GENMASK(22, 16)
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#define DWC2_GI2CCTL_I2CEN BIT(23)
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#define DWC2_GI2CCTL_ACK BIT(24)
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#define DWC2_GI2CCTL_I2CSUSPCTL BIT(25)
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#define DWC2_GI2CCTL_I2CDEVADDR_MASK GENMASK(27, 26)
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#define DWC2_GI2CCTL_RW BIT(30)
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#define DWC2_GI2CCTL_BSYDNE BIT(31)
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#define DWC2_HWCFG1_EP_DIR0_MASK GENMASK(1, 0)
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#define DWC2_HWCFG1_EP_DIR1_MASK GENMASK(3, 2)
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#define DWC2_HWCFG1_EP_DIR2_MASK GENMASK(5, 4)
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#define DWC2_HWCFG1_EP_DIR3_MASK GENMASK(7, 6)
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#define DWC2_HWCFG1_EP_DIR4_MASK GENMASK(9, 8)
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#define DWC2_HWCFG1_EP_DIR5_MASK GENMASK(11, 10)
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#define DWC2_HWCFG1_EP_DIR6_MASK GENMASK(13, 12)
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#define DWC2_HWCFG1_EP_DIR7_MASK GENMASK(15, 14)
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#define DWC2_HWCFG1_EP_DIR8_MASK GENMASK(17, 16)
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#define DWC2_HWCFG1_EP_DIR9_MASK GENMASK(19, 18)
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#define DWC2_HWCFG1_EP_DIR10_MASK GENMASK(21, 20)
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#define DWC2_HWCFG1_EP_DIR11_MASK GENMASK(23, 22)
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#define DWC2_HWCFG1_EP_DIR12_MASK GENMASK(25, 24)
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#define DWC2_HWCFG1_EP_DIR13_MASK GENMASK(27, 26)
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#define DWC2_HWCFG1_EP_DIR14_MASK GENMASK(29, 28)
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#define DWC2_HWCFG1_EP_DIR15_MASK GENMASK(31, 30)
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#define DWC2_HWCFG2_OP_MODE_MASK GENMASK(2, 0)
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#define DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY (0x0 << 3)
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#define DWC2_HWCFG2_ARCHITECTURE_EXT_DMA (0x1 << 3)
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#define DWC2_HWCFG2_ARCHITECTURE_INT_DMA (0x2 << 3)
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#define DWC2_HWCFG2_ARCHITECTURE_MASK GENMASK(4, 3)
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#define DWC2_HWCFG2_POINT2POINT BIT(5)
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#define DWC2_HWCFG2_HS_PHY_TYPE_MASK GENMASK(7, 6)
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#define DWC2_HWCFG2_FS_PHY_TYPE_MASK GENMASK(9, 8)
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#define DWC2_HWCFG2_NUM_DEV_EP_MASK GENMASK(13, 10)
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#define DWC2_HWCFG2_NUM_HOST_CHAN_MASK GENMASK(17, 14)
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#define DWC2_HWCFG2_PERIO_EP_SUPPORTED BIT(18)
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#define DWC2_HWCFG2_DYNAMIC_FIFO BIT(19)
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#define DWC2_HWCFG2_MULTI_PROC_INT BIT(20)
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#define DWC2_HWCFG2_NONPERIO_TX_Q_DEPTH_MASK GENMASK(23, 22)
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#define DWC2_HWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK GENMASK(25, 24)
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#define DWC2_HWCFG2_DEV_TOKEN_Q_DEPTH_MASK GENMASK(30, 26)
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#define DWC2_HWCFG3_XFER_SIZE_CNTR_WIDTH_MASK GENMASK(3, 0)
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#define DWC2_HWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK GENMASK(6, 4)
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#define DWC2_HWCFG3_OTG_FUNC BIT(7)
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#define DWC2_HWCFG3_I2C BIT(8)
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#define DWC2_HWCFG3_VENDOR_CTRL_IF BIT(9)
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#define DWC2_HWCFG3_OPTIONAL_FEATURES BIT(10)
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#define DWC2_HWCFG3_SYNCH_RESET_TYPE BIT(11)
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#define DWC2_HWCFG3_OTG_ENABLE_IC_USB BIT(12)
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#define DWC2_HWCFG3_OTG_ENABLE_HSIC BIT(13)
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#define DWC2_HWCFG3_OTG_LPM_EN BIT(15)
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#define DWC2_HWCFG3_DFIFO_DEPTH_MASK GENMASK(31, 16)
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#define DWC2_HWCFG4_NUM_DEV_PERIO_IN_EP_MASK GENMASK(3, 0)
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#define DWC2_HWCFG4_POWER_OPTIMIZ BIT(4)
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#define DWC2_HWCFG4_MIN_AHB_FREQ_MASK GENMASK(13, 5)
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#define DWC2_HWCFG4_UTMI_PHY_DATA_WIDTH_MASK GENMASK(15, 14)
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#define DWC2_HWCFG4_NUM_DEV_MODE_CTRL_EP_MASK GENMASK(19, 16)
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#define DWC2_HWCFG4_IDDIG_FILT_EN BIT(20)
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#define DWC2_HWCFG4_VBUS_VALID_FILT_EN BIT(21)
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#define DWC2_HWCFG4_A_VALID_FILT_EN BIT(22)
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#define DWC2_HWCFG4_B_VALID_FILT_EN BIT(23)
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#define DWC2_HWCFG4_SESSION_END_FILT_EN BIT(24)
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#define DWC2_HWCFG4_DED_FIFO_EN BIT(25)
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#define DWC2_HWCFG4_NUM_IN_EPS_MASK GENMASK(29, 26)
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#define DWC2_HWCFG4_DESC_DMA BIT(30)
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#define DWC2_HWCFG4_DESC_DMA_DYN BIT(31)
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#define DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ 0
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#define DWC2_HCFG_FSLSPCLKSEL_48_MHZ 1
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#define DWC2_HCFG_FSLSPCLKSEL_6_MHZ 2
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#define DWC2_HCFG_FSLSPCLKSEL_MASK GENMASK(1, 0)
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#define DWC2_HCFG_FSLSSUPP BIT(2)
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#define DWC2_HCFG_DESCDMA BIT(23)
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#define DWC2_HCFG_FRLISTEN_MASK GENMASK(25, 24)
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#define DWC2_HCFG_PERSCHEDENA BIT(26)
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#define DWC2_HCFG_PERSCHEDSTAT BIT(27)
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#define DWC2_HFIR_FRINT_MASK GENMASK(15, 0)
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#define DWC2_HFNUM_FRNUM_MASK GENMASK(15, 0)
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#define DWC2_HFNUM_FRREM_MASK GENMASK(31, 16)
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#define DWC2_HFNUM_MAX_FRNUM 0x3FFF
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#define DWC2_HPTXSTS_PTXFSPCAVAIL_MASK GENMASK(15, 0)
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#define DWC2_HPTXSTS_PTXQSPCAVAIL_MASK GENMASK(23, 16)
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#define DWC2_HPTXSTS_PTXQTOP_TERMINATE BIT(24)
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#define DWC2_HPTXSTS_PTXQTOP_TOKEN_MASK GENMASK(26, 25)
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#define DWC2_HPTXSTS_PTXQTOP_CHNUM_MASK GENMASK(30, 27)
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#define DWC2_HPTXSTS_PTXQTOP_ODD BIT(31)
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#define DWC2_HPRT0_PRTCONNSTS BIT(0)
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#define DWC2_HPRT0_PRTCONNDET BIT(1)
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#define DWC2_HPRT0_PRTENA BIT(2)
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#define DWC2_HPRT0_PRTENCHNG BIT(3)
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#define DWC2_HPRT0_PRTOVRCURRACT BIT(4)
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#define DWC2_HPRT0_PRTOVRCURRCHNG BIT(5)
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#define DWC2_HPRT0_PRTRES BIT(6)
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#define DWC2_HPRT0_PRTSUSP BIT(7)
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#define DWC2_HPRT0_PRTRST BIT(8)
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#define DWC2_HPRT0_PRTLNSTS_MASK GENMASK(11, 10)
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#define DWC2_HPRT0_PRTPWR BIT(12)
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#define DWC2_HPRT0_PRTTSTCTL_MASK GENMASK(16, 13)
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#define DWC2_HPRT0_PRTSPD_HIGH (0 << 17)
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#define DWC2_HPRT0_PRTSPD_FULL (1 << 17)
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#define DWC2_HPRT0_PRTSPD_LOW (2 << 17)
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#define DWC2_HPRT0_PRTSPD_MASK GENMASK(18, 17)
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#define DWC2_HPRT0_W1C_MASK (DWC2_HPRT0_PRTCONNDET | \
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DWC2_HPRT0_PRTENA | \
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DWC2_HPRT0_PRTENCHNG | \
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DWC2_HPRT0_PRTOVRCURRCHNG)
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#define DWC2_HAINT_CH0 BIT(0)
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#define DWC2_HAINT_CH1 BIT(1)
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#define DWC2_HAINT_CH2 BIT(2)
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#define DWC2_HAINT_CH3 BIT(3)
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#define DWC2_HAINT_CH4 BIT(4)
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#define DWC2_HAINT_CH5 BIT(5)
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#define DWC2_HAINT_CH6 BIT(6)
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#define DWC2_HAINT_CH7 BIT(7)
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#define DWC2_HAINT_CH8 BIT(8)
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#define DWC2_HAINT_CH9 BIT(9)
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#define DWC2_HAINT_CH10 BIT(10)
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#define DWC2_HAINT_CH11 BIT(11)
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#define DWC2_HAINT_CH12 BIT(12)
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#define DWC2_HAINT_CH13 BIT(13)
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#define DWC2_HAINT_CH14 BIT(14)
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#define DWC2_HAINT_CH15 BIT(15)
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#define DWC2_HAINT_CHINT_MASK GENMASK(15, 0)
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#define DWC2_HAINTMSK_CH0 BIT(0)
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#define DWC2_HAINTMSK_CH1 BIT(1)
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#define DWC2_HAINTMSK_CH2 BIT(2)
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#define DWC2_HAINTMSK_CH3 BIT(3)
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#define DWC2_HAINTMSK_CH4 BIT(4)
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#define DWC2_HAINTMSK_CH5 BIT(5)
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#define DWC2_HAINTMSK_CH6 BIT(6)
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#define DWC2_HAINTMSK_CH7 BIT(7)
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#define DWC2_HAINTMSK_CH8 BIT(8)
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#define DWC2_HAINTMSK_CH9 BIT(9)
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#define DWC2_HAINTMSK_CH10 BIT(10)
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#define DWC2_HAINTMSK_CH11 BIT(11)
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#define DWC2_HAINTMSK_CH12 BIT(12)
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#define DWC2_HAINTMSK_CH13 BIT(13)
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#define DWC2_HAINTMSK_CH14 BIT(14)
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#define DWC2_HAINTMSK_CH15 BIT(15)
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#define DWC2_HAINTMSK_CHINT_MASK GENMASK(15, 0)
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#define DWC2_HCCHAR_MPS_MASK GENMASK(10, 0)
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#define DWC2_HCCHAR_EPNUM_MASK GENMASK(14, 11)
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#define DWC2_HCCHAR_EPDIR BIT(15)
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#define DWC2_HCCHAR_LSPDDEV BIT(17)
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#define DWC2_HCCHAR_EPTYPE_CONTROL 0
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#define DWC2_HCCHAR_EPTYPE_ISOC 1
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#define DWC2_HCCHAR_EPTYPE_BULK 2
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#define DWC2_HCCHAR_EPTYPE_INTR 3
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#define DWC2_HCCHAR_EPTYPE_MASK GENMASK(19, 18)
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#define DWC2_HCCHAR_MULTICNT_MASK GENMASK(21, 20)
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#define DWC2_HCCHAR_DEVADDR_MASK GENMASK(28, 22)
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#define DWC2_HCCHAR_ODDFRM BIT(29)
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#define DWC2_HCCHAR_CHDIS BIT(30)
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#define DWC2_HCCHAR_CHEN BIT(31)
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#define DWC2_HCSPLT_PRTADDR_MASK GENMASK(6, 0)
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#define DWC2_HCSPLT_HUBADDR_MASK GENMASK(13, 7)
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#define DWC2_HCSPLT_XACTPOS_MASK GENMASK(15, 14)
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#define DWC2_HCSPLT_COMPSPLT BIT(16)
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#define DWC2_HCSPLT_SPLTENA BIT(31)
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#define DWC2_HCINT_XFERCOMP BIT(0)
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#define DWC2_HCINT_CHHLTD BIT(1)
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#define DWC2_HCINT_AHBERR BIT(2)
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#define DWC2_HCINT_STALL BIT(3)
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#define DWC2_HCINT_NAK BIT(4)
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#define DWC2_HCINT_ACK BIT(5)
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#define DWC2_HCINT_NYET BIT(6)
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#define DWC2_HCINT_XACTERR BIT(7)
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#define DWC2_HCINT_BBLERR BIT(8)
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#define DWC2_HCINT_FRMOVRUN BIT(9)
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#define DWC2_HCINT_DATATGLERR BIT(10)
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#define DWC2_HCINT_BNA BIT(11)
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#define DWC2_HCINT_XCS_XACT BIT(12)
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#define DWC2_HCINT_FRM_LIST_ROLL BIT(13)
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#define DWC2_HCINTMSK_XFERCOMPL BIT(0)
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#define DWC2_HCINTMSK_CHHLTD BIT(1)
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#define DWC2_HCINTMSK_AHBERR BIT(2)
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#define DWC2_HCINTMSK_STALL BIT(3)
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#define DWC2_HCINTMSK_NAK BIT(4)
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#define DWC2_HCINTMSK_ACK BIT(5)
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#define DWC2_HCINTMSK_NYET BIT(6)
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#define DWC2_HCINTMSK_XACTERR BIT(7)
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#define DWC2_HCINTMSK_BBLERR BIT(8)
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#define DWC2_HCINTMSK_FRMOVRUN BIT(9)
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#define DWC2_HCINTMSK_DATATGLERR BIT(10)
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#define DWC2_HCINTMSK_BNA BIT(11)
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#define DWC2_HCINTMSK_XCS_XACT BIT(12)
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#define DWC2_HCINTMSK_FRM_LIST_ROLL BIT(13)
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#define DWC2_HCTSIZ_XFERSIZE_MASK GENMASK(18, 0)
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#define DWC2_HCTSIZ_SCHINFO_MASK GENMASK(7, 0)
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#define DWC2_HCTSIZ_NTD_MASK GENMASK(15, 8)
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#define DWC2_HCTSIZ_PKTCNT_MASK GENMASK(28, 19)
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#define DWC2_HCTSIZ_PID_MASK GENMASK(30, 29)
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#define DWC2_HCTSIZ_DOPNG BIT(31)
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#define DWC2_HCDMA_CTD_MASK GENMASK(10, 3)
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#define DWC2_HCDMA_DMA_ADDR_MASK GENMASK(31, 11)
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#define DWC2_PCGCCTL_STOPPCLK BIT(0)
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#define DWC2_PCGCCTL_GATEHCLK BIT(1)
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#define DWC2_PCGCCTL_PWRCLMP BIT(2)
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#define DWC2_PCGCCTL_RSTPDWNMODULE BIT(3)
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#define DWC2_PCGCCTL_PHYSUSPENDED BIT(4)
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#define DWC2_PCGCCTL_ENBL_SLEEP_GATING BIT(5)
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#define DWC2_PCGCCTL_PHY_IN_SLEEP BIT(6)
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#define DWC2_PCGCCTL_DEEP_SLEEP BIT(7)
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#define DWC2_SNPSID_DEVID_VER_2xx (0x4f542 << 12)
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#define DWC2_SNPSID_DEVID_VER_3xx (0x4f543 << 12)
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#define DWC2_SNPSID_DEVID_MASK GENMASK(31, 12)
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/* Host controller specific */
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#define DWC2_HC_PID_DATA0 0
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#define DWC2_HC_PID_DATA2 1
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#define DWC2_HC_PID_DATA1 2
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#define DWC2_HC_PID_MDATA 3
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#define DWC2_HC_PID_SETUP 3
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/* roothub.a masks */
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#define RH_A_NDP GENMASK(7, 0) /* number of downstream ports */
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#define RH_A_PSM BIT(8) /* power switching mode */
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#define RH_A_NPS BIT(9) /* no power switching */
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#define RH_A_DT BIT(10) /* device type (mbz) */
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#define RH_A_OCPM BIT(11) /* over current protection mode */
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#define RH_A_NOCP BIT(12) /* no over current protection */
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#define RH_A_POTPGT GENMASK(31, 24) /* power on to power good time */
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/* roothub.b masks */
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#define RH_B_DR 0x0000ffff /* device removable flags */
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#define RH_B_PPCM 0xffff0000 /* port power control mask */
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/* Default driver configuration */
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#define DWC2_DMA_ENABLE
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#define DWC2_DMA_BURST_SIZE 32 /* DMA burst len */
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#undef DWC2_DFLT_SPEED_FULL /* Do not force DWC2 to FS */
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#define DWC2_ENABLE_DYNAMIC_FIFO /* Runtime FIFO size detect */
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#define DWC2_MAX_CHANNELS 16 /* Max # of EPs */
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#define DWC2_HOST_RX_FIFO_SIZE (516 + DWC2_MAX_CHANNELS)
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#define DWC2_HOST_NPERIO_TX_FIFO_SIZE 0x100 /* nPeriodic TX FIFO */
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#define DWC2_HOST_PERIO_TX_FIFO_SIZE 0x200 /* Periodic TX FIFO */
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#define DWC2_MAX_TRANSFER_SIZE 65535
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#define DWC2_MAX_PACKET_COUNT 511
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#define DWC2_PHY_TYPE_FS 0
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#define DWC2_PHY_TYPE_UTMI 1
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#define DWC2_PHY_TYPE_ULPI 2
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#define DWC2_PHY_TYPE DWC2_PHY_TYPE_UTMI /* PHY type */
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#ifndef DWC2_UTMI_WIDTH
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#define DWC2_UTMI_WIDTH 8 /* UTMI bus width (8/16) */
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#endif
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#undef DWC2_PHY_ULPI_DDR /* ULPI PHY uses DDR mode */
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#define DWC2_PHY_ULPI_EXT_VBUS /* ULPI PHY controls VBUS */
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#undef DWC2_I2C_ENABLE /* Enable I2C */
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#undef DWC2_ULPI_FS_LS /* ULPI is FS/LS */
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#undef DWC2_TS_DLINE /* External DLine pulsing */
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#undef DWC2_THR_CTL /* Threshold control */
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#define DWC2_TX_THR_LENGTH 64
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#undef DWC2_IC_USB_CAP /* IC Cap */
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#endif /* __DWC2_H__ */
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