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usb: dwc2: Clean up with bitfield macros

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Use FIELD_PREP, FIELD_GET, BIT, and GENMASK macros to standardize bit
manipulation across the DWC2 code, improving readability and
maintainability without altering functionality.

Signed-off-by: Kongyang Liu <seashell11234455@gmail.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
Link: https://lore.kernel.org/r/20250110-dwc2-dev-v4-4-987f4fd6f8b2@pigmoral.tech
Signed-off-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
This commit is contained in:
Kongyang Liu 2025-01-10 21:55:23 +08:00 committed by Mattijs Korpershoek
parent bd6ef5097d
commit a5699130f4
5 changed files with 515 additions and 851 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
drivers/usb/gadget/dwc2_udc_otg.c
View File

@ -29,6 +29,7 @@
#include <linux/delay.h> #include <linux/delay.h>
#include <linux/printk.h> #include <linux/printk.h>
#include <linux/bitfield.h>
#include <linux/errno.h> #include <linux/errno.h>
#include <linux/list.h> #include <linux/list.h>
@ -526,8 +527,8 @@ static void reconfig_usbd(struct dwc2_udc *dev)
} }
/* 8. Unmask EPO interrupts*/ /* 8. Unmask EPO interrupts*/
writel(((1 << EP0_CON) << DAINT_OUT_BIT) writel(FIELD_PREP(DAINT_OUTEP_MASK, BIT(EP0_CON)) |
| (1 << EP0_CON), &reg->device_regs.daintmsk); FIELD_PREP(DAINT_INEP_MASK, BIT(EP0_CON)), &reg->device_regs.daintmsk);
/* 9. Unmask device OUT EP common interrupts*/ /* 9. Unmask device OUT EP common interrupts*/
writel(DOEPMSK_INIT, &reg->device_regs.doepmsk); writel(DOEPMSK_INIT, &reg->device_regs.doepmsk);

246
drivers/usb/gadget/dwc2_udc_otg_regs.h
View File

@ -32,45 +32,44 @@ struct dwc2_usbotg_phy {
#define VB_VALOEN BIT(2) #define VB_VALOEN BIT(2)
/* DWC2_UDC_OTG_GOTINT */ /* DWC2_UDC_OTG_GOTINT */
#define GOTGINT_SES_END_DET (1<<2) #define GOTGINT_SES_END_DET BIT(2)
/* DWC2_UDC_OTG_GAHBCFG */ /* DWC2_UDC_OTG_GAHBCFG */
#define PTXFE_HALF (0<<8) #define PTXFE_HALF (0 << 8)
#define PTXFE_ZERO (1<<8) #define PTXFE_ZERO (1 << 8)
#define NPTXFE_HALF (0<<7) #define NPTXFE_HALF (0 << 7)
#define NPTXFE_ZERO (1<<7) #define NPTXFE_ZERO (1 << 7)
#define MODE_SLAVE (0<<5) #define MODE_SLAVE (0 << 5)
#define MODE_DMA (1<<5) #define MODE_DMA (1 << 5)
#define BURST_SINGLE (0<<1) #define BURST_SINGLE (0 << 1)
#define BURST_INCR (1<<1) #define BURST_INCR (1 << 1)
#define BURST_INCR4 (3<<1) #define BURST_INCR4 (3 << 1)
#define BURST_INCR8 (5<<1) #define BURST_INCR8 (5 << 1)
#define BURST_INCR16 (7<<1) #define BURST_INCR16 (7 << 1)
#define GBL_INT_UNMASK (1<<0) #define GBL_INT_UNMASK (1 << 0)
#define GBL_INT_MASK (0<<0) #define GBL_INT_MASK (0 << 0)
/* DWC2_UDC_OTG_GRSTCTL */ /* DWC2_UDC_OTG_GRSTCTL */
#define AHB_MASTER_IDLE (1u<<31) #define AHB_MASTER_IDLE BIT(31)
#define CORE_SOFT_RESET (0x1<<0) #define CORE_SOFT_RESET BIT(0)
/* DWC2_UDC_OTG_GINTSTS/DWC2_UDC_OTG_GINTMSK core interrupt register */ /* DWC2_UDC_OTG_GINTSTS/DWC2_UDC_OTG_GINTMSK core interrupt register */
#define INT_RESUME (1u<<31) #define INT_RESUME BIT(31)
#define INT_DISCONN (0x1<<29) #define INT_DISCONN BIT(29)
#define INT_CONN_ID_STS_CNG (0x1<<28) #define INT_CONN_ID_STS_CNG BIT(28)
#define INT_OUT_EP (0x1<<19) #define INT_OUT_EP BIT(19)
#define INT_IN_EP (0x1<<18) #define INT_IN_EP BIT(18)
#define INT_ENUMDONE (0x1<<13) #define INT_ENUMDONE BIT(13)
#define INT_RESET (0x1<<12) #define INT_RESET BIT(12)
#define INT_SUSPEND (0x1<<11) #define INT_SUSPEND BIT(11)
#define INT_EARLY_SUSPEND (0x1<<10) #define INT_EARLY_SUSPEND BIT(10)
#define INT_NP_TX_FIFO_EMPTY (0x1<<5) #define INT_GOUTNakEff BIT(7)
#define INT_RX_FIFO_NOT_EMPTY (0x1<<4) #define INT_GINNakEff BIT(6)
#define INT_SOF (0x1<<3) #define INT_NP_TX_FIFO_EMPTY BIT(5)
#define INT_OTG (0x1<<2) #define INT_RX_FIFO_NOT_EMPTY BIT(4)
#define INT_DEV_MODE (0x0<<0) #define INT_SOF BIT(3)
#define INT_HOST_MODE (0x1<<1) #define INT_OTG BIT(2)
#define INT_GOUTNakEff (0x01<<7) #define INT_HOST_MODE BIT(1)
#define INT_GINNakEff (0x01<<6)
#define FULL_SPEED_CONTROL_PKT_SIZE 8 #define FULL_SPEED_CONTROL_PKT_SIZE 8
#define FULL_SPEED_BULK_PKT_SIZE 64 #define FULL_SPEED_BULK_PKT_SIZE 64
@ -78,119 +77,117 @@ struct dwc2_usbotg_phy {
#define HIGH_SPEED_CONTROL_PKT_SIZE 64 #define HIGH_SPEED_CONTROL_PKT_SIZE 64
#define HIGH_SPEED_BULK_PKT_SIZE 512 #define HIGH_SPEED_BULK_PKT_SIZE 512
#define RX_FIFO_SIZE (1024) #define RX_FIFO_SIZE 1024
#define NPTX_FIFO_SIZE (1024) #define NPTX_FIFO_SIZE 1024
#define PTX_FIFO_SIZE (384) #define PTX_FIFO_SIZE 384
#define DEPCTL_TXFNUM_0 (0x0<<22) #define DEPCTL_TXFNUM_0 (0x0 << 22)
#define DEPCTL_TXFNUM_1 (0x1<<22) #define DEPCTL_TXFNUM_1 (0x1 << 22)
#define DEPCTL_TXFNUM_2 (0x2<<22) #define DEPCTL_TXFNUM_2 (0x2 << 22)
#define DEPCTL_TXFNUM_3 (0x3<<22) #define DEPCTL_TXFNUM_3 (0x3 << 22)
#define DEPCTL_TXFNUM_4 (0x4<<22) #define DEPCTL_TXFNUM_4 (0x4 << 22)
/* Enumeration speed */ /* Enumeration speed */
#define USB_HIGH_30_60MHZ (0x0<<1) #define USB_HIGH_30_60MHZ (0x0 << 1)
#define USB_FULL_30_60MHZ (0x1<<1) #define USB_FULL_30_60MHZ (0x1 << 1)
#define USB_LOW_6MHZ (0x2<<1) #define USB_LOW_6MHZ (0x2 << 1)
#define USB_FULL_48MHZ (0x3<<1) #define USB_FULL_48MHZ (0x3 << 1)
/* DWC2_UDC_OTG_GRXSTSP STATUS */ /* DWC2_UDC_OTG_GRXSTSP STATUS */
#define OUT_PKT_RECEIVED (0x2<<17) #define OUT_PKT_RECEIVED (0x2 << 17)
#define OUT_TRANSFER_COMPLELTED (0x3<<17) #define OUT_TRANSFER_COMPLELTED (0x3 << 17)
#define SETUP_TRANSACTION_COMPLETED (0x4<<17) #define SETUP_TRANSACTION_COMPLETED (0x4 << 17)
#define SETUP_PKT_RECEIVED (0x6<<17) #define SETUP_PKT_RECEIVED (0x6 << 17)
#define GLOBAL_OUT_NAK (0x1<<17) #define GLOBAL_OUT_NAK (0x1 << 17)
/* DWC2_UDC_OTG_DCTL device control register */ /* DWC2_UDC_OTG_DCTL device control register */
#define NORMAL_OPERATION (0x1<<0) #define NORMAL_OPERATION BIT(0)
#define SOFT_DISCONNECT (0x1<<1) #define SOFT_DISCONNECT BIT(1)
/* DWC2_UDC_OTG_DAINT device all endpoint interrupt register */ /* DWC2_UDC_OTG_DAINT device all endpoint interrupt register */
#define DAINT_OUT_BIT (16) #define DAINT_OUTEP_MASK GENMASK(31, 16)
#define DAINT_MASK (0xFFFF) #define DAINT_INEP_MASK GENMASK(15, 0)
/* DWC2_UDC_OTG_DIEPCTL0/DOEPCTL0 device /* DWC2_UDC_OTG_DIEPCTL0/DOEPCTL0 device
control IN/OUT endpoint 0 control register */ control IN/OUT endpoint 0 control register */
#define DEPCTL_EPENA (0x1<<31) #define DEPCTL_EPENA BIT(31)
#define DEPCTL_EPDIS (0x1<<30) #define DEPCTL_EPDIS BIT(30)
#define DEPCTL_SETD1PID (0x1<<29) #define DEPCTL_SETD1PID BIT(29)
#define DEPCTL_SETD0PID (0x1<<28) #define DEPCTL_SETD0PID BIT(28)
#define DEPCTL_SNAK (0x1<<27) #define DEPCTL_SNAK BIT(27)
#define DEPCTL_CNAK (0x1<<26) #define DEPCTL_CNAK BIT(26)
#define DEPCTL_STALL (0x1<<21) #define DEPCTL_STALL BIT(21)
#define DEPCTL_TYPE_BIT (18) #define DEPCTL_TYPE_MASK GENMASK(19, 18)
#define DEPCTL_TYPE_MASK (0x3<<18) #define DEPCTL_CTRL_TYPE (0x0 << 18)
#define DEPCTL_CTRL_TYPE (0x0<<18) #define DEPCTL_ISO_TYPE (0x1 << 18)
#define DEPCTL_ISO_TYPE (0x1<<18) #define DEPCTL_BULK_TYPE (0x2 << 18)
#define DEPCTL_BULK_TYPE (0x2<<18) #define DEPCTL_INTR_TYPE (0x3 << 18)
#define DEPCTL_INTR_TYPE (0x3<<18) #define DEPCTL_USBACTEP BIT(15)
#define DEPCTL_USBACTEP (0x1<<15) #define DEPCTL_NEXT_EP_MASK GENMASK(14, 11)
#define DEPCTL_NEXT_EP_BIT (11) #define DEPCTL_MPS_MASK GENMASK(10, 0)
#define DEPCTL_MPS_BIT (0)
#define DEPCTL_MPS_MASK (0x7FF)
#define DEPCTL0_MPS_64 (0x0<<0) #define DEPCTL0_MPS_64 (0x0 << 0)
#define DEPCTL0_MPS_32 (0x1<<0) #define DEPCTL0_MPS_32 (0x1 << 0)
#define DEPCTL0_MPS_16 (0x2<<0) #define DEPCTL0_MPS_16 (0x2 << 0)
#define DEPCTL0_MPS_8 (0x3<<0) #define DEPCTL0_MPS_8 (0x3 << 0)
#define DEPCTL_MPS_BULK_512 (512<<0) #define DEPCTL_MPS_BULK_512 (512 << 0)
#define DEPCTL_MPS_INT_MPS_16 (16<<0) #define DEPCTL_MPS_INT_MPS_16 (16 << 0)
#define DIEPCTL0_NEXT_EP_BIT (11) #define DIEPCTL0_NEXT_EP_BIT (11)
/* DWC2_UDC_OTG_DIEPMSK/DOEPMSK device IN/OUT endpoint /* DWC2_UDC_OTG_DIEPMSK/DOEPMSK device IN/OUT endpoint
common interrupt mask register */ common interrupt mask register */
/* DWC2_UDC_OTG_DIEPINTn/DOEPINTn device IN/OUT endpoint interrupt register */ /* DWC2_UDC_OTG_DIEPINTn/DOEPINTn device IN/OUT endpoint interrupt register */
#define BACK2BACK_SETUP_RECEIVED (0x1<<6) #define BACK2BACK_SETUP_RECEIVED BIT(6)
#define INTKNEPMIS (0x1<<5) #define INTKNEPMIS BIT(5)
#define INTKN_TXFEMP (0x1<<4) #define INTKN_TXFEMP BIT(4)
#define NON_ISO_IN_EP_TIMEOUT (0x1<<3) #define NON_ISO_IN_EP_TIMEOUT BIT(3)
#define CTRL_OUT_EP_SETUP_PHASE_DONE (0x1<<3) #define CTRL_OUT_EP_SETUP_PHASE_DONE BIT(3)
#define AHB_ERROR (0x1<<2) #define AHB_ERROR BIT(2)
#define EPDISBLD (0x1<<1) #define EPDISBLD BIT(1)
#define TRANSFER_DONE (0x1<<0) #define TRANSFER_DONE BIT(0)
#define USB_PHY_CTRL_EN0 (0x1 << 0) #define USB_PHY_CTRL_EN0 BIT(0)
/* OPHYPWR */ /* OPHYPWR */
#define PHY_0_SLEEP (0x1 << 5) #define PHY_0_SLEEP BIT(5)
#define OTG_DISABLE_0 (0x1 << 4) #define OTG_DISABLE_0 BIT(4)
#define ANALOG_PWRDOWN (0x1 << 3) #define ANALOG_PWRDOWN BIT(3)
#define FORCE_SUSPEND_0 (0x1 << 0) #define FORCE_SUSPEND_0 BIT(0)
/* URSTCON */ /* URSTCON */
#define HOST_SW_RST (0x1 << 4) #define HOST_SW_RST BIT(4)
#define PHY_SW_RST1 (0x1 << 3) #define PHY_SW_RST1 BIT(3)
#define PHYLNK_SW_RST (0x1 << 2) #define PHYLNK_SW_RST BIT(2)
#define LINK_SW_RST (0x1 << 1) #define LINK_SW_RST BIT(1)
#define PHY_SW_RST0 (0x1 << 0) #define PHY_SW_RST0 BIT(0)
/* OPHYCLK */ /* OPHYCLK */
#define COMMON_ON_N1 (0x1 << 7) #define COMMON_ON_N1 BIT(7)
#define COMMON_ON_N0 (0x1 << 4) #define COMMON_ON_N0 BIT(4)
#define ID_PULLUP0 (0x1 << 2) #define ID_PULLUP0 BIT(2)
#define CLK_SEL_24MHZ (0x3 << 0) #define CLK_SEL_24MHZ (0x3 << 0)
#define CLK_SEL_12MHZ (0x2 << 0) #define CLK_SEL_12MHZ (0x2 << 0)
#define CLK_SEL_48MHZ (0x0 << 0) #define CLK_SEL_48MHZ (0x0 << 0)
#define EXYNOS4X12_ID_PULLUP0 (0x01 << 3) #define EXYNOS4X12_ID_PULLUP0 BIT(3)
#define EXYNOS4X12_COMMON_ON_N0 (0x01 << 4) #define EXYNOS4X12_COMMON_ON_N0 BIT(4)
#define EXYNOS4X12_CLK_SEL_12MHZ (0x02 << 0) #define EXYNOS4X12_CLK_SEL_12MHZ (0x02 << 0)
#define EXYNOS4X12_CLK_SEL_24MHZ (0x05 << 0) #define EXYNOS4X12_CLK_SEL_24MHZ (0x05 << 0)
/* Device Configuration Register DCFG */ /* Device Configuration Register DCFG */
#define DEV_SPEED_HIGH_SPEED_20 (0x0 << 0) #define DEV_SPEED_HIGH_SPEED_20 (0x0 << 0)
#define DEV_SPEED_FULL_SPEED_20 (0x1 << 0) #define DEV_SPEED_FULL_SPEED_20 (0x1 << 0)
#define DEV_SPEED_LOW_SPEED_11 (0x2 << 0) #define DEV_SPEED_LOW_SPEED_11 (0x2 << 0)
#define DEV_SPEED_FULL_SPEED_11 (0x3 << 0) #define DEV_SPEED_FULL_SPEED_11 (0x3 << 0)
#define EP_MISS_CNT(x) (x << 18) #define EP_MISS_CNT(x) ((x) << 18)
#define DEVICE_ADDRESS(x) (x << 4) #define DEVICE_ADDRESS(x) ((x) << 4)
/* Core Reset Register (GRSTCTL) */ /* Core Reset Register (GRSTCTL) */
#define TX_FIFO_FLUSH (0x1 << 5) #define TX_FIFO_FLUSH BIT(5)
#define RX_FIFO_FLUSH (0x1 << 4) #define RX_FIFO_FLUSH BIT(4)
#define TX_FIFO_NUMBER(x) (x << 6) #define TX_FIFO_NUMBER(x) ((x) << 6)
#define TX_FIFO_FLUSH_ALL TX_FIFO_NUMBER(0x10) #define TX_FIFO_FLUSH_ALL TX_FIFO_NUMBER(0x10)
/* Masks definitions */ /* Masks definitions */
#define GINTMSK_INIT (INT_OUT_EP | INT_IN_EP | INT_RESUME | INT_ENUMDONE\ #define GINTMSK_INIT (INT_OUT_EP | INT_IN_EP | INT_RESUME | INT_ENUMDONE\
@ -201,29 +198,28 @@ struct dwc2_usbotg_phy {
| GBL_INT_UNMASK) | GBL_INT_UNMASK)
/* Device Endpoint X Transfer Size Register (DIEPTSIZX) */ /* Device Endpoint X Transfer Size Register (DIEPTSIZX) */
#define DIEPT_SIZ_PKT_CNT(x) (x << 19) #define DIEPT_SIZ_PKT_CNT(x) ((x) << 19)
#define DIEPT_SIZ_XFER_SIZE(x) (x << 0) #define DIEPT_SIZ_XFER_SIZE(x) ((x) << 0)
/* Device OUT Endpoint X Transfer Size Register (DOEPTSIZX) */ /* Device OUT Endpoint X Transfer Size Register (DOEPTSIZX) */
#define DOEPT_SIZ_PKT_CNT(x) (x << 19) #define DOEPT_SIZ_PKT_CNT(x) ((x) << 19)
#define DOEPT_SIZ_XFER_SIZE(x) (x << 0) #define DOEPT_SIZ_XFER_SIZE(x) ((x) << 0)
#define DOEPT_SIZ_XFER_SIZE_MAX_EP0 (0x7F << 0) #define DOEPT_SIZ_XFER_SIZE_MAX_EP0 (0x7F << 0)
#define DOEPT_SIZ_XFER_SIZE_MAX_EP (0x7FFF << 0) #define DOEPT_SIZ_XFER_SIZE_MAX_EP (0x7FFF << 0)
/* Device Endpoint-N Control Register (DIEPCTLn/DOEPCTLn) */ /* Device Endpoint-N Control Register (DIEPCTLn/DOEPCTLn) */
#define DIEPCTL_TX_FIFO_NUM(x) (x << 22) #define DIEPCTL_TX_FIFO_NUM_MASK GENMASK(25, 22)
#define DIEPCTL_TX_FIFO_NUM_MASK (~DIEPCTL_TX_FIFO_NUM(0xF))
/* Device ALL Endpoints Interrupt Register (DAINT) */ /* Device ALL Endpoints Interrupt Register (DAINT) */
#define DAINT_IN_EP_INT(x) (x << 0) #define DAINT_IN_EP_INT(x) ((x) << 0)
#define DAINT_OUT_EP_INT(x) (x << 16) #define DAINT_OUT_EP_INT(x) ((x) << 16)
/* User HW Config4 */ /* User HW Config4 */
#define GHWCFG4_NUM_IN_EPS_MASK (0xf << 26) #define GHWCFG4_NUM_IN_EPS_MASK (0xf << 26)
#define GHWCFG4_NUM_IN_EPS_SHIFT 26 #define GHWCFG4_NUM_IN_EPS_SHIFT 26
/* OTG general core configuration register (OTG_GCCFG:0x38) for STM32MP1 */ /* OTG general core configuration register (OTG_GCCFG:0x38) for STM32MP1 */
#define GGPIO_STM32_OTG_GCCFG_VBDEN BIT(21) #define GGPIO_STM32_OTG_GCCFG_VBDEN BIT(21)
#define GGPIO_STM32_OTG_GCCFG_IDEN BIT(22) #define GGPIO_STM32_OTG_GCCFG_IDEN BIT(22)
#endif #endif

21
drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c
View File

@ -19,6 +19,7 @@
#include <cpu_func.h> #include <cpu_func.h>
#include <log.h> #include <log.h>
#include <linux/bitfield.h>
#include <linux/bug.h> #include <linux/bug.h>
static u8 clear_feature_num; static u8 clear_feature_num;
@ -174,11 +175,11 @@ static int setdma_tx(struct dwc2_ep *ep, struct dwc2_request *req)
ctrl = readl(&reg->device_regs.in_endp[ep_num].diepctl); ctrl = readl(&reg->device_regs.in_endp[ep_num].diepctl);
/* Write the FIFO number to be used for this endpoint */ /* Write the FIFO number to be used for this endpoint */
ctrl &= DIEPCTL_TX_FIFO_NUM_MASK; ctrl &= ~DIEPCTL_TX_FIFO_NUM_MASK;
ctrl |= DIEPCTL_TX_FIFO_NUM(ep->fifo_num); ctrl |= FIELD_PREP(DIEPCTL_TX_FIFO_NUM_MASK, ep->fifo_num);
/* Clear reserved (Next EP) bits */ /* Clear reserved (Next EP) bits */
ctrl = (ctrl&~(EP_MASK<<DEPCTL_NEXT_EP_BIT)); ctrl &= ~DEPCTL_NEXT_EP_MASK;
writel(DEPCTL_EPENA | DEPCTL_CNAK | ctrl, &reg->device_regs.in_endp[ep_num].diepctl); writel(DEPCTL_EPENA | DEPCTL_CNAK | ctrl, &reg->device_regs.in_endp[ep_num].diepctl);
@ -380,7 +381,7 @@ static void process_ep_in_intr(struct dwc2_udc *dev)
debug_cond(DEBUG_IN_EP, debug_cond(DEBUG_IN_EP,
"*** %s: EP In interrupt : DAINT = 0x%x\n", __func__, ep_intr); "*** %s: EP In interrupt : DAINT = 0x%x\n", __func__, ep_intr);
ep_intr &= DAINT_MASK; ep_intr = FIELD_GET(DAINT_INEP_MASK, ep_intr);
while (ep_intr) { while (ep_intr) {
if (ep_intr & DAINT_IN_EP_INT(1)) { if (ep_intr & DAINT_IN_EP_INT(1)) {
@ -431,10 +432,10 @@ static void process_ep_out_intr(struct dwc2_udc *dev)
"*** %s: EP OUT interrupt : DAINT = 0x%x\n", "*** %s: EP OUT interrupt : DAINT = 0x%x\n",
__func__, ep_intr); __func__, ep_intr);
ep_intr = (ep_intr >> DAINT_OUT_BIT) & DAINT_MASK; ep_intr = FIELD_GET(DAINT_OUTEP_MASK, ep_intr);
while (ep_intr) { while (ep_intr) {
if (ep_intr & 0x1) { if (ep_intr & BIT(EP0_CON)) {
ep_intr_status = readl(&reg->device_regs.out_endp[ep_num].doepint); ep_intr_status = readl(&reg->device_regs.out_endp[ep_num].doepint);
debug_cond(DEBUG_OUT_EP != 0, debug_cond(DEBUG_OUT_EP != 0,
"\tEP%d-OUT : DOEPINT = 0x%x\n", "\tEP%d-OUT : DOEPINT = 0x%x\n",
@ -1114,10 +1115,10 @@ static void dwc2_udc_ep_activate(struct dwc2_ep *ep)
/* Read DEPCTLn register */ /* Read DEPCTLn register */
if (ep_is_in(ep)) { if (ep_is_in(ep)) {
ep_ctrl = readl(&reg->device_regs.in_endp[ep_num].diepctl); ep_ctrl = readl(&reg->device_regs.in_endp[ep_num].diepctl);
daintmsk = 1 << ep_num; daintmsk = FIELD_PREP(DAINT_INEP_MASK, BIT(ep_num));
} else { } else {
ep_ctrl = readl(&reg->device_regs.out_endp[ep_num].doepctl); ep_ctrl = readl(&reg->device_regs.out_endp[ep_num].doepctl);
daintmsk = (1 << ep_num) << DAINT_OUT_BIT; daintmsk = FIELD_PREP(DAINT_OUTEP_MASK, BIT(ep_num));
} }
debug("%s: EPCTRL%d = 0x%x, ep_is_in = %d\n", debug("%s: EPCTRL%d = 0x%x, ep_is_in = %d\n",
@ -1127,9 +1128,9 @@ static void dwc2_udc_ep_activate(struct dwc2_ep *ep)
* register. */ * register. */
if (!(ep_ctrl & DEPCTL_USBACTEP)) { if (!(ep_ctrl & DEPCTL_USBACTEP)) {
ep_ctrl = (ep_ctrl & ~DEPCTL_TYPE_MASK) | ep_ctrl = (ep_ctrl & ~DEPCTL_TYPE_MASK) |
(ep->bmAttributes << DEPCTL_TYPE_BIT); FIELD_PREP(DEPCTL_TYPE_MASK, ep->bmAttributes);
ep_ctrl = (ep_ctrl & ~DEPCTL_MPS_MASK) | ep_ctrl = (ep_ctrl & ~DEPCTL_MPS_MASK) |
(ep->ep.maxpacket << DEPCTL_MPS_BIT); FIELD_PREP(DEPCTL_MPS_MASK, ep->ep.maxpacket);
ep_ctrl |= (DEPCTL_SETD0PID | DEPCTL_USBACTEP | DEPCTL_SNAK); ep_ctrl |= (DEPCTL_SETD0PID | DEPCTL_USBACTEP | DEPCTL_SNAK);
if (ep_is_in(ep)) { if (ep_is_in(ep)) {

101
drivers/usb/host/dwc2.c
View File

@ -19,6 +19,7 @@
#include <asm/cache.h> #include <asm/cache.h>
#include <asm/io.h> #include <asm/io.h>
#include <dm/device_compat.h> #include <dm/device_compat.h>
#include <linux/bitfield.h>
#include <linux/delay.h> #include <linux/delay.h>
#include <linux/usb/otg.h> #include <linux/usb/otg.h>
#include <power/regulator.h> #include <power/regulator.h>
@ -95,10 +96,8 @@ static void init_fslspclksel(struct dwc2_core_regs *regs)
#ifdef DWC2_ULPI_FS_LS #ifdef DWC2_ULPI_FS_LS
uint32_t hwcfg2 = readl(&regs->global_regs.ghwcfg2); uint32_t hwcfg2 = readl(&regs->global_regs.ghwcfg2);
uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >> uint32_t hval = FIELD_GET(GHWCFG2_HS_PHY_TYPE_MASK, ghwcfg2);
DWC2_HWCFG2_HS_PHY_TYPE_OFFSET; uint32_t fval = FIELD_GET(GHWCFG2_FS_PHY_TYPE_MASK, ghwcfg2);
uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
if (hval == 2 && fval == 1) if (hval == 2 && fval == 1)
phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */ phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */
@ -106,7 +105,7 @@ static void init_fslspclksel(struct dwc2_core_regs *regs)
clrsetbits_le32(&regs->host_regs.hcfg, clrsetbits_le32(&regs->host_regs.hcfg,
DWC2_HCFG_FSLSPCLKSEL_MASK, DWC2_HCFG_FSLSPCLKSEL_MASK,
phyclk << DWC2_HCFG_FSLSPCLKSEL_OFFSET); FIELD_PREP(DWC2_HCFG_FSLSPCLKSEL_MASK, phyclk));
} }
/* /*
@ -120,7 +119,7 @@ static void dwc_otg_flush_tx_fifo(struct udevice *dev,
{ {
int ret; int ret;
writel(DWC2_GRSTCTL_TXFFLSH | (num << DWC2_GRSTCTL_TXFNUM_OFFSET), writel(DWC2_GRSTCTL_TXFFLSH | FIELD_PREP(DWC2_GRSTCTL_TXFNUM_MASK, num),
&regs->global_regs.grstctl); &regs->global_regs.grstctl);
ret = wait_for_bit_le32(&regs->global_regs.grstctl, DWC2_GRSTCTL_TXFFLSH, ret = wait_for_bit_le32(&regs->global_regs.grstctl, DWC2_GRSTCTL_TXFFLSH,
false, 1000, false); false, 1000, false);
@ -266,18 +265,14 @@ static void dwc_otg_core_host_init(struct udevice *dev,
writel(DWC2_HOST_RX_FIFO_SIZE, &regs->global_regs.grxfsiz); writel(DWC2_HOST_RX_FIFO_SIZE, &regs->global_regs.grxfsiz);
/* Non-periodic Tx FIFO */ /* Non-periodic Tx FIFO */
nptxfifosize |= DWC2_HOST_NPERIO_TX_FIFO_SIZE << nptxfifosize |= FIELD_PREP(DWC2_FIFOSIZE_DEPTH_MASK, DWC2_HOST_NPERIO_TX_FIFO_SIZE);
DWC2_FIFOSIZE_DEPTH_OFFSET; nptxfifosize |= FIELD_PREP(DWC2_FIFOSIZE_STARTADDR_MASK, DWC2_HOST_RX_FIFO_SIZE);
nptxfifosize |= DWC2_HOST_RX_FIFO_SIZE <<
DWC2_FIFOSIZE_STARTADDR_OFFSET;
writel(nptxfifosize, &regs->global_regs.gnptxfsiz); writel(nptxfifosize, &regs->global_regs.gnptxfsiz);
/* Periodic Tx FIFO */ /* Periodic Tx FIFO */
ptxfifosize |= DWC2_HOST_PERIO_TX_FIFO_SIZE << ptxfifosize |= FIELD_PREP(DWC2_FIFOSIZE_DEPTH_MASK, DWC2_HOST_PERIO_TX_FIFO_SIZE);
DWC2_FIFOSIZE_DEPTH_OFFSET; ptxfifosize |= FIELD_PREP(DWC2_FIFOSIZE_STARTADDR_MASK, DWC2_HOST_RX_FIFO_SIZE +
ptxfifosize |= (DWC2_HOST_RX_FIFO_SIZE + DWC2_HOST_NPERIO_TX_FIFO_SIZE);
DWC2_HOST_NPERIO_TX_FIFO_SIZE) <<
DWC2_FIFOSIZE_STARTADDR_OFFSET;
writel(ptxfifosize, &regs->global_regs.hptxfsiz); writel(ptxfifosize, &regs->global_regs.hptxfsiz);
} }
#endif #endif
@ -290,10 +285,8 @@ static void dwc_otg_core_host_init(struct udevice *dev,
dwc_otg_flush_rx_fifo(dev, regs); dwc_otg_flush_rx_fifo(dev, regs);
/* Flush out any leftover queued requests. */ /* Flush out any leftover queued requests. */
num_channels = readl(&regs->global_regs.ghwcfg2); num_channels = FIELD_GET(DWC2_HWCFG2_NUM_HOST_CHAN_MASK,
num_channels &= DWC2_HWCFG2_NUM_HOST_CHAN_MASK; readl(&regs->global_regs.ghwcfg2)) + 1;
num_channels >>= DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET;
num_channels += 1;
for (i = 0; i < num_channels; i++) for (i = 0; i < num_channels; i++)
clrsetbits_le32(&regs->host_regs.hc[i].hcchar, clrsetbits_le32(&regs->host_regs.hc[i].hcchar,
@ -390,7 +383,7 @@ static void dwc_otg_core_init(struct udevice *dev)
/* Program GI2CCTL.I2CEn */ /* Program GI2CCTL.I2CEn */
clrsetbits_le32(&regs->global_regs.gi2cctl, DWC2_GI2CCTL_I2CEN | clrsetbits_le32(&regs->global_regs.gi2cctl, DWC2_GI2CCTL_I2CEN |
DWC2_GI2CCTL_I2CDEVADDR_MASK, DWC2_GI2CCTL_I2CDEVADDR_MASK,
1 << DWC2_GI2CCTL_I2CDEVADDR_OFFSET); FIELD_PREP(DWC2_GI2CCTL_I2CDEVADDR_MASK, 1));
setbits_le32(&regs->global_regs.gi2cctl, DWC2_GI2CCTL_I2CEN); setbits_le32(&regs->global_regs.gi2cctl, DWC2_GI2CCTL_I2CEN);
#endif #endif
@ -429,10 +422,8 @@ static void dwc_otg_core_init(struct udevice *dev)
usbcfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M); usbcfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M);
#ifdef DWC2_ULPI_FS_LS #ifdef DWC2_ULPI_FS_LS
uint32_t hwcfg2 = readl(&regs->global_regs.ghwcfg2); uint32_t hwcfg2 = readl(&regs->global_regs.ghwcfg2);
uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >> uint32_t hval = FIELD_GET(DWC2_HWCFG2_HS_PHY_TYPE_MASK, ghwcfg2);
DWC2_HWCFG2_HS_PHY_TYPE_OFFSET; uint32_t fval = FIELD_GET(DWC2_HWCFG2_FS_PHY_TYPE_MASK, ghwcfg2);
uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
if (hval == 2 && fval == 1) { if (hval == 2 && fval == 1) {
usbcfg |= DWC2_GUSBCFG_ULPI_FSLS; usbcfg |= DWC2_GUSBCFG_ULPI_FSLS;
usbcfg |= DWC2_GUSBCFG_ULPI_CLK_SUS_M; usbcfg |= DWC2_GUSBCFG_ULPI_CLK_SUS_M;
@ -444,12 +435,11 @@ static void dwc_otg_core_init(struct udevice *dev)
writel(usbcfg, &regs->global_regs.gusbcfg); writel(usbcfg, &regs->global_regs.gusbcfg);
/* Program the GAHBCFG Register. */ /* Program the GAHBCFG Register. */
switch (readl(&regs->global_regs.ghwcfg2) & DWC2_HWCFG2_ARCHITECTURE_MASK) { switch (FIELD_GET(DWC2_HWCFG2_ARCHITECTURE_MASK, readl(&regs->global_regs.ghwcfg2))) {
case DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY: case DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY:
break; break;
case DWC2_HWCFG2_ARCHITECTURE_EXT_DMA: case DWC2_HWCFG2_ARCHITECTURE_EXT_DMA:
ahbcfg |= (LOG2(brst_sz >> 1) << DWC2_GAHBCFG_HBURSTLEN_OFFSET) & ahbcfg |= FIELD_PREP(DWC2_GAHBCFG_HBURSTLEN_MASK, LOG2(brst_sz >> 1));
DWC2_GAHBCFG_HBURSTLEN_MASK;
#ifdef DWC2_DMA_ENABLE #ifdef DWC2_DMA_ENABLE
ahbcfg |= DWC2_GAHBCFG_DMAENABLE; ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
@ -492,11 +482,11 @@ static void dwc_otg_hc_init(struct dwc2_core_regs *regs, uint8_t hc_num,
uint8_t ep_is_in, uint8_t ep_type, uint16_t max_packet) uint8_t ep_is_in, uint8_t ep_type, uint16_t max_packet)
{ {
struct dwc2_hc_regs *hc_regs = &regs->host_regs.hc[hc_num]; struct dwc2_hc_regs *hc_regs = &regs->host_regs.hc[hc_num];
uint32_t hcchar = (dev_addr << DWC2_HCCHAR_DEVADDR_OFFSET) | u32 hcchar = FIELD_PREP(DWC2_HCCHAR_DEVADDR_MASK, dev_addr) |
(ep_num << DWC2_HCCHAR_EPNUM_OFFSET) | FIELD_PREP(DWC2_HCCHAR_EPNUM_MASK, ep_num) |
(ep_is_in << DWC2_HCCHAR_EPDIR_OFFSET) | FIELD_PREP(DWC2_HCCHAR_EPDIR, ep_is_in) |
(ep_type << DWC2_HCCHAR_EPTYPE_OFFSET) | FIELD_PREP(DWC2_HCCHAR_EPTYPE_MASK, ep_type) |
(max_packet << DWC2_HCCHAR_MPS_OFFSET); FIELD_PREP(DWC2_HCCHAR_MPS_MASK, max_packet);
if (dev->speed == USB_SPEED_LOW) if (dev->speed == USB_SPEED_LOW)
hcchar |= DWC2_HCCHAR_LSPDDEV; hcchar |= DWC2_HCCHAR_LSPDDEV;
@ -517,8 +507,8 @@ static void dwc_otg_hc_init_split(struct dwc2_hc_regs *hc_regs,
uint32_t hcsplt = 0; uint32_t hcsplt = 0;
hcsplt = DWC2_HCSPLT_SPLTENA; hcsplt = DWC2_HCSPLT_SPLTENA;
hcsplt |= hub_devnum << DWC2_HCSPLT_HUBADDR_OFFSET; hcsplt |= FIELD_PREP(DWC2_HCSPLT_HUBADDR_MASK, hub_devnum);
hcsplt |= hub_port << DWC2_HCSPLT_PRTADDR_OFFSET; hcsplt |= FIELD_PREP(DWC2_HCSPLT_PRTADDR_MASK, hub_port);
/* Program the HCSPLIT register for SPLITs */ /* Program the HCSPLIT register for SPLITs */
writel(hcsplt, &hc_regs->hcsplt); writel(hcsplt, &hc_regs->hcsplt);
@ -567,11 +557,14 @@ static int dwc_otg_submit_rh_msg_in_status(struct dwc2_core_regs *regs,
if (hprt0 & DWC2_HPRT0_PRTPWR) if (hprt0 & DWC2_HPRT0_PRTPWR)
port_status |= USB_PORT_STAT_POWER; port_status |= USB_PORT_STAT_POWER;
if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == DWC2_HPRT0_PRTSPD_LOW) switch (FIELD_GET(DWC2_HPRT0_PRTSPD_MASK, hprt0)) {
case DWC2_HPRT0_PRTSPD_LOW:
port_status |= USB_PORT_STAT_LOW_SPEED; port_status |= USB_PORT_STAT_LOW_SPEED;
else if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == break;
DWC2_HPRT0_PRTSPD_HIGH) case DWC2_HPRT0_PRTSPD_HIGH:
port_status |= USB_PORT_STAT_HIGH_SPEED; port_status |= USB_PORT_STAT_HIGH_SPEED;
break;
}
if (hprt0 & DWC2_HPRT0_PRTENCHNG) if (hprt0 & DWC2_HPRT0_PRTENCHNG)
port_change |= USB_PORT_STAT_C_ENABLE; port_change |= USB_PORT_STAT_C_ENABLE;
@ -822,9 +815,8 @@ int wait_for_chhltd(struct dwc2_hc_regs *hc_regs, uint32_t *sub, u8 *toggle)
hcint = readl(&hc_regs->hcint); hcint = readl(&hc_regs->hcint);
hctsiz = readl(&hc_regs->hctsiz); hctsiz = readl(&hc_regs->hctsiz);
*sub = (hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK) >> *sub = FIELD_GET(DWC2_HCTSIZ_XFERSIZE_MASK, hctsiz);
DWC2_HCTSIZ_XFERSIZE_OFFSET; *toggle = FIELD_GET(DWC2_HCTSIZ_PID_MASK, hctsiz);
*toggle = (hctsiz & DWC2_HCTSIZ_PID_MASK) >> DWC2_HCTSIZ_PID_OFFSET;
debug("%s: HCINT=%08x sub=%u toggle=%d\n", __func__, hcint, *sub, debug("%s: HCINT=%08x sub=%u toggle=%d\n", __func__, hcint, *sub,
*toggle); *toggle);
@ -856,9 +848,9 @@ static int transfer_chunk(struct dwc2_hc_regs *hc_regs, void *aligned_buffer,
debug("%s: chunk: pid %d xfer_len %u pkts %u\n", __func__, debug("%s: chunk: pid %d xfer_len %u pkts %u\n", __func__,
*pid, xfer_len, num_packets); *pid, xfer_len, num_packets);
writel((xfer_len << DWC2_HCTSIZ_XFERSIZE_OFFSET) | writel(FIELD_PREP(DWC2_HCTSIZ_XFERSIZE_MASK, xfer_len) |
(num_packets << DWC2_HCTSIZ_PKTCNT_OFFSET) | FIELD_PREP(DWC2_HCTSIZ_PKTCNT_MASK, num_packets) |
(*pid << DWC2_HCTSIZ_PID_OFFSET), FIELD_PREP(DWC2_HCTSIZ_PID_MASK, *pid),
&hc_regs->hctsiz); &hc_regs->hctsiz);
if (xfer_len) { if (xfer_len) {
@ -885,8 +877,8 @@ static int transfer_chunk(struct dwc2_hc_regs *hc_regs, void *aligned_buffer,
clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK | clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS | DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS |
DWC2_HCCHAR_ODDFRM, DWC2_HCCHAR_ODDFRM,
(1 << DWC2_HCCHAR_MULTICNT_OFFSET) | FIELD_PREP(DWC2_HCCHAR_MULTICNT_MASK, 1) |
(odd_frame << DWC2_HCCHAR_ODDFRM_OFFSET) | FIELD_PREP(DWC2_HCCHAR_ODDFRM, odd_frame) |
DWC2_HCCHAR_CHEN); DWC2_HCCHAR_CHEN);
ret = wait_for_chhltd(hc_regs, &sub, pid); ret = wait_for_chhltd(hc_regs, &sub, pid);
@ -950,8 +942,7 @@ int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev,
uint8_t hub_port; uint8_t hub_port;
uint32_t hprt0 = readl(&regs->host_regs.hprt0); uint32_t hprt0 = readl(&regs->host_regs.hprt0);
if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == if (FIELD_GET(DWC2_HPRT0_PRTSPD_MASK, hprt0) == DWC2_HPRT0_PRTSPD_HIGH) {
DWC2_HPRT0_PRTSPD_HIGH) {
usb_find_usb2_hub_address_port(dev, &hub_addr, usb_find_usb2_hub_address_port(dev, &hub_addr,
&hub_port); &hub_port);
dwc_otg_hc_init_split(hc_regs, hub_addr, hub_port); dwc_otg_hc_init_split(hc_regs, hub_addr, hub_port);
@ -995,17 +986,17 @@ int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev,
stop_transfer = 0; stop_transfer = 0;
if (hcint & DWC2_HCINT_NYET) { if (hcint & DWC2_HCINT_NYET) {
ret = 0; ret = 0;
int frame_num = DWC2_HFNUM_MAX_FRNUM & int frame_num = FIELD_GET(DWC2_HFNUM_FRNUM_MASK,
readl(&host_regs->hfnum); readl(&host_regs->hfnum));
if (((frame_num - ssplit_frame_num) &
DWC2_HFNUM_MAX_FRNUM) > 4) if (((frame_num - ssplit_frame_num) & DWC2_HFNUM_FRNUM_MASK) > 4)
ret = -EAGAIN; ret = -EAGAIN;
} else } else
complete_split = 0; complete_split = 0;
} else if (do_split) { } else if (do_split) {
if (hcint & DWC2_HCINT_ACK) { if (hcint & DWC2_HCINT_ACK) {
ssplit_frame_num = DWC2_HFNUM_MAX_FRNUM & ssplit_frame_num = FIELD_GET(DWC2_HFNUM_FRNUM_MASK,
readl(&host_regs->hfnum); readl(&host_regs->hfnum));
ret = 0; ret = 0;
complete_split = 1; complete_split = 1;
} }
@ -1183,8 +1174,8 @@ static int dwc2_init_common(struct udevice *dev, struct dwc2_priv *priv)
dev_info(dev, "Core Release: %x.%03x\n", dev_info(dev, "Core Release: %x.%03x\n",
snpsid >> 12 & 0xf, snpsid & 0xfff); snpsid >> 12 & 0xf, snpsid & 0xfff);
if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx && if (FIELD_GET(DWC2_SNPSID_DEVID_MASK, snpsid) != DWC2_SNPSID_DEVID_VER_2xx &&
(snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_3xx) { FIELD_GET(DWC2_SNPSID_DEVID_MASK, snpsid) != DWC2_SNPSID_DEVID_VER_3xx) {
dev_info(dev, "SNPSID invalid (not DWC2 OTG device): %08x\n", dev_info(dev, "SNPSID invalid (not DWC2 OTG device): %08x\n",
snpsid); snpsid);
return -ENODEV; return -ENODEV;

993
drivers/usb/host/dwc2.h
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