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Merge tag 'u-boot-socfpga-next-20251217' of https://source.denx.de/u-boot/custodians/u-boot-socfpga into next

Browse Source 
This pull request brings together a set of fixes and enhancements across
the SoCFPGA platform family, with a focus on MMC/SPL robustness, EFI
boot enablement, and Agilex5 SD/eMMC support.

CI: https://source.denx.de/u-boot/custodians/u-boot-socfpga/-/pipelines/28776

Highlights:

  *
    SPL / MMC:
      o
        Fix Kconfig handling for
        SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
      o
        Correct raw sector calculations and respect explicit sector values
        when loading U-Boot from MMC in SPL
      o
        Adjust raw MMC loading logic for SoCFPGA platforms
  *
    EFI boot:
      o
        Permit EFI booting on SoCFPGA platforms
      o
        Disable mkeficapsule tool build for Arria 10 where unsupported
  *
    Agilex5:
      o
        Upgrade SDHCI controller from SD4HC to SD6HC
      o
        Enable MMC and Cadence SDHCI support in defconfig
      o
        Add dedicated eMMC device tree and defconfig for Agilex5 SoCDK
      o
        Revert incorrect GPIO configuration for SDIO_SEL
      o
        Refine U-Boot DT handling for SD and eMMC boot variants
  *
    SPI:
      o
        Allow disabling the DesignWare SPI driver in SPL via Kconfig
  *
    Board / configuration fixes:
      o
        Enable random MAC address generation for Cyclone V
      o
        Fix DE0-Nano-SoC boot configuration
      o
        Remove obsolete or conflicting options from multiple legacy
        SoCFPGA defconfigs
This commit is contained in:
Tom Rini 2025-12-18 08:06:10 -06:00
commit 930eff5416
73 changed files with 679 additions and 196 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm/dts/Makefile
View File

@ -451,6 +451,7 @@ dtb-$(CONFIG_TARGET_THUNDERX_88XX) += thunderx-88xx.dtb
dtb-$(CONFIG_ARCH_SOCFPGA) += \
socfpga_agilex5_socdk.dtb \
socfpga_agilex5_socdk_emmc.dtb \
socfpga_arria5_secu1.dtb \
socfpga_arria5_socdk.dtb \
socfpga_arria10_chameleonv3_270_2.dtb \

3
arch/arm/dts/rk3588-rock-5b-plus-u-boot.dtsi Normal file
View File

@ -0,0 +1,3 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
#include "rk3588-rock-5b-u-boot.dtsi"

5
arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
View File

@ -46,6 +46,11 @@
};
};
&saradc {
bootph-pre-ram;
vdd-microvolts = <1800000>;
};
&sdhci {
cap-mmc-highspeed;
mmc-hs200-1_8v;

3
arch/arm/dts/rk3588-rock-5t-u-boot.dtsi Normal file
View File

@ -0,0 +1,3 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
#include "rk3588-rock-5b-u-boot.dtsi"

33
arch/arm/dts/rockchip-u-boot.dtsi
View File

@ -226,5 +226,38 @@
};
};
#endif /* CONFIG_ROCKCHIP_SPI_IMAGE */
#ifdef CONFIG_ROCKCHIP_MASKROM_IMAGE
simple-bin-usb471 {
filename = "u-boot-rockchip-usb471.bin";
#ifdef CONFIG_ROCKCHIP_EXTERNAL_TPL
rockchip-tpl {
};
#elif defined(CONFIG_TPL)
u-boot-tpl {
no-write-symbols;
};
#endif
};
simple-bin-usb472 {
filename = "u-boot-rockchip-usb472.bin";
pad-byte = <0x00>;
u-boot-spl {
no-write-symbols;
};
#ifdef HAS_FIT
fit {
insert-template = <&fit_template>;
#else
u-boot-img {
#endif
offset = <(CONFIG_SPL_LOAD_FIT_ADDRESS - CFG_SYS_SDRAM_BASE)>;
};
};
#endif /* CONFIG_ROCKCHIP_MASKROM_IMAGE */
};
#endif /* CONFIG_SPL */

14
arch/arm/dts/socfpga_agilex5-u-boot.dtsi
View File

@ -681,17 +681,6 @@
bootph-all;
};
&gpio1 {
/* Configure GPIO 1 pin 3 as output pin with value 0 during GPIO probe */
portb: gpio-controller@0{
sdio_sel {
gpio-hog;
gpios = <3 GPIO_ACTIVE_HIGH>;
output-low;
};
};
};
&i2c0 {
reset-names = "i2c";
};
@ -709,7 +698,8 @@
};
&mmc {
resets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>;
resets = <&rst COMBOPHY_RESET>, <&rst SDMMC_OCP_RESET>, <&rst SDMMC_RESET>;
reset-names = "combophy", "sdmmc-ocp", "sdhc-reset";
};
&porta {

29
arch/arm/dts/socfpga_agilex5.dtsi
View File

@ -303,30 +303,33 @@
status = "disabled";
};
combophy0: combophy@0 {
#phy-cells = <0>;
phy-type = <1>;
compatible = "cdns,combophy";
reg = <0x10808000 0x1000>;
resets = <&rst COMBOPHY_RESET>;
reset-names = "reset";
status = "disabled";
sd_emmc_power: regulator-fixed-3p3v {
compatible = "regulator-fixed";
regulator-name = "card-power";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
sd_io_1v8_reg: regulator-1p8v {
compatible = "regulator-gpio";
regulator-name = "sd-bus-io-power";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
states = <1800000 0x1>,
<3300000 0x0>;
};
mmc: mmc0@10808000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "cdns,sd4hc";
compatible = "altr,agilex5-sd6hc", "cdns,sd6hc";
reg = <0x10808000 0x1000>;
interrupts = <0 96 4>;
phys = <&combophy0>;
phy-names = "combo-phy";
clocks = <&clkmgr AGILEX5_L4_MP_CLK>,
<&clkmgr AGILEX5_SDMMC_CLK>;
clock-names = "biu", "ciu";
fifo-depth = <0x800>;
resets = <&rst SDMMC_RESET>;
reset-names = "reset";
iommus = <&smmu 5>;
status = "disabled";
};

79
arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
View File

@ -91,53 +91,46 @@
bootph-all;
};
&mmc {
status = "okay";
bus-width = <4>;
sd-uhs-sdr50;
cap-mmc-highspeed;
&gpio1 {
portb: gpio-controller@0 {
bootph-all;
};
};
&sd_emmc_power {
bootph-all;
};
&combophy0 {
status = "okay";
&sd_io_1v8_reg {
gpios = <&portb 3 GPIO_ACTIVE_HIGH>;
bootph-all;
};
&mmc {
status = "okay";
no-mmc;
no-1-8-v;
disable-wp;
cap-sd-highspeed;
vmmc-supply = <&sd_emmc_power>;
vqmmc-supply = <&sd_io_1v8_reg>;
max-frequency = <200000000>;
/* SD card default speed (DS) and UHS-I SDR12 mode timing configuration */
cdns,phy-dqs-timing-delay-sd-ds = <0x00780000>;
cdns,phy-gate-lpbk_ctrl-delay-sd-ds = <0x81a40040>;
cdns,phy-dll-slave-ctrl-sd-ds = <0x00a000fe>;
cdns,phy-dq-timing-delay-sd-ds = <0x28000001>;
/* SD card high speed and UHS-I SDR25 mode timing configuration */
cdns,phy-dqs-timing-delay-sd-hs = <0x780001>;
cdns,phy-gate-lpbk_ctrl-delay-sd-hs = <0x81a40040>;
cdns,phy-dq-timing-delay-sd-hs = <0x10000001>;
cdns,ctrl-hrs16-slave-ctrl-sd-hs = <0x101>;
cdns,ctrl-hrs07-timing-delay-sd-hs = <0xA0001>;
bootph-all;
cdns,phy-use-ext-lpbk-dqs = <1>;
cdns,phy-use-lpbk-dqs = <1>;
cdns,phy-use-phony-dqs = <1>;
cdns,phy-use-phony-dqs-cmd = <1>;
cdns,phy-io-mask-always-on = <0>;
cdns,phy-io-mask-end = <5>;
cdns,phy-io-mask-start = <0>;
cdns,phy-data-select-oe-end = <1>;
cdns,phy-sync-method = <1>;
cdns,phy-sw-half-cycle-shift = <0>;
cdns,phy-rd-del-sel = <52>;
cdns,phy-underrun-suppress = <1>;
cdns,phy-gate-cfg-always-on = <1>;
cdns,phy-param-dll-bypass-mode = <1>;
cdns,phy-param-phase-detect-sel = <2>;
cdns,phy-param-dll-start-point = <254>;
cdns,phy-read-dqs-cmd-delay = <0>;
cdns,phy-clk-wrdqs-delay = <0>;
cdns,phy-clk-wr-delay = <0>;
cdns,phy-read-dqs-delay = <0>;
cdns,phy-phony-dqs-timing = <0>;
cdns,hrs09-rddata-en = <1>;
cdns,hrs09-rdcmd-en = <1>;
cdns,hrs09-extended-wr-mode = <1>;
cdns,hrs09-extended-rd-mode = <1>;
cdns,hrs10-hcsdclkadj = <3>;
cdns,hrs16-wrdata1-sdclk-dly = <0>;
cdns,hrs16-wrdata0-sdclk-dly = <0>;
cdns,hrs16-wrcmd1-sdclk-dly = <0>;
cdns,hrs16-wrcmd0-sdclk-dly = <0>;
cdns,hrs16-wrdata1-dly = <0>;
cdns,hrs16-wrdata0-dly = <0>;
cdns,hrs16-wrcmd1-dly = <0>;
cdns,hrs16-wrcmd0-dly = <0>;
cdns,hrs07-rw-compensate = <10>;
cdns,hrs07-idelay-val = <0>;
};
&qspi {

172
arch/arm/dts/socfpga_agilex5_socdk_emmc-u-boot.dtsi Normal file
View File

@ -0,0 +1,172 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* U-Boot additions for Agilex5 SocDK eMMC
*
* Copyright (C) 2025 Altera Corporation <www.altera.com>
*/
#include "socfpga_agilex5-u-boot.dtsi"
/{
aliases {
spi0 = &qspi;
freeze_br0 = &freeze_controller;
};
soc {
freeze_controller: freeze_controller@0x20000450 {
compatible = "altr,freeze-bridge-controller";
reg = <0x20000450 0x00000010>;
status = "disabled";
};
};
/*
* Both Memory base address and size default info is retrieved from HW setting.
* Reconfiguration / Overwrite these info can be done with examples below.
*
* When LPDDR ECC is enabled, the last 1/8 of the memory region must
* be reserved for the Inline ECC buffer.
*
* Example for memory size with 2GB:
* memory {
* reg = <0x0 0x80000000 0x0 0x80000000>;
* };
*
* Example for memory size with 8GB:
* memory {
* reg = <0x0 0x80000000 0x0 0x80000000>,
* <0x8 0x80000000 0x1 0x80000000>;
* };
*
* Example for memory size with 32GB:
* memory {
* reg = <0x0 0x80000000 0x0 0x80000000>,
* <0x8 0x80000000 0x7 0x80000000>;
* };
*
* Example for memory size with 512GB:
* memory {
* reg = <0x0 0x80000000 0x0 0x80000000>,
* <0x8 0x80000000 0x7 0x80000000>,
* <0x88 0x00000000 0x78 0x00000000>;
* };
*
* Example for memory size with 2GB with LPDDR Inline ECC ON:
* memory {
* reg = <0x0 0x80000000 0x0 0x70000000>;
* };
*
* Example for memory size with 8GB with LPDDR Inline ECC ON:
* memory {
* reg = <0x0 0x80000000 0x0 0x80000000>,
* <0x8 0x80000000 0x1 0x40000000>;
* };
*/
chosen {
stdout-path = "serial0:115200n8";
u-boot,spl-boot-order = &mmc,&flash0,&nand,"/memory";
};
};
&flash0 {
compatible = "jedec,spi-nor";
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
bootph-all;
/delete-property/ cdns,read-delay;
};
&flash1 {
bootph-all;
};
&i3c0 {
bootph-all;
};
&i3c1 {
bootph-all;
};
&gpio1 {
portb: gpio-controller@0 {
bootph-all;
};
};
&sd_emmc_power {
bootph-all;
};
&emmc_io_1v8_reg {
bootph-all;
};
&mmc {
bootph-all;
};
&qspi {
status = "okay";
};
&nand {
status = "disabled";
bootph-all;
};
&timer0 {
bootph-all;
};
&timer1 {
bootph-all;
};
&timer2 {
bootph-all;
};
&timer3 {
bootph-all;
};
&watchdog0 {
bootph-all;
};
&gmac0 {
status = "okay";
phy-mode = "rgmii";
phy-handle = <&emac0_phy0>;
max-frame-size = <9000>;
mdio0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwxgmac-mdio";
emac0_phy0: ethernet-phy@0 {
reg = <0>;
};
};
};
&gmac2 {
status = "okay";
phy-mode = "rgmii";
phy-handle = <&emac2_phy0>;
max-frame-size = <9000>;
mdio0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwxgmac-mdio";
emac2_phy0: ethernet-phy@0 {
reg = <0>;
};
};
};

49
arch/arm/dts/socfpga_agilex5_socdk_emmc.dts Normal file
View File

@ -0,0 +1,49 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2025 Altera Corporation <www.altera.com>
*/
#include "socfpga_agilex5_socdk.dts"
/ {
soc {
emmc_io_1v8_reg: regulator-fixed-1p8v {
compatible = "regulator-fixed";
regulator-name = "emmc-io-power";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
};
};
&mmc {
status = "okay";
no-sd;
no-sdio;
disable-wp;
non-removable;
cap-mmc-highspeed;
bus-width = <8>;
vmmc-supply = <&sd_emmc_power>;
vqmmc-supply = <&emmc_io_1v8_reg>;
max-frequency = <200000000>;
/* eMMC legacy mode timing configuration */
cdns,phy-dqs-timing-delay-sd-ds = <0x00780000>;
cdns,phy-gate-lpbk-ctrl-delay-sd-ds = <0x81a40040>;
cdns,phy-dll-slave-ctrl-sd-ds = <0x00a000fe>;
cdns,phy-dq-timing-delay-sd-ds = <0x28000001>;
/* eMMC SDR mode timing configuration */
cdns,phy-dqs-timing-delay-emmc-sdr = <0x780001>;
cdns,phy-gate-lpbk-ctrl-delay-emmc-sdr = <0x81a40040>;
cdns,phy-dll-slave-ctrl-emmc-sdr = <0x00000000>;
cdns,phy-dq-timing-delay-emmc-sdr = <0x10000001>;
cdns,ctrl-hrs09-timing-delay-emmc-sdr = <0x1800c>;
cdns,ctrl-hrs10-lpbk-ctrl-delay-emmc-sdr = <0x30000>;
cdns,ctrl-hrs16-slave-ctrl-emmc-sdr = <0x101>;
cdns,ctrl-hrs07-timing-delay-emmc-sdr = <0xA0001>;
};

3
arch/arm/include/asm/arch-rockchip/sdram.h
View File

@ -87,6 +87,9 @@ enum {
#define SYS_REG_CS1_COL_SHIFT(ch) (0 + (ch) * 2)
#define SYS_REG_CS1_COL_MASK 3
/* Get sdram type decode from reg */
u8 rockchip_sdram_type(phys_addr_t reg);
/* Get sdram size decode from reg */
size_t rockchip_sdram_size(phys_addr_t reg);

14
arch/arm/mach-rockchip/Kconfig
View File

@ -705,6 +705,14 @@ config ROCKCHIP_SPI_IMAGE
option to produce a SPI-flash image containing U-Boot. The image
is built by binman. U-Boot sits near the start of the image.
config ROCKCHIP_MASKROM_IMAGE
bool "Build a maskrom mode image for Rockchip"
depends on TPL || ROCKCHIP_EXTERNAL_TPL
select SPL_RAM_DEVICE
help
Rockchip SoCs support maskrom mode boot over USB. Enable this
option to produce maskrom mode boot images containing U-Boot.
config LNX_KRNL_IMG_TEXT_OFFSET_BASE
default TEXT_BASE
@ -767,9 +775,9 @@ config TPL_SYS_MALLOC_F_LEN
default 0x4000 if CUSTOM_SYS_INIT_SP_ADDR = 0x03f00000
config TEXT_BASE
default 0x60200000 if SPL_TEXT_BASE = 0x60000000
default 0x40200000 if SPL_TEXT_BASE = 0x40000000
default 0x00200000 if SPL_TEXT_BASE = 0x00000000
default 0x60800000 if SPL_TEXT_BASE = 0x60000000
default 0x40800000 if SPL_TEXT_BASE = 0x40000000
default 0x00800000 if SPL_TEXT_BASE = 0x00000000
config SPL_TEXT_BASE
default 0x60000000 if ROCKCHIP_RK3036 || ROCKCHIP_RK3066 || \

3
arch/arm/mach-rockchip/rk3308/Kconfig
View File

@ -17,9 +17,6 @@ config ROCKCHIP_STIMER_BASE
config SYS_SOC
default "rk3308"
config TEXT_BASE
default 0x00600000
source "board/rockchip/evb_rk3308/Kconfig"
source "board/firefly/firefly-rk3308/Kconfig"

3
arch/arm/mach-rockchip/rk3568/Kconfig
View File

@ -70,9 +70,6 @@ config ROCKCHIP_STIMER_BASE
config SYS_SOC
default "rk3568"
config TEXT_BASE
default 0x00a00000
source "board/rockchip/evb_rk3568/Kconfig"
source "board/anbernic/rgxx3_rk3566/Kconfig"
source "board/hardkernel/odroid_m1/Kconfig"

3
arch/arm/mach-rockchip/rk3588/Kconfig
View File

@ -417,9 +417,6 @@ config ROCKCHIP_STIMER_BASE
config SYS_SOC
default "rk3588"
config TEXT_BASE
default 0x00a00000
source "board/armsom/sige7-rk3588/Kconfig"
source "board/coolpi/genbook_cm5_rk3588/Kconfig"
source "board/edgeble/neural-compute-module-6/Kconfig"

15
arch/arm/mach-rockchip/sdram.c
View File

@ -345,6 +345,21 @@ int dram_init_banksize(void)
return 0;
}
u8 rockchip_sdram_type(phys_addr_t reg)
{
u32 dram_type, version;
u32 sys_reg2 = readl(reg);
u32 sys_reg3 = readl(reg + 4);
dram_type = (sys_reg2 >> SYS_REG_DDRTYPE_SHIFT) & SYS_REG_DDRTYPE_MASK;
version = (sys_reg3 >> SYS_REG_VERSION_SHIFT) & SYS_REG_VERSION_MASK;
if (version >= 3)
dram_type |= ((sys_reg3 >> SYS_REG_EXTEND_DDRTYPE_SHIFT) &
SYS_REG_EXTEND_DDRTYPE_MASK) << 3;
return dram_type;
}
size_t rockchip_sdram_size(phys_addr_t reg)
{
u32 rank, cs0_col, bk, cs0_row, cs1_row, bw, row_3_4;

14
arch/arm/mach-rockchip/spl-boot-order.c
View File

@ -8,6 +8,7 @@
#include <log.h>
#include <mmc.h>
#include <spl.h>
#include <asm/arch-rockchip/bootrom.h>
#include <asm/global_data.h>
#include <dm/uclass-internal.h>
@ -98,15 +99,22 @@ __weak const char *board_spl_was_booted_from(void)
void board_boot_order(u32 *spl_boot_list)
{
int idx = 0;
/* Add RAM boot for maskrom mode boot over USB */
if (BROM_BOOTSOURCE_ID_ADDR && CONFIG_IS_ENABLED(RAM_DEVICE) &&
read_brom_bootsource_id() == BROM_BOOTSOURCE_USB) {
spl_boot_list[idx++] = BOOT_DEVICE_RAM;
}
/* In case of no fdt (or only plat), use spl_boot_device() */
if (!CONFIG_IS_ENABLED(OF_CONTROL) || CONFIG_IS_ENABLED(OF_PLATDATA)) {
spl_boot_list[0] = spl_boot_device();
spl_boot_list[idx++] = spl_boot_device();
return;
}
const void *blob = gd->fdt_blob;
int chosen_node = fdt_path_offset(blob, "/chosen");
int idx = 0;
int elem;
int boot_device;
int node;
@ -115,7 +123,7 @@ void board_boot_order(u32 *spl_boot_list)
if (chosen_node < 0) {
debug("%s: /chosen not found, using spl_boot_device()\n",
__func__);
spl_boot_list[0] = spl_boot_device();
spl_boot_list[idx++] = spl_boot_device();
return;
}

11
arch/arm/mach-socfpga/board.c
View File

@ -14,6 +14,7 @@
#include <hang.h>
#include <handoff.h>
#include <image.h>
#include <spl.h>
#include <usb.h>
#include <usb/dwc2_udc.h>
#include <asm/global_data.h>
@ -209,3 +210,13 @@ void lmb_arch_add_memory(void)
}
}
#endif
#if (defined(CONFIG_TARGET_SOCFPGA_ARRIA10) || \
defined(CONFIG_TARGET_SOCFPGA_GEN5)) && defined(CONFIG_XPL_BUILD)
unsigned long board_spl_mmc_get_uboot_raw_sector(struct mmc *mmc,
unsigned long raw_sect)
{
/* offset of u-boot proper inside u-boot-with-spl.sfp image */
return (CONFIG_SPL_PAD_TO * 4) / 512 + raw_sect;
}
#endif

4
arch/sandbox/config.mk
View File

@ -50,10 +50,10 @@ cmd_u-boot-spl = (cd $(obj) && \
ifeq ($(HOST_ARCH),$(HOST_ARCH_X86_64))
EFI_LDS := ${SRCDIR}/../../../arch/x86/lib/elf_x86_64_efi.lds
EFI_TARGET := --target=efi-app-x86_64
EFI_TARGET := --output-target=efi-app-x86_64
else ifeq ($(HOST_ARCH),$(HOST_ARCH_X86))
EFI_LDS := ${SRCDIR}/../../../arch/x86/lib/elf_ia32_efi.lds
EFI_TARGET := --target=efi-app-ia32
EFI_TARGET := --output-target=efi-app-ia32
else ifeq ($(HOST_ARCH),$(HOST_ARCH_AARCH64))
EFI_LDS := ${SRCDIR}/../../../arch/arm/lib/elf_aarch64_efi.lds
OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .data \

6
arch/x86/config.mk
View File

@ -69,7 +69,7 @@ endif
LDSCRIPT_EFI := $(srctree)/arch/x86/lib/elf_$(EFIARCH)_efi.lds
EFISTUB := crt0_$(EFIARCH)_efi.o reloc_$(EFIARCH)_efi.o
OBJCOPYFLAGS_EFI += --target=efi-app-$(EFIARCH)
OBJCOPYFLAGS_EFI += --output-target=efi-app-$(EFIARCH)
CPPFLAGS_REMOVE_crt0-efi-$(EFIARCH).o += $(CFLAGS_NON_EFI)
CPPFLAGS_crt0-efi-$(EFIARCH).o += $(CFLAGS_EFI)
@ -127,7 +127,7 @@ endif
endif
ifdef CONFIG_X86_64
EFI_TARGET := --target=efi-app-x86_64
EFI_TARGET := --output-target=efi-app-x86_64
else
EFI_TARGET := --target=efi-app-ia32
EFI_TARGET := --output-target=efi-app-ia32
endif

5
board/radxa/rock5b-rk3588/Kconfig
View File

@ -9,4 +9,9 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "rock5b-rk3588"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ADC
select SPL_ADC
endif

3
board/radxa/rock5b-rk3588/MAINTAINERS
View File

@ -5,5 +5,4 @@ S: Maintained
F: board/radxa/rock5b-rk3588
F: include/configs/rock5b-rk3588.h
F: configs/rock5b-rk3588_defconfig
F: arch/arm/dts/rk3588-rock-5b.dts
F: arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
F: arch/arm/dts/rk3588-rock-5b*

64
board/radxa/rock5b-rk3588/rock5b-rk3588.c
View File

@ -3,8 +3,72 @@
* Copyright (c) 2023-2024 Collabora Ltd.
*/
#include <adc.h>
#include <env.h>
#include <fdtdec.h>
#include <fdt_support.h>
#include <asm/arch-rockchip/sdram.h>
#include <linux/errno.h>
#define PMU1GRF_BASE 0xfd58a000
#define OS_REG2_REG 0x208
#define HW_ID_CHANNEL 5
struct board_model {
unsigned int dram;
unsigned int low;
unsigned int high;
const char *fdtfile;
};
static const struct board_model board_models[] = {
{ LPDDR5, 926, 1106, "rockchip/rk3588-rock-5t.dtb" },
{ LPDDR5, 4005, 4185, "rockchip/rk3588-rock-5b-plus.dtb" },
};
static const struct board_model *get_board_model(void)
{
unsigned int val, dram_type;
int i, ret;
dram_type = rockchip_sdram_type(PMU1GRF_BASE + OS_REG2_REG);
ret = adc_channel_single_shot("adc@fec10000", HW_ID_CHANNEL, &val);
if (ret)
return NULL;
for (i = 0; i < ARRAY_SIZE(board_models); i++) {
unsigned int dram = board_models[i].dram;
unsigned int min = board_models[i].low;
unsigned int max = board_models[i].high;
if (dram == dram_type && min <= val && val <= max)
return &board_models[i];
}
return NULL;
}
int rk_board_late_init(void)
{
const struct board_model *model = get_board_model();
if (model)
env_set("fdtfile", model->fdtfile);
return 0;
}
int board_fit_config_name_match(const char *name)
{
const struct board_model *model = get_board_model();
if (model && !strcmp(name, model->fdtfile))
return 0;
return -EINVAL;
}
#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, struct bd_info *bd)

1
board/rockchip/rockchip-ramboot.config Normal file
View File

@ -0,0 +1 @@
CONFIG_ROCKCHIP_MASKROM_IMAGE=y

3
boot/Kconfig
View File

@ -249,6 +249,9 @@ config SPL_LOAD_FIT_ADDRESS
hex "load address of fit image"
depends on SPL_LOAD_FIT
default 0x44000000 if ARCH_IMX8M
default 0x60080000 if ARCH_ROCKCHIP && SPL_TEXT_BASE = 0x60000000
default 0x40200000 if ARCH_ROCKCHIP && SPL_TEXT_BASE = 0x40000000
default 0x00200000 if ARCH_ROCKCHIP && SPL_TEXT_BASE = 0x00000000
default 0x0
help
Specify the load address of the fit image that will be loaded

1
common/spl/Kconfig
View File

@ -573,6 +573,7 @@ config SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
config SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
bool "MMC raw mode: by partition type"
select SPL_LOAD_BLOCK
depends on DOS_PARTITION
help
Use partition type for specifying U-Boot partition on MMC/SD in

21
common/spl/spl_mmc.c
View File

@ -106,7 +106,8 @@ static int spl_mmc_find_device(struct mmc **mmcp, int mmc_dev)
return 0;
}
#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
#if defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION) || \
defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE)
static int mmc_load_image_raw_partition(struct spl_image_info *spl_image,
struct spl_boot_device *bootdev,
struct mmc *mmc, int partition,
@ -136,11 +137,7 @@ static int mmc_load_image_raw_partition(struct spl_image_info *spl_image,
return ret;
}
#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
return mmc_load_image_raw_sector(spl_image, bootdev, mmc, info.start + sector);
#else
return mmc_load_image_raw_sector(spl_image, bootdev, mmc, info.start);
#endif
}
#endif
@ -419,19 +416,19 @@ int spl_mmc_load(struct spl_image_info *spl_image,
raw_sect = spl_mmc_get_uboot_raw_sector(mmc, raw_sect);
#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
ret = mmc_load_image_raw_partition(spl_image, bootdev,
mmc, raw_part,
raw_sect);
if (!ret)
return 0;
#endif
#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
ret = mmc_load_image_raw_sector(spl_image, bootdev, mmc,
raw_sect +
spl_mmc_raw_uboot_offset(part));
if (!ret)
return 0;
#elif defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION) || \
defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE)
ret = mmc_load_image_raw_partition(spl_image, bootdev,
mmc, raw_part,
raw_sect);
if (!ret)
return 0;
#endif
/* If RAW mode fails, try FS mode. */
fallthrough;

1
configs/am43xx_hs_evm_defconfig
View File

@ -15,6 +15,7 @@ CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE=0x01c00000
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_TEXT_BASE=0x403018e0
CONFIG_SPL=y
CONFIG_SYS_MEM_TOP_HIDE=0x4000000
CONFIG_SPL_LOAD_FIT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y

1
configs/am43xx_hs_evm_qspi_defconfig
View File

@ -14,6 +14,7 @@ CONFIG_TI_SECURE_EMIF_REGION_START=0xbdb00000
CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x02000000
CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE=0x01c00000
CONFIG_ENV_OFFSET_REDUND=0x120000
CONFIG_SYS_MEM_TOP_HIDE=0x4000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_QSPI_BOOT=y
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"

1
configs/rock5b-rk3588_defconfig
View File

@ -47,6 +47,7 @@ CONFIG_CMD_REGULATOR=y
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
CONFIG_OF_LIST="rockchip/rk3588-rock-5b rockchip/rk3588-rock-5b-plus rockchip/rk3588-rock-5t"
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_REGMAP=y

22
configs/socfpga_agilex5_defconfig
View File

@ -67,8 +67,7 @@ CONFIG_CMD_WDT=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_UBI=y
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
CONFIG_CMD_MMC=y
CONFIG_OF_LIST=""
CONFIG_ENV_IS_IN_FAT=y
CONFIG_ENV_IS_IN_UBI=y
@ -79,8 +78,6 @@ CONFIG_ENV_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_ALTERA_SDRAM=y
CONFIG_GPIO_HOG=y
CONFIG_SPL_GPIO_HOG=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
@ -109,5 +106,22 @@ CONFIG_USB_DWC3=y
CONFIG_USB_HUB_DEBOUNCE_TIMEOUT=3000
CONFIG_DESIGNWARE_WATCHDOG=y
CONFIG_WDT=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SPL_DWAPB_GPIO=y
CONFIG_SPL_DM_REGULATOR=y
CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_SPL_DM_REGULATOR_GPIO=y
CONFIG_SPL_MMC=y
CONFIG_SPL_DM_MMC=y
CONFIG_SPL_MMC_IO_VOLTAGE=y
CONFIG_SPL_MMC_SDHCI_ADMA=y
CONFIG_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_DM_MMC=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_SDHCI_ADMA=y
CONFIG_MMC_SDHCI_CADENCE=y
# CONFIG_SPL_USE_TINY_PRINTF is not set
CONFIG_PANIC_HANG=y

6
configs/socfpga_agilex5_emmc_defconfig Normal file
View File

@ -0,0 +1,6 @@
#include <configs/socfpga_agilex5_defconfig>
CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex5_socdk_emmc"
# CONFIG_SPL_DM_REGULATOR_GPIO is not set
# CONFIG_DM_REGULATOR_GPIO is not set
# CONFIG_SPL_DWAPB_GPIO is not set

2
configs/socfpga_agilex_defconfig
View File

@ -57,8 +57,6 @@ CONFIG_CMD_USB=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_SMC=y
CONFIG_CMD_UBI=y
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
CONFIG_OF_UPSTREAM=y
CONFIG_OF_LIST=""
CONFIG_ENV_IS_IN_FAT=y

1
configs/socfpga_arria10_defconfig
View File

@ -68,3 +68,4 @@ CONFIG_DESIGNWARE_APB_TIMER=y
CONFIG_USB=y
CONFIG_USB_DWC2=y
# CONFIG_SPL_WDT is not set
# CONFIG_TOOLS_MKEFICAPSULE is not set

2
configs/socfpga_arria5_defconfig
View File

@ -44,8 +44,6 @@ CONFIG_CMD_EXT4_WRITE=y
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)"
CONFIG_CMD_UBI=y
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
CONFIG_VERSION_VARIABLE=y

3
configs/socfpga_cyclone5_defconfig
View File

@ -45,8 +45,6 @@ CONFIG_CMD_EXT4_WRITE=y
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)"
CONFIG_CMD_UBI=y
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
CONFIG_VERSION_VARIABLE=y
@ -67,6 +65,7 @@ CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_MII=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPI=y
CONFIG_CADENCE_QSPI=y
CONFIG_DESIGNWARE_SPI=y

3
configs/socfpga_de0_nano_soc_defconfig
View File

@ -28,6 +28,7 @@ CONFIG_SPL_NO_BSS_LIMIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_HAVE_INIT_STACK=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_SYS_MAXARGS=32
@ -45,8 +46,6 @@ CONFIG_CMD_EXT4_WRITE=y
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)"
CONFIG_CMD_UBI=y
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
CONFIG_VERSION_VARIABLE=y

2
configs/socfpga_de10_nano_defconfig
View File

@ -42,8 +42,6 @@ CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
CONFIG_VERSION_VARIABLE=y

2
configs/socfpga_de10_standard_defconfig
View File

@ -42,8 +42,6 @@ CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
CONFIG_VERSION_VARIABLE=y

2
configs/socfpga_de1_soc_defconfig
View File

@ -42,8 +42,6 @@ CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
CONFIG_VERSION_VARIABLE=y

2
configs/socfpga_is1_defconfig
View File

@ -44,8 +44,6 @@ CONFIG_CMD_EXT4_WRITE=y
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)"
CONFIG_CMD_UBI=y
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
CONFIG_USE_BOOTFILE=y

2
configs/socfpga_mcvevk_defconfig
View File

@ -42,8 +42,6 @@ CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_RELOC_GD_ENV_ADDR=y

2
configs/socfpga_secu1_defconfig
View File

@ -63,8 +63,6 @@ CONFIG_MTDIDS_DEFAULT="nand0=denali-nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=denali-nand:512k(nand.4spl),512k(nand.uboot),128k(nand.env1),128k(nand.env2),0x1000000(nand.rec),0x3ee40000(nand.ubi),0x80000@0x3ff80000(nand.bbt)"
CONFIG_CMD_UBI=y
# CONFIG_CMD_UBIFS is not set
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_ENV_REDUNDANT=y

2
configs/socfpga_sockit_defconfig
View File

@ -44,8 +44,6 @@ CONFIG_CMD_EXT4_WRITE=y
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)"
CONFIG_CMD_UBI=y
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
CONFIG_VERSION_VARIABLE=y

2
configs/socfpga_socrates_defconfig
View File

@ -44,8 +44,6 @@ CONFIG_CMD_EXT4_WRITE=y
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)"
CONFIG_CMD_UBI=y
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
CONFIG_VERSION_VARIABLE=y

2
configs/socfpga_sr1500_defconfig
View File

@ -51,8 +51,6 @@ CONFIG_CMD_EXT4_WRITE=y
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)"
CONFIG_CMD_UBI=y
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_ENV_REDUNDANT=y
CONFIG_ENV_RELOC_GD_ENV_ADDR=y

2
configs/socfpga_vining_fpga_defconfig
View File

@ -58,8 +58,6 @@ CONFIG_CMD_EXT4_WRITE=y
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),64k(env1),64k(env2),256k(softing1),256k(softing2),-(rcvrfs);"
CONFIG_CMD_UBI=y
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_ENV_REDUNDANT=y
CONFIG_ENV_RELOC_GD_ENV_ADDR=y

1
disk/Kconfig
View File

@ -142,6 +142,7 @@ config SPL_EFI_PARTITION
bool "Enable EFI GPT partition table for SPL"
depends on SPL
default n if ARCH_MVEBU
default n if ARCH_SOCFPGA
default n if ARCH_SUNXI
default y if EFI_PARTITION
select SPL_PARTITIONS

2
doc/board/rockchip/rockchip.rst
View File

@ -162,7 +162,7 @@ List of mainline supported Rockchip boards:
- Pine64 QuartzPro64 (quartzpro64-rk3588)
- Radxa ROCK 5 ITX (rock-5-itx-rk3588)
- Radxa ROCK 5A (rock5a-rk3588s)
- Radxa ROCK 5B (rock5b-rk3588)
- Radxa ROCK 5B/5B+/5T (rock5b-rk3588)
- Radxa ROCK 5C (rock-5c-rk3588s)
- Rockchip Toybrick TB-RK3588X (toybrick-rk3588)
- Theobroma Systems RK3588-SBC Jaguar (jaguar-rk3588)

46
doc/board/theobroma-systems/jaguar_rk3588.rst
View File

@ -32,24 +32,47 @@ It provides the following features:
Here is the step-by-step to boot to U-Boot on SBC-RK3588-AMR Jaguar from Theobroma
Systems.
Get the TF-A and DDR init (TPL) binaries
----------------------------------------
Get DDR init (TPL) binary
-------------------------
.. prompt:: bash
git clone https://github.com/rockchip-linux/rkbin
cd rkbin
export RKBIN=$(pwd)
export BL31=$RKBIN/bin/rk35/rk3588_bl31_v1.47.elf
export ROCKCHIP_TPL=$RKBIN/bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v1.18.bin
export ROCKCHIP_TPL=$(readlink -f bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v*.bin | head -1)
sed -i 's/^uart baudrate=.*$/uart baudrate=115200/' tools/ddrbin_param.txt
./tools/ddrbin_tool rk3588 tools/ddrbin_param.txt "$ROCKCHIP_TPL"
sed -i 's/^uart iomux=.*$/uart iomux=0/' tools/ddrbin_param.txt
python3 ./tools/ddrbin_tool.py rk3588 tools/ddrbin_param.txt "$ROCKCHIP_TPL"
./tools/boot_merger RKBOOT/RK3588MINIALL.ini
export RKDB=$RKBIN/rk3588_spl_loader_v1.11.112.bin
export RKDB=$(readlink -f rk3588_spl_loader_v*.bin | head -1)
This will setup all required external dependencies for compiling U-Boot. This will
be updated in the future once upstream Trusted-Firmware-A supports RK3588 or U-Boot
gains support for open-source DRAM initialization in TPL.
be updated in the future once U-Boot gains support for open-source DRAM initialization
in TPL.
Get TF-A
--------
There are two possible options, pick one or the other. Note that the instructions need
to be run from the ``rkbin`` directory.
Prebuilt binary from Rockchip
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
.. prompt:: bash
export BL31=$(readlink -f bin/rk35/rk3588_bl31_v*.elf | head -1)
Upstream
~~~~~~~~
.. prompt:: bash
cd ../
git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git
cd trusted-firmware-a
make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3588 bl31
export BL31=$PWD/build/rk3588/release/bl31/bl31.elf
Build U-Boot
------------
@ -59,6 +82,11 @@ Build U-Boot
cd ../u-boot
make CROSS_COMPILE=aarch64-linux-gnu- jaguar-rk3588_defconfig all
.. note::
If using upstream TF-A, one should disable ``SPL_ATF_NO_PLATFORM_PARAM`` symbol in
U-Boot config (via e.g. ``make CROSS_COMPILE=aarch64-linux-gnu- menuconfig``) which
will, among other things, enable console output in TF-A.
This will build ``u-boot-rockchip.bin`` which can be written to an MMC device
(eMMC or SD card).

6
doc/board/theobroma-systems/puma_rk3399.rst
View File

@ -95,8 +95,9 @@ To flash U-Boot on the eMMC with ``rkdeveloptool``:
git clone https://github.com/rockchip-linux/rkbin.git
cd rkbin
./tools/boot_merger RKBOOT/RK3399MINIALL.ini
export RKDB=$(readlink -f rk3399_loader_v*.bin | head -1)
cd ..
./rkdeveloptool db rkbin/rk3399_loader_v1.30.130.bin
./rkdeveloptool db "$RKDB"
./rkdeveloptool wl 64 ../u-boot-rockchip.bin
NOR-Flash
@ -121,7 +122,8 @@ To flash U-Boot on the SPI with ``rkdeveloptool``:
git clone https://github.com/rockchip-linux/rkbin.git
cd rkbin
./tools/boot_merger RKBOOT/RK3399MINIALL_SPINOR.ini
export RKDB=$(readlink -f rk3399_loader_spinor_v*.bin | head -1)
cd ..
./rkdeveloptool db rkbin/rk3399_loader_spinor_v1.30.114.bin
./rkdeveloptool db "$RKDB"
./rkdeveloptool ef
./rkdeveloptool wl 0 ../u-boot-rockchip-spi.bin

3
doc/board/theobroma-systems/ringneck_px30.rst
View File

@ -90,6 +90,7 @@ To flash U-Boot on the eMMC with ``rkdeveloptool``:
git clone https://github.com/rockchip-linux/rkbin.git
cd rkbin
./tools/boot_merger RKBOOT/PX30MINIALL.ini
export RKDB=$(readlink -f px30_loader_v*.bin | head -1)
cd ..
./rkdeveloptool db rkbin/px30_loader_v2.08.135.bin
./rkdeveloptool db "$RKDB"
./rkdeveloptool wl 64 ../u-boot-rockchip.bin

45
doc/board/theobroma-systems/tiger_rk3588.rst
View File

@ -39,25 +39,47 @@ It provides the following feature set:
Here is the step-by-step to boot to U-Boot on SOM-RK3588-Q7 Tiger from Theobroma
Systems.
Get the TF-A and DDR init (TPL) binaries
----------------------------------------
Get DDR init (TPL) binary
-------------------------
.. prompt:: bash
git clone https://github.com/rockchip-linux/rkbin
cd rkbin
export RKBIN=$(pwd)
export BL31=$RKBIN/bin/rk35/rk3588_bl31_v1.47.elf
export ROCKCHIP_TPL=$RKBIN/bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v1.18.bin
export ROCKCHIP_TPL=$(readlink -f bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v*.bin | head -1)
sed -i 's/^uart baudrate=.*$/uart baudrate=115200/' tools/ddrbin_param.txt
sed -i 's/^uart iomux=.*$/uart iomux=2/' tools/ddrbin_param.txt
./tools/ddrbin_tool rk3588 tools/ddrbin_param.txt "$ROCKCHIP_TPL"
python3 ./tools/ddrbin_tool.py rk3588 tools/ddrbin_param.txt "$ROCKCHIP_TPL"
./tools/boot_merger RKBOOT/RK3588MINIALL.ini
export RKDB=$RKBIN/rk3588_spl_loader_v1.11.112.bin
export RKDB=$(readlink -f rk3588_spl_loader_v*.bin | head -1)
This will setup all required external dependencies for compiling U-Boot. This will
be updated in the future once upstream Trusted-Firmware-A supports RK3588 or U-Boot
gains support for open-source DRAM initialization in TPL.
be updated in the future once U-Boot gains support for open-source DRAM initialization
in TPL.
Get TF-A
--------
There are two possible options, pick one or the other. Note that the instructions need
to be run from the ``rkbin`` directory.
Prebuilt binary from Rockchip
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
.. prompt:: bash
export BL31=$(readlink -f bin/rk35/rk3588_bl31_v*.elf | head -1)
Upstream
~~~~~~~~
.. prompt:: bash
cd ../
git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git
cd trusted-firmware-a
make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3588 bl31
export BL31=$PWD/build/rk3588/release/bl31/bl31.elf
Build U-Boot
------------
@ -67,6 +89,11 @@ Build U-Boot
cd ../u-boot
make CROSS_COMPILE=aarch64-linux-gnu- tiger-rk3588_defconfig all
.. note::
If using upstream TF-A, one should disable ``SPL_ATF_NO_PLATFORM_PARAM`` symbol in
U-Boot config (via e.g. ``make CROSS_COMPILE=aarch64-linux-gnu- menuconfig``) which
will, among other things, enable console output in TF-A.
This will build ``u-boot-rockchip.bin`` which can be written to an MMC device
(eMMC or SD card).

23
doc/board/ti/j784s4_evm.rst
View File

@ -1,8 +1,8 @@
.. SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
.. sectionauthor:: Apurva Nandan <a-nandan@ti.com>
J784S4 and AM69 Platforms
=========================
J742S2, J784S4 and AM69 Platforms
=================================
Introduction
------------
@ -37,6 +37,11 @@ Platform information:
* https://www.ti.com/tool/J784S4XEVM
* https://www.ti.com/tool/SK-AM69
J742S2 is derivative of J784S24 SOC, More info can be found in
* TRM : https://www.ti.com/lit/ug/spruje3/spruje3.pdf
* Platform Information : https://www.ti.com/tool/J742S2XH01EVM
Boot Flow
---------
Below is the pictorial representation of boot flow:
@ -99,6 +104,13 @@ Set the variables corresponding to this platform:
export UBOOT_CFG_CORTEXR=am69_sk_r5_defconfig
export UBOOT_CFG_CORTEXA=am69_sk_a72_defconfig
For J742S2-EVM, use the following U_BOOT_CFG instead:
.. prompt:: bash
export UBOOT_CFG_CORTEXR=j742s2_evm_r5_defconfig
export UBOOT_CFG_CORTEXA=j742s2_evm_a72_defconfig
.. j784s4_evm_rst_include_start_build_steps
1. Trusted Firmware-A
@ -143,14 +155,21 @@ variant (GP, HS-FS, HS-SE) requires a different source for these files.
* tiboot3-j784s4-gp-evm.bin from :ref:`step 3.1 <j784s4_evm_rst_u_boot_r5>`
* tispl.bin_unsigned, u-boot.img_unsigned from :ref:`step 3.2 <j784s4_evm_rst_u_boot_a72>`
.. note::
For J742S2, GP variant is not available.
- HS-FS
* tiboot3-j784s4-hs-fs-evm.bin from :ref:`step 3.1 <j784s4_evm_rst_u_boot_r5>`
* tiboot3-j742s2-hs-fs-evm.bin from :ref:`step 3.1 <j784s4_evm_rst_u_boot_r5>`
* tispl.bin, u-boot.img from :ref:`step 3.2 <j784s4_evm_rst_u_boot_a72>`
- HS-SE
* tiboot3-j784s4-hs-evm.bin from :ref:`step 3.1 <j784s4_evm_rst_u_boot_r5>`
* tiboot3-j742s2-hs-evm.bin from :ref:`step 3.1 <j784s4_evm_rst_u_boot_r5>`
* tispl.bin, u-boot.img from :ref:`step 3.2 <j784s4_evm_rst_u_boot_a72>`
Image formats

6
doc/board/ti/k3.rst
View File

@ -653,9 +653,9 @@ Refer (:ref:`U-boot ARMV8 build <k3_rst_include_start_build_steps_uboot>`)
Saving environment
------------------
SAVEENV is disabled by default and for the new flow uses Uenv.txt as the default
way for saving the environments. This has been done as Uenv.txt is more granular
then the saveenv command and can be used across various bootmodes too.
SAVEENV is disabled by default and for the new flow uses uEnv.txt as the default
way for saving the environments. This has been done as uEnv.txt is more granular
than the saveenv command and can be used across various bootmodes too.
**Writing to MMC/EMMC**

2
doc/usage/cmd/part.rst
View File

@ -83,7 +83,7 @@ part must be specified as partition name.
dev
device number
part
partition number
partition name
varname
a variable to store the current partition number value into

3
drivers/clk/mediatek/clk-mtk.h
View File

@ -133,8 +133,7 @@ struct mtk_parent {
* struct mtk_composite - aggregate clock of mux, divider and gate clocks
*
* @id: index of clocks
* @parent: index of parnet clocks
* @parent: index of parnet clocks
* @parent: index of parent clocks
* @parent_flags: table of parent clocks with flags
* @mux_reg: hardware-specific mux register
* @gate_reg: hardware-specific gate register

27
drivers/i2c/rk_i2c.c
View File

@ -137,7 +137,7 @@ static int rk_i2c_send_stop_bit(struct rk_i2c *i2c)
writel(I2C_IPD_ALL_CLEAN, &regs->ipd);
writel(I2C_CON_EN | I2C_CON_STOP, &regs->con);
writel(I2C_CON_STOP, &regs->ien);
writel(I2C_STOPIEN, &regs->ien);
start = get_timer(0);
while (1) {
@ -195,13 +195,14 @@ static int rk_i2c_read(struct rk_i2c *i2c, uchar chip, uint reg, uint r_len,
while (bytes_remain_len) {
if (bytes_remain_len > RK_I2C_FIFO_SIZE) {
/*
* The hw can read up to 32 bytes at a time. If we need
* more than one chunk, send an ACK after the last byte
* of the current chunk.
*/
con = I2C_CON_EN;
bytes_xferred = 32;
} else {
/*
* The hw can read up to 32 bytes at a time. If we need
* more than one chunk, send an ACK after the last byte.
*/
con = I2C_CON_EN | I2C_CON_LASTACK;
bytes_xferred = bytes_remain_len;
}
@ -254,8 +255,6 @@ static int rk_i2c_read(struct rk_i2c *i2c, uchar chip, uint reg, uint r_len,
}
i2c_exit:
rk_i2c_disable(i2c);
return err;
}
@ -332,8 +331,6 @@ static int rk_i2c_write(struct rk_i2c *i2c, uchar chip, uint reg, uint r_len,
}
i2c_exit:
rk_i2c_disable(i2c);
return err;
}
@ -358,6 +355,18 @@ static int rockchip_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
ret = -EREMOTEIO;
break;
}
/*
* The HW is actually not capable of REPEATED START. But we can
* get the intended effect by resetting its internal state
* and issuing an ordinary START.
*
* Do NOT disable the controller after the last message (before
* sending the STOP condition) as this triggers an illegal
* START condition followed by a STOP condition.
*/
if (nmsgs > 1)
rk_i2c_disable(i2c);
}
rk_i2c_send_stop_bit(i2c);

1
drivers/mmc/sdhci-cadence.c
View File

@ -298,6 +298,7 @@ static int sdhci_cdns_probe(struct udevice *dev)
static const struct udevice_id sdhci_cdns_match[] = {
{ .compatible = "socionext,uniphier-sd4hc" },
{ .compatible = "cdns,sd4hc" },
{ .compatible = "altr,agilex5-sd6hc" },
{ .compatible = "cdns,sd6hc" },
{ /* sentinel */ }
};

8
drivers/spi/Kconfig
View File

@ -677,6 +677,14 @@ config SH_QSPI
Enable the Renesas Quad SPI controller driver. This driver can be
used on Renesas SoCs.
config SPL_DESIGNWARE_SPI
bool "Designware SPI driver in SPL"
depends on SPL_DM_SPI
default y if DESIGNWARE_SPI
help
Enable the Designware SPI driver during SPL.
See the help of DESIGNWARE_SPI for details.
config MXC_SPI
bool "MXC SPI Driver"
depends on MACH_IMX

2
drivers/spi/Makefile
View File

@ -35,7 +35,7 @@ obj-$(CONFIG_CF_SPI) += cf_spi.o
obj-$(CONFIG_CORTINA_SFLASH) += ca_sflash.o
obj-$(CONFIG_CV1800B_SPIF) += cv1800b_spif.o
obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
obj-$(CONFIG_DESIGNWARE_SPI) += designware_spi.o
obj-$(CONFIG_$(PHASE_)DESIGNWARE_SPI) += designware_spi.o
obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o
obj-$(CONFIG_FSL_DSPI) += fsl_dspi.o
obj-$(CONFIG_FSL_ESPI) += fsl_espi.o

5
fs/fat/fat.c
View File

@ -216,6 +216,11 @@ static __u32 get_fatent(fsdata *mydata, __u32 entry)
if (flush_dirty_fat_buffer(mydata) < 0)
return -1;
if (getsize > FATBUFBLOCKS) {
debug("getsize is too large for bufptr\n");
getsize = FATBUFBLOCKS;
}
if (disk_read(startblock, getsize, bufptr) < 0) {
debug("Error reading FAT blocks\n");
return ret;

5
include/configs/am43xx_evm.h
View File

@ -148,9 +148,4 @@
#define NANDBOOT
#endif /* CONFIG_MTD_RAW_NAND */
#if defined(CONFIG_TI_SECURE_DEVICE)
/* Avoid relocating onto firewalled area at end of DRAM */
#define CFG_PRAM (64 * 1024)
#endif /* CONFIG_TI_SECURE_DEVICE */
#endif /* __CONFIG_AM43XX_EVM_H */

3
include/part.h
View File

@ -461,7 +461,8 @@ ulong disk_blk_erase(struct udevice *dev, lbaint_t start, lbaint_t blkcnt);
#ifdef CONFIG_XPL_BUILD
# define part_print_ptr(x) NULL
# if defined(CONFIG_SPL_FS_EXT4) || defined(CONFIG_SPL_FS_FAT) || \
defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION)
defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION) || \
defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE)
# define part_get_info_ptr(x) x
# else
# define part_get_info_ptr(x) NULL

4
lib/uuid.c
View File

@ -139,6 +139,10 @@ static const struct {
NULL, "Disk IO",
EFI_DISK_IO_PROTOCOL_GUID,
},
{
NULL, "Partition Info",
EFI_PARTITION_INFO_PROTOCOL_GUID,
},
{
NULL, "Simple File System",
EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_GUID,

23
test/dm/fdtdec.c
View File

@ -14,14 +14,19 @@
DECLARE_GLOBAL_DATA_PTR;
#define FDTDEC_MAX_SIZE (2 * 1024 * 1024)
static int dm_test_fdtdec_set_carveout(struct unit_test_state *uts)
{
struct fdt_memory resv;
void *blob;
const fdt32_t *prop;
int blob_sz, len, offset;
int blob_sz, len, offset, fdt_sz;
blob_sz = fdt_totalsize(gd->fdt_blob) + 4096;
fdt_sz = fdt_totalsize(gd->fdt_blob);
ut_assert(fdt_sz > 0 && fdt_sz < FDTDEC_MAX_SIZE);
blob_sz = fdt_sz + 4096;
blob = malloc(blob_sz);
ut_assertnonnull(blob);
@ -67,10 +72,13 @@ static int dm_test_fdtdec_add_reserved_memory(struct unit_test_state *uts)
fdt_size_t size;
void *blob;
unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP;
int blob_sz, parent, subnode;
int blob_sz, parent, subnode, fdt_sz;
uint32_t phandle, phandle1;
blob_sz = fdt_totalsize(gd->fdt_blob) + 128;
fdt_sz = fdt_totalsize(gd->fdt_blob);
ut_assert(fdt_sz > 0 && fdt_sz < FDTDEC_MAX_SIZE);
blob_sz = fdt_sz + 128;
blob = malloc(blob_sz);
ut_assertnonnull(blob);
@ -138,14 +146,17 @@ static int dm_test_fdt_chosen_smbios(struct unit_test_state *uts)
void *blob;
ulong val;
struct smbios3_entry *entry;
int chosen, blob_sz;
int chosen, blob_sz, fdt_sz;
const fdt64_t *prop;
if (!CONFIG_IS_ENABLED(GENERATE_SMBIOS_TABLE)) {
return -EAGAIN;
}
blob_sz = fdt_totalsize(gd->fdt_blob) + 4096;
fdt_sz = fdt_totalsize(gd->fdt_blob);
ut_assert(fdt_sz > 0 && fdt_sz < FDTDEC_MAX_SIZE);
blob_sz = fdt_sz + 4096;
blob = memalign(8, blob_sz);
ut_assertnonnull(blob);

2
tools/binman/pyproject.toml
View File

@ -1,5 +1,5 @@
[build-system]
requires = ["setuptools>=61.0"]
requires = ["setuptools>=78.1.1"]
build-backend = "setuptools.build_meta"
[project]

2
tools/buildman/pyproject.toml
View File

@ -1,5 +1,5 @@
[build-system]
requires = ["setuptools>=61.0"]
requires = ["setuptools>=78.1.1"]
build-backend = "setuptools.build_meta"
[project]

2
tools/dtoc/pyproject.toml
View File

@ -1,5 +1,5 @@
[build-system]
requires = ["setuptools>=61.0"]
requires = ["setuptools>=78.1.1"]
build-backend = "setuptools.build_meta"
[project]

2
tools/libfdt/fdt_rw.c
View File

@ -1,4 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0+ BSD-2-Clause */
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
#include "fdt_host.h"
#include "../../scripts/dtc/libfdt/fdt_rw.c"

2
tools/patman/pyproject.toml
View File

@ -1,5 +1,5 @@
[build-system]
requires = ["setuptools>=61.0"]
requires = ["setuptools>=78.1.1"]
build-backend = "setuptools.build_meta"
[project]

24
tools/rkcommon.c
View File

@ -76,13 +76,29 @@ struct header0_info_v2 {
/**
* struct header0_info - header block for boot ROM
*
* This is stored at SD card block 64 (where each block is 512 bytes, or at
* the start of SPI flash. It is encoded with RC4.
* This is stored at MMC block 64 (where each block is 512 bytes), or at
* the start of SPI flash. It is encoded with RC4 with the below rc4_key.
*
* In Rockchip terminology:
*
* "init" means the stage that is loaded into SRAM. TPL if there is one, SPL
* otherwise.
*
* "boot" means the next stages after "init" stage that are loaded by the
* BootROM into DRAM. Only applicable if "init" stage returns to BootROM (via
* the appropriate ROCKCHIP_BACK_TO_BROM symbol, BOOT_DEVICE_BOOTROM is used as
* boot device for the next stage and the "init" stage successfully booted) and
* if "init_boot_size" > "init_size".
* Basically, it is the content of "init" plus the SPL or even U-Boot proper if
* relevant.
*
* @magic: Magic (must be RK_MAGIC)
* @disable_rc4: 0 to use rc4 for boot image, 1 to use plain binary
* @init_offset: Offset in blocks of the SPL code from this header
* block. E.g. 4 means 2KB after the start of this header.
* @init_offset: Offset in 512-byte blocks of the "init" code from the
* start of this header. For instance, 4 means 2KiB.
* @init_size: Size (in blocks) of the "init" code.
* @init_boot_size: Size (in blocks) of the "init" and "boot" code combined.
*
* Other fields are not used by U-Boot
*/
struct header0_info {

2
tools/u_boot_pylib/pyproject.toml
View File

@ -1,5 +1,5 @@
[build-system]
requires = ["setuptools>=61.0"]
requires = ["setuptools>=78.1.1"]
build-backend = "setuptools.build_meta"
[project]