From f0baa0a6685db0b59d8e9860c6cfcb942f74697f Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 19 Nov 2025 00:17:14 +0100 Subject: [PATCH 01/40] stm32mp: Fix handling of OPTEE in the middle of DRAM STM32MP13xx may have OPTEE-OS at 0xdd000000 even on systems with 1 GiB of DRAM at 0xc0000000, which is not the end of DRAM anymore. This puts the OPTEE-OS in the middle of DRAM. Currently, the code sets RAM top to 0xdd000000 and prevents the DRAM range past OPTEE at 0xe0000000..0xffffffff from being set as cacheable and from being usable. The code also sets the area over OPTEE as invalid region in MMU tables, which is not correct. Adjust the code such, that it only ever sets RAM top just before OPTEE in case the OPTEE is really at the end of DRAM, mainly to be backward compatible. Furthermore, adjust the MMU table configuration such, that the regions over the OPTEE are simply skipped and not reconfigured, and the regions between end of OPTEE and RAM top are set as cacheable, if any actually exist. Signed-off-by: Marek Vasut Reviewed-by: Patrice Chotard Tested-by: Patrice Chotard --- arch/arm/mach-stm32mp/dram_init.c | 4 +++- arch/arm/mach-stm32mp/stm32mp1/cpu.c | 11 ++++++----- 2 files changed, 9 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-stm32mp/dram_init.c b/arch/arm/mach-stm32mp/dram_init.c index 34b958d7afd..e36e42e7c61 100644 --- a/arch/arm/mach-stm32mp/dram_init.c +++ b/arch/arm/mach-stm32mp/dram_init.c @@ -65,6 +65,7 @@ int dram_init(void) phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { + phys_addr_t top = gd->ram_top; phys_size_t size; phys_addr_t reg; u32 optee_start, optee_size; @@ -86,7 +87,8 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size) /* Reserved memory for OP-TEE at END of DDR for STM32MP1 SoC */ if (IS_ENABLED(CONFIG_STM32MP13X) || IS_ENABLED(CONFIG_STM32MP15X)) { if (!optee_get_reserved_memory(&optee_start, &optee_size)) - reg = ALIGN(optee_start - size, MMU_SECTION_SIZE); + if (optee_start + optee_size == top) + reg = ALIGN(optee_start - size, MMU_SECTION_SIZE); } /* before relocation, mark the U-Boot memory as cacheable by default */ diff --git a/arch/arm/mach-stm32mp/stm32mp1/cpu.c b/arch/arm/mach-stm32mp/stm32mp1/cpu.c index e0c6f8ba937..252aef1852e 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/cpu.c +++ b/arch/arm/mach-stm32mp/stm32mp1/cpu.c @@ -82,11 +82,12 @@ void dram_bank_mmu_setup(int bank) i++) { addr = i << MMU_SECTION_SHIFT; option = DCACHE_DEFAULT_OPTION; - if (use_lmb && - (lmb_is_reserved_flags(i << MMU_SECTION_SHIFT, LMB_NOMAP) || - (gd->ram_top && addr >= gd->ram_top)) - ) - option = 0; /* INVALID ENTRY in TLB */ + if (use_lmb) { + if (lmb_is_reserved_flags(i << MMU_SECTION_SHIFT, LMB_NOMAP)) + continue; + if (gd->ram_top && addr >= gd->ram_top) + option = 0; /* INVALID ENTRY in TLB */ + } set_section_dcache(i, option); } } From fd26267b4c2b882363e639c7a1eed97068aaff01 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 19 Nov 2025 00:19:17 +0100 Subject: [PATCH 02/40] ARM: dts: stm32: Fix 512 MiB DRAM settings for DH STM32MP13xx DHCOR SoM Update DRAM chip type and density comment for 512 MiB DRAM settings for DH STM32MP13xx DHCOR DHSBC to match the chip on the SoM. No functional change. Signed-off-by: Marek Vasut Reviewed-by: Patrice Chotard --- arch/arm/dts/stm32mp13-ddr3-dhsom-1x2Gb-1066-binG.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/dts/stm32mp13-ddr3-dhsom-1x2Gb-1066-binG.dtsi b/arch/arm/dts/stm32mp13-ddr3-dhsom-1x2Gb-1066-binG.dtsi index 7b344541c3e..b464c04aa2b 100644 --- a/arch/arm/dts/stm32mp13-ddr3-dhsom-1x2Gb-1066-binG.dtsi +++ b/arch/arm/dts/stm32mp13-ddr3-dhsom-1x2Gb-1066-binG.dtsi @@ -3,13 +3,13 @@ * Copyright (C) 2025, DH electronics - All Rights Reserved * * STM32MP13xx DHSOM configuration - * 1x DDR3L 1Gb, 16-bit, 533MHz, Single Die Package in flyby topology. - * Reference used W631GU6MB15I from Winbond + * 1x DDR3L 4Gb, 16-bit, 533MHz, Single Die Package in flyby topology. + * Reference used W634GU6RB11I from Winbond * * DDR type / Platform DDR3/3L * freq 533MHz * width 16 - * datasheet 0 = W631GU6MB15I / DDR3-1333 + * datasheet 0 = W634GU6RB11I / DDR3-1866 * DDR density 2 * timing mode optimized * address mapping : RBC From 86ff2cfa80e9abb71789b299cfcbfc0b9337174d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 19 Nov 2025 00:19:36 +0100 Subject: [PATCH 03/40] ARM: dts: stm32: Add 1 GiB DRAM settings for DH STM32MP13xx DHCOR SoM Add DRAM settings for 1 GiB variant of DH STM32MP13xx DHCOR SoM and support for SoM DRAM coding HW straps decoding and automatic DRAM configuration selection. Enable CONFIG_BOARD_EARLY_INIT_F on all STM32MP1 DHSOM, as it is required for the HW straps decoding. Signed-off-by: Marek Vasut Reviewed-by: Patrice Chotard --- .../stm32mp13-ddr3-dhsom-1x4Gb-1066-binG.dtsi | 100 ++++++++++++++++++ arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi | 1 + board/dhelectronics/dh_stm32mp1/board.c | 30 ++++-- configs/stm32mp15_dhsom.config | 1 - configs/stm32mp_dhsom.config | 1 + 5 files changed, 123 insertions(+), 10 deletions(-) create mode 100644 arch/arm/dts/stm32mp13-ddr3-dhsom-1x4Gb-1066-binG.dtsi diff --git a/arch/arm/dts/stm32mp13-ddr3-dhsom-1x4Gb-1066-binG.dtsi b/arch/arm/dts/stm32mp13-ddr3-dhsom-1x4Gb-1066-binG.dtsi new file mode 100644 index 00000000000..1d268d58b54 --- /dev/null +++ b/arch/arm/dts/stm32mp13-ddr3-dhsom-1x4Gb-1066-binG.dtsi @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2025, DH electronics - All Rights Reserved + * + * STM32MP13xx DHSOM configuration + * 1x DDR3L 8Gb, 16-bit, 533MHz, Single Die Package in flyby topology. + * Reference used W638GU6QB11I from Winbond + * + * DDR type / Platform DDR3/3L + * freq 533MHz + * width 16 + * datasheet 0 = W638GU6QB11I / DDR3-1866 + * DDR density 4 + * timing mode optimized + * address mapping : RBC + * Tc > + 85C : J + */ +#define DDR_MEM_COMPATIBLE ddr3l-dhsom-1066-888-bin-g-1x4gb-533mhz +#define DDR_MEM_NAME "DDR3-DDR3L 16bits 533000kHz" +#define DDR_MEM_SPEED 533000 +#define DDR_MEM_SIZE 0x40000000 + +#define DDR_MSTR 0x00040401 +#define DDR_MRCTRL0 0x00000010 +#define DDR_MRCTRL1 0x00000000 +#define DDR_DERATEEN 0x00000000 +#define DDR_DERATEINT 0x00800000 +#define DDR_PWRCTL 0x00000000 +#define DDR_PWRTMG 0x00400010 +#define DDR_HWLPCTL 0x00000000 +#define DDR_RFSHCTL0 0x00210000 +#define DDR_RFSHCTL3 0x00000000 +#define DDR_RFSHTMG 0x0081008B +#define DDR_CRCPARCTL0 0x00000000 +#define DDR_DRAMTMG0 0x121B2414 +#define DDR_DRAMTMG1 0x000A041B +#define DDR_DRAMTMG2 0x0607080F +#define DDR_DRAMTMG3 0x0050400C +#define DDR_DRAMTMG4 0x07040607 +#define DDR_DRAMTMG5 0x06060403 +#define DDR_DRAMTMG6 0x02020002 +#define DDR_DRAMTMG7 0x00000202 +#define DDR_DRAMTMG8 0x00001005 +#define DDR_DRAMTMG14 0x000000A0 +#define DDR_ZQCTL0 0xC2000040 +#define DDR_DFITMG0 0x02050105 +#define DDR_DFITMG1 0x00000202 +#define DDR_DFILPCFG0 0x07000000 +#define DDR_DFIUPD0 0xC0400003 +#define DDR_DFIUPD1 0x00000000 +#define DDR_DFIUPD2 0x00000000 +#define DDR_DFIPHYMSTR 0x00000000 +#define DDR_ADDRMAP1 0x00080808 +#define DDR_ADDRMAP2 0x00000000 +#define DDR_ADDRMAP3 0x00000000 +#define DDR_ADDRMAP4 0x00001F1F +#define DDR_ADDRMAP5 0x07070707 +#define DDR_ADDRMAP6 0x07070707 +#define DDR_ADDRMAP9 0x00000000 +#define DDR_ADDRMAP10 0x00000000 +#define DDR_ADDRMAP11 0x00000000 +#define DDR_ODTCFG 0x06000600 +#define DDR_ODTMAP 0x00000001 +#define DDR_SCHED 0x00000F01 +#define DDR_SCHED1 0x00000000 +#define DDR_PERFHPR1 0x00000001 +#define DDR_PERFLPR1 0x04000200 +#define DDR_PERFWR1 0x08000400 +#define DDR_DBG0 0x00000000 +#define DDR_DBG1 0x00000000 +#define DDR_DBGCMD 0x00000000 +#define DDR_POISONCFG 0x00000000 +#define DDR_PCCFG 0x00000010 +#define DDR_PCFGR_0 0x00000000 +#define DDR_PCFGW_0 0x00000000 +#define DDR_PCFGQOS0_0 0x00100009 +#define DDR_PCFGQOS1_0 0x00000020 +#define DDR_PCFGWQOS0_0 0x01100B03 +#define DDR_PCFGWQOS1_0 0x01000200 +#define DDR_PGCR 0x01442E02 +#define DDR_PTR0 0x0022AA5B +#define DDR_PTR1 0x04841104 +#define DDR_PTR2 0x042DA068 +#define DDR_ACIOCR 0x10400812 +#define DDR_DXCCR 0x00000C40 +#define DDR_DSGCR 0xF200011F +#define DDR_DCR 0x0000000B +#define DDR_DTPR0 0x36D477D0 +#define DDR_DTPR1 0x098B00D8 +#define DDR_DTPR2 0x10023600 +#define DDR_MR0 0x00000830 +#define DDR_MR1 0x00000000 +#define DDR_MR2 0x00000208 +#define DDR_MR3 0x00000000 +#define DDR_ODTCR 0x00010000 +#define DDR_ZQ0CR1 0x00000038 +#define DDR_DX0GCR 0x0000CE81 +#define DDR_DX1GCR 0x0000CE81 + +#include "stm32mp13-ddr.dtsi" diff --git a/arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi b/arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi index bedb7c600d5..39ac5692e08 100644 --- a/arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi +++ b/arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi @@ -6,6 +6,7 @@ #include #include "stm32mp13-u-boot.dtsi" #include "stm32mp13-ddr3-dhsom-1x2Gb-1066-binG.dtsi" +#include "stm32mp13-ddr3-dhsom-1x4Gb-1066-binG.dtsi" / { aliases { diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c index c18f1911fe4..55526189d5a 100644 --- a/board/dhelectronics/dh_stm32mp1/board.c +++ b/board/dhelectronics/dh_stm32mp1/board.c @@ -304,17 +304,29 @@ static void board_get_coding_straps(void) int board_stm32mp1_ddr_config_name_match(struct udevice *dev, const char *name) { - if (ddr3code == 1 && - !strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-2x1gb-533mhz")) - return 0; + if (IS_ENABLED(CONFIG_TARGET_DH_STM32MP13X)) { + if (ddr3code == 1 && + !strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-1x2gb-533mhz")) + return 0; - if (ddr3code == 2 && - !strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-2x2gb-533mhz")) - return 0; + if (ddr3code == 2 && + !strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-1x4gb-533mhz")) + return 0; + } - if (ddr3code == 3 && - !strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-2x4gb-533mhz")) - return 0; + if (IS_ENABLED(CONFIG_TARGET_DH_STM32MP15X)) { + if (ddr3code == 1 && + !strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-2x1gb-533mhz")) + return 0; + + if (ddr3code == 2 && + !strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-2x2gb-533mhz")) + return 0; + + if (ddr3code == 3 && + !strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-2x4gb-533mhz")) + return 0; + } return -EINVAL; } diff --git a/configs/stm32mp15_dhsom.config b/configs/stm32mp15_dhsom.config index 210ec201bf5..d5ecbac29e0 100644 --- a/configs/stm32mp15_dhsom.config +++ b/configs/stm32mp15_dhsom.config @@ -2,7 +2,6 @@ # CONFIG_ARMV7_VIRT is not set # CONFIG_BINMAN_FDT is not set -CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_SIZE_LIMIT=1441792 CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_BOOTDELAY=1 diff --git a/configs/stm32mp_dhsom.config b/configs/stm32mp_dhsom.config index 56a40839d28..31fae2de19d 100644 --- a/configs/stm32mp_dhsom.config +++ b/configs/stm32mp_dhsom.config @@ -6,6 +6,7 @@ # CONFIG_SPL_PARTITION_UUIDS is not set # CONFIG_SPL_PINCTRL_FULL is not set # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOOTCOMMAND="run bootcmd_stm32mp" CONFIG_BOOTCOUNT_LIMIT=y CONFIG_CMD_BOOTCOUNT=y From 78e94666dd794ccfab561a9ef6e5b9d6a785ee97 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 19 Nov 2025 00:17:23 +0100 Subject: [PATCH 04/40] ARM: stm32: Add missing build of debug UART init code on DH STM32MP1 DHSOM Commit c37a6684818d ("stm32mp: fix compilation issue with DEBUG_UART") split the debug UART initialization code into two files, but failed to update other non-ST boards. This did not lead to noticeable breakage until debug UART is enabled, which is not the default. Update the Makefile accordingly to allow debug UART to work. Fixes: c37a6684818d ("stm32mp: fix compilation issue with DEBUG_UART") Signed-off-by: Marek Vasut Reviewed-by: Patrice Chotard --- board/dhelectronics/dh_stm32mp1/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/board/dhelectronics/dh_stm32mp1/Makefile b/board/dhelectronics/dh_stm32mp1/Makefile index 2f4a301d1a0..429e01453bb 100644 --- a/board/dhelectronics/dh_stm32mp1/Makefile +++ b/board/dhelectronics/dh_stm32mp1/Makefile @@ -3,6 +3,8 @@ # Copyright (C) 2018, STMicroelectronics - All Rights Reserved # +obj-$(CONFIG_DEBUG_UART_BOARD_INIT) += ../../st/stm32mp1/debug_uart.o + obj-$(CONFIG_PMIC_STPMIC1) += ../../st/common/stpmic1.o obj-y += board.o From 7da7ca7cf50f4996493b99198e939726e721906d Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Mon, 8 Dec 2025 21:47:38 +0100 Subject: [PATCH 05/40] Makefile: use --output-target instead of --target The objcopy man-page teaches: --target=bfdname Use bfdname as the object format for both the input and the output file This implies for --target=efi-app-x86_64 that the input file would have to be an EFI app. Objcopy in binutils 2.45 checks this more strictly than previous versions and refuses to accept an ELF file as input with --target=efi-app-x86_64. Replace --target by --output-target for building sandbox and x86 EFI binaries. Signed-off-by: Heinrich Schuchardt Reviewed-by: Tom Rini --- arch/sandbox/config.mk | 4 ++-- arch/x86/config.mk | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/sandbox/config.mk b/arch/sandbox/config.mk index 9a61e803a57..275661a1f3a 100644 --- a/arch/sandbox/config.mk +++ b/arch/sandbox/config.mk @@ -50,10 +50,10 @@ cmd_u-boot-spl = (cd $(obj) && \ ifeq ($(HOST_ARCH),$(HOST_ARCH_X86_64)) EFI_LDS := ${SRCDIR}/../../../arch/x86/lib/elf_x86_64_efi.lds -EFI_TARGET := --target=efi-app-x86_64 +EFI_TARGET := --output-target=efi-app-x86_64 else ifeq ($(HOST_ARCH),$(HOST_ARCH_X86)) EFI_LDS := ${SRCDIR}/../../../arch/x86/lib/elf_ia32_efi.lds -EFI_TARGET := --target=efi-app-ia32 +EFI_TARGET := --output-target=efi-app-ia32 else ifeq ($(HOST_ARCH),$(HOST_ARCH_AARCH64)) EFI_LDS := ${SRCDIR}/../../../arch/arm/lib/elf_aarch64_efi.lds OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .data \ diff --git a/arch/x86/config.mk b/arch/x86/config.mk index 6d4839dfb38..c2bb5549b7c 100644 --- a/arch/x86/config.mk +++ b/arch/x86/config.mk @@ -69,7 +69,7 @@ endif LDSCRIPT_EFI := $(srctree)/arch/x86/lib/elf_$(EFIARCH)_efi.lds EFISTUB := crt0_$(EFIARCH)_efi.o reloc_$(EFIARCH)_efi.o -OBJCOPYFLAGS_EFI += --target=efi-app-$(EFIARCH) +OBJCOPYFLAGS_EFI += --output-target=efi-app-$(EFIARCH) CPPFLAGS_REMOVE_crt0-efi-$(EFIARCH).o += $(CFLAGS_NON_EFI) CPPFLAGS_crt0-efi-$(EFIARCH).o += $(CFLAGS_EFI) @@ -127,7 +127,7 @@ endif endif ifdef CONFIG_X86_64 -EFI_TARGET := --target=efi-app-x86_64 +EFI_TARGET := --output-target=efi-app-x86_64 else -EFI_TARGET := --target=efi-app-ia32 +EFI_TARGET := --output-target=efi-app-ia32 endif From da54deb1ac8ee65475c7dca556df751b7e31806e Mon Sep 17 00:00:00 2001 From: Beleswar Padhi Date: Tue, 9 Dec 2025 11:20:43 +0530 Subject: [PATCH 06/40] configs: am43xx: Migrate to CONFIG_SYS_MEM_TOP_HIDE from CFG_PRAM The TI AM43xx HS boards have been using CFG_PRAM to hide the top 64MB firewalled DRAM memory from U-Boot. However, CFG_PRAM only prevents U-Boot from relocating into that memory, but it is still open for access for any other usage. Therefore, migrate into using CONFIG_SYS_MEM_TOP_HIDE which reduces the ram size itself ensuring that memory is not visible to U-Boot at all (either for reloc, or general usage). Signed-off-by: Beleswar Padhi --- configs/am43xx_hs_evm_defconfig | 1 + configs/am43xx_hs_evm_qspi_defconfig | 1 + include/configs/am43xx_evm.h | 5 ----- 3 files changed, 2 insertions(+), 5 deletions(-) diff --git a/configs/am43xx_hs_evm_defconfig b/configs/am43xx_hs_evm_defconfig index c95fc0886bf..8bb13848a6a 100644 --- a/configs/am43xx_hs_evm_defconfig +++ b/configs/am43xx_hs_evm_defconfig @@ -15,6 +15,7 @@ CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE=0x01c00000 CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_TEXT_BASE=0x403018e0 CONFIG_SPL=y +CONFIG_SYS_MEM_TOP_HIDE=0x4000000 CONFIG_SPL_LOAD_FIT=y CONFIG_DISTRO_DEFAULTS=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/am43xx_hs_evm_qspi_defconfig b/configs/am43xx_hs_evm_qspi_defconfig index cc444ac2817..9b4bc178ed0 100644 --- a/configs/am43xx_hs_evm_qspi_defconfig +++ b/configs/am43xx_hs_evm_qspi_defconfig @@ -14,6 +14,7 @@ CONFIG_TI_SECURE_EMIF_REGION_START=0xbdb00000 CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x02000000 CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE=0x01c00000 CONFIG_ENV_OFFSET_REDUND=0x120000 +CONFIG_SYS_MEM_TOP_HIDE=0x4000000 CONFIG_DISTRO_DEFAULTS=y CONFIG_QSPI_BOOT=y CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index 036995cbb48..99d3ecb3fff 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -148,9 +148,4 @@ #define NANDBOOT #endif /* CONFIG_MTD_RAW_NAND */ -#if defined(CONFIG_TI_SECURE_DEVICE) -/* Avoid relocating onto firewalled area at end of DRAM */ -#define CFG_PRAM (64 * 1024) -#endif /* CONFIG_TI_SECURE_DEVICE */ - #endif /* __CONFIG_AM43XX_EVM_H */ From 93d000bc5237a82e74d437b5fc3c5fdf5237df2d Mon Sep 17 00:00:00 2001 From: Adriana Nicolae Date: Tue, 9 Dec 2025 07:55:38 -0800 Subject: [PATCH 07/40] test: dm: fdtdec: Validate FDT size in unit test The current FDT decoding tests calculate the memory required for FDT manipulation by directly adding a fixed margin to fdt_totalsize(gd->fdt_blob). The static analyzer flagged "gd->fdt_blob->totalsize" as a tainted value being passed to fdt_open_into(). Ensure the size is validated by checking that the total size is within a reasonable maximum FDT limit for unit tests. Signed-off-by: Adriana Nicolae --- test/dm/fdtdec.c | 23 +++++++++++++++++------ 1 file changed, 17 insertions(+), 6 deletions(-) diff --git a/test/dm/fdtdec.c b/test/dm/fdtdec.c index ea5a494612c..495f57234a4 100644 --- a/test/dm/fdtdec.c +++ b/test/dm/fdtdec.c @@ -14,14 +14,19 @@ DECLARE_GLOBAL_DATA_PTR; +#define FDTDEC_MAX_SIZE (2 * 1024 * 1024) + static int dm_test_fdtdec_set_carveout(struct unit_test_state *uts) { struct fdt_memory resv; void *blob; const fdt32_t *prop; - int blob_sz, len, offset; + int blob_sz, len, offset, fdt_sz; - blob_sz = fdt_totalsize(gd->fdt_blob) + 4096; + fdt_sz = fdt_totalsize(gd->fdt_blob); + ut_assert(fdt_sz > 0 && fdt_sz < FDTDEC_MAX_SIZE); + + blob_sz = fdt_sz + 4096; blob = malloc(blob_sz); ut_assertnonnull(blob); @@ -67,10 +72,13 @@ static int dm_test_fdtdec_add_reserved_memory(struct unit_test_state *uts) fdt_size_t size; void *blob; unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP; - int blob_sz, parent, subnode; + int blob_sz, parent, subnode, fdt_sz; uint32_t phandle, phandle1; - blob_sz = fdt_totalsize(gd->fdt_blob) + 128; + fdt_sz = fdt_totalsize(gd->fdt_blob); + ut_assert(fdt_sz > 0 && fdt_sz < FDTDEC_MAX_SIZE); + + blob_sz = fdt_sz + 128; blob = malloc(blob_sz); ut_assertnonnull(blob); @@ -138,14 +146,17 @@ static int dm_test_fdt_chosen_smbios(struct unit_test_state *uts) void *blob; ulong val; struct smbios3_entry *entry; - int chosen, blob_sz; + int chosen, blob_sz, fdt_sz; const fdt64_t *prop; if (!CONFIG_IS_ENABLED(GENERATE_SMBIOS_TABLE)) { return -EAGAIN; } - blob_sz = fdt_totalsize(gd->fdt_blob) + 4096; + fdt_sz = fdt_totalsize(gd->fdt_blob); + ut_assert(fdt_sz > 0 && fdt_sz < FDTDEC_MAX_SIZE); + + blob_sz = fdt_sz + 4096; blob = memalign(8, blob_sz); ut_assertnonnull(blob); From ff80e95fed188ec3d4001129445e414c9c811beb Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Tue, 9 Dec 2025 23:32:38 +0100 Subject: [PATCH 08/40] tools: use setuptools 78.1.1 CVE-2025-47273 describes a path traversal vulnerability. Signed-off-by: Heinrich Schuchardt Reviewed-by: Tom Rini --- tools/binman/pyproject.toml | 2 +- tools/buildman/pyproject.toml | 2 +- tools/dtoc/pyproject.toml | 2 +- tools/patman/pyproject.toml | 2 +- tools/u_boot_pylib/pyproject.toml | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/tools/binman/pyproject.toml b/tools/binman/pyproject.toml index ba34437fc53..7c9ab0f2a27 100644 --- a/tools/binman/pyproject.toml +++ b/tools/binman/pyproject.toml @@ -1,5 +1,5 @@ [build-system] -requires = ["setuptools>=61.0"] +requires = ["setuptools>=78.1.1"] build-backend = "setuptools.build_meta" [project] diff --git a/tools/buildman/pyproject.toml b/tools/buildman/pyproject.toml index 68bfa45c3f4..274042df155 100644 --- a/tools/buildman/pyproject.toml +++ b/tools/buildman/pyproject.toml @@ -1,5 +1,5 @@ [build-system] -requires = ["setuptools>=61.0"] +requires = ["setuptools>=78.1.1"] build-backend = "setuptools.build_meta" [project] diff --git a/tools/dtoc/pyproject.toml b/tools/dtoc/pyproject.toml index 9f59788e616..cc96cf784c6 100644 --- a/tools/dtoc/pyproject.toml +++ b/tools/dtoc/pyproject.toml @@ -1,5 +1,5 @@ [build-system] -requires = ["setuptools>=61.0"] +requires = ["setuptools>=78.1.1"] build-backend = "setuptools.build_meta" [project] diff --git a/tools/patman/pyproject.toml b/tools/patman/pyproject.toml index 06e169cdf48..91802c8cc27 100644 --- a/tools/patman/pyproject.toml +++ b/tools/patman/pyproject.toml @@ -1,5 +1,5 @@ [build-system] -requires = ["setuptools>=61.0"] +requires = ["setuptools>=78.1.1"] build-backend = "setuptools.build_meta" [project] diff --git a/tools/u_boot_pylib/pyproject.toml b/tools/u_boot_pylib/pyproject.toml index ce2355084ac..a860d134551 100644 --- a/tools/u_boot_pylib/pyproject.toml +++ b/tools/u_boot_pylib/pyproject.toml @@ -1,5 +1,5 @@ [build-system] -requires = ["setuptools>=61.0"] +requires = ["setuptools>=78.1.1"] build-backend = "setuptools.build_meta" [project] From f9f4f8df57996708c5767eda9a2a3fbcbd48a105 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Sun, 7 Dec 2025 12:18:45 +0100 Subject: [PATCH 09/40] lib: uuid: add EFI_PARTITION_INFO_PROTOCOL_GUID translation Add support for translating the EFI_PARTITION_INFO_PROTOCOL_GUID to a text. Reviewed-by: Ilias Apalodimas Signed-off-by: Heinrich Schuchardt --- lib/uuid.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/lib/uuid.c b/lib/uuid.c index e0f8d55438b..0a166320e07 100644 --- a/lib/uuid.c +++ b/lib/uuid.c @@ -139,6 +139,10 @@ static const struct { NULL, "Disk IO", EFI_DISK_IO_PROTOCOL_GUID, }, + { + NULL, "Partition Info", + EFI_PARTITION_INFO_PROTOCOL_GUID, + }, { NULL, "Simple File System", EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_GUID, From 1205204a43791183c8779cb5241cfcc4455b360c Mon Sep 17 00:00:00 2001 From: Udit Kumar Date: Sun, 7 Dec 2025 18:52:30 +0530 Subject: [PATCH 10/40] doc: board: ti: Add J742S2 support J742S2 SOC is derivative of J784S4, most of build infra of j784s4 is used to build u-boot for J742S2 EVM board. Add guide users on how to build for that board. Signed-off-by: Udit Kumar Reviewed-by: Mattijs Korpershoek --- doc/board/ti/j784s4_evm.rst | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/doc/board/ti/j784s4_evm.rst b/doc/board/ti/j784s4_evm.rst index 22442874110..d858dc7cdbb 100644 --- a/doc/board/ti/j784s4_evm.rst +++ b/doc/board/ti/j784s4_evm.rst @@ -1,8 +1,8 @@ .. SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause .. sectionauthor:: Apurva Nandan -J784S4 and AM69 Platforms -========================= +J742S2, J784S4 and AM69 Platforms +================================= Introduction ------------ @@ -37,6 +37,11 @@ Platform information: * https://www.ti.com/tool/J784S4XEVM * https://www.ti.com/tool/SK-AM69 +J742S2 is derivative of J784S24 SOC, More info can be found in + +* TRM : https://www.ti.com/lit/ug/spruje3/spruje3.pdf +* Platform Information : https://www.ti.com/tool/J742S2XH01EVM + Boot Flow --------- Below is the pictorial representation of boot flow: @@ -99,6 +104,13 @@ Set the variables corresponding to this platform: export UBOOT_CFG_CORTEXR=am69_sk_r5_defconfig export UBOOT_CFG_CORTEXA=am69_sk_a72_defconfig + For J742S2-EVM, use the following U_BOOT_CFG instead: + + .. prompt:: bash + + export UBOOT_CFG_CORTEXR=j742s2_evm_r5_defconfig + export UBOOT_CFG_CORTEXA=j742s2_evm_a72_defconfig + .. j784s4_evm_rst_include_start_build_steps 1. Trusted Firmware-A @@ -143,14 +155,21 @@ variant (GP, HS-FS, HS-SE) requires a different source for these files. * tiboot3-j784s4-gp-evm.bin from :ref:`step 3.1 ` * tispl.bin_unsigned, u-boot.img_unsigned from :ref:`step 3.2 ` + .. note:: + + For J742S2, GP variant is not available. + + - HS-FS * tiboot3-j784s4-hs-fs-evm.bin from :ref:`step 3.1 ` + * tiboot3-j742s2-hs-fs-evm.bin from :ref:`step 3.1 ` * tispl.bin, u-boot.img from :ref:`step 3.2 ` - HS-SE * tiboot3-j784s4-hs-evm.bin from :ref:`step 3.1 ` + * tiboot3-j742s2-hs-evm.bin from :ref:`step 3.1 ` * tispl.bin, u-boot.img from :ref:`step 3.2 ` Image formats From ec1c966285758489ee45cfc2af703d0ede1a376e Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Mon, 8 Dec 2025 13:16:23 -0600 Subject: [PATCH 11/40] doc: board: ti: k3: Fix a couple small typos s/Uenv.txt/uEnv.txt s/then/than Signed-off-by: Andrew Davis Reviewed-by: Bryan Brattlof --- doc/board/ti/k3.rst | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/doc/board/ti/k3.rst b/doc/board/ti/k3.rst index 37a66b3c69d..913cdd7d09e 100644 --- a/doc/board/ti/k3.rst +++ b/doc/board/ti/k3.rst @@ -653,9 +653,9 @@ Refer (:ref:`U-boot ARMV8 build `) Saving environment ------------------ -SAVEENV is disabled by default and for the new flow uses Uenv.txt as the default -way for saving the environments. This has been done as Uenv.txt is more granular -then the saveenv command and can be used across various bootmodes too. +SAVEENV is disabled by default and for the new flow uses uEnv.txt as the default +way for saving the environments. This has been done as uEnv.txt is more granular +than the saveenv command and can be used across various bootmodes too. **Writing to MMC/EMMC** From 87d85139a96a39429120cca838e739408ef971a2 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 9 Dec 2025 15:23:01 -0600 Subject: [PATCH 12/40] fs: fat: Perform sanity checks on getsize in get_fatent() We do not perform a check on the value of getsize in get_fatent to ensure that it will fit within the allocated buffer. For safety sake, add a check now and if the value exceeds FATBUFBLOCKS use that value instead. While not currently actively exploitable, it was in the past so adding this check is worthwhile. This addresses CVE-2025-24857 and was originally reported by Harvey Phillips of Amazon Element55. Signed-off-by: Tom Rini --- fs/fat/fat.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/fs/fat/fat.c b/fs/fat/fat.c index 89f2acbba1e..9ce5df59f9b 100644 --- a/fs/fat/fat.c +++ b/fs/fat/fat.c @@ -216,6 +216,11 @@ static __u32 get_fatent(fsdata *mydata, __u32 entry) if (flush_dirty_fat_buffer(mydata) < 0) return -1; + if (getsize > FATBUFBLOCKS) { + debug("getsize is too large for bufptr\n"); + getsize = FATBUFBLOCKS; + } + if (disk_read(startblock, getsize, bufptr) < 0) { debug("Error reading FAT blocks\n"); return ret; From a4dcf3183ff04321bea3a1ab2054e40cda2f672f Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Wed, 30 Jul 2025 14:46:33 +0200 Subject: [PATCH 13/40] board: theobroma-systems: update instructions for newer Rockchip rkbin The instructions are regularly out of date because the generated or prebuilt binaries are updated and the filename doesn't match our instructions anymore. Additionally, since commit 55a95caaef15 ("tools: ddrbin_tool: add ddrbin_tool.py and update to v1.21 20241211") end of October 2024, ddrbin_tool doesn't exist anymore and has been replaced by ddrbin_tool.py python script (which currently isn't an executable) so let's update these instructions as well. Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang --- doc/board/theobroma-systems/jaguar_rk3588.rst | 9 ++++----- doc/board/theobroma-systems/puma_rk3399.rst | 6 ++++-- doc/board/theobroma-systems/ringneck_px30.rst | 3 ++- doc/board/theobroma-systems/tiger_rk3588.rst | 9 ++++----- 4 files changed, 14 insertions(+), 13 deletions(-) diff --git a/doc/board/theobroma-systems/jaguar_rk3588.rst b/doc/board/theobroma-systems/jaguar_rk3588.rst index cba4fd066ab..33cd7276852 100644 --- a/doc/board/theobroma-systems/jaguar_rk3588.rst +++ b/doc/board/theobroma-systems/jaguar_rk3588.rst @@ -39,13 +39,12 @@ Get the TF-A and DDR init (TPL) binaries git clone https://github.com/rockchip-linux/rkbin cd rkbin - export RKBIN=$(pwd) - export BL31=$RKBIN/bin/rk35/rk3588_bl31_v1.47.elf - export ROCKCHIP_TPL=$RKBIN/bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v1.18.bin + export BL31=$(readlink -f bin/rk35/rk3588_bl31_v*.elf | head -1) + export ROCKCHIP_TPL=$(readlink -f bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v*.bin | head -1) sed -i 's/^uart baudrate=.*$/uart baudrate=115200/' tools/ddrbin_param.txt - ./tools/ddrbin_tool rk3588 tools/ddrbin_param.txt "$ROCKCHIP_TPL" + python3 ./tools/ddrbin_tool.py rk3588 tools/ddrbin_param.txt "$ROCKCHIP_TPL" ./tools/boot_merger RKBOOT/RK3588MINIALL.ini - export RKDB=$RKBIN/rk3588_spl_loader_v1.11.112.bin + export RKDB=$(readlink -f rk3588_spl_loader_v*.bin | head -1) This will setup all required external dependencies for compiling U-Boot. This will be updated in the future once upstream Trusted-Firmware-A supports RK3588 or U-Boot diff --git a/doc/board/theobroma-systems/puma_rk3399.rst b/doc/board/theobroma-systems/puma_rk3399.rst index a2a5e7bca4b..1a8d33f188d 100644 --- a/doc/board/theobroma-systems/puma_rk3399.rst +++ b/doc/board/theobroma-systems/puma_rk3399.rst @@ -95,8 +95,9 @@ To flash U-Boot on the eMMC with ``rkdeveloptool``: git clone https://github.com/rockchip-linux/rkbin.git cd rkbin ./tools/boot_merger RKBOOT/RK3399MINIALL.ini + export RKDB=$(readlink -f rk3399_loader_v*.bin | head -1) cd .. - ./rkdeveloptool db rkbin/rk3399_loader_v1.30.130.bin + ./rkdeveloptool db "$RKDB" ./rkdeveloptool wl 64 ../u-boot-rockchip.bin NOR-Flash @@ -121,7 +122,8 @@ To flash U-Boot on the SPI with ``rkdeveloptool``: git clone https://github.com/rockchip-linux/rkbin.git cd rkbin ./tools/boot_merger RKBOOT/RK3399MINIALL_SPINOR.ini + export RKDB=$(readlink -f rk3399_loader_spinor_v*.bin | head -1) cd .. - ./rkdeveloptool db rkbin/rk3399_loader_spinor_v1.30.114.bin + ./rkdeveloptool db "$RKDB" ./rkdeveloptool ef ./rkdeveloptool wl 0 ../u-boot-rockchip-spi.bin diff --git a/doc/board/theobroma-systems/ringneck_px30.rst b/doc/board/theobroma-systems/ringneck_px30.rst index c16b9ed17ed..d3feedf6062 100644 --- a/doc/board/theobroma-systems/ringneck_px30.rst +++ b/doc/board/theobroma-systems/ringneck_px30.rst @@ -90,6 +90,7 @@ To flash U-Boot on the eMMC with ``rkdeveloptool``: git clone https://github.com/rockchip-linux/rkbin.git cd rkbin ./tools/boot_merger RKBOOT/PX30MINIALL.ini + export RKDB=$(readlink -f px30_loader_v*.bin | head -1) cd .. - ./rkdeveloptool db rkbin/px30_loader_v2.08.135.bin + ./rkdeveloptool db "$RKDB" ./rkdeveloptool wl 64 ../u-boot-rockchip.bin diff --git a/doc/board/theobroma-systems/tiger_rk3588.rst b/doc/board/theobroma-systems/tiger_rk3588.rst index 4586b8d8b5a..71dbe4c59de 100644 --- a/doc/board/theobroma-systems/tiger_rk3588.rst +++ b/doc/board/theobroma-systems/tiger_rk3588.rst @@ -46,14 +46,13 @@ Get the TF-A and DDR init (TPL) binaries git clone https://github.com/rockchip-linux/rkbin cd rkbin - export RKBIN=$(pwd) - export BL31=$RKBIN/bin/rk35/rk3588_bl31_v1.47.elf - export ROCKCHIP_TPL=$RKBIN/bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v1.18.bin + export BL31=$(readlink -f bin/rk35/rk3588_bl31_v*.elf | head -1) + export ROCKCHIP_TPL=$(readlink -f bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v*.bin | head -1) sed -i 's/^uart baudrate=.*$/uart baudrate=115200/' tools/ddrbin_param.txt sed -i 's/^uart iomux=.*$/uart iomux=2/' tools/ddrbin_param.txt - ./tools/ddrbin_tool rk3588 tools/ddrbin_param.txt "$ROCKCHIP_TPL" + python3 ./tools/ddrbin_tool.py rk3588 tools/ddrbin_param.txt "$ROCKCHIP_TPL" ./tools/boot_merger RKBOOT/RK3588MINIALL.ini - export RKDB=$RKBIN/rk3588_spl_loader_v1.11.112.bin + export RKDB=$(readlink -f rk3588_spl_loader_v*.bin | head -1) This will setup all required external dependencies for compiling U-Boot. This will be updated in the future once upstream Trusted-Firmware-A supports RK3588 or U-Boot From 1bea4284b0f0a5722bb1b6fec4baa096cb808bc4 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Wed, 30 Jul 2025 14:46:34 +0200 Subject: [PATCH 14/40] board: theobroma-systems: add instructions for how to use upstream TF-A Upstream TF-A has support for RK3588 since v2.12 so let's document how to use upstream TF-A instead of the prebuilt binary blob from Rockchip if one wants to do that. Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang --- doc/board/theobroma-systems/jaguar_rk3588.rst | 38 ++++++++++++++++--- doc/board/theobroma-systems/tiger_rk3588.rst | 38 ++++++++++++++++--- 2 files changed, 66 insertions(+), 10 deletions(-) diff --git a/doc/board/theobroma-systems/jaguar_rk3588.rst b/doc/board/theobroma-systems/jaguar_rk3588.rst index 33cd7276852..eff0ee7347c 100644 --- a/doc/board/theobroma-systems/jaguar_rk3588.rst +++ b/doc/board/theobroma-systems/jaguar_rk3588.rst @@ -32,14 +32,13 @@ It provides the following features: Here is the step-by-step to boot to U-Boot on SBC-RK3588-AMR Jaguar from Theobroma Systems. -Get the TF-A and DDR init (TPL) binaries ----------------------------------------- +Get DDR init (TPL) binary +------------------------- .. prompt:: bash git clone https://github.com/rockchip-linux/rkbin cd rkbin - export BL31=$(readlink -f bin/rk35/rk3588_bl31_v*.elf | head -1) export ROCKCHIP_TPL=$(readlink -f bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v*.bin | head -1) sed -i 's/^uart baudrate=.*$/uart baudrate=115200/' tools/ddrbin_param.txt python3 ./tools/ddrbin_tool.py rk3588 tools/ddrbin_param.txt "$ROCKCHIP_TPL" @@ -47,8 +46,32 @@ Get the TF-A and DDR init (TPL) binaries export RKDB=$(readlink -f rk3588_spl_loader_v*.bin | head -1) This will setup all required external dependencies for compiling U-Boot. This will -be updated in the future once upstream Trusted-Firmware-A supports RK3588 or U-Boot -gains support for open-source DRAM initialization in TPL. +be updated in the future once U-Boot gains support for open-source DRAM initialization +in TPL. + +Get TF-A +-------- + +There are two possible options, pick one or the other. Note that the instructions need +to be run from the ``rkbin`` directory. + +Prebuilt binary from Rockchip +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. prompt:: bash + + export BL31=$(readlink -f bin/rk35/rk3588_bl31_v*.elf | head -1) + +Upstream +~~~~~~~~ + +.. prompt:: bash + + cd ../ + git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git + cd trusted-firmware-a + make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3588 bl31 + export BL31=$PWD/build/rk3588/release/bl31/bl31.elf Build U-Boot ------------ @@ -58,6 +81,11 @@ Build U-Boot cd ../u-boot make CROSS_COMPILE=aarch64-linux-gnu- jaguar-rk3588_defconfig all +.. note:: + If using upstream TF-A, one should disable ``SPL_ATF_NO_PLATFORM_PARAM`` symbol in + U-Boot config (via e.g. ``make CROSS_COMPILE=aarch64-linux-gnu- menuconfig``) which + will, among other things, enable console output in TF-A. + This will build ``u-boot-rockchip.bin`` which can be written to an MMC device (eMMC or SD card). diff --git a/doc/board/theobroma-systems/tiger_rk3588.rst b/doc/board/theobroma-systems/tiger_rk3588.rst index 71dbe4c59de..493f191020f 100644 --- a/doc/board/theobroma-systems/tiger_rk3588.rst +++ b/doc/board/theobroma-systems/tiger_rk3588.rst @@ -39,14 +39,13 @@ It provides the following feature set: Here is the step-by-step to boot to U-Boot on SOM-RK3588-Q7 Tiger from Theobroma Systems. -Get the TF-A and DDR init (TPL) binaries ----------------------------------------- +Get DDR init (TPL) binary +------------------------- .. prompt:: bash git clone https://github.com/rockchip-linux/rkbin cd rkbin - export BL31=$(readlink -f bin/rk35/rk3588_bl31_v*.elf | head -1) export ROCKCHIP_TPL=$(readlink -f bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v*.bin | head -1) sed -i 's/^uart baudrate=.*$/uart baudrate=115200/' tools/ddrbin_param.txt sed -i 's/^uart iomux=.*$/uart iomux=2/' tools/ddrbin_param.txt @@ -55,8 +54,32 @@ Get the TF-A and DDR init (TPL) binaries export RKDB=$(readlink -f rk3588_spl_loader_v*.bin | head -1) This will setup all required external dependencies for compiling U-Boot. This will -be updated in the future once upstream Trusted-Firmware-A supports RK3588 or U-Boot -gains support for open-source DRAM initialization in TPL. +be updated in the future once U-Boot gains support for open-source DRAM initialization +in TPL. + +Get TF-A +-------- + +There are two possible options, pick one or the other. Note that the instructions need +to be run from the ``rkbin`` directory. + +Prebuilt binary from Rockchip +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. prompt:: bash + + export BL31=$(readlink -f bin/rk35/rk3588_bl31_v*.elf | head -1) + +Upstream +~~~~~~~~ + +.. prompt:: bash + + cd ../ + git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git + cd trusted-firmware-a + make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3588 bl31 + export BL31=$PWD/build/rk3588/release/bl31/bl31.elf Build U-Boot ------------ @@ -66,6 +89,11 @@ Build U-Boot cd ../u-boot make CROSS_COMPILE=aarch64-linux-gnu- tiger-rk3588_defconfig all +.. note:: + If using upstream TF-A, one should disable ``SPL_ATF_NO_PLATFORM_PARAM`` symbol in + U-Boot config (via e.g. ``make CROSS_COMPILE=aarch64-linux-gnu- menuconfig``) which + will, among other things, enable console output in TF-A. + This will build ``u-boot-rockchip.bin`` which can be written to an MMC device (eMMC or SD card). From b3a141846b05f00e8f2654d888a2e2cd7d11b40d Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Wed, 30 Jul 2025 14:46:35 +0200 Subject: [PATCH 15/40] board: theobroma-systems: jaguar_rk3588: explicit UART IOMUX When one attempts to build Tiger and Jaguar from the same directory, because Tiger will set the IOMUX to 2 but Jaguar doesn't reset it, Jaguar will have IOMUX set to 2 if built after Tiger. This isn't an issue if in separate directories or building Tiger after Jaguar because the default if missing from the configuration file is 0. Let's make it explicit that the iomux is 0 for Jaguar. Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang --- doc/board/theobroma-systems/jaguar_rk3588.rst | 1 + 1 file changed, 1 insertion(+) diff --git a/doc/board/theobroma-systems/jaguar_rk3588.rst b/doc/board/theobroma-systems/jaguar_rk3588.rst index eff0ee7347c..d09cfaa88ff 100644 --- a/doc/board/theobroma-systems/jaguar_rk3588.rst +++ b/doc/board/theobroma-systems/jaguar_rk3588.rst @@ -41,6 +41,7 @@ Get DDR init (TPL) binary cd rkbin export ROCKCHIP_TPL=$(readlink -f bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v*.bin | head -1) sed -i 's/^uart baudrate=.*$/uart baudrate=115200/' tools/ddrbin_param.txt + sed -i 's/^uart iomux=.*$/uart iomux=0/' tools/ddrbin_param.txt python3 ./tools/ddrbin_tool.py rk3588 tools/ddrbin_param.txt "$ROCKCHIP_TPL" ./tools/boot_merger RKBOOT/RK3588MINIALL.ini export RKDB=$(readlink -f rk3588_spl_loader_v*.bin | head -1) From b57363a2b9b6bbc6a4fa63d93681485b812ccc51 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 2 Aug 2025 22:07:22 +0000 Subject: [PATCH 16/40] rockchip: Move TEXT_BASE to 8 MiB offset from start of DRAM Drop SoC specific TEXT_BASE and use a common TEXT_BASE for all SoCs. Move the common TEXT_BASE to 8 MiB offset from start of DRAM to help support RAM boot from maskrom introduced in next patch. RAM boot from maskrom mode will expect the FIT payload to be located at 2 MiB offset from start or DRAM. Signed-off-by: Jonas Karlman Tested-by: Arnaud Patard Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/Kconfig | 6 +++--- arch/arm/mach-rockchip/rk3308/Kconfig | 3 --- arch/arm/mach-rockchip/rk3568/Kconfig | 3 --- arch/arm/mach-rockchip/rk3588/Kconfig | 3 --- 4 files changed, 3 insertions(+), 12 deletions(-) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 342933ca509..c9ce3076029 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -768,9 +768,9 @@ config TPL_SYS_MALLOC_F_LEN default 0x4000 if CUSTOM_SYS_INIT_SP_ADDR = 0x03f00000 config TEXT_BASE - default 0x60200000 if SPL_TEXT_BASE = 0x60000000 - default 0x40200000 if SPL_TEXT_BASE = 0x40000000 - default 0x00200000 if SPL_TEXT_BASE = 0x00000000 + default 0x60800000 if SPL_TEXT_BASE = 0x60000000 + default 0x40800000 if SPL_TEXT_BASE = 0x40000000 + default 0x00800000 if SPL_TEXT_BASE = 0x00000000 config SPL_TEXT_BASE default 0x60000000 if ROCKCHIP_RK3036 || ROCKCHIP_RK3066 || \ diff --git a/arch/arm/mach-rockchip/rk3308/Kconfig b/arch/arm/mach-rockchip/rk3308/Kconfig index 06572d545f6..b8d25c52542 100644 --- a/arch/arm/mach-rockchip/rk3308/Kconfig +++ b/arch/arm/mach-rockchip/rk3308/Kconfig @@ -17,9 +17,6 @@ config ROCKCHIP_STIMER_BASE config SYS_SOC default "rk3308" -config TEXT_BASE - default 0x00600000 - source "board/rockchip/evb_rk3308/Kconfig" source "board/firefly/firefly-rk3308/Kconfig" diff --git a/arch/arm/mach-rockchip/rk3568/Kconfig b/arch/arm/mach-rockchip/rk3568/Kconfig index 01b53a47ddb..2730220a18e 100644 --- a/arch/arm/mach-rockchip/rk3568/Kconfig +++ b/arch/arm/mach-rockchip/rk3568/Kconfig @@ -70,9 +70,6 @@ config ROCKCHIP_STIMER_BASE config SYS_SOC default "rk3568" -config TEXT_BASE - default 0x00a00000 - source "board/rockchip/evb_rk3568/Kconfig" source "board/anbernic/rgxx3_rk3566/Kconfig" source "board/hardkernel/odroid_m1/Kconfig" diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig index 9fbe3f225aa..60c16d2f32d 100644 --- a/arch/arm/mach-rockchip/rk3588/Kconfig +++ b/arch/arm/mach-rockchip/rk3588/Kconfig @@ -417,9 +417,6 @@ config ROCKCHIP_STIMER_BASE config SYS_SOC default "rk3588" -config TEXT_BASE - default 0x00a00000 - source "board/armsom/sige7-rk3588/Kconfig" source "board/coolpi/genbook_cm5_rk3588/Kconfig" source "board/edgeble/neural-compute-module-6/Kconfig" From e22335a221f88e7f61171e752ca195663f86d81f Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 2 Aug 2025 22:07:23 +0000 Subject: [PATCH 17/40] rockchip: Add support for RAM boot from maskrom mode The BootROM in Rockchip SoCs will enter maskrom mode when boot firmware cannot be found in nand/spi/mmc storage. In maskrom mode the USB OTG port can accept one of two custom commands. Initially a 0x471 command to load TPL into SRAM. After TPL has been executed and it has returned back-to-BROM, a 0x472 command to load SPL into start of DRAM. Add two binman images that can be used to RAM boot from maskrom mode: - u-boot-rockchip-usb471.bin that contains TPL to init DRAM. - u-boot-rockchip-usb472.bin that contains SPL and the normal FIT payload with i.e. U-Boot proper, TF-A and FDT. A config fragment rockchip-ramboot.config can be used to enable building of these two binman images, e.g.: make generic-rk3588_defconfig rockchip-ramboot.config These binman images can be used with the proprietary rkbin boot_merger tool to create a special loader image that can be used with tools such as rkdeveloptool or rockusb tools to RAM boot from maskrom, e.g.: Create loader image: $ ../rkbin/tools/boot_merger ./RK3588MINIALL.ini Boot from maskrom: $ rkdeveloptool db u-boot-rockchip-rk3588-loader.bin or $ rockusb download-boot u-boot-rockchip-rk3588-loader.bin Another option that does not require use of proprietary tools is using open source tools such as rkflashtool or rkusbboot that can load the binman images directly without any need to first create a special loader image to RAM boot from maskrom, e.g.: $ rkflashtool l < u-boot-rockchip-usb471.bin $ rkflashtool L < u-boot-rockchip-usb472.bin or $ rkusbboot u-boot-rockchip-usb471.bin u-boot-rockchip-usb472.bin Signed-off-by: Jonas Karlman Tested-by: Arnaud Patard Reviewed-by: Kever Yang --- arch/arm/dts/rockchip-u-boot.dtsi | 33 +++++++++++++++++++++++++ arch/arm/mach-rockchip/Kconfig | 8 ++++++ arch/arm/mach-rockchip/spl-boot-order.c | 14 ++++++++--- board/rockchip/rockchip-ramboot.config | 1 + boot/Kconfig | 3 +++ 5 files changed, 56 insertions(+), 3 deletions(-) create mode 100644 board/rockchip/rockchip-ramboot.config diff --git a/arch/arm/dts/rockchip-u-boot.dtsi b/arch/arm/dts/rockchip-u-boot.dtsi index cc2feed6464..71d7623fe2c 100644 --- a/arch/arm/dts/rockchip-u-boot.dtsi +++ b/arch/arm/dts/rockchip-u-boot.dtsi @@ -226,5 +226,38 @@ }; }; #endif /* CONFIG_ROCKCHIP_SPI_IMAGE */ + +#ifdef CONFIG_ROCKCHIP_MASKROM_IMAGE + simple-bin-usb471 { + filename = "u-boot-rockchip-usb471.bin"; + +#ifdef CONFIG_ROCKCHIP_EXTERNAL_TPL + rockchip-tpl { + }; +#elif defined(CONFIG_TPL) + u-boot-tpl { + no-write-symbols; + }; +#endif + }; + + simple-bin-usb472 { + filename = "u-boot-rockchip-usb472.bin"; + pad-byte = <0x00>; + + u-boot-spl { + no-write-symbols; + }; + +#ifdef HAS_FIT + fit { + insert-template = <&fit_template>; +#else + u-boot-img { +#endif + offset = <(CONFIG_SPL_LOAD_FIT_ADDRESS - CFG_SYS_SDRAM_BASE)>; + }; + }; +#endif /* CONFIG_ROCKCHIP_MASKROM_IMAGE */ }; #endif /* CONFIG_SPL */ diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index c9ce3076029..e32e49ff59a 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -706,6 +706,14 @@ config ROCKCHIP_SPI_IMAGE option to produce a SPI-flash image containing U-Boot. The image is built by binman. U-Boot sits near the start of the image. +config ROCKCHIP_MASKROM_IMAGE + bool "Build a maskrom mode image for Rockchip" + depends on TPL || ROCKCHIP_EXTERNAL_TPL + select SPL_RAM_DEVICE + help + Rockchip SoCs support maskrom mode boot over USB. Enable this + option to produce maskrom mode boot images containing U-Boot. + config LNX_KRNL_IMG_TEXT_OFFSET_BASE default TEXT_BASE diff --git a/arch/arm/mach-rockchip/spl-boot-order.c b/arch/arm/mach-rockchip/spl-boot-order.c index 1ea1033b5ea..6572dde29f6 100644 --- a/arch/arm/mach-rockchip/spl-boot-order.c +++ b/arch/arm/mach-rockchip/spl-boot-order.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include @@ -98,15 +99,22 @@ __weak const char *board_spl_was_booted_from(void) void board_boot_order(u32 *spl_boot_list) { + int idx = 0; + + /* Add RAM boot for maskrom mode boot over USB */ + if (BROM_BOOTSOURCE_ID_ADDR && CONFIG_IS_ENABLED(RAM_DEVICE) && + read_brom_bootsource_id() == BROM_BOOTSOURCE_USB) { + spl_boot_list[idx++] = BOOT_DEVICE_RAM; + } + /* In case of no fdt (or only plat), use spl_boot_device() */ if (!CONFIG_IS_ENABLED(OF_CONTROL) || CONFIG_IS_ENABLED(OF_PLATDATA)) { - spl_boot_list[0] = spl_boot_device(); + spl_boot_list[idx++] = spl_boot_device(); return; } const void *blob = gd->fdt_blob; int chosen_node = fdt_path_offset(blob, "/chosen"); - int idx = 0; int elem; int boot_device; int node; @@ -115,7 +123,7 @@ void board_boot_order(u32 *spl_boot_list) if (chosen_node < 0) { debug("%s: /chosen not found, using spl_boot_device()\n", __func__); - spl_boot_list[0] = spl_boot_device(); + spl_boot_list[idx++] = spl_boot_device(); return; } diff --git a/board/rockchip/rockchip-ramboot.config b/board/rockchip/rockchip-ramboot.config new file mode 100644 index 00000000000..312363e542b --- /dev/null +++ b/board/rockchip/rockchip-ramboot.config @@ -0,0 +1 @@ +CONFIG_ROCKCHIP_MASKROM_IMAGE=y diff --git a/boot/Kconfig b/boot/Kconfig index 85f4d468069..245e120c70b 100644 --- a/boot/Kconfig +++ b/boot/Kconfig @@ -275,6 +275,9 @@ config SPL_LOAD_FIT_ADDRESS hex "load address of fit image" depends on SPL_LOAD_FIT default 0x44000000 if ARCH_IMX8M + default 0x60080000 if ARCH_ROCKCHIP && SPL_TEXT_BASE = 0x60000000 + default 0x40200000 if ARCH_ROCKCHIP && SPL_TEXT_BASE = 0x40000000 + default 0x00200000 if ARCH_ROCKCHIP && SPL_TEXT_BASE = 0x00000000 default 0x0 help Specify the load address of the fit image that will be loaded From 57dc75fb9be8f2508cb8c32dc5909c5b57876ace Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Fri, 1 Aug 2025 17:09:27 +0000 Subject: [PATCH 18/40] rockchip: sdram: Add rockchip_sdram_type() helper Add a helper function based on rockchip_sdram_size() that return what DRAM type is used on current running board. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/include/asm/arch-rockchip/sdram.h | 3 +++ arch/arm/mach-rockchip/sdram.c | 15 +++++++++++++++ 2 files changed, 18 insertions(+) diff --git a/arch/arm/include/asm/arch-rockchip/sdram.h b/arch/arm/include/asm/arch-rockchip/sdram.h index 4fb45ac5c76..476fc1c4ee3 100644 --- a/arch/arm/include/asm/arch-rockchip/sdram.h +++ b/arch/arm/include/asm/arch-rockchip/sdram.h @@ -87,6 +87,9 @@ enum { #define SYS_REG_CS1_COL_SHIFT(ch) (0 + (ch) * 2) #define SYS_REG_CS1_COL_MASK 3 +/* Get sdram type decode from reg */ +u8 rockchip_sdram_type(phys_addr_t reg); + /* Get sdram size decode from reg */ size_t rockchip_sdram_size(phys_addr_t reg); diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c index 3bc482331c7..d560f90e873 100644 --- a/arch/arm/mach-rockchip/sdram.c +++ b/arch/arm/mach-rockchip/sdram.c @@ -345,6 +345,21 @@ int dram_init_banksize(void) return 0; } +u8 rockchip_sdram_type(phys_addr_t reg) +{ + u32 dram_type, version; + u32 sys_reg2 = readl(reg); + u32 sys_reg3 = readl(reg + 4); + + dram_type = (sys_reg2 >> SYS_REG_DDRTYPE_SHIFT) & SYS_REG_DDRTYPE_MASK; + version = (sys_reg3 >> SYS_REG_VERSION_SHIFT) & SYS_REG_VERSION_MASK; + if (version >= 3) + dram_type |= ((sys_reg3 >> SYS_REG_EXTEND_DDRTYPE_SHIFT) & + SYS_REG_EXTEND_DDRTYPE_MASK) << 3; + + return dram_type; +} + size_t rockchip_sdram_size(phys_addr_t reg) { u32 rank, cs0_col, bk, cs0_row, cs1_row, bw, row_3_4; From 2df3666a241b706005ac8130c06188678c32ba39 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Fri, 1 Aug 2025 17:09:28 +0000 Subject: [PATCH 19/40] rockchip: rock5b-rk3588: Add support for ROCK 5B+ Include FDTs for both ROCK 5B and 5B+ in the FIT and add board selection code to load the 5B+ FDT when the DRAM type is LPDDR5 and ADC channel 5 value is close to 4095. U-Boot 2025.07 (Jul 14 2025 - 21:28:20 +0000) Model: Radxa ROCK 5B+ SoC: RK3588 DRAM: 8 GiB Features tested on a ROCK 5B+ v1.2: - SD-card boot - eMMC boot - SPI flash boot - PCIe/NVMe - Ethernet - USB/TCPM Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rk3588-rock-5b-plus-u-boot.dtsi | 3 + arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 5 ++ board/radxa/rock5b-rk3588/Kconfig | 5 ++ board/radxa/rock5b-rk3588/MAINTAINERS | 3 +- board/radxa/rock5b-rk3588/rock5b-rk3588.c | 63 ++++++++++++++++++++ configs/rock5b-rk3588_defconfig | 1 + doc/board/rockchip/rockchip.rst | 2 +- 7 files changed, 79 insertions(+), 3 deletions(-) create mode 100644 arch/arm/dts/rk3588-rock-5b-plus-u-boot.dtsi diff --git a/arch/arm/dts/rk3588-rock-5b-plus-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-plus-u-boot.dtsi new file mode 100644 index 00000000000..c07696c8391 --- /dev/null +++ b/arch/arm/dts/rk3588-rock-5b-plus-u-boot.dtsi @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3588-rock-5b-u-boot.dtsi" diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi index d51fbf51cb8..e07b549c767 100644 --- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi +++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi @@ -46,6 +46,11 @@ }; }; +&saradc { + bootph-pre-ram; + vdd-microvolts = <1800000>; +}; + &sdhci { cap-mmc-highspeed; mmc-hs200-1_8v; diff --git a/board/radxa/rock5b-rk3588/Kconfig b/board/radxa/rock5b-rk3588/Kconfig index 41dfe2402b1..98d63011783 100644 --- a/board/radxa/rock5b-rk3588/Kconfig +++ b/board/radxa/rock5b-rk3588/Kconfig @@ -9,4 +9,9 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "rock5b-rk3588" +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ADC + select SPL_ADC + endif diff --git a/board/radxa/rock5b-rk3588/MAINTAINERS b/board/radxa/rock5b-rk3588/MAINTAINERS index 4460c9971a9..c8a43769105 100644 --- a/board/radxa/rock5b-rk3588/MAINTAINERS +++ b/board/radxa/rock5b-rk3588/MAINTAINERS @@ -5,5 +5,4 @@ S: Maintained F: board/radxa/rock5b-rk3588 F: include/configs/rock5b-rk3588.h F: configs/rock5b-rk3588_defconfig -F: arch/arm/dts/rk3588-rock-5b.dts -F: arch/arm/dts/rk3588-rock-5b-u-boot.dtsi +F: arch/arm/dts/rk3588-rock-5b* diff --git a/board/radxa/rock5b-rk3588/rock5b-rk3588.c b/board/radxa/rock5b-rk3588/rock5b-rk3588.c index fc2f69db224..6bf4497ce3a 100644 --- a/board/radxa/rock5b-rk3588/rock5b-rk3588.c +++ b/board/radxa/rock5b-rk3588/rock5b-rk3588.c @@ -3,8 +3,71 @@ * Copyright (c) 2023-2024 Collabora Ltd. */ +#include +#include #include #include +#include +#include + +#define PMU1GRF_BASE 0xfd58a000 +#define OS_REG2_REG 0x208 + +#define HW_ID_CHANNEL 5 + +struct board_model { + unsigned int dram; + unsigned int low; + unsigned int high; + const char *fdtfile; +}; + +static const struct board_model board_models[] = { + { LPDDR5, 4005, 4185, "rockchip/rk3588-rock-5b-plus.dtb" }, +}; + +static const struct board_model *get_board_model(void) +{ + unsigned int val, dram_type; + int i, ret; + + dram_type = rockchip_sdram_type(PMU1GRF_BASE + OS_REG2_REG); + + ret = adc_channel_single_shot("adc@fec10000", HW_ID_CHANNEL, &val); + if (ret) + return NULL; + + for (i = 0; i < ARRAY_SIZE(board_models); i++) { + unsigned int dram = board_models[i].dram; + unsigned int min = board_models[i].low; + unsigned int max = board_models[i].high; + + if (dram == dram_type && min <= val && val <= max) + return &board_models[i]; + } + + return NULL; +} + +int rk_board_late_init(void) +{ + const struct board_model *model = get_board_model(); + + if (model) + env_set("fdtfile", model->fdtfile); + + return 0; +} + +int board_fit_config_name_match(const char *name) +{ + const struct board_model *model = get_board_model(); + + if (model && !strcmp(name, model->fdtfile)) + return 0; + + return -EINVAL; +} #ifdef CONFIG_OF_BOARD_SETUP int ft_board_setup(void *blob, struct bd_info *bd) diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig index 6349e879145..967cebc2054 100644 --- a/configs/rock5b-rk3588_defconfig +++ b/configs/rock5b-rk3588_defconfig @@ -47,6 +47,7 @@ CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y +CONFIG_OF_LIST="rockchip/rk3588-rock-5b rockchip/rk3588-rock-5b-plus" CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_REGMAP=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 0acccb51ad5..9af701feb5d 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -162,7 +162,7 @@ List of mainline supported Rockchip boards: - Pine64 QuartzPro64 (quartzpro64-rk3588) - Radxa ROCK 5 ITX (rock-5-itx-rk3588) - Radxa ROCK 5A (rock5a-rk3588s) - - Radxa ROCK 5B (rock5b-rk3588) + - Radxa ROCK 5B/5B+ (rock5b-rk3588) - Radxa ROCK 5C (rock-5c-rk3588s) - Rockchip Toybrick TB-RK3588X (toybrick-rk3588) - Theobroma Systems RK3588-SBC Jaguar (jaguar-rk3588) From 73159af02d023d01d9c4c08d319eb86cb10f1983 Mon Sep 17 00:00:00 2001 From: FUKAUMI Naoki Date: Fri, 7 Nov 2025 06:47:16 +0000 Subject: [PATCH 20/40] rockchip: rock5b-rk3588: Add support for Radxa ROCK 5T Include the FDT for Radxa ROCK 5T in the FIT, in addition to those for 5B and 5B+, and add board selection code to load the 5T FDT when the DRAM type is LPDDR5 and ADC channel 5 value is close to 1016. Signed-off-by: FUKAUMI Naoki Reviewed-by: Kever Yang --- arch/arm/dts/rk3588-rock-5t-u-boot.dtsi | 3 +++ board/radxa/rock5b-rk3588/rock5b-rk3588.c | 1 + configs/rock5b-rk3588_defconfig | 2 +- doc/board/rockchip/rockchip.rst | 2 +- 4 files changed, 6 insertions(+), 2 deletions(-) create mode 100644 arch/arm/dts/rk3588-rock-5t-u-boot.dtsi diff --git a/arch/arm/dts/rk3588-rock-5t-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5t-u-boot.dtsi new file mode 100644 index 00000000000..c07696c8391 --- /dev/null +++ b/arch/arm/dts/rk3588-rock-5t-u-boot.dtsi @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3588-rock-5b-u-boot.dtsi" diff --git a/board/radxa/rock5b-rk3588/rock5b-rk3588.c b/board/radxa/rock5b-rk3588/rock5b-rk3588.c index 6bf4497ce3a..2c172d04499 100644 --- a/board/radxa/rock5b-rk3588/rock5b-rk3588.c +++ b/board/radxa/rock5b-rk3588/rock5b-rk3588.c @@ -23,6 +23,7 @@ struct board_model { }; static const struct board_model board_models[] = { + { LPDDR5, 926, 1106, "rockchip/rk3588-rock-5t.dtb" }, { LPDDR5, 4005, 4185, "rockchip/rk3588-rock-5b-plus.dtb" }, }; diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig index 967cebc2054..567f649ea69 100644 --- a/configs/rock5b-rk3588_defconfig +++ b/configs/rock5b-rk3588_defconfig @@ -47,7 +47,7 @@ CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y -CONFIG_OF_LIST="rockchip/rk3588-rock-5b rockchip/rk3588-rock-5b-plus" +CONFIG_OF_LIST="rockchip/rk3588-rock-5b rockchip/rk3588-rock-5b-plus rockchip/rk3588-rock-5t" CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_REGMAP=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 9af701feb5d..6ae4d4371ff 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -162,7 +162,7 @@ List of mainline supported Rockchip boards: - Pine64 QuartzPro64 (quartzpro64-rk3588) - Radxa ROCK 5 ITX (rock-5-itx-rk3588) - Radxa ROCK 5A (rock5a-rk3588s) - - Radxa ROCK 5B/5B+ (rock5b-rk3588) + - Radxa ROCK 5B/5B+/5T (rock5b-rk3588) - Radxa ROCK 5C (rock-5c-rk3588s) - Rockchip Toybrick TB-RK3588X (toybrick-rk3588) - Theobroma Systems RK3588-SBC Jaguar (jaguar-rk3588) From c9d27133159d0a84bf11052f588194a734cb48d4 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Fri, 7 Nov 2025 12:39:17 +0100 Subject: [PATCH 21/40] rockchip: i2c: fix incorrect STOP flag for the interrupt enable register I2C_CON_STOP is a flag to be used for the con register, where it is bit 4 to send the STOP condition. To enable the interrupt the controller sends to tell it's finished sending the STOP condition, it's the ien register at bit 5. Let's use the proper offset. My hunch is that enabling the interrupt is useless as the interrupt status register is always up-to-date and enabling the interrupt is just so that the interrupt is available via the GIC. However, U-Boot has no interrupt support and the logic was working well before this patch. This is just so people aren't side-tracked when debugging I2C issues on Rockchip by checking all writes are proper. Fixes: 3437469985df ("rockchip: Add I2C driver") Signed-off-by: Quentin Schulz Reviewed-by: Heiko Schocher Reviewed-by: Kever Yang --- drivers/i2c/rk_i2c.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i2c/rk_i2c.c b/drivers/i2c/rk_i2c.c index fa167268ae7..fe09e75d3fb 100644 --- a/drivers/i2c/rk_i2c.c +++ b/drivers/i2c/rk_i2c.c @@ -137,7 +137,7 @@ static int rk_i2c_send_stop_bit(struct rk_i2c *i2c) writel(I2C_IPD_ALL_CLEAN, ®s->ipd); writel(I2C_CON_EN | I2C_CON_STOP, ®s->con); - writel(I2C_CON_STOP, ®s->ien); + writel(I2C_STOPIEN, ®s->ien); start = get_timer(0); while (1) { From 1cf8d0b68d6d853a2727bbb0a785fc7d93304ca4 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Fri, 7 Nov 2025 12:39:18 +0100 Subject: [PATCH 22/40] rockchip: i2c: move ACK comment where it applies The I2C_CON_LASTACK is kind of a misnomer as setting it means sending a NACK as last byte acknowledge when the controller is in receive mode. It should therefore be used only when there's no more data to transfer after this. Move the comment in the proper if block. Sync the comment with the Linux kernel's while at it so it's more explicit. Fixes: 5deaa530280f ("rockchip: i2c: fix >32 byte reads") Signed-off-by: Quentin Schulz Reviewed-by: Heiko Schocher Reviewed-by: Kever Yang --- drivers/i2c/rk_i2c.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/i2c/rk_i2c.c b/drivers/i2c/rk_i2c.c index fe09e75d3fb..3c44d0e65f5 100644 --- a/drivers/i2c/rk_i2c.c +++ b/drivers/i2c/rk_i2c.c @@ -195,13 +195,14 @@ static int rk_i2c_read(struct rk_i2c *i2c, uchar chip, uint reg, uint r_len, while (bytes_remain_len) { if (bytes_remain_len > RK_I2C_FIFO_SIZE) { + /* + * The hw can read up to 32 bytes at a time. If we need + * more than one chunk, send an ACK after the last byte + * of the current chunk. + */ con = I2C_CON_EN; bytes_xferred = 32; } else { - /* - * The hw can read up to 32 bytes at a time. If we need - * more than one chunk, send an ACK after the last byte. - */ con = I2C_CON_EN | I2C_CON_LASTACK; bytes_xferred = bytes_remain_len; } From 0e5e98081943586b20a45f711bf3f4801191e762 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Fri, 7 Nov 2025 12:39:19 +0100 Subject: [PATCH 23/40] rockchip: i2c: fix illegal I2C START/STOP condition In the last message sent in rockchip_i2c_xfer, the controller is disabled (see rk_i2c_disable() in rk_i2c_read()/rk_i2c_write()), then the STOP condition is sent (see rk_i2c_send_stop_bit() in rockchip_i2c_xfer()) and the controller is disabled once again (see rk_i2c_disable() right after). The issue is that re-enabling the controller just to send the STOP condition doesn't work. When, the controller is disabled, the SCL and SDA lanes are not driven anymore and thus enter the idle mode where they are kept high by the external HW pull-up. To send a STOP condition, one needs to drive the SDA line so that a rising edge happens while SCL is high. Experimentally (on PX30 and RK3399), when enabling the controller to send a STOP condition after it's been disabled, the controller only drives the SDA line to trigger the rising edge for the STOP condition, leaving SCL undriven (and thus, high). This means, that because SDA is high before this happens and that we need a rising edge, the controller drives the SDA line low and then releases it, meaning we trigger a START condition followed by a STOP condition: SCL _________ _____... __ _____ _____... \/ SDA ^ STOP ^ START This is illegal in I2C protocol[1]: 5. A START condition immediately followed by a STOP condition (void message) is an illegal format. Many devices however are designed to operate properly under this condition. My guess is that the I2C controller IP knows that it makes only sense to send a STOP condition after a START condition, meaning the controller is already driving the SCL line low and neither the device nor controller drive the SDA line after the last ACK/NACK as there's no need to, then it needs to drive SDA, release SCL to make it high and then release the SDA line. However, after it's been disabled, the SCL is already released so the controller only essentially drives SDA and then releases it. It happens that this seems to be breaking the SE050 Secure Element after a few transfers in the middle of a transfer where it starts clock stretching the bus forever. It may be related to Errata 3.2[2] but the description of the setup isn't an exact match to the current situation. It seems to be required to disable the I2C controller between messages as the Linux kernel states that "The HW is actually not capable of REPEATED START. But we can get the intended effect by resetting its internal state and issuing an ordinary START.". Between messages, this logic seems fine as I get an Sr (repeated START condition) before starting the next message in the transfer without a STOP condition. However, we should NOT disable the controller after the last message in the transfer otherwise we do this illegal START condition followed by the STOP condition, hence the added check. [1] https://www.nxp.com/docs/en/user-guide/UM10204.pdf 3.1.10 The target address and R/W bit point 5 [2] https://www.nxp.com/docs/en/errata/SE050_Erratasheet.pdf Fixes: c9fca5ec8849 ("rockchip: i2c: don't sent stop bit after each message") Signed-off-by: Quentin Schulz Reviewed-by: Heiko Schocher Reviewed-by: Kever Yang --- drivers/i2c/rk_i2c.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/drivers/i2c/rk_i2c.c b/drivers/i2c/rk_i2c.c index 3c44d0e65f5..def07018148 100644 --- a/drivers/i2c/rk_i2c.c +++ b/drivers/i2c/rk_i2c.c @@ -255,8 +255,6 @@ static int rk_i2c_read(struct rk_i2c *i2c, uchar chip, uint reg, uint r_len, } i2c_exit: - rk_i2c_disable(i2c); - return err; } @@ -333,8 +331,6 @@ static int rk_i2c_write(struct rk_i2c *i2c, uchar chip, uint reg, uint r_len, } i2c_exit: - rk_i2c_disable(i2c); - return err; } @@ -359,6 +355,18 @@ static int rockchip_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, ret = -EREMOTEIO; break; } + + /* + * The HW is actually not capable of REPEATED START. But we can + * get the intended effect by resetting its internal state + * and issuing an ordinary START. + * + * Do NOT disable the controller after the last message (before + * sending the STOP condition) as this triggers an illegal + * START condition followed by a STOP condition. + */ + if (nmsgs > 1) + rk_i2c_disable(i2c); } rk_i2c_send_stop_bit(i2c); From 0ed7abc85d1664a3d7432795a7126ff6a1d01147 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Wed, 12 Nov 2025 15:58:00 +0100 Subject: [PATCH 24/40] rockchip: mkimage: enhance comments for v1 header Improve the image header documentation for v1 header: - specify this applies to all MMC, not only SD cards, - specify the offset for SPI flashes, - specify the key used for RC4 encoding, - specify what "init" refers to, especially since some configs enable TPL, - specify what "init_boot_size" refers to, especially since some configs enable TPL, - specify the size of a block, - add documentation for init_size and init_boot_size, Note that the offset on the storage medium isn't necessarily 32KiB (64 blocks) for MMC or 0 for SPI flashes, it's just the first offset the BootROM checks. Barebox[1] lists a few options, though those are applicable to RK35xx which use the v2 header, so not guaranteed they can be shared. On RK3399, the binary can at least be stored at offset 0 and 32KiB on SPI flashes. [1] https://git.pengutronix.de/cgit/barebox/tree/arch/arm/mach-rockchip/bbu.c#n19 Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang --- tools/rkcommon.c | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/tools/rkcommon.c b/tools/rkcommon.c index d191ea72c63..e7e78ef7e5b 100644 --- a/tools/rkcommon.c +++ b/tools/rkcommon.c @@ -76,13 +76,29 @@ struct header0_info_v2 { /** * struct header0_info - header block for boot ROM * - * This is stored at SD card block 64 (where each block is 512 bytes, or at - * the start of SPI flash. It is encoded with RC4. + * This is stored at MMC block 64 (where each block is 512 bytes), or at + * the start of SPI flash. It is encoded with RC4 with the below rc4_key. + * + * In Rockchip terminology: + * + * "init" means the stage that is loaded into SRAM. TPL if there is one, SPL + * otherwise. + * + * "boot" means the next stages after "init" stage that are loaded by the + * BootROM into DRAM. Only applicable if "init" stage returns to BootROM (via + * the appropriate ROCKCHIP_BACK_TO_BROM symbol, BOOT_DEVICE_BOOTROM is used as + * boot device for the next stage and the "init" stage successfully booted) and + * if "init_boot_size" > "init_size". + * Basically, it is the content of "init" plus the SPL or even U-Boot proper if + * relevant. * * @magic: Magic (must be RK_MAGIC) * @disable_rc4: 0 to use rc4 for boot image, 1 to use plain binary - * @init_offset: Offset in blocks of the SPL code from this header - * block. E.g. 4 means 2KB after the start of this header. + * @init_offset: Offset in 512-byte blocks of the "init" code from the + * start of this header. For instance, 4 means 2KiB. + * @init_size: Size (in blocks) of the "init" code. + * @init_boot_size: Size (in blocks) of the "init" and "boot" code combined. + * * Other fields are not used by U-Boot */ struct header0_info { From 798bef8e8322101a6add9a5797f6dfc748f44ed6 Mon Sep 17 00:00:00 2001 From: Max Merchel Date: Tue, 26 Aug 2025 08:30:29 +0200 Subject: [PATCH 25/40] tools/libfdt/fdt_rw: fix SPDX-License-Identifier Currently, the terms of both licenses (GPL 2.0 and BSD-2-Clause) must be met. However, before switching to the SPDX license identifier, the license information in the file begins with: "libfdt is dual licensed: you can use it either under the terms of the GPL, or the BSD license, at your option." Therefore, the missing "OR" between the licenses is added. Fixes: 3508476 ("libfdt: SPDX-License-Identifier: GPL-2.0+ BSD-2-Clause") Signed-off-by: Max Merchel --- tools/libfdt/fdt_rw.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/libfdt/fdt_rw.c b/tools/libfdt/fdt_rw.c index 7189f014295..3d3395b125b 100644 --- a/tools/libfdt/fdt_rw.c +++ b/tools/libfdt/fdt_rw.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0+ BSD-2-Clause */ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) #include "fdt_host.h" #include "../../scripts/dtc/libfdt/fdt_rw.c" From 9d08916a575beba3632c3969b96f74be08560ef7 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Thu, 11 Dec 2025 15:05:27 -0600 Subject: [PATCH 26/40] clk: mediatek: remove duplicate '@parent' field doc Remove duplicate '@parent' field documentation in struct mtk_composite. There is no need to say the same thing twice. Also fix spelling mistake in the word "parent" while we're at it. Signed-off-by: David Lechner --- drivers/clk/mediatek/clk-mtk.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index 4ef1341aea6..89479001ba8 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -133,8 +133,7 @@ struct mtk_parent { * struct mtk_composite - aggregate clock of mux, divider and gate clocks * * @id: index of clocks - * @parent: index of parnet clocks - * @parent: index of parnet clocks + * @parent: index of parent clocks * @parent_flags: table of parent clocks with flags * @mux_reg: hardware-specific mux register * @gate_reg: hardware-specific gate register From 47b50fb1125c539d80ed3e7f739c02c6486e1b52 Mon Sep 17 00:00:00 2001 From: Jonathan GUILLOT Date: Thu, 11 Dec 2025 22:20:39 +0100 Subject: [PATCH 27/40] cmd: part: Fix part argument description for `part number` Signed-off-by: Jonathan GUILLOT Fixes: ff6ef4b9093f ("doc: man-page for the part command") Reviewed-by: Quentin Schulz --- doc/usage/cmd/part.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/usage/cmd/part.rst b/doc/usage/cmd/part.rst index 72f5d8b8de7..bd3df15203a 100644 --- a/doc/usage/cmd/part.rst +++ b/doc/usage/cmd/part.rst @@ -82,7 +82,7 @@ part must be specified as partition name. dev device number part - partition number + partition name varname a variable to store the current partition number value into From 85a3ee15e0363fafe221de4c57cb62e59f920914 Mon Sep 17 00:00:00 2001 From: Alif Zakuan Yuslaimi Date: Mon, 1 Dec 2025 21:36:26 -0800 Subject: [PATCH 28/40] configs: cyclone5: Enable random MAC address Enable CONFIG_NET_RANDOM_ETHADDR to allow U-Boot to assign a random MAC address during Ethernet initialization when a valid MAC is not programmed in hardware. This avoids network initialization failures and MAC address conflicts, especially on boards used for development or shipped without a factory-programmed MAC. Signed-off-by: Tien Fong Chee Signed-off-by: Alif Zakuan Yuslaimi Reviewed-by: Tien Fong Chee --- configs/socfpga_cyclone5_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig index 992abdbfdc4..2256eb2ecb8 100644 --- a/configs/socfpga_cyclone5_defconfig +++ b/configs/socfpga_cyclone5_defconfig @@ -67,6 +67,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y +CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPI=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y From 029e6f250cd5caa166f37c5bbb3d00af2cff9baf Mon Sep 17 00:00:00 2001 From: Tanmay Kathpalia Date: Mon, 15 Dec 2025 03:01:14 -0800 Subject: [PATCH 29/40] Revert "arch: arm: dts: agilex5: Set SDIO_SEL GPIO pin as output" Remove GPIO hog configuration for SDIO_SEL pin as it is now handled through the voltage regulator framework for SD ultra high speed mode support. The GPIO pin 3 on portb controller is used to control the level shifter for SD card I/O voltage switching. The regulator-based approach provides proper voltage switching control for UHS-I modes (SDR50, SDR104) while maintaining compatibility with the MMC subsystem's voltage switching protocols. This reverts commit b0dbc9fcb7dfb7522be25ee205997be2fb5e1bdc. Signed-off-by: Tanmay Kathpalia Reviewed-by: Tien Fong Chee --- arch/arm/dts/socfpga_agilex5-u-boot.dtsi | 11 ----------- configs/socfpga_agilex5_defconfig | 3 --- 2 files changed, 14 deletions(-) diff --git a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi index d51a9e2ff7f..35b198b79ef 100644 --- a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi @@ -681,17 +681,6 @@ bootph-all; }; -&gpio1 { - /* Configure GPIO 1 pin 3 as output pin with value 0 during GPIO probe */ - portb: gpio-controller@0{ - sdio_sel { - gpio-hog; - gpios = <3 GPIO_ACTIVE_HIGH>; - output-low; - }; - }; -}; - &i2c0 { reset-names = "i2c"; }; diff --git a/configs/socfpga_agilex5_defconfig b/configs/socfpga_agilex5_defconfig index 64f2f1bf115..799ea910f03 100644 --- a/configs/socfpga_agilex5_defconfig +++ b/configs/socfpga_agilex5_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_SPL_SYS_DCACHE_OFF=y CONFIG_ARCH_SOCFPGA=y CONFIG_TEXT_BASE=0x80200000 -CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=3 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80300000 @@ -79,8 +78,6 @@ CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_ALTERA_SDRAM=y -CONFIG_GPIO_HOG=y -CONFIG_SPL_GPIO_HOG=y CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y From eb367367301ceee26bf94a7a134a894a1a6cd775 Mon Sep 17 00:00:00 2001 From: Tanmay Kathpalia Date: Mon, 15 Dec 2025 03:01:15 -0800 Subject: [PATCH 30/40] arm: dts: socfpga: agilex5: Upgrade SDHCI controller from SD4HC to SD6HC Upgrade the SDHCI Cadence controller from SD4HC to SD6HC for Agilex5 platform to support the newer controller version with enhanced features. Key changes: - Remove combophy0 node and associated references as SD6HC doesn't require separate PHY configuration node - Upgrade MMC controller compatible from "cdns,sd4hc" to "cdns,sd6hc" - Add Agilex5-specific compatible string "altr,agilex5-sd6hc" for platform-specific optimizations Hardware configuration updates: - Add voltage regulator support: * sd_emmc_power: Fixed 3.3V regulator for card power supply * sd_io_1v8_reg: GPIO-controlled regulator for 1.8V/3.3V I/O switching - Configure proper reset control with named resets including combophy reset - Add GPIO control via portb pin 3 for voltage switching SD card operation: - Configure for SD card specific operation (no-mmc, cap-sd-highspeed) - Set maximum frequency to 200MHz - Configure timing parameters for SD modes: * Default Speed (DS) and UHS-I SDR12 mode timing: * High Speed and UHS-I SDR25 mode timing: - Add PHY timing delays for optimal signal integrity Signed-off-by: Tanmay Kathpalia Reviewed-by: Tien Fong Chee --- arch/arm/dts/socfpga_agilex5-u-boot.dtsi | 3 +- arch/arm/dts/socfpga_agilex5.dtsi | 29 ++++--- .../arm/dts/socfpga_agilex5_socdk-u-boot.dtsi | 79 +++++++++---------- drivers/mmc/sdhci-cadence.c | 1 + 4 files changed, 55 insertions(+), 57 deletions(-) diff --git a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi index 35b198b79ef..0f0f457de54 100644 --- a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi @@ -698,7 +698,8 @@ }; &mmc { - resets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>; + resets = <&rst COMBOPHY_RESET>, <&rst SDMMC_OCP_RESET>, <&rst SDMMC_RESET>; + reset-names = "combophy", "sdmmc-ocp", "sdhc-reset"; }; &porta { diff --git a/arch/arm/dts/socfpga_agilex5.dtsi b/arch/arm/dts/socfpga_agilex5.dtsi index 7f4266dd5f1..769678af31a 100644 --- a/arch/arm/dts/socfpga_agilex5.dtsi +++ b/arch/arm/dts/socfpga_agilex5.dtsi @@ -303,30 +303,33 @@ status = "disabled"; }; - combophy0: combophy@0 { - #phy-cells = <0>; - phy-type = <1>; - compatible = "cdns,combophy"; - reg = <0x10808000 0x1000>; - resets = <&rst COMBOPHY_RESET>; - reset-names = "reset"; - status = "disabled"; + sd_emmc_power: regulator-fixed-3p3v { + compatible = "regulator-fixed"; + regulator-name = "card-power"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sd_io_1v8_reg: regulator-1p8v { + compatible = "regulator-gpio"; + regulator-name = "sd-bus-io-power"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + states = <1800000 0x1>, + <3300000 0x0>; }; mmc: mmc0@10808000 { #address-cells = <1>; #size-cells = <0>; - compatible = "cdns,sd4hc"; + compatible = "altr,agilex5-sd6hc", "cdns,sd6hc"; reg = <0x10808000 0x1000>; interrupts = <0 96 4>; - phys = <&combophy0>; - phy-names = "combo-phy"; clocks = <&clkmgr AGILEX5_L4_MP_CLK>, <&clkmgr AGILEX5_SDMMC_CLK>; clock-names = "biu", "ciu"; fifo-depth = <0x800>; - resets = <&rst SDMMC_RESET>; - reset-names = "reset"; iommus = <&smmu 5>; status = "disabled"; }; diff --git a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi index 938ddb04c04..5a7aa5841e3 100644 --- a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi @@ -91,53 +91,46 @@ bootph-all; }; -&mmc { - status = "okay"; - bus-width = <4>; - sd-uhs-sdr50; - cap-mmc-highspeed; +&gpio1 { + portb: gpio-controller@0 { + bootph-all; + }; +}; + +&sd_emmc_power { bootph-all; }; -&combophy0 { - status = "okay"; +&sd_io_1v8_reg { + gpios = <&portb 3 GPIO_ACTIVE_HIGH>; + bootph-all; +}; + +&mmc { + status = "okay"; + + no-mmc; + no-1-8-v; + disable-wp; + cap-sd-highspeed; + vmmc-supply = <&sd_emmc_power>; + vqmmc-supply = <&sd_io_1v8_reg>; + max-frequency = <200000000>; + + /* SD card default speed (DS) and UHS-I SDR12 mode timing configuration */ + cdns,phy-dqs-timing-delay-sd-ds = <0x00780000>; + cdns,phy-gate-lpbk_ctrl-delay-sd-ds = <0x81a40040>; + cdns,phy-dll-slave-ctrl-sd-ds = <0x00a000fe>; + cdns,phy-dq-timing-delay-sd-ds = <0x28000001>; + + /* SD card high speed and UHS-I SDR25 mode timing configuration */ + cdns,phy-dqs-timing-delay-sd-hs = <0x780001>; + cdns,phy-gate-lpbk_ctrl-delay-sd-hs = <0x81a40040>; + cdns,phy-dq-timing-delay-sd-hs = <0x10000001>; + cdns,ctrl-hrs16-slave-ctrl-sd-hs = <0x101>; + cdns,ctrl-hrs07-timing-delay-sd-hs = <0xA0001>; + bootph-all; - cdns,phy-use-ext-lpbk-dqs = <1>; - cdns,phy-use-lpbk-dqs = <1>; - cdns,phy-use-phony-dqs = <1>; - cdns,phy-use-phony-dqs-cmd = <1>; - cdns,phy-io-mask-always-on = <0>; - cdns,phy-io-mask-end = <5>; - cdns,phy-io-mask-start = <0>; - cdns,phy-data-select-oe-end = <1>; - cdns,phy-sync-method = <1>; - cdns,phy-sw-half-cycle-shift = <0>; - cdns,phy-rd-del-sel = <52>; - cdns,phy-underrun-suppress = <1>; - cdns,phy-gate-cfg-always-on = <1>; - cdns,phy-param-dll-bypass-mode = <1>; - cdns,phy-param-phase-detect-sel = <2>; - cdns,phy-param-dll-start-point = <254>; - cdns,phy-read-dqs-cmd-delay = <0>; - cdns,phy-clk-wrdqs-delay = <0>; - cdns,phy-clk-wr-delay = <0>; - cdns,phy-read-dqs-delay = <0>; - cdns,phy-phony-dqs-timing = <0>; - cdns,hrs09-rddata-en = <1>; - cdns,hrs09-rdcmd-en = <1>; - cdns,hrs09-extended-wr-mode = <1>; - cdns,hrs09-extended-rd-mode = <1>; - cdns,hrs10-hcsdclkadj = <3>; - cdns,hrs16-wrdata1-sdclk-dly = <0>; - cdns,hrs16-wrdata0-sdclk-dly = <0>; - cdns,hrs16-wrcmd1-sdclk-dly = <0>; - cdns,hrs16-wrcmd0-sdclk-dly = <0>; - cdns,hrs16-wrdata1-dly = <0>; - cdns,hrs16-wrdata0-dly = <0>; - cdns,hrs16-wrcmd1-dly = <0>; - cdns,hrs16-wrcmd0-dly = <0>; - cdns,hrs07-rw-compensate = <10>; - cdns,hrs07-idelay-val = <0>; }; &qspi { diff --git a/drivers/mmc/sdhci-cadence.c b/drivers/mmc/sdhci-cadence.c index 7d169efa476..6cdb7f95cc5 100644 --- a/drivers/mmc/sdhci-cadence.c +++ b/drivers/mmc/sdhci-cadence.c @@ -260,6 +260,7 @@ static int sdhci_cdns_probe(struct udevice *dev) static const struct udevice_id sdhci_cdns_match[] = { { .compatible = "socionext,uniphier-sd4hc" }, { .compatible = "cdns,sd4hc" }, + { .compatible = "altr,agilex5-sd6hc" }, { .compatible = "cdns,sd6hc" }, { /* sentinel */ } }; From 77387f05c0670c52174c6b7609dd005832ada28e Mon Sep 17 00:00:00 2001 From: Tanmay Kathpalia Date: Mon, 15 Dec 2025 03:01:16 -0800 Subject: [PATCH 31/40] configs: socfpga_agilex5: Enable MMC and Cadence SDHCI support Enable MMC support with Cadence SDHCI controller for both SPL and U-Boot proper on Agilex5 platform to support SD card operations in legacy and high speed timing modes. MMC controller configuration: - Enable MMC subsystem (CONFIG_MMC=y, CONFIG_DM_MMC=y) - Add Cadence SDHCI controller support (CONFIG_MMC_SDHCI_CADENCE=y) - Enable SDHCI with ADMA support for better performance - Add MMC command support for user interaction SPL configuration: - Enable MMC support in SPL (CONFIG_SPL_DM_MMC=y) - Add SDHCI ADMA support in SPL (CONFIG_SPL_MMC_SDHCI_ADMA=y) - Enable GPIO support in SPL (CONFIG_SPL_DWAPB_GPIO=y) Voltage regulator support: - Add device model regulator framework (CONFIG_DM_REGULATOR=y) - Enable fixed voltage regulator support for card power - Add GPIO-controlled regulator for I/O voltage switching - Include regulator support in SPL for early initialization These changes enable SD card functionality with legacy and high speed timing modes, providing proper voltage regulation and GPIO control for the Agilex5 SoCDK platform. Signed-off-by: Tanmay Kathpalia Reviewed-by: Tien Fong Chee --- configs/socfpga_agilex5_defconfig | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/configs/socfpga_agilex5_defconfig b/configs/socfpga_agilex5_defconfig index 799ea910f03..3eabc372269 100644 --- a/configs/socfpga_agilex5_defconfig +++ b/configs/socfpga_agilex5_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_SPL_SYS_DCACHE_OFF=y CONFIG_ARCH_SOCFPGA=y CONFIG_TEXT_BASE=0x80200000 +CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=3 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80300000 @@ -66,6 +67,7 @@ CONFIG_CMD_WDT=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIMER=y CONFIG_CMD_UBI=y +CONFIG_CMD_MMC=y # CONFIG_ISO_PARTITION is not set # CONFIG_EFI_PARTITION is not set CONFIG_OF_LIST="" @@ -106,5 +108,22 @@ CONFIG_USB_DWC3=y CONFIG_USB_HUB_DEBOUNCE_TIMEOUT=3000 CONFIG_DESIGNWARE_WATCHDOG=y CONFIG_WDT=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DWAPB_GPIO=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_SPL_DM_REGULATOR_GPIO=y +CONFIG_SPL_MMC=y +CONFIG_SPL_DM_MMC=y +CONFIG_SPL_MMC_IO_VOLTAGE=y +CONFIG_SPL_MMC_SDHCI_ADMA=y +CONFIG_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_SDHCI_ADMA=y +CONFIG_MMC_SDHCI_CADENCE=y # CONFIG_SPL_USE_TINY_PRINTF is not set CONFIG_PANIC_HANG=y From ed7725c25e43cbb288cfc35080334db7728e358a Mon Sep 17 00:00:00 2001 From: Tanmay Kathpalia Date: Mon, 15 Dec 2025 03:01:17 -0800 Subject: [PATCH 32/40] arm: dts: socfpga: agilex5: Add dedicated eMMC device tree support Add dedicated device tree support for eMMC configuration on the Agilex5 SoCDK board, providing an alternative to the default SD card setup. Changes to socfpga_agilex5.dtsi: - - Configure always-on regulator for stable eMMC operation New device tree files: - socfpga_agilex5_socdk_emmc.dts: Main eMMC device tree configuration * Configure for eMMC operation (no-sd, no-sdio, non-removable) * Set 8-bit bus width and high speed capability * Add timing parameters for legacy and SDR modes * Configure voltage supplies for eMMC power and I/O * Add fixed 1.8V regulator for eMMC I/O voltage supply - socfpga_agilex5_socdk_emmc-u-boot.dtsi: U-Boot specific additions * Include common Agilex5 U-Boot configurations * Set SPL boot order with eMMC support * Enable necessary peripherals for boot-time operation Configuration files: - configs/socfpga_agilex5_emmc_defconfig: eMMC-specific configuration * Inherit from base Agilex5 configuration * Disable GPIO regulator support (not needed for fixed eMMC setup) * Set eMMC-specific device tree Build system integration: - Add socfpga_agilex5_socdk_emmc.dtb target to Makefile Signed-off-by: Tanmay Kathpalia Reviewed-by: Tien Fong Chee --- arch/arm/dts/Makefile | 1 + .../socfpga_agilex5_socdk_emmc-u-boot.dtsi | 172 ++++++++++++++++++ arch/arm/dts/socfpga_agilex5_socdk_emmc.dts | 49 +++++ configs/socfpga_agilex5_emmc_defconfig | 6 + 4 files changed, 228 insertions(+) create mode 100644 arch/arm/dts/socfpga_agilex5_socdk_emmc-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_agilex5_socdk_emmc.dts create mode 100644 configs/socfpga_agilex5_emmc_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index fcad6fb2fc7..4e39c795e1e 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -451,6 +451,7 @@ dtb-$(CONFIG_TARGET_THUNDERX_88XX) += thunderx-88xx.dtb dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_agilex5_socdk.dtb \ + socfpga_agilex5_socdk_emmc.dtb \ socfpga_arria5_secu1.dtb \ socfpga_arria5_socdk.dtb \ socfpga_arria10_chameleonv3_270_2.dtb \ diff --git a/arch/arm/dts/socfpga_agilex5_socdk_emmc-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5_socdk_emmc-u-boot.dtsi new file mode 100644 index 00000000000..3c03b00c0d9 --- /dev/null +++ b/arch/arm/dts/socfpga_agilex5_socdk_emmc-u-boot.dtsi @@ -0,0 +1,172 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot additions for Agilex5 SocDK eMMC + * + * Copyright (C) 2025 Altera Corporation + */ + +#include "socfpga_agilex5-u-boot.dtsi" + +/{ + aliases { + spi0 = &qspi; + freeze_br0 = &freeze_controller; + }; + + soc { + freeze_controller: freeze_controller@0x20000450 { + compatible = "altr,freeze-bridge-controller"; + reg = <0x20000450 0x00000010>; + status = "disabled"; + }; + }; + + /* + * Both Memory base address and size default info is retrieved from HW setting. + * Reconfiguration / Overwrite these info can be done with examples below. + * + * When LPDDR ECC is enabled, the last 1/8 of the memory region must + * be reserved for the Inline ECC buffer. + * + * Example for memory size with 2GB: + * memory { + * reg = <0x0 0x80000000 0x0 0x80000000>; + * }; + * + * Example for memory size with 8GB: + * memory { + * reg = <0x0 0x80000000 0x0 0x80000000>, + * <0x8 0x80000000 0x1 0x80000000>; + * }; + * + * Example for memory size with 32GB: + * memory { + * reg = <0x0 0x80000000 0x0 0x80000000>, + * <0x8 0x80000000 0x7 0x80000000>; + * }; + * + * Example for memory size with 512GB: + * memory { + * reg = <0x0 0x80000000 0x0 0x80000000>, + * <0x8 0x80000000 0x7 0x80000000>, + * <0x88 0x00000000 0x78 0x00000000>; + * }; + * + * Example for memory size with 2GB with LPDDR Inline ECC ON: + * memory { + * reg = <0x0 0x80000000 0x0 0x70000000>; + * }; + * + * Example for memory size with 8GB with LPDDR Inline ECC ON: + * memory { + * reg = <0x0 0x80000000 0x0 0x80000000>, + * <0x8 0x80000000 0x1 0x40000000>; + * }; + */ + + chosen { + stdout-path = "serial0:115200n8"; + u-boot,spl-boot-order = &mmc,&flash0,&nand,"/memory"; + }; +}; + +&flash0 { + compatible = "jedec,spi-nor"; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + bootph-all; + /delete-property/ cdns,read-delay; +}; + +&flash1 { + bootph-all; +}; + +&i3c0 { + bootph-all; +}; + +&i3c1 { + bootph-all; +}; + +&gpio1 { + portb: gpio-controller@0 { + bootph-all; + }; +}; + +&sd_emmc_power { + bootph-all; +}; + +&emmc_io_1v8_reg { + bootph-all; +}; + +&mmc { + bootph-all; +}; + +&qspi { + status = "okay"; +}; + +&nand { + status = "disabled"; + bootph-all; +}; + +&timer0 { + bootph-all; +}; + +&timer1 { + bootph-all; +}; + +&timer2 { + bootph-all; +}; + +&timer3 { + bootph-all; +}; + +&watchdog0 { + bootph-all; +}; + +&gmac0 { + status = "okay"; + phy-mode = "rgmii"; + phy-handle = <&emac0_phy0>; + + max-frame-size = <9000>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwxgmac-mdio"; + emac0_phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + +&gmac2 { + status = "okay"; + phy-mode = "rgmii"; + phy-handle = <&emac2_phy0>; + + max-frame-size = <9000>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwxgmac-mdio"; + emac2_phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; diff --git a/arch/arm/dts/socfpga_agilex5_socdk_emmc.dts b/arch/arm/dts/socfpga_agilex5_socdk_emmc.dts new file mode 100644 index 00000000000..f6848c373cd --- /dev/null +++ b/arch/arm/dts/socfpga_agilex5_socdk_emmc.dts @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 Altera Corporation + */ + +#include "socfpga_agilex5_socdk.dts" + +/ { + soc { + emmc_io_1v8_reg: regulator-fixed-1p8v { + compatible = "regulator-fixed"; + regulator-name = "emmc-io-power"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + }; +}; + +&mmc { + status = "okay"; + + no-sd; + no-sdio; + disable-wp; + non-removable; + cap-mmc-highspeed; + + bus-width = <8>; + vmmc-supply = <&sd_emmc_power>; + vqmmc-supply = <&emmc_io_1v8_reg>; + max-frequency = <200000000>; + + /* eMMC legacy mode timing configuration */ + cdns,phy-dqs-timing-delay-sd-ds = <0x00780000>; + cdns,phy-gate-lpbk-ctrl-delay-sd-ds = <0x81a40040>; + cdns,phy-dll-slave-ctrl-sd-ds = <0x00a000fe>; + cdns,phy-dq-timing-delay-sd-ds = <0x28000001>; + + /* eMMC SDR mode timing configuration */ + cdns,phy-dqs-timing-delay-emmc-sdr = <0x780001>; + cdns,phy-gate-lpbk-ctrl-delay-emmc-sdr = <0x81a40040>; + cdns,phy-dll-slave-ctrl-emmc-sdr = <0x00000000>; + cdns,phy-dq-timing-delay-emmc-sdr = <0x10000001>; + cdns,ctrl-hrs09-timing-delay-emmc-sdr = <0x1800c>; + cdns,ctrl-hrs10-lpbk-ctrl-delay-emmc-sdr = <0x30000>; + cdns,ctrl-hrs16-slave-ctrl-emmc-sdr = <0x101>; + cdns,ctrl-hrs07-timing-delay-emmc-sdr = <0xA0001>; +}; diff --git a/configs/socfpga_agilex5_emmc_defconfig b/configs/socfpga_agilex5_emmc_defconfig new file mode 100644 index 00000000000..9254ab92e0c --- /dev/null +++ b/configs/socfpga_agilex5_emmc_defconfig @@ -0,0 +1,6 @@ +#include + +CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex5_socdk_emmc" +# CONFIG_SPL_DM_REGULATOR_GPIO is not set +# CONFIG_DM_REGULATOR_GPIO is not set +# CONFIG_SPL_DWAPB_GPIO is not set From 26eb2cda3995b6ce1553e6c1df93afa146e08c2f Mon Sep 17 00:00:00 2001 From: Alif Zakuan Yuslaimi Date: Wed, 3 Dec 2025 18:08:10 -0800 Subject: [PATCH 33/40] configs: arria10: Disable mkeficapsule tool build mkeficapsule tool will be built by default if EFI_LOADER is set due to commit b7a625b1ce49 ("tools: Build mkeficapsule tool by default if EFI_LOADER is set"). This will cause compilation error on all our SoCFPGA devices, hence we will be disabling this config as we do not utilize this tool. Signed-off-by: Alif Zakuan Yuslaimi Reviewed-by: Tien Fong Chee --- configs/socfpga_arria10_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig index 76fdc0aa4a6..b32f40ae408 100644 --- a/configs/socfpga_arria10_defconfig +++ b/configs/socfpga_arria10_defconfig @@ -68,3 +68,4 @@ CONFIG_DESIGNWARE_APB_TIMER=y CONFIG_USB=y CONFIG_USB_DWC2=y # CONFIG_SPL_WDT is not set +# CONFIG_TOOLS_MKEFICAPSULE is not set From 136d750c2ed00e11d1acf571fe59f7f4d389f826 Mon Sep 17 00:00:00 2001 From: Ralph Siemsen Date: Thu, 11 Dec 2025 11:05:23 -0500 Subject: [PATCH 34/40] spi: designware: Allow disabling designware driver in SPL To reduce SPL size, make it possible to exclude designware driver, while keeping it enabled in the main u-boot. Signed-off-by: Ralph Siemsen Reviewed-by: Sean Anderson --- drivers/spi/Kconfig | 8 ++++++++ drivers/spi/Makefile | 2 +- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 2afb15fff1e..e31db9d4e31 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -677,6 +677,14 @@ config SH_QSPI Enable the Renesas Quad SPI controller driver. This driver can be used on Renesas SoCs. +config SPL_DESIGNWARE_SPI + bool "Designware SPI driver in SPL" + depends on SPL_DM_SPI + default y if DESIGNWARE_SPI + help + Enable the Designware SPI driver during SPL. + See the help of DESIGNWARE_SPI for details. + config MXC_SPI bool "MXC SPI Driver" depends on MACH_IMX diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index d5d1e543588..0dc2d23e172 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -35,7 +35,7 @@ obj-$(CONFIG_CF_SPI) += cf_spi.o obj-$(CONFIG_CORTINA_SFLASH) += ca_sflash.o obj-$(CONFIG_CV1800B_SPIF) += cv1800b_spif.o obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o -obj-$(CONFIG_DESIGNWARE_SPI) += designware_spi.o +obj-$(CONFIG_$(PHASE_)DESIGNWARE_SPI) += designware_spi.o obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o obj-$(CONFIG_FSL_DSPI) += fsl_dspi.o obj-$(CONFIG_FSL_ESPI) += fsl_espi.o From a47b1e165e69418ef66fe74b32b2df170fe68907 Mon Sep 17 00:00:00 2001 From: Jan Kiszka Date: Thu, 11 Dec 2025 17:34:55 +0100 Subject: [PATCH 35/40] spl: Kconfig: Add missing SPL_LOAD_BLOCK for SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE We need to explicitly select SPL_LOAD_BLOCK when USE_PARTITION_TYPE is enabled, just like the other choices do. Fixes: 2a00d73d081a ("spl: mmc: Try to clean up raw-mode options") Signed-off-by: Jan Kiszka Reviewed-by: Tien Fong Chee --- common/spl/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 3b7b6cafef8..142cdb34cd5 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -573,6 +573,7 @@ config SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION config SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE bool "MMC raw mode: by partition type" + select SPL_LOAD_BLOCK depends on DOS_PARTITION help Use partition type for specifying U-Boot partition on MMC/SD in From 94d0c1d3edb4a71b49c1ff85f5f3990c727bcaba Mon Sep 17 00:00:00 2001 From: Jan Kiszka Date: Thu, 11 Dec 2025 17:34:56 +0100 Subject: [PATCH 36/40] spl: mmc: Account for SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE being a choice Add SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE as condition where so far SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION was enough - though often by chance as both options were enabled. Reorder the #ifdef blocks at this chance to follow the order in the Kconfig menu. Fixes: 2a00d73d081a ("spl: mmc: Try to clean up raw-mode options") Signed-off-by: Jan Kiszka Reviewed-by: Tien Fong Chee --- common/spl/spl_mmc.c | 17 +++++++++-------- include/part.h | 3 ++- 2 files changed, 11 insertions(+), 9 deletions(-) diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c index d8ce3a84614..1942e417075 100644 --- a/common/spl/spl_mmc.c +++ b/common/spl/spl_mmc.c @@ -106,7 +106,8 @@ static int spl_mmc_find_device(struct mmc **mmcp, int mmc_dev) return 0; } -#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION +#if defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION) || \ + defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE) static int mmc_load_image_raw_partition(struct spl_image_info *spl_image, struct spl_boot_device *bootdev, struct mmc *mmc, int partition, @@ -419,19 +420,19 @@ int spl_mmc_load(struct spl_image_info *spl_image, raw_sect = spl_mmc_get_uboot_raw_sector(mmc, raw_sect); -#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION - ret = mmc_load_image_raw_partition(spl_image, bootdev, - mmc, raw_part, - raw_sect); - if (!ret) - return 0; -#endif #ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR ret = mmc_load_image_raw_sector(spl_image, bootdev, mmc, raw_sect + spl_mmc_raw_uboot_offset(part)); if (!ret) return 0; +#elif defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION) || \ + defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE) + ret = mmc_load_image_raw_partition(spl_image, bootdev, + mmc, raw_part, + raw_sect); + if (!ret) + return 0; #endif /* If RAW mode fails, try FS mode. */ fallthrough; diff --git a/include/part.h b/include/part.h index 6caaa6526aa..ba4a63ddc75 100644 --- a/include/part.h +++ b/include/part.h @@ -461,7 +461,8 @@ ulong disk_blk_erase(struct udevice *dev, lbaint_t start, lbaint_t blkcnt); #ifdef CONFIG_XPL_BUILD # define part_print_ptr(x) NULL # if defined(CONFIG_SPL_FS_EXT4) || defined(CONFIG_SPL_FS_FAT) || \ - defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION) + defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION) || \ + defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE) # define part_get_info_ptr(x) x # else # define part_get_info_ptr(x) NULL From 62584916c9f7b029e8a43d7102189713b365d241 Mon Sep 17 00:00:00 2001 From: Jan Kiszka Date: Thu, 11 Dec 2025 17:34:57 +0100 Subject: [PATCH 37/40] spl: mmc: Respect sector value passed to mmc_load_image_raw_partition This function and the sector parameter evolved over the time. By now, sector is influenced by spl_mmc_get_uboot_raw_sector which allows to adjust the read sector with an offset that U-Boot proper may have inside the partition. That used to work by chance if both CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR and CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION were enabled. Since 2a00d73d081a they are a choice, and we need to drop the condition to maintain this feature. Signed-off-by: Jan Kiszka Reviewed-by: Tien Fong Chee --- common/spl/spl_mmc.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c index 1942e417075..47cfe4aef58 100644 --- a/common/spl/spl_mmc.c +++ b/common/spl/spl_mmc.c @@ -137,11 +137,7 @@ static int mmc_load_image_raw_partition(struct spl_image_info *spl_image, return ret; } -#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR return mmc_load_image_raw_sector(spl_image, bootdev, mmc, info.start + sector); -#else - return mmc_load_image_raw_sector(spl_image, bootdev, mmc, info.start); -#endif } #endif From 1cf1b504f412121aa5929d12beb3d7f6cf3ac50e Mon Sep 17 00:00:00 2001 From: Jan Kiszka Date: Thu, 11 Dec 2025 17:34:58 +0100 Subject: [PATCH 38/40] arch: arm: mach-socfpga: Adjust a raw sectors for MMC loading of U-Boot from SPL If U-Boot is located on MMC, SPL and U-Boot proper are glued together. More precisely, SPL is stored 4 times. Take this and its padding into account and adjust sector number via board_spl_mmc_get_uboot_raw_sector. This allows loading from a partition, without the need to hard-code the offset via SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR Signed-off-by: Jan Kiszka Reviewed-by: Tien Fong Chee --- arch/arm/mach-socfpga/board.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c index 28554b7a109..7f65aed4540 100644 --- a/arch/arm/mach-socfpga/board.c +++ b/arch/arm/mach-socfpga/board.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -209,3 +210,13 @@ void lmb_arch_add_memory(void) } } #endif + +#if (defined(CONFIG_TARGET_SOCFPGA_ARRIA10) || \ + defined(CONFIG_TARGET_SOCFPGA_GEN5)) && defined(CONFIG_XPL_BUILD) +unsigned long board_spl_mmc_get_uboot_raw_sector(struct mmc *mmc, + unsigned long raw_sect) +{ + /* offset of u-boot proper inside u-boot-with-spl.sfp image */ + return (CONFIG_SPL_PAD_TO * 4) / 512 + raw_sect; +} +#endif From 217eb9b119ce0097d5ca641a96780b258002076e Mon Sep 17 00:00:00 2001 From: Jan Kiszka Date: Thu, 11 Dec 2025 17:34:59 +0100 Subject: [PATCH 39/40] configs: socfpga: Fix de0_nano_soc boot By default, the de0_nano_soc used raw sectors, but the address became invalid due the raw-mode refactorings. With loading via partition type fixed, we can switch to that mode which is in line with what the ROM loader does. Fixes: 2a00d73d081a ("spl: mmc: Try to clean up raw-mode options") Signed-off-by: Jan Kiszka Reviewed-by: Tien Fong Chee --- configs/socfpga_de0_nano_soc_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig index 32cdf6d3a6c..6564cbd03c6 100644 --- a/configs/socfpga_de0_nano_soc_defconfig +++ b/configs/socfpga_de0_nano_soc_defconfig @@ -28,6 +28,7 @@ CONFIG_SPL_NO_BSS_LIMIT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_HAVE_INIT_STACK=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 CONFIG_SYS_MAXARGS=32 From 6f419247baa45917fcdd67062e271b8884d8c7aa Mon Sep 17 00:00:00 2001 From: Jan Kiszka Date: Thu, 11 Dec 2025 17:36:28 +0100 Subject: [PATCH 40/40] configs: socfpga: Permit EFI booting Commit f369e1564cf4 turned those off because the SPL size grew too large. It also argued that those boards would never support EFI booting. The former is correct, therefore keep CONFIG_SPL_EFI_PARTITION off. CONFIG_SPL_ISO_PARTITION is default off. What is not correct is that those boards are limited to legacy boot - you just need a hybrid partition table to make both the bootrom and UEFI happy. Signed-off-by: Jan Kiszka Reviewed-by: Tien Fong Chee --- configs/socfpga_agilex5_defconfig | 2 -- configs/socfpga_agilex_defconfig | 2 -- configs/socfpga_arria5_defconfig | 2 -- configs/socfpga_cyclone5_defconfig | 2 -- configs/socfpga_de0_nano_soc_defconfig | 2 -- configs/socfpga_de10_nano_defconfig | 2 -- configs/socfpga_de10_standard_defconfig | 2 -- configs/socfpga_de1_soc_defconfig | 2 -- configs/socfpga_is1_defconfig | 2 -- configs/socfpga_mcvevk_defconfig | 2 -- configs/socfpga_secu1_defconfig | 2 -- configs/socfpga_sockit_defconfig | 2 -- configs/socfpga_socrates_defconfig | 2 -- configs/socfpga_sr1500_defconfig | 2 -- configs/socfpga_vining_fpga_defconfig | 2 -- disk/Kconfig | 1 + 16 files changed, 1 insertion(+), 30 deletions(-) diff --git a/configs/socfpga_agilex5_defconfig b/configs/socfpga_agilex5_defconfig index 3eabc372269..b00cbcc6158 100644 --- a/configs/socfpga_agilex5_defconfig +++ b/configs/socfpga_agilex5_defconfig @@ -68,8 +68,6 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_TIMER=y CONFIG_CMD_UBI=y CONFIG_CMD_MMC=y -# CONFIG_ISO_PARTITION is not set -# CONFIG_EFI_PARTITION is not set CONFIG_OF_LIST="" CONFIG_ENV_IS_IN_FAT=y CONFIG_ENV_IS_IN_UBI=y diff --git a/configs/socfpga_agilex_defconfig b/configs/socfpga_agilex_defconfig index 1c3664bc0d7..eb99392f0ea 100644 --- a/configs/socfpga_agilex_defconfig +++ b/configs/socfpga_agilex_defconfig @@ -57,8 +57,6 @@ CONFIG_CMD_USB=y CONFIG_CMD_CACHE=y CONFIG_CMD_SMC=y CONFIG_CMD_UBI=y -# CONFIG_ISO_PARTITION is not set -# CONFIG_EFI_PARTITION is not set CONFIG_OF_UPSTREAM=y CONFIG_OF_LIST="" CONFIG_ENV_IS_IN_FAT=y diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig index 3c860f97ae9..88ef2eb0c76 100644 --- a/configs/socfpga_arria5_defconfig +++ b/configs/socfpga_arria5_defconfig @@ -44,8 +44,6 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)" CONFIG_CMD_UBI=y -# CONFIG_ISO_PARTITION is not set -# CONFIG_EFI_PARTITION is not set CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_VERSION_VARIABLE=y diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig index 2256eb2ecb8..a3fbc7be1b4 100644 --- a/configs/socfpga_cyclone5_defconfig +++ b/configs/socfpga_cyclone5_defconfig @@ -45,8 +45,6 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)" CONFIG_CMD_UBI=y -# CONFIG_ISO_PARTITION is not set -# CONFIG_EFI_PARTITION is not set CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_VERSION_VARIABLE=y diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig index 6564cbd03c6..3b021634bb9 100644 --- a/configs/socfpga_de0_nano_soc_defconfig +++ b/configs/socfpga_de0_nano_soc_defconfig @@ -46,8 +46,6 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)" CONFIG_CMD_UBI=y -# CONFIG_ISO_PARTITION is not set -# CONFIG_EFI_PARTITION is not set CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_VERSION_VARIABLE=y diff --git a/configs/socfpga_de10_nano_defconfig b/configs/socfpga_de10_nano_defconfig index 4fabd63f2b4..941f9e9f3bc 100644 --- a/configs/socfpga_de10_nano_defconfig +++ b/configs/socfpga_de10_nano_defconfig @@ -42,8 +42,6 @@ CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0" -# CONFIG_ISO_PARTITION is not set -# CONFIG_EFI_PARTITION is not set CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_VERSION_VARIABLE=y diff --git a/configs/socfpga_de10_standard_defconfig b/configs/socfpga_de10_standard_defconfig index 1c9ecbf2bc8..d2b0274249b 100644 --- a/configs/socfpga_de10_standard_defconfig +++ b/configs/socfpga_de10_standard_defconfig @@ -42,8 +42,6 @@ CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0" -# CONFIG_ISO_PARTITION is not set -# CONFIG_EFI_PARTITION is not set CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_VERSION_VARIABLE=y diff --git a/configs/socfpga_de1_soc_defconfig b/configs/socfpga_de1_soc_defconfig index 52ed0ff7ffa..f97b3a4055b 100644 --- a/configs/socfpga_de1_soc_defconfig +++ b/configs/socfpga_de1_soc_defconfig @@ -42,8 +42,6 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_EXT4_WRITE=y CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0" -# CONFIG_ISO_PARTITION is not set -# CONFIG_EFI_PARTITION is not set CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_VERSION_VARIABLE=y diff --git a/configs/socfpga_is1_defconfig b/configs/socfpga_is1_defconfig index 45d3b2f0807..4136d22e90e 100644 --- a/configs/socfpga_is1_defconfig +++ b/configs/socfpga_is1_defconfig @@ -44,8 +44,6 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)" CONFIG_CMD_UBI=y -# CONFIG_ISO_PARTITION is not set -# CONFIG_EFI_PARTITION is not set CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig index bff0c41336f..db288a2cf05 100644 --- a/configs/socfpga_mcvevk_defconfig +++ b/configs/socfpga_mcvevk_defconfig @@ -42,8 +42,6 @@ CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y -# CONFIG_ISO_PARTITION is not set -# CONFIG_EFI_PARTITION is not set CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y diff --git a/configs/socfpga_secu1_defconfig b/configs/socfpga_secu1_defconfig index 5fe35fe6eb8..552ded52873 100644 --- a/configs/socfpga_secu1_defconfig +++ b/configs/socfpga_secu1_defconfig @@ -63,8 +63,6 @@ CONFIG_MTDIDS_DEFAULT="nand0=denali-nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=denali-nand:512k(nand.4spl),512k(nand.uboot),128k(nand.env1),128k(nand.env2),0x1000000(nand.rec),0x3ee40000(nand.ubi),0x80000@0x3ff80000(nand.bbt)" CONFIG_CMD_UBI=y # CONFIG_CMD_UBIFS is not set -# CONFIG_ISO_PARTITION is not set -# CONFIG_EFI_PARTITION is not set CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_REDUNDANT=y diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig index fed1dd83dc2..6dec5758fba 100644 --- a/configs/socfpga_sockit_defconfig +++ b/configs/socfpga_sockit_defconfig @@ -44,8 +44,6 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)" CONFIG_CMD_UBI=y -# CONFIG_ISO_PARTITION is not set -# CONFIG_EFI_PARTITION is not set CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_VERSION_VARIABLE=y diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig index a08c7c0d9e0..3bfb05fa419 100644 --- a/configs/socfpga_socrates_defconfig +++ b/configs/socfpga_socrates_defconfig @@ -44,8 +44,6 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)" CONFIG_CMD_UBI=y -# CONFIG_ISO_PARTITION is not set -# CONFIG_EFI_PARTITION is not set CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_VERSION_VARIABLE=y diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig index 7744ff9a888..814b4e8ce1d 100644 --- a/configs/socfpga_sr1500_defconfig +++ b/configs/socfpga_sr1500_defconfig @@ -51,8 +51,6 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)" CONFIG_CMD_UBI=y -# CONFIG_ISO_PARTITION is not set -# CONFIG_EFI_PARTITION is not set CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_REDUNDANT=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig index 396b7a9715d..f698b86e59f 100644 --- a/configs/socfpga_vining_fpga_defconfig +++ b/configs/socfpga_vining_fpga_defconfig @@ -58,8 +58,6 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),64k(env1),64k(env2),256k(softing1),256k(softing2),-(rcvrfs);" CONFIG_CMD_UBI=y -# CONFIG_ISO_PARTITION is not set -# CONFIG_EFI_PARTITION is not set CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_REDUNDANT=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y diff --git a/disk/Kconfig b/disk/Kconfig index b0bd02539ee..a58717bda30 100644 --- a/disk/Kconfig +++ b/disk/Kconfig @@ -142,6 +142,7 @@ config SPL_EFI_PARTITION bool "Enable EFI GPT partition table for SPL" depends on SPL default n if ARCH_MVEBU + default n if ARCH_SOCFPGA default n if ARCH_SUNXI default y if EFI_PARTITION select SPL_PARTITIONS