mirror of
https://source.denx.de/u-boot/u-boot.git
synced 2025-08-06 07:17:01 +02:00
Subtree merge tag 'v6.16-dts' of dts repo [1] into dts/upstream
[1] https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git Perform a few fixups in our dts* files to match upstream changes. Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini
commit
79f3e77133
@ -15,6 +15,6 @@
|
||||
* because SBL de-initialises them. Indicate that the UART pins should be configured
|
||||
* during all boot stages.
|
||||
*/
|
||||
&blsp_uart2_default {
|
||||
&blsp_uart2_console_default {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
@ -463,7 +463,7 @@
|
||||
drive-strength = <16>;
|
||||
};
|
||||
|
||||
&blsp_uart1_default {
|
||||
&blsp_uart1_console_default {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
|
||||
@ -646,7 +646,7 @@
|
||||
reg = <0x01cb4000 0x3000>;
|
||||
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_CSI>,
|
||||
<&ccu CLK_CSI1_SCLK>,
|
||||
<&ccu CLK_CSI_SCLK>,
|
||||
<&ccu CLK_DRAM_CSI>;
|
||||
clock-names = "bus", "mod", "ram";
|
||||
resets = <&ccu RST_BUS_CSI>;
|
||||
|
||||
@ -47,6 +47,7 @@ properties:
|
||||
- novtech,chameleon96
|
||||
- samtec,vining
|
||||
- terasic,de0-atlas
|
||||
- terasic,de10-nano
|
||||
- terasic,socfpga-cyclone5-sockit
|
||||
- const: altr,socfpga-cyclone5
|
||||
- const: altr,socfpga
|
||||
|
||||
@ -9,20 +9,120 @@ title: Altera SOCFPGA Clock Manager
|
||||
maintainers:
|
||||
- Dinh Nguyen <dinguyen@kernel.org>
|
||||
|
||||
description: test
|
||||
description:
|
||||
This binding describes the Altera SOCFGPA Clock Manager and its associated
|
||||
tree of clocks, pll's, and clock gates for the Cyclone5, Arria5 and Arria10
|
||||
chip families.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: altr,clk-mgr
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
type: object
|
||||
additionalProperties: false
|
||||
|
||||
properties:
|
||||
"#address-cells":
|
||||
const: 1
|
||||
|
||||
"#size-cells":
|
||||
const: 0
|
||||
|
||||
patternProperties:
|
||||
"^osc[0-9]$":
|
||||
type: object
|
||||
|
||||
"^[a-z0-9,_]+(clk|pll|clk_gate|clk_divided)(@[a-f0-9]+)?$":
|
||||
type: object
|
||||
$ref: '#/$defs/clock-props'
|
||||
unevaluatedProperties: false
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- altr,socfpga-pll-clock
|
||||
- altr,socfpga-perip-clk
|
||||
- altr,socfpga-gate-clk
|
||||
- altr,socfpga-a10-pll-clock
|
||||
- altr,socfpga-a10-perip-clk
|
||||
- altr,socfpga-a10-gate-clk
|
||||
- fixed-clock
|
||||
|
||||
clocks:
|
||||
description: one or more phandles to input clock
|
||||
minItems: 1
|
||||
maxItems: 5
|
||||
|
||||
"#address-cells":
|
||||
const: 1
|
||||
|
||||
"#size-cells":
|
||||
const: 0
|
||||
|
||||
patternProperties:
|
||||
"^[a-z0-9,_]+(clk|pll)(@[a-f0-9]+)?$":
|
||||
type: object
|
||||
$ref: '#/$defs/clock-props'
|
||||
unevaluatedProperties: false
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- altr,socfpga-perip-clk
|
||||
- altr,socfpga-gate-clk
|
||||
- altr,socfpga-a10-perip-clk
|
||||
- altr,socfpga-a10-gate-clk
|
||||
|
||||
clocks:
|
||||
description: one or more phandles to input clock
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- "#clock-cells"
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- "#clock-cells"
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
$defs:
|
||||
clock-props:
|
||||
properties:
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#clock-cells":
|
||||
const: 0
|
||||
|
||||
clk-gate:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
items:
|
||||
- description: gating register offset
|
||||
- description: bit index
|
||||
|
||||
div-reg:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
items:
|
||||
- description: divider register offset
|
||||
- description: bit shift
|
||||
- description: bit width
|
||||
|
||||
fixed-divider:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
examples:
|
||||
- |
|
||||
clkmgr@ffd04000 {
|
||||
|
||||
@ -27,6 +27,7 @@ properties:
|
||||
items:
|
||||
- enum:
|
||||
- minix,neo-x8
|
||||
- tcu,fernsehfee3
|
||||
- const: amlogic,meson8
|
||||
|
||||
- description: Boards with the Amlogic Meson8m2 SoC
|
||||
@ -73,6 +74,13 @@ properties:
|
||||
- const: amlogic,s805x
|
||||
- const: amlogic,meson-gxl
|
||||
|
||||
- description: Boards with the Amlogic Meson GXL S805Y SoC
|
||||
items:
|
||||
- enum:
|
||||
- xiaomi,aquaman
|
||||
- const: amlogic,s805y
|
||||
- const: amlogic,meson-gxl
|
||||
|
||||
- description: Boards with the Amlogic Meson GXL S905W SoC
|
||||
items:
|
||||
- enum:
|
||||
@ -237,6 +245,24 @@ properties:
|
||||
- amlogic,aq222
|
||||
- const: amlogic,s4
|
||||
|
||||
- description: Boards with the Amlogic S6 S905X5 SoC
|
||||
items:
|
||||
- enum:
|
||||
- amlogic,bl209
|
||||
- const: amlogic,s6
|
||||
|
||||
- description: Boards with the Amlogic S7 S805X3 SoC
|
||||
items:
|
||||
- enum:
|
||||
- amlogic,bp201
|
||||
- const: amlogic,s7
|
||||
|
||||
- description: Boards with the Amlogic S7D S905X5M SoC
|
||||
items:
|
||||
- enum:
|
||||
- amlogic,bm202
|
||||
- const: amlogic,s7d
|
||||
|
||||
- description: Boards with the Amlogic T7 A311D2 SoC
|
||||
items:
|
||||
- enum:
|
||||
|
||||
@ -30,6 +30,19 @@ properties:
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 3
|
||||
|
||||
clock-names:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum: [apb_pclk, atclk]
|
||||
- items: # Zynq-700
|
||||
- const: apb_pclk
|
||||
- const: dbg_trc
|
||||
- const: dbg_apb
|
||||
|
||||
in-ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
additionalProperties: false
|
||||
|
||||
49
dts/upstream/Bindings/arm/atmel,sama5d2-secumod.yaml
Normal file
49
dts/upstream/Bindings/arm/atmel,sama5d2-secumod.yaml
Normal file
@ -0,0 +1,49 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/atmel,sama5d2-secumod.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Microchip AT91 Security Module (SECUMOD)
|
||||
|
||||
maintainers:
|
||||
- Nicolas Ferre <nicolas.ferre@microchip.com>
|
||||
|
||||
description:
|
||||
The Security Module also offers the PIOBU pins which can be used as GPIO pins.
|
||||
Note that they maintain their voltage during Backup/Self-refresh.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: atmel,sama5d2-secumod
|
||||
- const: syscon
|
||||
- items:
|
||||
- enum:
|
||||
- microchip,sama7d65-secumod
|
||||
- microchip,sama7g5-secumod
|
||||
- const: atmel,sama5d2-secumod
|
||||
- const: syscon
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
gpio-controller: true
|
||||
|
||||
"#gpio-cells":
|
||||
const: 2
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
security-module@fc040000 {
|
||||
compatible = "atmel,sama5d2-secumod", "syscon";
|
||||
reg = <0xfc040000 0x100>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
@ -46,28 +46,3 @@ Examples:
|
||||
reg = <0xffffe800 0x200>;
|
||||
};
|
||||
|
||||
Security Module (SECUMOD)
|
||||
|
||||
The Security Module macrocell provides all necessary secure functions to avoid
|
||||
voltage, temperature, frequency and mechanical attacks on the chip. It also
|
||||
embeds secure memories that can be scrambled.
|
||||
|
||||
The Security Module also offers the PIOBU pins which can be used as GPIO pins.
|
||||
Note that they maintain their voltage during Backup/Self-refresh.
|
||||
|
||||
required properties:
|
||||
- compatible: Should be "atmel,<chip>-secumod", "syscon".
|
||||
<chip> can be "sama5d2".
|
||||
- reg: Should contain registers location and length
|
||||
- gpio-controller: Marks the port as GPIO controller.
|
||||
- #gpio-cells: There are 2. The pin number is the
|
||||
first, the second represents additional
|
||||
parameters such as GPIO_ACTIVE_HIGH/LOW.
|
||||
|
||||
|
||||
secumod@fc040000 {
|
||||
compatible = "atmel,sama5d2-secumod", "syscon";
|
||||
reg = <0xfc040000 0x100>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
@ -52,6 +52,7 @@ properties:
|
||||
- description: BCM2837 based Boards
|
||||
items:
|
||||
- enum:
|
||||
- raspberrypi,2-model-b-rev2
|
||||
- raspberrypi,3-model-a-plus
|
||||
- raspberrypi,3-model-b
|
||||
- raspberrypi,3-model-b-plus
|
||||
|
||||
@ -10,9 +10,9 @@ maintainers:
|
||||
- Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
|
||||
|
||||
description: |+
|
||||
The device tree allows to describe the layout of CPUs in a system through
|
||||
the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
|
||||
defining properties for every cpu.
|
||||
The device tree allows to describe the layout of CPUs in a system through the
|
||||
"cpus" node, which in turn contains a number of subnodes (ie "cpu") defining
|
||||
properties for every cpu.
|
||||
|
||||
Bindings for CPU nodes follow the Devicetree Specification, available from:
|
||||
|
||||
@ -41,45 +41,40 @@ description: |+
|
||||
properties:
|
||||
reg:
|
||||
maxItems: 1
|
||||
description: |
|
||||
Usage and definition depend on ARM architecture version and
|
||||
configuration:
|
||||
description: >
|
||||
Usage and definition depend on ARM architecture version and configuration:
|
||||
|
||||
On uniprocessor ARM architectures previous to v7
|
||||
this property is required and must be set to 0.
|
||||
On uniprocessor ARM architectures previous to v7 this property is required
|
||||
and must be set to 0.
|
||||
|
||||
On ARM 11 MPcore based systems this property is
|
||||
required and matches the CPUID[11:0] register bits.
|
||||
On ARM 11 MPcore based systems this property is required and matches the
|
||||
CPUID[11:0] register bits.
|
||||
|
||||
Bits [11:0] in the reg cell must be set to
|
||||
bits [11:0] in CPU ID register.
|
||||
Bits [11:0] in the reg cell must be set to bits [11:0] in CPU ID register.
|
||||
|
||||
All other bits in the reg cell must be set to 0.
|
||||
|
||||
On 32-bit ARM v7 or later systems this property is
|
||||
required and matches the CPU MPIDR[23:0] register
|
||||
bits.
|
||||
On 32-bit ARM v7 or later systems this property is required and matches
|
||||
the CPU MPIDR[23:0] register bits.
|
||||
|
||||
Bits [23:0] in the reg cell must be set to
|
||||
bits [23:0] in MPIDR.
|
||||
Bits [23:0] in the reg cell must be set to bits [23:0] in MPIDR.
|
||||
|
||||
All other bits in the reg cell must be set to 0.
|
||||
|
||||
On ARM v8 64-bit systems this property is required
|
||||
and matches the MPIDR_EL1 register affinity bits.
|
||||
On ARM v8 64-bit systems this property is required and matches the
|
||||
MPIDR_EL1 register affinity bits.
|
||||
|
||||
* If cpus node's #address-cells property is set to 2
|
||||
|
||||
The first reg cell bits [7:0] must be set to
|
||||
bits [39:32] of MPIDR_EL1.
|
||||
The first reg cell bits [7:0] must be set to bits [39:32] of
|
||||
MPIDR_EL1.
|
||||
|
||||
The second reg cell bits [23:0] must be set to
|
||||
bits [23:0] of MPIDR_EL1.
|
||||
The second reg cell bits [23:0] must be set to bits [23:0] of
|
||||
MPIDR_EL1.
|
||||
|
||||
* If cpus node's #address-cells property is set to 1
|
||||
|
||||
The reg cell bits [23:0] must be set to bits [23:0]
|
||||
of MPIDR_EL1.
|
||||
The reg cell bits [23:0] must be set to bits [23:0] of MPIDR_EL1.
|
||||
|
||||
All other bits in the reg cells must be set to 0.
|
||||
|
||||
@ -273,103 +268,122 @@ properties:
|
||||
description:
|
||||
The DT specification defines this as 64-bit always, but some 32-bit Arm
|
||||
systems have used a 32-bit value which must be supported.
|
||||
Required for systems that have an "enable-method"
|
||||
property value of "spin-table".
|
||||
|
||||
cpu-idle-states:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
items:
|
||||
maxItems: 1
|
||||
description: |
|
||||
List of phandles to idle state nodes supported
|
||||
by this cpu (see ./idle-states.yaml).
|
||||
description:
|
||||
List of phandles to idle state nodes supported by this cpu (see
|
||||
./idle-states.yaml).
|
||||
|
||||
capacity-dmips-mhz:
|
||||
description:
|
||||
u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in
|
||||
DMIPS/MHz, relative to highest capacity-dmips-mhz
|
||||
in the system.
|
||||
DMIPS/MHz, relative to highest capacity-dmips-mhz in the system.
|
||||
|
||||
cci-control-port: true
|
||||
|
||||
dynamic-power-coefficient:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
A u32 value that represents the running time dynamic
|
||||
power coefficient in units of uW/MHz/V^2. The
|
||||
coefficient can either be calculated from power
|
||||
description: >
|
||||
A u32 value that represents the running time dynamic power coefficient in
|
||||
units of uW/MHz/V^2. The coefficient can either be calculated from power
|
||||
measurements or derived by analysis.
|
||||
|
||||
The dynamic power consumption of the CPU is
|
||||
proportional to the square of the Voltage (V) and
|
||||
the clock frequency (f). The coefficient is used to
|
||||
The dynamic power consumption of the CPU is proportional to the square of
|
||||
the Voltage (V) and the clock frequency (f). The coefficient is used to
|
||||
calculate the dynamic power as below -
|
||||
|
||||
Pdyn = dynamic-power-coefficient * V^2 * f
|
||||
|
||||
where voltage is in V, frequency is in MHz.
|
||||
|
||||
interconnects:
|
||||
minItems: 1
|
||||
maxItems: 3
|
||||
|
||||
nvmem-cells:
|
||||
maxItems: 1
|
||||
|
||||
nvmem-cell-names:
|
||||
const: speed_grade
|
||||
|
||||
performance-domains:
|
||||
maxItems: 1
|
||||
description:
|
||||
List of phandles and performance domain specifiers, as defined by
|
||||
bindings of the performance domain provider. See also
|
||||
dvfs/performance-domain.yaml.
|
||||
|
||||
power-domains:
|
||||
description:
|
||||
List of phandles and PM domain specifiers, as defined by bindings of the
|
||||
PM domain provider (see also ../power_domain.txt).
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
power-domain-names:
|
||||
description:
|
||||
A list of power domain name strings sorted in the same order as the
|
||||
power-domains property.
|
||||
|
||||
For PSCI based platforms, the name corresponding to the index of the PSCI
|
||||
PM domain provider, must be "psci". For SCMI based platforms, the name
|
||||
corresponding to the index of an SCMI performance domain provider, must be
|
||||
"perf".
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
items:
|
||||
enum: [ psci, perf, cpr ]
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
arm-supply:
|
||||
deprecated: true
|
||||
description: Use 'cpu-supply' instead
|
||||
|
||||
cpu0-supply:
|
||||
deprecated: true
|
||||
description: Use 'cpu-supply' instead
|
||||
|
||||
mem-supply: true
|
||||
|
||||
proc-supply:
|
||||
deprecated: true
|
||||
description: Use 'cpu-supply' instead
|
||||
|
||||
sram-supply:
|
||||
deprecated: true
|
||||
description: Use 'mem-supply' instead
|
||||
|
||||
mediatek,cci:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description: Link to Mediatek Cache Coherent Interconnect
|
||||
|
||||
qcom,saw:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description: |
|
||||
Specifies the SAW* node associated with this CPU.
|
||||
|
||||
Required for systems that have an "enable-method" property
|
||||
value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
|
||||
|
||||
* arm/msm/qcom,saw2.txt
|
||||
description:
|
||||
Specifies the SAW node associated with this CPU.
|
||||
|
||||
qcom,acc:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description: |
|
||||
Specifies the ACC* node associated with this CPU.
|
||||
description:
|
||||
Specifies the ACC node associated with this CPU.
|
||||
|
||||
Required for systems that have an "enable-method" property
|
||||
value of "qcom,kpss-acc-v1", "qcom,kpss-acc-v2", "qcom,msm8226-smp" or
|
||||
"qcom,msm8916-smp".
|
||||
|
||||
* arm/msm/qcom,kpss-acc.txt
|
||||
qcom,freq-domain:
|
||||
description: Specifies the QCom CPUFREQ HW associated with the CPU.
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
maxItems: 1
|
||||
|
||||
rockchip,pmu:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description: |
|
||||
description: >
|
||||
Specifies the syscon node controlling the cpu core power domains.
|
||||
|
||||
Optional for systems that have an "enable-method"
|
||||
property value of "rockchip,rk3066-smp"
|
||||
While optional, it is the preferred way to get access to
|
||||
the cpu-core power-domains.
|
||||
Optional for systems that have an "enable-method" property value of
|
||||
"rockchip,rk3066-smp". While optional, it is the preferred way to get
|
||||
access to the cpu-core power-domains.
|
||||
|
||||
secondary-boot-reg:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
description: >
|
||||
Required for systems that have an "enable-method" property value of
|
||||
"brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp".
|
||||
|
||||
This includes the following SoCs: |
|
||||
BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550
|
||||
This includes the following SoCs:
|
||||
BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550,
|
||||
BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
|
||||
|
||||
The secondary-boot-reg property is a u32 value that specifies the
|
||||
@ -378,22 +392,66 @@ properties:
|
||||
formed by encoding the target CPU id into the low bits of the
|
||||
physical start address it should jump to.
|
||||
|
||||
if:
|
||||
# If the enable-method property contains one of those values
|
||||
properties:
|
||||
enable-method:
|
||||
contains:
|
||||
enum:
|
||||
- brcm,bcm11351-cpu-method
|
||||
- brcm,bcm23550
|
||||
- brcm,bcm-nsp-smp
|
||||
# and if enable-method is present
|
||||
required:
|
||||
- enable-method
|
||||
thermal-idle:
|
||||
type: object
|
||||
|
||||
then:
|
||||
required:
|
||||
- secondary-boot-reg
|
||||
allOf:
|
||||
- $ref: /schemas/cpu.yaml#
|
||||
- $ref: /schemas/opp/opp-v1.yaml#
|
||||
- if:
|
||||
# If the enable-method property contains one of those values
|
||||
properties:
|
||||
enable-method:
|
||||
contains:
|
||||
enum:
|
||||
- brcm,bcm11351-cpu-method
|
||||
- brcm,bcm23550
|
||||
- brcm,bcm-nsp-smp
|
||||
# and if enable-method is present
|
||||
required:
|
||||
- enable-method
|
||||
then:
|
||||
required:
|
||||
- secondary-boot-reg
|
||||
- if:
|
||||
properties:
|
||||
enable-method:
|
||||
enum:
|
||||
- spin-table
|
||||
- renesas,r9a06g032-smp
|
||||
required:
|
||||
- enable-method
|
||||
then:
|
||||
required:
|
||||
- cpu-release-addr
|
||||
- if:
|
||||
properties:
|
||||
enable-method:
|
||||
enum:
|
||||
- qcom,kpss-acc-v1
|
||||
- qcom,kpss-acc-v2
|
||||
- qcom,msm8226-smp
|
||||
- qcom,msm8916-smp
|
||||
required:
|
||||
- enable-method
|
||||
then:
|
||||
required:
|
||||
- qcom,acc
|
||||
- qcom,saw
|
||||
else:
|
||||
if:
|
||||
# 2 Qualcomm platforms bootloaders need qcom,acc and qcom,saw yet use
|
||||
# "spin-table" or "psci" enable-methods. Disallowing the properties for
|
||||
# all other CPUs is the best we can do as there's not any way to
|
||||
# distinguish these Qualcomm platforms.
|
||||
not:
|
||||
properties:
|
||||
compatible:
|
||||
const: arm,cortex-a53
|
||||
then:
|
||||
properties:
|
||||
qcom,acc: false
|
||||
qcom,saw: false
|
||||
|
||||
required:
|
||||
- device_type
|
||||
@ -403,7 +461,7 @@ required:
|
||||
dependencies:
|
||||
rockchip,pmu: [enable-method]
|
||||
|
||||
additionalProperties: true
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
41
dts/upstream/Bindings/arm/freescale/fsl,imx51-m4if.yaml
Normal file
41
dts/upstream/Bindings/arm/freescale/fsl,imx51-m4if.yaml
Normal file
@ -0,0 +1,41 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/freescale/fsl,imx51-m4if.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Freescale Multi Master Multi Memory Interface (M4IF) and Tigerp module
|
||||
|
||||
description: collect the imx devices, which only have compatible and reg property
|
||||
|
||||
maintainers:
|
||||
- Frank Li <Frank.Li@nxp.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- enum:
|
||||
- fsl,imx51-m4if
|
||||
- fsl,imx51-tigerp
|
||||
- fsl,imx51-aipstz
|
||||
- fsl,imx53-aipstz
|
||||
- fsl,imx7d-pcie-phy
|
||||
- items:
|
||||
- const: fsl,imx53-tigerp
|
||||
- const: fsl,imx51-tigerp
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
m4if@83fd8000 {
|
||||
compatible = "fsl,imx51-m4if";
|
||||
reg = <0x83fd8000 0x1000>;
|
||||
};
|
||||
@ -1,12 +0,0 @@
|
||||
* Freescale Multi Master Multi Memory Interface (M4IF) module
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be "fsl,imx51-m4if"
|
||||
- reg : Address and length of the register set for the device
|
||||
|
||||
Example:
|
||||
|
||||
m4if: m4if@83fd8000 {
|
||||
compatible = "fsl,imx51-m4if";
|
||||
reg = <0x83fd8000 0x1000>;
|
||||
};
|
||||
@ -1,12 +0,0 @@
|
||||
* Freescale Tigerp platform module
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be "fsl,imx51-tigerp"
|
||||
- reg : Address and length of the register set for the device
|
||||
|
||||
Example:
|
||||
|
||||
tigerp: tigerp@83fa0000 {
|
||||
compatible = "fsl,imx51-tigerp";
|
||||
reg = <0x83fa0000 0x28>;
|
||||
};
|
||||
@ -1120,6 +1120,12 @@ properties:
|
||||
- const: avnet,sm2s-imx8mp # SM2S-IMX8PLUS SoM
|
||||
- const: fsl,imx8mp
|
||||
|
||||
- description: Boundary Devices Nitrogen8M Plus ENC Carrier Board
|
||||
items:
|
||||
- const: boundary,imx8mp-nitrogen-enc-carrier-board
|
||||
- const: boundary,imx8mp-nitrogen-som
|
||||
- const: fsl,imx8mp
|
||||
|
||||
- description: Boundary Device Nitrogen8MP Universal SMARC Carrier Board
|
||||
items:
|
||||
- const: boundary,imx8mp-nitrogen-smarc-universal-board
|
||||
@ -1156,6 +1162,13 @@ properties:
|
||||
- const: kontron,imx8mp-osm-s # Kontron i.MX8MP OSM-S SoM
|
||||
- const: fsl,imx8mp
|
||||
|
||||
- description: PHYTEC phyCORE-i.MX8MP FPSC based boards
|
||||
items:
|
||||
- enum:
|
||||
- phytec,imx8mp-libra-rdk-fpsc # i.MX 8M Plus Libra RDK
|
||||
- const: phytec,imx8mp-phycore-fpsc # phyCORE-i.MX 8M Plus FPSC
|
||||
- const: fsl,imx8mp
|
||||
|
||||
- description: PHYTEC phyCORE-i.MX8MP SoM based boards
|
||||
items:
|
||||
- const: phytec,imx8mp-phyboard-pollux-rdk # phyBOARD-Pollux RDK
|
||||
@ -1176,6 +1189,12 @@ properties:
|
||||
- const: polyhex,imx8mp-debix-som-a # Polyhex Debix SOM A
|
||||
- const: fsl,imx8mp
|
||||
|
||||
- description: Toradex Boards with SMARC iMX8M Plus Modules
|
||||
items:
|
||||
- const: toradex,smarc-imx8mp-dev # Toradex SMARC iMX8M Plus on Toradex SMARC Development Board
|
||||
- const: toradex,smarc-imx8mp # Toradex SMARC iMX8M Plus Module
|
||||
- const: fsl,imx8mp
|
||||
|
||||
- description: Toradex Boards with Verdin iMX8M Plus Modules
|
||||
items:
|
||||
- enum:
|
||||
@ -1333,6 +1352,22 @@ properties:
|
||||
- const: tq,imx8qxp-tqma8xqp # TQ-Systems GmbH TQMa8XQP SOM (with i.MX8QXP)
|
||||
- const: fsl,imx8qxp
|
||||
|
||||
- description:
|
||||
TQMa8XxS is a series of SOM featuring NXP i.MX8X system-on-chip
|
||||
variants. It has the SMARC-2.0 form factor and is designed to be placed on
|
||||
different carrier boards. MB-SMARC-2 is a carrier reference design.
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- tq,imx8qxp-tqma8xqps-mb-smarc-2 # TQ-Systems GmbH TQMa8QXPS SOM on MB-SMARC-2
|
||||
- const: tq,imx8qxp-tqma8xqps # TQ-Systems GmbH TQMa8QXPS SOM
|
||||
- const: fsl,imx8qxp
|
||||
- items:
|
||||
- enum:
|
||||
- tq,imx8dxp-tqma8xdps-mb-smarc-2 # TQ-Systems GmbH TQMa8XDPS SOM on MB-SMARC-2
|
||||
- const: tq,imx8dxp-tqma8xdps # TQ-Systems GmbH TQMa8XDPS SOM
|
||||
- const: fsl,imx8dxp
|
||||
|
||||
- description: i.MX8ULP based Boards
|
||||
items:
|
||||
- enum:
|
||||
@ -1347,6 +1382,12 @@ properties:
|
||||
- fsl,imx93-14x14-evk # i.MX93 14x14 EVK Board
|
||||
- const: fsl,imx93
|
||||
|
||||
- description: i.MX94 based Boards
|
||||
items:
|
||||
- enum:
|
||||
- fsl,imx943-evk # i.MX943 EVK Board
|
||||
- const: fsl,imx94
|
||||
|
||||
- description: i.MX95 based Boards
|
||||
items:
|
||||
- enum:
|
||||
@ -1374,12 +1415,16 @@ properties:
|
||||
All SOM and CPU variants use the same device tree hence only one
|
||||
compatible is needed. Bootloader disables all features not present
|
||||
in the assembled SOC.
|
||||
MBa91xxCA mainboard can be used as starterkit for the SOM
|
||||
soldered on an adapter board or for the connector variant
|
||||
to evaluate RGB display support.
|
||||
MBa93xxCA mainboard can be used as starterkit for the SOM
|
||||
soldered on an adapter board or for the connector variant
|
||||
MBa93xxLA mainboard is a single board computer using the solderable
|
||||
SOM variant
|
||||
items:
|
||||
- enum:
|
||||
- tq,imx93-tqma9352-mba91xxca # TQ-Systems GmbH i.MX93 TQMa93xxCA/LA SOM on MBa91xxCA
|
||||
- tq,imx93-tqma9352-mba93xxca # TQ-Systems GmbH i.MX93 TQMa93xxCA/LA SOM on MBa93xxCA
|
||||
- tq,imx93-tqma9352-mba93xxla # TQ-Systems GmbH i.MX93 TQMa93xxLA SOM on MBa93xxLA SBC
|
||||
- const: tq,imx93-tqma9352 # TQ-Systems GmbH i.MX93 TQMa93xxCA/LA SOM
|
||||
@ -1387,8 +1432,10 @@ properties:
|
||||
|
||||
- description: PHYTEC phyCORE-i.MX93 SoM based boards
|
||||
items:
|
||||
- const: phytec,imx93-phyboard-segin # phyBOARD-Segin with i.MX93
|
||||
- const: phytec,imx93-phycore-som # phyCORE-i.MX93 SoM
|
||||
- enum:
|
||||
- phytec,imx93-phyboard-nash # phyBOARD-Nash-i.MX93
|
||||
- phytec,imx93-phyboard-segin # phyBOARD-Segin with i.MX93
|
||||
- const: phytec,imx93-phycore-som # phyCORE-i.MX93 SoM
|
||||
- const: fsl,imx93
|
||||
|
||||
- description: Variscite VAR-SOM-MX93 based boards
|
||||
@ -1403,6 +1450,16 @@ properties:
|
||||
- const: kontron,imx93-osm-s # Kontron OSM-S i.MX93 SoM
|
||||
- const: fsl,imx93
|
||||
|
||||
- description:
|
||||
TQMa95xxSA is a series of SOM featuring NXP i.MX95 SoC variants.
|
||||
It has the SMARC form factor and is designed to be placed on
|
||||
different carrier boards. MB-SMARC-2 is a carrier reference design.
|
||||
items:
|
||||
- enum:
|
||||
- tq,imx95-tqma9596sa-mb-smarc-2 # TQ-Systems GmbH i.MX95 TQMa95xxSA SOM on MB-SMARC-2
|
||||
- const: tq,imx95-tqma9596sa # TQ-Systems GmbH i.MX95 TQMa95xxSA SOM
|
||||
- const: fsl,imx95
|
||||
|
||||
- description:
|
||||
Freescale Vybrid Platform Device Tree Bindings
|
||||
|
||||
|
||||
@ -25,6 +25,7 @@ properties:
|
||||
items:
|
||||
- enum:
|
||||
- intel,socfpga-agilex5-socdk
|
||||
- intel,socfpga-agilex5-socdk-nand
|
||||
- const: intel,socfpga-agilex5
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
@ -104,6 +104,10 @@ properties:
|
||||
- enum:
|
||||
- bananapi,bpi-r4
|
||||
- const: mediatek,mt7988a
|
||||
- items:
|
||||
- const: bananapi,bpi-r4-2g5
|
||||
- const: bananapi,bpi-r4
|
||||
- const: mediatek,mt7988a
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8127-moose
|
||||
@ -285,6 +289,13 @@ properties:
|
||||
- const: google,steelix-sku393218
|
||||
- const: google,steelix
|
||||
- const: mediatek,mt8186
|
||||
- description: Google Ponyta
|
||||
items:
|
||||
- enum:
|
||||
- google,ponyta-sku0
|
||||
- google,ponyta-sku1
|
||||
- const: google,ponyta
|
||||
- const: mediatek,mt8186
|
||||
- description: Google Rusty (Lenovo 100e Chromebook Gen 4)
|
||||
items:
|
||||
- const: google,steelix-sku196609
|
||||
|
||||
@ -191,27 +191,27 @@ examples:
|
||||
#size-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
|
||||
CPU0: cpu@0 {
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x0>;
|
||||
enable-method = "psci";
|
||||
power-domains = <&CPU_PD0>;
|
||||
power-domains = <&cpu_pd0>;
|
||||
power-domain-names = "psci";
|
||||
};
|
||||
|
||||
CPU1: cpu@1 {
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x100>;
|
||||
enable-method = "psci";
|
||||
power-domains = <&CPU_PD1>;
|
||||
power-domains = <&cpu_pd1>;
|
||||
power-domain-names = "psci";
|
||||
};
|
||||
|
||||
idle-states {
|
||||
|
||||
CPU_PWRDN: cpu-power-down {
|
||||
cpu_pwrdn: cpu-power-down {
|
||||
compatible = "arm,idle-state";
|
||||
arm,psci-suspend-param = <0x0000001>;
|
||||
entry-latency-us = <10>;
|
||||
@ -222,7 +222,7 @@ examples:
|
||||
|
||||
domain-idle-states {
|
||||
|
||||
CLUSTER_RET: cluster-retention {
|
||||
cluster_ret: cluster-retention {
|
||||
compatible = "domain-idle-state";
|
||||
arm,psci-suspend-param = <0x1000011>;
|
||||
entry-latency-us = <500>;
|
||||
@ -230,7 +230,7 @@ examples:
|
||||
min-residency-us = <2000>;
|
||||
};
|
||||
|
||||
CLUSTER_PWRDN: cluster-power-down {
|
||||
cluster_pwrdn: cluster-power-down {
|
||||
compatible = "domain-idle-state";
|
||||
arm,psci-suspend-param = <0x1000031>;
|
||||
entry-latency-us = <2000>;
|
||||
@ -244,21 +244,21 @@ examples:
|
||||
compatible = "arm,psci-1.0";
|
||||
method = "smc";
|
||||
|
||||
CPU_PD0: power-domain-cpu0 {
|
||||
cpu_pd0: power-domain-cpu0 {
|
||||
#power-domain-cells = <0>;
|
||||
domain-idle-states = <&CPU_PWRDN>;
|
||||
power-domains = <&CLUSTER_PD>;
|
||||
domain-idle-states = <&cpu_pwrdn>;
|
||||
power-domains = <&cluster_pd>;
|
||||
};
|
||||
|
||||
CPU_PD1: power-domain-cpu1 {
|
||||
cpu_pd1: power-domain-cpu1 {
|
||||
#power-domain-cells = <0>;
|
||||
domain-idle-states = <&CPU_PWRDN>;
|
||||
power-domains = <&CLUSTER_PD>;
|
||||
domain-idle-states = <&cpu_pwrdn>;
|
||||
power-domains = <&cluster_pd>;
|
||||
};
|
||||
|
||||
CLUSTER_PD: power-domain-cluster {
|
||||
cluster_pd: power-domain-cluster {
|
||||
#power-domain-cells = <0>;
|
||||
domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>;
|
||||
domain-idle-states = <&cluster_ret>, <&cluster_pwrdn>;
|
||||
};
|
||||
};
|
||||
...
|
||||
|
||||
@ -90,6 +90,7 @@ description: |
|
||||
sm6350
|
||||
sm6375
|
||||
sm7125
|
||||
sm7150
|
||||
sm7225
|
||||
sm7325
|
||||
sm8150
|
||||
@ -1020,6 +1021,7 @@ properties:
|
||||
- items:
|
||||
- enum:
|
||||
- sony,pdx201
|
||||
- xiaomi,ginkgo
|
||||
- xiaomi,laurel-sprout
|
||||
- const: qcom,sm6125
|
||||
|
||||
@ -1039,6 +1041,11 @@ properties:
|
||||
- xiaomi,joyeuse
|
||||
- const: qcom,sm7125
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- google,sunfish
|
||||
- const: qcom,sm7150
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- fairphone,fp4
|
||||
@ -1123,14 +1130,18 @@ properties:
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- lenovo,thinkpad-t14s
|
||||
- lenovo,thinkpad-t14s-lcd
|
||||
- lenovo,thinkpad-t14s-oled
|
||||
- const: lenovo,thinkpad-t14s
|
||||
- const: qcom,x1e78100
|
||||
- const: qcom,x1e80100
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- asus,vivobook-s15
|
||||
- asus,zenbook-a14-ux3407ra
|
||||
- dell,xps13-9345
|
||||
- hp,elitebook-ultra-g1q
|
||||
- hp,omnibook-x14
|
||||
- lenovo,yoga-slim7x
|
||||
- microsoft,romulus13
|
||||
@ -1141,6 +1152,7 @@ properties:
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- asus,zenbook-a14-ux3407qa
|
||||
- qcom,x1p42100-crd
|
||||
- const: qcom,x1p42100
|
||||
|
||||
|
||||
@ -946,6 +946,11 @@ properties:
|
||||
- const: radxa,rock-5b
|
||||
- const: rockchip,rk3588
|
||||
|
||||
- description: Radxa ROCK 5B+
|
||||
items:
|
||||
- const: radxa,rock-5b-plus
|
||||
- const: rockchip,rk3588
|
||||
|
||||
- description: Radxa ROCK 5C
|
||||
items:
|
||||
- const: radxa,rock-5c
|
||||
@ -1047,6 +1052,11 @@ properties:
|
||||
- const: rockchip,rk3399-evb
|
||||
- const: rockchip,rk3399
|
||||
|
||||
- description: Rockchip RK3399 Industry Evaluation board
|
||||
items:
|
||||
- const: rockchip,rk3399-evb-ind
|
||||
- const: rockchip,rk3399
|
||||
|
||||
- description: Rockchip RK3399 Sapphire standalone
|
||||
items:
|
||||
- const: rockchip,rk3399-sapphire
|
||||
@ -1057,6 +1067,11 @@ properties:
|
||||
- const: rockchip,rk3399-sapphire-excavator
|
||||
- const: rockchip,rk3399
|
||||
|
||||
- description: Rockchip RK3562 Evaluation board 2
|
||||
items:
|
||||
- const: rockchip,rk3562-evb2-v10
|
||||
- const: rockchip,rk3562
|
||||
|
||||
- description: Rockchip RK3566 BOX Evaluation Demo board
|
||||
items:
|
||||
- const: rockchip,rk3566-box-demo
|
||||
@ -1074,7 +1089,9 @@ properties:
|
||||
|
||||
- description: Rockchip RK3588 Evaluation board
|
||||
items:
|
||||
- const: rockchip,rk3588-evb1-v10
|
||||
- enum:
|
||||
- rockchip,rk3588-evb1-v10
|
||||
- rockchip,rk3588-evb2-v10
|
||||
- const: rockchip,rk3588
|
||||
|
||||
- description: Rockchip RK3588S Evaluation board
|
||||
@ -1109,6 +1126,24 @@ properties:
|
||||
- rockchip,rv1126
|
||||
- rockchip,rv1109
|
||||
|
||||
- description: Theobroma Systems PX30-Cobra
|
||||
items:
|
||||
- enum:
|
||||
- tsd,px30-cobra-ltk050h3146w
|
||||
- tsd,px30-cobra-ltk050h3146w-a2
|
||||
- tsd,px30-cobra-ltk050h3148w
|
||||
- tsd,px30-cobra-ltk500hd1829
|
||||
- const: tsd,px30-cobra
|
||||
- const: rockchip,px30
|
||||
|
||||
- description: Theobroma Systems PX30-PP1516
|
||||
items:
|
||||
- enum:
|
||||
- tsd,px30-pp1516-ltk050h3146w-a2
|
||||
- tsd,px30-pp1516-ltk050h3148w
|
||||
- const: tsd,px30-pp1516
|
||||
- const: rockchip,px30
|
||||
|
||||
- description: Theobroma Systems PX30-uQ7 with Haikou baseboard
|
||||
items:
|
||||
- const: tsd,px30-ringneck-haikou
|
||||
|
||||
@ -25,6 +25,7 @@ select:
|
||||
- rockchip,rk3288-pmu
|
||||
- rockchip,rk3368-pmu
|
||||
- rockchip,rk3399-pmu
|
||||
- rockchip,rk3562-pmu
|
||||
- rockchip,rk3568-pmu
|
||||
- rockchip,rk3576-pmu
|
||||
- rockchip,rk3588-pmu
|
||||
@ -43,6 +44,7 @@ properties:
|
||||
- rockchip,rk3288-pmu
|
||||
- rockchip,rk3368-pmu
|
||||
- rockchip,rk3399-pmu
|
||||
- rockchip,rk3562-pmu
|
||||
- rockchip,rk3568-pmu
|
||||
- rockchip,rk3576-pmu
|
||||
- rockchip,rk3588-pmu
|
||||
|
||||
@ -212,6 +212,14 @@ properties:
|
||||
- samsung,exynos7-espresso # Samsung Exynos7 Espresso
|
||||
- const: samsung,exynos7
|
||||
|
||||
- description: Exynos7870 based boards
|
||||
items:
|
||||
- enum:
|
||||
- samsung,a2corelte # Samsung Galaxy A2 Core
|
||||
- samsung,j6lte # Samsung Galaxy J6
|
||||
- samsung,on7xelte # Samsung Galaxy J7 Prime
|
||||
- const: samsung,exynos7870
|
||||
|
||||
- description: Exynos7885 based boards
|
||||
items:
|
||||
- enum:
|
||||
|
||||
@ -188,6 +188,11 @@ properties:
|
||||
- const: phytec,phycore-stm32mp157c-som
|
||||
- const: st,stm32mp157
|
||||
|
||||
- description: Ultratronik STM32MP1 SBC based Boards
|
||||
items:
|
||||
- const: ultratronik,stm32mp157c-ultra-fly-sbc
|
||||
- const: st,stm32mp157
|
||||
|
||||
- description: ST STM32MP257 based Boards
|
||||
items:
|
||||
- enum:
|
||||
|
||||
@ -492,6 +492,11 @@ properties:
|
||||
- const: lamobo,lamobo-r1
|
||||
- const: allwinner,sun7i-a20
|
||||
|
||||
- description: Liontron H-A133L
|
||||
items:
|
||||
- const: liontron,h-a133l
|
||||
- const: allwinner,sun50i-a100
|
||||
|
||||
- description: HAOYU Electronics Marsboard A10
|
||||
items:
|
||||
- const: haoyu,a10-marsboard
|
||||
@ -845,6 +850,11 @@ properties:
|
||||
- const: allwinner,r7-tv-dongle
|
||||
- const: allwinner,sun5i-a10s
|
||||
|
||||
- description: Radxa Cubie A5E
|
||||
items:
|
||||
- const: radxa,cubie-a5e
|
||||
- const: allwinner,sun55i-a527
|
||||
|
||||
- description: Remix Mini PC
|
||||
items:
|
||||
- const: jide,remix-mini-pc
|
||||
@ -966,6 +976,11 @@ properties:
|
||||
- const: hechuang,x96-mate
|
||||
- const: allwinner,sun50i-h616
|
||||
|
||||
- description: X96Q Pro+
|
||||
items:
|
||||
- const: amediatech,x96q-pro-plus
|
||||
- const: allwinner,sun55i-h728
|
||||
|
||||
- description: Xunlong OrangePi
|
||||
items:
|
||||
- const: xunlong,orangepi
|
||||
@ -1081,4 +1096,14 @@ properties:
|
||||
- const: xunlong,orangepi-zero3
|
||||
- const: allwinner,sun50i-h618
|
||||
|
||||
- description: YuzukiHD Avaota A1
|
||||
items:
|
||||
- const: yuzukihd,avaota-a1
|
||||
- const: allwinner,sun55i-t527
|
||||
|
||||
- description: YuzukiHD Chameleon
|
||||
items:
|
||||
- const: yuzukihd,chameleon
|
||||
- const: allwinner,sun50i-h618
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
@ -52,17 +52,14 @@ properties:
|
||||
- nvidia,cardhu-a04
|
||||
- const: nvidia,cardhu
|
||||
- const: nvidia,tegra30
|
||||
- items:
|
||||
- const: asus,tf201
|
||||
- const: nvidia,tegra30
|
||||
- items:
|
||||
- const: asus,tf300t
|
||||
- const: nvidia,tegra30
|
||||
- items:
|
||||
- const: asus,tf300tg
|
||||
- const: nvidia,tegra30
|
||||
- items:
|
||||
- const: asus,tf700t
|
||||
- description: ASUS Transformers Device family
|
||||
items:
|
||||
- enum:
|
||||
- asus,tf201
|
||||
- asus,tf300t
|
||||
- asus,tf300tg
|
||||
- asus,tf300tl
|
||||
- asus,tf700t
|
||||
- const: nvidia,tegra30
|
||||
- description: LG Optimus 4X P880
|
||||
items:
|
||||
|
||||
@ -46,6 +46,7 @@ properties:
|
||||
- description: K3 AM625 SoC
|
||||
items:
|
||||
- enum:
|
||||
- beagle,am62-pocketbeagle2
|
||||
- beagle,am625-beagleplay
|
||||
- ti,am625-sk
|
||||
- ti,am62-lp-sk
|
||||
@ -75,6 +76,30 @@ properties:
|
||||
- const: toradex,verdin-am62 # Verdin AM62 Module
|
||||
- const: ti,am625
|
||||
|
||||
- description: K3 AM62P5 SoC Toradex Verdin Modules and Carrier Boards
|
||||
items:
|
||||
- enum:
|
||||
- toradex,verdin-am62p-nonwifi-dahlia # Verdin AM62P Module on Dahlia
|
||||
- toradex,verdin-am62p-nonwifi-dev # Verdin AM62P Module on Verdin Development Board
|
||||
- toradex,verdin-am62p-nonwifi-ivy # Verdin AM62P Module on Ivy
|
||||
- toradex,verdin-am62p-nonwifi-mallow # Verdin AM62P Module on Mallow
|
||||
- toradex,verdin-am62p-nonwifi-yavia # Verdin AM62P Module on Yavia
|
||||
- const: toradex,verdin-am62p-nonwifi # Verdin AM62P Module without Wi-Fi / BT
|
||||
- const: toradex,verdin-am62p # Verdin AM62P Module
|
||||
- const: ti,am62p5
|
||||
|
||||
- description: K3 AM62P5 SoC Toradex Verdin Modules and Carrier Boards with Wi-Fi / BT
|
||||
items:
|
||||
- enum:
|
||||
- toradex,verdin-am62p-wifi-dahlia # Verdin AM62P Wi-Fi / BT Module on Dahlia
|
||||
- toradex,verdin-am62p-wifi-dev # Verdin AM62P Wi-Fi / BT M. on Verdin Development B.
|
||||
- toradex,verdin-am62p-wifi-ivy # Verdin AM62P Wi-Fi / BT Module on Ivy
|
||||
- toradex,verdin-am62p-wifi-mallow # Verdin AM62P Wi-Fi / BT Module on Mallow
|
||||
- toradex,verdin-am62p-wifi-yavia # Verdin AM62P Wi-Fi / BT Module on Yavia
|
||||
- const: toradex,verdin-am62p-wifi # Verdin AM62P Wi-Fi / BT Module
|
||||
- const: toradex,verdin-am62p # Verdin AM62P Module
|
||||
- const: ti,am62p5
|
||||
|
||||
- description: K3 AM642 SoC
|
||||
items:
|
||||
- enum:
|
||||
@ -139,6 +164,13 @@ properties:
|
||||
- ti,j721s2-evm
|
||||
- const: ti,j721s2
|
||||
|
||||
- description: K3 J721s2 SoC Phytec SoM based boards
|
||||
items:
|
||||
- enum:
|
||||
- phytec,am68-phyboard-izar
|
||||
- const: phytec,am68-phycore-som
|
||||
- const: ti,j721s2
|
||||
|
||||
- description: K3 J722S SoC and Boards
|
||||
items:
|
||||
- enum:
|
||||
|
||||
@ -7,14 +7,13 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
title: VIA/Wondermedia VT8500 Platforms
|
||||
|
||||
maintainers:
|
||||
- Tony Prisk <linux@prisktech.co.nz>
|
||||
description: test
|
||||
- Alexey Charkov <alchark@gmail.com>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
items:
|
||||
oneOf:
|
||||
- enum:
|
||||
- via,vt8500
|
||||
- wm,wm8505
|
||||
@ -22,4 +21,9 @@ properties:
|
||||
- wm,wm8750
|
||||
- wm,wm8850
|
||||
|
||||
- description: VIA APC Rock and Paper boards
|
||||
items:
|
||||
- const: via,apc-rock
|
||||
- const: wm,wm8950
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
@ -1,21 +0,0 @@
|
||||
Device tree binding for the TI DM816 AHCI SATA Controller
|
||||
---------------------------------------------------------
|
||||
|
||||
Required properties:
|
||||
- compatible: must be "ti,dm816-ahci"
|
||||
- reg: physical base address and size of the register region used by
|
||||
the controller (as defined by the AHCI 1.1 standard)
|
||||
- interrupts: interrupt specifier (refer to the interrupt binding)
|
||||
- clocks: list of phandle and clock specifier pairs (or only
|
||||
phandles for clock providers with '0' defined for
|
||||
#clock-cells); two clocks must be specified: the functional
|
||||
clock and an external reference clock
|
||||
|
||||
Example:
|
||||
|
||||
sata: sata@4a140000 {
|
||||
compatible = "ti,dm816-ahci";
|
||||
reg = <0x4a140000 0x10000>;
|
||||
interrupts = <16>;
|
||||
clocks = <&sysclk5_ck>, <&sata_refclk>;
|
||||
};
|
||||
@ -1,35 +0,0 @@
|
||||
STMicroelectronics STi SATA controller
|
||||
|
||||
This binding describes a SATA device.
|
||||
|
||||
Required properties:
|
||||
- compatible : Must be "st,ahci"
|
||||
- reg : Physical base addresses and length of register sets
|
||||
- interrupts : Interrupt associated with the SATA device
|
||||
- interrupt-names : Associated name must be; "hostc"
|
||||
- clocks : The phandle for the clock
|
||||
- clock-names : Associated name must be; "ahci_clk"
|
||||
- phys : The phandle for the PHY port
|
||||
- phy-names : Associated name must be; "ahci_phy"
|
||||
|
||||
Optional properties:
|
||||
- resets : The power-down, soft-reset and power-reset lines of SATA IP
|
||||
- reset-names : Associated names must be; "pwr-dwn", "sw-rst" and "pwr-rst"
|
||||
|
||||
Example:
|
||||
|
||||
/* Example for stih407 family silicon */
|
||||
sata0: sata@9b20000 {
|
||||
compatible = "st,ahci";
|
||||
reg = <0x9b20000 0x1000>;
|
||||
interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>;
|
||||
interrupt-names = "hostc";
|
||||
phys = <&phy_port0 PHY_TYPE_SATA>;
|
||||
phy-names = "ahci_phy";
|
||||
resets = <&powerdown STIH407_SATA0_POWERDOWN>,
|
||||
<&softreset STIH407_SATA0_SOFTRESET>,
|
||||
<&softreset STIH407_SATA0_PWR_SOFTRESET>;
|
||||
reset-names = "pwr-dwn", "sw-rst", "pwr-rst";
|
||||
clocks = <&clk_s_c0_flexgen CLK_ICN_REG>;
|
||||
clock-names = "ahci_clk";
|
||||
};
|
||||
58
dts/upstream/Bindings/ata/apm,xgene-ahci.yaml
Normal file
58
dts/upstream/Bindings/ata/apm,xgene-ahci.yaml
Normal file
@ -0,0 +1,58 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/ata/apm,xgene-ahci.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: APM X-Gene 6.0 Gb/s SATA host controller
|
||||
|
||||
maintainers:
|
||||
- Rob Herring <robh@kernel.org>
|
||||
|
||||
allOf:
|
||||
- $ref: ahci-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- apm,xgene-ahci
|
||||
- apm,xgene-ahci-pcie
|
||||
|
||||
reg:
|
||||
minItems: 4
|
||||
items:
|
||||
- description: AHCI memory resource
|
||||
- description: Host controller core
|
||||
- description: Host controller diagnostic
|
||||
- description: Host controller AXI
|
||||
- description: Host controller MUX
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- phys
|
||||
- phy-names
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
sata@1a400000 {
|
||||
compatible = "apm,xgene-ahci";
|
||||
reg = <0x1a400000 0x1000>,
|
||||
<0x1f220000 0x1000>,
|
||||
<0x1f22d000 0x1000>,
|
||||
<0x1f22e000 0x1000>,
|
||||
<0x1f227000 0x1000>;
|
||||
clocks = <&sataclk 0>;
|
||||
dma-coherent;
|
||||
interrupts = <0x0 0x87 0x4>;
|
||||
phys = <&phy2 0>;
|
||||
phy-names = "sata-phy";
|
||||
};
|
||||
@ -1,77 +0,0 @@
|
||||
* APM X-Gene 6.0 Gb/s SATA host controller nodes
|
||||
|
||||
SATA host controller nodes are defined to describe on-chip Serial ATA
|
||||
controllers. Each SATA controller (pair of ports) have its own node.
|
||||
|
||||
Required properties:
|
||||
- compatible : Shall contain:
|
||||
* "apm,xgene-ahci"
|
||||
- reg : First memory resource shall be the AHCI memory
|
||||
resource.
|
||||
Second memory resource shall be the host controller
|
||||
core memory resource.
|
||||
Third memory resource shall be the host controller
|
||||
diagnostic memory resource.
|
||||
4th memory resource shall be the host controller
|
||||
AXI memory resource.
|
||||
5th optional memory resource shall be the host
|
||||
controller MUX memory resource if required.
|
||||
- interrupts : Interrupt-specifier for SATA host controller IRQ.
|
||||
- clocks : Reference to the clock entry.
|
||||
- phys : A list of phandles + phy-specifiers, one for each
|
||||
entry in phy-names.
|
||||
- phy-names : Should contain:
|
||||
* "sata-phy" for the SATA 6.0Gbps PHY
|
||||
|
||||
Optional properties:
|
||||
- dma-coherent : Present if dma operations are coherent
|
||||
- status : Shall be "ok" if enabled or "disabled" if disabled.
|
||||
Default is "ok".
|
||||
|
||||
Example:
|
||||
sataclk: sataclk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <1>;
|
||||
clock-frequency = <100000000>;
|
||||
clock-output-names = "sataclk";
|
||||
};
|
||||
|
||||
phy2: phy@1f22a000 {
|
||||
compatible = "apm,xgene-phy";
|
||||
reg = <0x0 0x1f22a000 0x0 0x100>;
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
|
||||
phy3: phy@1f23a000 {
|
||||
compatible = "apm,xgene-phy";
|
||||
reg = <0x0 0x1f23a000 0x0 0x100>;
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
|
||||
sata2: sata@1a400000 {
|
||||
compatible = "apm,xgene-ahci";
|
||||
reg = <0x0 0x1a400000 0x0 0x1000>,
|
||||
<0x0 0x1f220000 0x0 0x1000>,
|
||||
<0x0 0x1f22d000 0x0 0x1000>,
|
||||
<0x0 0x1f22e000 0x0 0x1000>,
|
||||
<0x0 0x1f227000 0x0 0x1000>;
|
||||
interrupts = <0x0 0x87 0x4>;
|
||||
dma-coherent;
|
||||
clocks = <&sataclk 0>;
|
||||
phys = <&phy2 0>;
|
||||
phy-names = "sata-phy";
|
||||
};
|
||||
|
||||
sata3: sata@1a800000 {
|
||||
compatible = "apm,xgene-ahci-pcie";
|
||||
reg = <0x0 0x1a800000 0x0 0x1000>,
|
||||
<0x0 0x1f230000 0x0 0x1000>,
|
||||
<0x0 0x1f23d000 0x0 0x1000>,
|
||||
<0x0 0x1f23e000 0x0 0x1000>,
|
||||
<0x0 0x1f237000 0x0 0x1000>;
|
||||
interrupts = <0x0 0x88 0x4>;
|
||||
dma-coherent;
|
||||
clocks = <&sataclk 0>;
|
||||
phys = <&phy3 0>;
|
||||
phy-names = "sata-phy";
|
||||
};
|
||||
70
dts/upstream/Bindings/ata/arasan,cf-spear1340.yaml
Normal file
70
dts/upstream/Bindings/ata/arasan,cf-spear1340.yaml
Normal file
@ -0,0 +1,70 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/ata/arasan,cf-spear1340.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Arasan PATA Compact Flash Controller
|
||||
|
||||
maintainers:
|
||||
- Viresh Kumar <viresh.kumar@linaro.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: arasan,cf-spear1340
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
arasan,broken-udma:
|
||||
description: UDMA mode is unusable
|
||||
type: boolean
|
||||
|
||||
arasan,broken-mwdma:
|
||||
description: MWDMA mode is unusable
|
||||
type: boolean
|
||||
|
||||
arasan,broken-pio:
|
||||
description: PIO mode is unusable
|
||||
type: boolean
|
||||
|
||||
dmas:
|
||||
maxItems: 1
|
||||
|
||||
dma-names:
|
||||
items:
|
||||
- const: data
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
not:
|
||||
required:
|
||||
- arasan,broken-udma
|
||||
- arasan,broken-mwdma
|
||||
then:
|
||||
required:
|
||||
- dmas
|
||||
- dma-names
|
||||
|
||||
examples:
|
||||
- |
|
||||
cf@fc000000 {
|
||||
compatible = "arasan,cf-spear1340";
|
||||
reg = <0xfc000000 0x1000>;
|
||||
interrupts = <12>;
|
||||
dmas = <&dma 23>;
|
||||
dma-names = "data";
|
||||
};
|
||||
59
dts/upstream/Bindings/ata/cavium,ebt3000-compact-flash.yaml
Normal file
59
dts/upstream/Bindings/ata/cavium,ebt3000-compact-flash.yaml
Normal file
@ -0,0 +1,59 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/ata/cavium,ebt3000-compact-flash.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Cavium Compact Flash
|
||||
|
||||
maintainers:
|
||||
- Rob Herring <robh@kernel.org>
|
||||
|
||||
description:
|
||||
The Cavium Compact Flash device is connected to the Octeon Boot Bus, and is
|
||||
thus a child of the Boot Bus device. It can read and write industry standard
|
||||
compact flash devices.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: cavium,ebt3000-compact-flash
|
||||
|
||||
reg:
|
||||
description: The base address of the CF chip select banks.
|
||||
items:
|
||||
- description: CF chip select bank 0
|
||||
- description: CF chip select bank 1
|
||||
|
||||
cavium,bus-width:
|
||||
description: The width of the connection to the CF devices.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [8, 16]
|
||||
|
||||
cavium,true-ide:
|
||||
description: True IDE mode when present.
|
||||
type: boolean
|
||||
|
||||
cavium,dma-engine-handle:
|
||||
description: A phandle for the DMA Engine connected to this device.
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
bus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
|
||||
compact-flash@5,0 {
|
||||
compatible = "cavium,ebt3000-compact-flash";
|
||||
reg = <5 0 0x10000>, <6 0 0x10000>;
|
||||
cavium,bus-width = <16>;
|
||||
cavium,true-ide;
|
||||
cavium,dma-engine-handle = <&dma0>;
|
||||
};
|
||||
};
|
||||
@ -1,30 +0,0 @@
|
||||
* Compact Flash
|
||||
|
||||
The Cavium Compact Flash device is connected to the Octeon Boot Bus,
|
||||
and is thus a child of the Boot Bus device. It can read and write
|
||||
industry standard compact flash devices.
|
||||
|
||||
Properties:
|
||||
- compatible: "cavium,ebt3000-compact-flash";
|
||||
|
||||
Compatibility with many Cavium evaluation boards.
|
||||
|
||||
- reg: The base address of the CF chip select banks. Depending on
|
||||
the device configuration, there may be one or two banks.
|
||||
|
||||
- cavium,bus-width: The width of the connection to the CF devices. Valid
|
||||
values are 8 and 16.
|
||||
|
||||
- cavium,true-ide: Optional, if present the CF connection is in True IDE mode.
|
||||
|
||||
- cavium,dma-engine-handle: Optional, a phandle for the DMA Engine connected
|
||||
to this device.
|
||||
|
||||
Example:
|
||||
compact-flash@5,0 {
|
||||
compatible = "cavium,ebt3000-compact-flash";
|
||||
reg = <5 0 0x10000>, <6 0 0x10000>;
|
||||
cavium,bus-width = <16>;
|
||||
cavium,true-ide;
|
||||
cavium,dma-engine-handle = <&dma0>;
|
||||
};
|
||||
83
dts/upstream/Bindings/ata/marvell,orion-sata.yaml
Normal file
83
dts/upstream/Bindings/ata/marvell,orion-sata.yaml
Normal file
@ -0,0 +1,83 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/ata/marvell,orion-sata.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Marvell Orion SATA
|
||||
|
||||
maintainers:
|
||||
- Andrew Lunn <andrew@lunn.ch>
|
||||
- Gregory Clement <gregory.clement@bootlin.com>
|
||||
|
||||
allOf:
|
||||
- $ref: sata-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- marvell,orion-sata
|
||||
- marvell,armada-370-sata
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 8
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: '0'
|
||||
- const: '1'
|
||||
- const: '2'
|
||||
- const: '3'
|
||||
- const: '4'
|
||||
- const: '5'
|
||||
- const: '6'
|
||||
- const: '7'
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
nr-ports:
|
||||
description:
|
||||
Number of SATA ports in use.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
maximum: 8
|
||||
|
||||
phys:
|
||||
minItems: 1
|
||||
maxItems: 8
|
||||
|
||||
phy-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: port0
|
||||
- const: port1
|
||||
- const: port2
|
||||
- const: port3
|
||||
- const: port4
|
||||
- const: port5
|
||||
- const: port6
|
||||
- const: port7
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- nr-ports
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
sata@80000 {
|
||||
compatible = "marvell,orion-sata";
|
||||
reg = <0x80000 0x5000>;
|
||||
interrupts = <21>;
|
||||
phys = <&sata_phy0>, <&sata_phy1>;
|
||||
phy-names = "port0", "port1";
|
||||
nr-ports = <2>;
|
||||
};
|
||||
@ -1,22 +0,0 @@
|
||||
* Marvell Orion SATA
|
||||
|
||||
Required Properties:
|
||||
- compatibility : "marvell,orion-sata" or "marvell,armada-370-sata"
|
||||
- reg : Address range of controller
|
||||
- interrupts : Interrupt controller is using
|
||||
- nr-ports : Number of SATA ports in use.
|
||||
|
||||
Optional Properties:
|
||||
- phys : List of phandles to sata phys
|
||||
- phy-names : Should be "0", "1", etc, one number per phandle
|
||||
|
||||
Example:
|
||||
|
||||
sata@80000 {
|
||||
compatible = "marvell,orion-sata";
|
||||
reg = <0x80000 0x5000>;
|
||||
interrupts = <21>;
|
||||
phys = <&sata_phy0>, <&sata_phy1>;
|
||||
phy-names = "0", "1";
|
||||
nr-ports = <2>;
|
||||
}
|
||||
@ -1,37 +0,0 @@
|
||||
* ARASAN PATA COMPACT FLASH CONTROLLER
|
||||
|
||||
Required properties:
|
||||
- compatible: "arasan,cf-spear1340"
|
||||
- reg: Address range of the CF registers
|
||||
- interrupt: Should contain the CF interrupt number
|
||||
- clock-frequency: Interface clock rate, in Hz, one of
|
||||
25000000
|
||||
33000000
|
||||
40000000
|
||||
50000000
|
||||
66000000
|
||||
75000000
|
||||
100000000
|
||||
125000000
|
||||
150000000
|
||||
166000000
|
||||
200000000
|
||||
|
||||
Optional properties:
|
||||
- arasan,broken-udma: if present, UDMA mode is unusable
|
||||
- arasan,broken-mwdma: if present, MWDMA mode is unusable
|
||||
- arasan,broken-pio: if present, PIO mode is unusable
|
||||
- dmas: one DMA channel, as described in bindings/dma/dma.txt
|
||||
required unless both UDMA and MWDMA mode are broken
|
||||
- dma-names: the corresponding channel name, must be "data"
|
||||
|
||||
Example:
|
||||
|
||||
cf@fc000000 {
|
||||
compatible = "arasan,cf-spear1340";
|
||||
reg = <0xfc000000 0x1000>;
|
||||
interrupt-parent = <&vic1>;
|
||||
interrupts = <12>;
|
||||
dmas = <&dma-controller 23>;
|
||||
dma-names = "data";
|
||||
};
|
||||
@ -20,6 +20,7 @@ select:
|
||||
contains:
|
||||
enum:
|
||||
- rockchip,rk3568-dwc-ahci
|
||||
- rockchip,rk3576-dwc-ahci
|
||||
- rockchip,rk3588-dwc-ahci
|
||||
required:
|
||||
- compatible
|
||||
@ -29,6 +30,7 @@ properties:
|
||||
items:
|
||||
- enum:
|
||||
- rockchip,rk3568-dwc-ahci
|
||||
- rockchip,rk3576-dwc-ahci
|
||||
- rockchip,rk3588-dwc-ahci
|
||||
- const: snps,dwc-ahci
|
||||
|
||||
@ -83,6 +85,7 @@ allOf:
|
||||
contains:
|
||||
enum:
|
||||
- rockchip,rk3568-dwc-ahci
|
||||
- rockchip,rk3576-dwc-ahci
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
|
||||
72
dts/upstream/Bindings/ata/st,ahci.yaml
Normal file
72
dts/upstream/Bindings/ata/st,ahci.yaml
Normal file
@ -0,0 +1,72 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/ata/st,ahci.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: STMicroelectronics STi SATA controller
|
||||
|
||||
maintainers:
|
||||
- Patrice Chotard <patrice.chotard@foss.st.com>
|
||||
|
||||
allOf:
|
||||
- $ref: ahci-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: st,ahci
|
||||
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: hostc
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: ahci_clk
|
||||
|
||||
resets:
|
||||
items:
|
||||
- description: Power-down line
|
||||
- description: Soft-reset line
|
||||
- description: Power-reset line
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: pwr-dwn
|
||||
- const: sw-rst
|
||||
- const: pwr-rst
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- interrupt-names
|
||||
- phys
|
||||
- phy-names
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
#include <dt-bindings/reset/stih407-resets.h>
|
||||
#include <dt-bindings/clock/stih407-clks.h>
|
||||
|
||||
sata@9b20000 {
|
||||
compatible = "st,ahci";
|
||||
reg = <0x9b20000 0x1000>;
|
||||
interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>;
|
||||
interrupt-names = "hostc";
|
||||
phys = <&phy_port0 PHY_TYPE_SATA>;
|
||||
phy-names = "sata-phy";
|
||||
resets = <&powerdown STIH407_SATA0_POWERDOWN>,
|
||||
<&softreset STIH407_SATA0_SOFTRESET>,
|
||||
<&softreset STIH407_SATA0_PWR_SOFTRESET>;
|
||||
reset-names = "pwr-dwn", "sw-rst", "pwr-rst";
|
||||
clocks = <&clk_s_c0_flexgen CLK_ICN_REG>;
|
||||
clock-names = "ahci_clk";
|
||||
};
|
||||
43
dts/upstream/Bindings/ata/ti,dm816-ahci.yaml
Normal file
43
dts/upstream/Bindings/ata/ti,dm816-ahci.yaml
Normal file
@ -0,0 +1,43 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/ata/ti,dm816-ahci.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: TI DM816 AHCI SATA Controller
|
||||
|
||||
maintainers:
|
||||
- Bartosz Golaszewski <brgl@bgdev.pl>
|
||||
|
||||
allOf:
|
||||
- $ref: ahci-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: ti,dm816-ahci
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: functional clock
|
||||
- description: external reference clock
|
||||
|
||||
ti,hwmods:
|
||||
const: sata
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
sata@4a140000 {
|
||||
compatible = "ti,dm816-ahci";
|
||||
reg = <0x4a140000 0x10000>;
|
||||
interrupts = <16>;
|
||||
clocks = <&sysclk5_ck>, <&sata_refclk>;
|
||||
};
|
||||
@ -10,8 +10,8 @@ maintainers:
|
||||
- Saurabh Sengar <ssengar@linux.microsoft.com>
|
||||
|
||||
description:
|
||||
VMBus is a software bus that implement the protocols for communication
|
||||
between the root or host OS and guest OSs (virtual machines).
|
||||
VMBus is a software bus that implements the protocols for communication
|
||||
between the root or host OS and guest OS'es (virtual machines).
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
@ -25,9 +25,16 @@ properties:
|
||||
'#size-cells':
|
||||
const: 1
|
||||
|
||||
dma-coherent: true
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
description: Interrupt is used to report a message from the host.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- ranges
|
||||
- interrupts
|
||||
- '#address-cells'
|
||||
- '#size-cells'
|
||||
|
||||
@ -35,6 +42,8 @@ additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
@ -49,6 +58,9 @@ examples:
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0f 0xf0000000 0x0f 0xf0000000 0x10000000>;
|
||||
dma-coherent;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_PPI 2 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -21,6 +21,7 @@ properties:
|
||||
- const: nvidia,tegra210-aconnect
|
||||
- items:
|
||||
- enum:
|
||||
- nvidia,tegra264-aconnect
|
||||
- nvidia,tegra234-aconnect
|
||||
- nvidia,tegra186-aconnect
|
||||
- nvidia,tegra194-aconnect
|
||||
|
||||
@ -28,6 +28,9 @@ select:
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- andestech,qilai-ax45mp-cache
|
||||
- renesas,r9a07g043f-ax45mp-cache
|
||||
- const: andestech,ax45mp-cache
|
||||
- const: cache
|
||||
|
||||
@ -65,12 +68,27 @@ required:
|
||||
- cache-size
|
||||
- cache-unified
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: andestech,qilai-ax45mp-cache
|
||||
|
||||
then:
|
||||
properties:
|
||||
cache-sets:
|
||||
const: 2048
|
||||
cache-size:
|
||||
const: 2097152
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
cache-controller@13400000 {
|
||||
compatible = "andestech,ax45mp-cache", "cache";
|
||||
compatible = "renesas,r9a07g043f-ax45mp-cache", "andestech,ax45mp-cache",
|
||||
"cache";
|
||||
reg = <0x13400000 0x100000>;
|
||||
interrupts = <508 IRQ_TYPE_LEVEL_HIGH>;
|
||||
cache-line-size = <64>;
|
||||
|
||||
@ -1,16 +0,0 @@
|
||||
* Marvell Feroceon Cache
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be either "marvell,feroceon-cache" or
|
||||
"marvell,kirkwood-cache".
|
||||
|
||||
Optional properties:
|
||||
- reg : Address of the L2 cache control register. Mandatory for
|
||||
"marvell,kirkwood-cache", not used by "marvell,feroceon-cache"
|
||||
|
||||
|
||||
Example:
|
||||
l2: l2-cache@20128 {
|
||||
compatible = "marvell,kirkwood-cache";
|
||||
reg = <0x20128 0x4>;
|
||||
};
|
||||
45
dts/upstream/Bindings/cache/marvell,kirkwood-cache.yaml
vendored
Normal file
45
dts/upstream/Bindings/cache/marvell,kirkwood-cache.yaml
vendored
Normal file
@ -0,0 +1,45 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/cache/marvell,kirkwood-cache.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Marvell Feroceon/Kirkwood Cache
|
||||
|
||||
maintainers:
|
||||
- Andrew Lunn <andrew@lunn.ch>
|
||||
- Gregory Clement <gregory.clement@bootlin.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- marvell,feroceon-cache
|
||||
- marvell,kirkwood-cache
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: marvell,kirkwood-cache
|
||||
then:
|
||||
required:
|
||||
- reg
|
||||
else:
|
||||
properties:
|
||||
reg: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
l2-cache@20128 {
|
||||
compatible = "marvell,kirkwood-cache";
|
||||
reg = <0x20128 0x4>;
|
||||
};
|
||||
@ -1,17 +0,0 @@
|
||||
* Marvell Tauros2 Cache
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be "marvell,tauros2-cache".
|
||||
- marvell,tauros2-cache-features : Specify the features supported for the
|
||||
tauros2 cache.
|
||||
The features including
|
||||
CACHE_TAUROS2_PREFETCH_ON (1 << 0)
|
||||
CACHE_TAUROS2_LINEFILL_BURST8 (1 << 1)
|
||||
The definition can be found at
|
||||
arch/arm/include/asm/hardware/cache-tauros2.h
|
||||
|
||||
Example:
|
||||
L2: l2-cache {
|
||||
compatible = "marvell,tauros2-cache";
|
||||
marvell,tauros2-cache-features = <0x3>;
|
||||
};
|
||||
39
dts/upstream/Bindings/cache/marvell,tauros2-cache.yaml
vendored
Normal file
39
dts/upstream/Bindings/cache/marvell,tauros2-cache.yaml
vendored
Normal file
@ -0,0 +1,39 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/cache/marvell,tauros2-cache.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Marvell Tauros2 Cache
|
||||
|
||||
maintainers:
|
||||
- Andrew Lunn <andrew@lunn.ch>
|
||||
- Gregory Clement <gregory.clement@bootlin.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: marvell,tauros2-cache
|
||||
|
||||
marvell,tauros2-cache-features:
|
||||
description: >
|
||||
Specify the features supported for the tauros2 cache. The features include:
|
||||
|
||||
- CACHE_TAUROS2_PREFETCH_ON (1 << 0)
|
||||
- CACHE_TAUROS2_LINEFILL_BURST8 (1 << 1)
|
||||
|
||||
The definition can be found at arch/arm/include/asm/hardware/cache-tauros2.h
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
maximum: 0x3
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- marvell,tauros2-cache-features
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
l2-cache {
|
||||
compatible = "marvell,tauros2-cache";
|
||||
marvell,tauros2-cache-features = <0x3>;
|
||||
};
|
||||
2
dts/upstream/Bindings/cache/qcom,llcc.yaml
vendored
2
dts/upstream/Bindings/cache/qcom,llcc.yaml
vendored
@ -40,6 +40,7 @@ properties:
|
||||
- qcom,sm8450-llcc
|
||||
- qcom,sm8550-llcc
|
||||
- qcom,sm8650-llcc
|
||||
- qcom,sm8750-llcc
|
||||
- qcom,x1e80100-llcc
|
||||
|
||||
reg:
|
||||
@ -274,6 +275,7 @@ allOf:
|
||||
- qcom,sm8450-llcc
|
||||
- qcom,sm8550-llcc
|
||||
- qcom,sm8650-llcc
|
||||
- qcom,sm8750-llcc
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
|
||||
44
dts/upstream/Bindings/cache/sifive,ccache0.yaml
vendored
44
dts/upstream/Bindings/cache/sifive,ccache0.yaml
vendored
@ -39,6 +39,7 @@ properties:
|
||||
- const: cache
|
||||
- items:
|
||||
- enum:
|
||||
- eswin,eic7700-l3-cache
|
||||
- starfive,jh7100-ccache
|
||||
- starfive,jh7110-ccache
|
||||
- const: sifive,ccache0
|
||||
@ -55,10 +56,10 @@ properties:
|
||||
enum: [2, 3]
|
||||
|
||||
cache-sets:
|
||||
enum: [1024, 2048]
|
||||
enum: [1024, 2048, 4096]
|
||||
|
||||
cache-size:
|
||||
const: 2097152
|
||||
enum: [2097152, 4194304]
|
||||
|
||||
cache-unified: true
|
||||
|
||||
@ -89,6 +90,7 @@ allOf:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- eswin,eic7700-l3-cache
|
||||
- sifive,fu740-c000-ccache
|
||||
- starfive,jh7100-ccache
|
||||
- starfive,jh7110-ccache
|
||||
@ -108,6 +110,22 @@ allOf:
|
||||
Must contain entries for DirError, DataError and DataFail signals.
|
||||
maxItems: 3
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: eswin,eic7700-l3-cache
|
||||
|
||||
then:
|
||||
properties:
|
||||
cache-size:
|
||||
const: 4194304
|
||||
|
||||
else:
|
||||
properties:
|
||||
cache-size:
|
||||
const: 2097152
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
@ -122,11 +140,31 @@ allOf:
|
||||
cache-sets:
|
||||
const: 2048
|
||||
|
||||
else:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- microchip,mpfs-ccache
|
||||
- sifive,fu540-c000-ccache
|
||||
|
||||
then:
|
||||
properties:
|
||||
cache-sets:
|
||||
const: 1024
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- eswin,eic7700-l3-cache
|
||||
|
||||
then:
|
||||
properties:
|
||||
cache-sets:
|
||||
const: 4096
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
|
||||
@ -25,6 +25,7 @@ properties:
|
||||
- const: allwinner,sun50i-a64-de2-clk
|
||||
- const: allwinner,sun50i-h5-de2-clk
|
||||
- const: allwinner,sun50i-h6-de3-clk
|
||||
- const: allwinner,sun50i-h616-de33-clk
|
||||
- items:
|
||||
- const: allwinner,sun8i-r40-de2-clk
|
||||
- const: allwinner,sun8i-h3-de2-clk
|
||||
|
||||
@ -1,30 +0,0 @@
|
||||
Device Tree Clock bindings for Altera's SoCFPGA platform
|
||||
|
||||
This binding uses the common clock binding[1].
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be one of the following:
|
||||
"altr,socfpga-pll-clock" - for a PLL clock
|
||||
"altr,socfpga-perip-clock" - The peripheral clock divided from the
|
||||
PLL clock.
|
||||
"altr,socfpga-gate-clk" - Clocks that directly feed peripherals and
|
||||
can get gated.
|
||||
|
||||
- reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.
|
||||
- clocks : shall be the input parent clock phandle for the clock. This is
|
||||
either an oscillator or a pll output.
|
||||
- #clock-cells : from common clock binding, shall be set to 0.
|
||||
|
||||
Optional properties:
|
||||
- fixed-divider : If clocks have a fixed divider value, use this property.
|
||||
- clk-gate : For "socfpga-gate-clk", clk-gate contains the gating register
|
||||
and the bit index.
|
||||
- div-reg : For "socfpga-gate-clk" and "socfpga-periph-clock", div-reg contains
|
||||
the divider register, bit shift, and width.
|
||||
- clk-phase : For the sdmmc_clk, contains the value of the clock phase that controls
|
||||
the SDMMC CIU clock. The first value is the clk_sample(smpsel), and the second
|
||||
value is the cclk_in_drv(drvsel). The clk-phase is used to enable the correct
|
||||
hold/delay times that is needed for the SD/MMC CIU clock. The values of both
|
||||
can be 0-315 degrees, in 45 degree increments.
|
||||
@ -1,31 +0,0 @@
|
||||
Broadcom BCM2835 auxiliary peripheral support
|
||||
|
||||
This binding uses the common clock binding:
|
||||
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
The auxiliary peripherals (UART, SPI1, and SPI2) have a small register
|
||||
area controlling clock gating to the peripherals, and providing an IRQ
|
||||
status register.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "brcm,bcm2835-aux"
|
||||
- #clock-cells: Should be <1>. The permitted clock-specifier values can be
|
||||
found in include/dt-bindings/clock/bcm2835-aux.h
|
||||
- reg: Specifies base physical address and size of the registers
|
||||
- clocks: The parent clock phandle
|
||||
|
||||
Example:
|
||||
|
||||
clocks: cprman@7e101000 {
|
||||
compatible = "brcm,bcm2835-cprman";
|
||||
#clock-cells = <1>;
|
||||
reg = <0x7e101000 0x2000>;
|
||||
clocks = <&clk_osc>;
|
||||
};
|
||||
|
||||
aux: aux@7e215004 {
|
||||
compatible = "brcm,bcm2835-aux";
|
||||
#clock-cells = <1>;
|
||||
reg = <0x7e215000 0x8>;
|
||||
clocks = <&clocks BCM2835_CLOCK_VPU>;
|
||||
};
|
||||
47
dts/upstream/Bindings/clock/brcm,bcm2835-aux-clock.yaml
Normal file
47
dts/upstream/Bindings/clock/brcm,bcm2835-aux-clock.yaml
Normal file
@ -0,0 +1,47 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/brcm,bcm2835-aux-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom BCM2835 auxiliary peripheral clock
|
||||
|
||||
maintainers:
|
||||
- Stefan Wahren <wahrenst@gmx.net>
|
||||
- Raspberry Pi Kernel Maintenance <kernel-list@raspberrypi.com>
|
||||
|
||||
description:
|
||||
The auxiliary peripherals (UART, SPI1, and SPI2) have a small register
|
||||
area controlling clock gating to the peripherals, and providing an IRQ
|
||||
status register.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: brcm,bcm2835-aux
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- "#clock-cells"
|
||||
- clocks
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/bcm2835.h>
|
||||
clock@7e215000 {
|
||||
compatible = "brcm,bcm2835-aux";
|
||||
reg = <0x7e215000 0x8>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&clocks BCM2835_CLOCK_VPU>;
|
||||
};
|
||||
58
dts/upstream/Bindings/clock/fsl,vf610-ccm.yaml
Normal file
58
dts/upstream/Bindings/clock/fsl,vf610-ccm.yaml
Normal file
@ -0,0 +1,58 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/fsl,vf610-ccm.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Clock for Freescale Vybrid VF610 SOC
|
||||
|
||||
description:
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/vf610-clock.h
|
||||
for the full list of VF610 clock IDs
|
||||
|
||||
maintainers:
|
||||
- Frank Li <Frank.Li@nxp.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: fsl,vf610-ccm
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: external crystal oscillator 32KHz, recommended
|
||||
- description: external crystal oscillator 24MHz, recommended
|
||||
- description: audio
|
||||
- description: enet
|
||||
minItems: 2
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: sxosc
|
||||
- const: fxosc
|
||||
- const: enet_ext
|
||||
- const: audio_ext
|
||||
minItems: 2
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@4006b000 {
|
||||
compatible = "fsl,vf610-ccm";
|
||||
reg = <0x4006b000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&sxosc>, <&fxosc>;
|
||||
clock-names = "sxosc", "fxosc";
|
||||
};
|
||||
|
||||
@ -1,114 +0,0 @@
|
||||
Binding for Maxim MAX77686/MAX77802/MAX77620 32k clock generator block
|
||||
|
||||
This is a part of device tree bindings of MAX77686/MAX77802/MAX77620
|
||||
multi-function device. More information can be found in MFD DT binding
|
||||
doc as follows:
|
||||
bindings/mfd/max77686.txt for MAX77686 and
|
||||
bindings/mfd/max77802.txt for MAX77802 and
|
||||
bindings/mfd/max77620.txt for MAX77620.
|
||||
|
||||
The MAX77686 contains three 32.768khz clock outputs that can be controlled
|
||||
(gated/ungated) over I2C. Clocks are defined as preprocessor macros in
|
||||
dt-bindings/clock/maxim,max77686.h.
|
||||
|
||||
|
||||
The MAX77802 contains two 32.768khz clock outputs that can be controlled
|
||||
(gated/ungated) over I2C. Clocks are defined as preprocessor macros in
|
||||
dt-bindings/clock/maxim,max77802.h.
|
||||
|
||||
The MAX77686 contains one 32.768khz clock outputs that can be controlled
|
||||
(gated/ungated) over I2C. Clocks are defined as preprocessor macros in
|
||||
dt-bindings/clock/maxim,max77620.h.
|
||||
|
||||
Following properties should be presend in main device node of the MFD chip.
|
||||
|
||||
Required properties:
|
||||
|
||||
- #clock-cells: from common clock binding; shall be set to 1.
|
||||
|
||||
Optional properties:
|
||||
- clock-output-names: From common clock binding.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. Following indices are allowed:
|
||||
- 0: 32khz_ap clock (max77686, max77802), 32khz_out0 (max77620)
|
||||
- 1: 32khz_cp clock (max77686, max77802),
|
||||
- 2: 32khz_pmic clock (max77686).
|
||||
|
||||
Clocks are defined as preprocessor macros in above dt-binding header for
|
||||
respective chips.
|
||||
|
||||
Example:
|
||||
|
||||
1. With MAX77686:
|
||||
|
||||
#include <dt-bindings/clock/maxim,max77686.h>
|
||||
/* ... */
|
||||
|
||||
Node of the MFD chip
|
||||
max77686: max77686@9 {
|
||||
compatible = "maxim,max77686";
|
||||
interrupt-parent = <&wakeup_eint>;
|
||||
interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
|
||||
reg = <0x09>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
/* ... */
|
||||
};
|
||||
|
||||
Clock consumer node
|
||||
|
||||
foo@0 {
|
||||
compatible = "bar,foo";
|
||||
/* ... */
|
||||
clock-names = "my-clock";
|
||||
clocks = <&max77686 MAX77686_CLK_PMIC>;
|
||||
};
|
||||
|
||||
2. With MAX77802:
|
||||
|
||||
#include <dt-bindings/clock/maxim,max77802.h>
|
||||
/* ... */
|
||||
|
||||
Node of the MFD chip
|
||||
max77802: max77802@9 {
|
||||
compatible = "maxim,max77802";
|
||||
interrupt-parent = <&wakeup_eint>;
|
||||
interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
|
||||
reg = <0x09>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
/* ... */
|
||||
};
|
||||
|
||||
Clock consumer node
|
||||
|
||||
foo@0 {
|
||||
compatible = "bar,foo";
|
||||
/* ... */
|
||||
clock-names = "my-clock";
|
||||
clocks = <&max77802 MAX77802_CLK_32K_AP>;
|
||||
};
|
||||
|
||||
|
||||
3. With MAX77620:
|
||||
|
||||
#include <dt-bindings/clock/maxim,max77620.h>
|
||||
/* ... */
|
||||
|
||||
Node of the MFD chip
|
||||
max77620: max77620@3c {
|
||||
compatible = "maxim,max77620";
|
||||
reg = <0x3c>;
|
||||
#clock-cells = <1>;
|
||||
/* ... */
|
||||
};
|
||||
|
||||
Clock consumer node
|
||||
|
||||
foo@0 {
|
||||
compatible = "bar,foo";
|
||||
/* ... */
|
||||
clock-names = "my-clock";
|
||||
clocks = <&max77620 MAX77620_CLK_32K_OUT0>;
|
||||
};
|
||||
@ -52,6 +52,9 @@ properties:
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
@ -14,6 +14,7 @@ description: |
|
||||
domains on Qualcomm SoCs.
|
||||
|
||||
See also::
|
||||
include/dt-bindings/clock/qcom,sm6350-videocc.h
|
||||
include/dt-bindings/clock/qcom,videocc-sc7180.h
|
||||
include/dt-bindings/clock/qcom,videocc-sc7280.h
|
||||
include/dt-bindings/clock/qcom,videocc-sdm845.h
|
||||
@ -26,6 +27,7 @@ properties:
|
||||
- qcom,sc7180-videocc
|
||||
- qcom,sc7280-videocc
|
||||
- qcom,sdm845-videocc
|
||||
- qcom,sm6350-videocc
|
||||
- qcom,sm8150-videocc
|
||||
- qcom,sm8250-videocc
|
||||
|
||||
@ -87,6 +89,24 @@ allOf:
|
||||
- const: bi_tcxo
|
||||
- const: bi_tcxo_ao
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sm6350-videocc
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: Video AHB clock from GCC
|
||||
- description: Board XO source
|
||||
- description: Sleep Clock source
|
||||
clock-names:
|
||||
items:
|
||||
- const: iface
|
||||
- const: bi_tcxo
|
||||
- const: sleep_clk
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
|
||||
@ -4,13 +4,13 @@
|
||||
$id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Renesas RZ/{G3E,V2H(P)} Clock Pulse Generator (CPG)
|
||||
title: Renesas RZ/{G3E,V2H(P),V2N} Clock Pulse Generator (CPG)
|
||||
|
||||
maintainers:
|
||||
- Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
|
||||
|
||||
description:
|
||||
On Renesas RZ/{G3E,V2H(P)} SoCs, the CPG (Clock Pulse Generator) handles
|
||||
On Renesas RZ/{G3E,V2H(P),V2N} SoCs, the CPG (Clock Pulse Generator) handles
|
||||
generation and control of clock signals for the IP modules, generation and
|
||||
control of resets, and control over booting, low power consumption and power
|
||||
supply domains.
|
||||
@ -19,6 +19,7 @@ properties:
|
||||
compatible:
|
||||
enum:
|
||||
- renesas,r9a09g047-cpg # RZ/G3E
|
||||
- renesas,r9a09g056-cpg # RZ/V2N
|
||||
- renesas,r9a09g057-cpg # RZ/V2H
|
||||
|
||||
reg:
|
||||
|
||||
@ -8,6 +8,7 @@ title: Samsung ExynosAuto v920 SoC clock controller
|
||||
|
||||
maintainers:
|
||||
- Sunyeal Hong <sunyeal.hong@samsung.com>
|
||||
- Shin Son <shin.son@samsung.com>
|
||||
- Chanwoo Choi <cw00.choi@samsung.com>
|
||||
- Krzysztof Kozlowski <krzk@kernel.org>
|
||||
- Sylwester Nawrocki <s.nawrocki@samsung.com>
|
||||
@ -32,6 +33,9 @@ properties:
|
||||
compatible:
|
||||
enum:
|
||||
- samsung,exynosautov920-cmu-top
|
||||
- samsung,exynosautov920-cmu-cpucl0
|
||||
- samsung,exynosautov920-cmu-cpucl1
|
||||
- samsung,exynosautov920-cmu-cpucl2
|
||||
- samsung,exynosautov920-cmu-peric0
|
||||
- samsung,exynosautov920-cmu-peric1
|
||||
- samsung,exynosautov920-cmu-misc
|
||||
@ -69,6 +73,71 @@ allOf:
|
||||
items:
|
||||
- const: oscclk
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- samsung,exynosautov920-cmu-cpucl0
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (38.4 MHz)
|
||||
- description: CMU_CPUCL0 SWITCH clock (from CMU_TOP)
|
||||
- description: CMU_CPUCL0 CLUSTER clock (from CMU_TOP)
|
||||
- description: CMU_CPUCL0 DBG clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: switch
|
||||
- const: cluster
|
||||
- const: dbg
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- samsung,exynosautov920-cmu-cpucl1
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (38.4 MHz)
|
||||
- description: CMU_CPUCL1 SWITCH clock (from CMU_TOP)
|
||||
- description: CMU_CPUCL1 CLUSTER clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: switch
|
||||
- const: cluster
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- samsung,exynosautov920-cmu-cpucl2
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (38.4 MHz)
|
||||
- description: CMU_CPUCL2 SWITCH clock (from CMU_TOP)
|
||||
- description: CMU_CPUCL2 CLUSTER clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: switch
|
||||
- const: cluster
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
|
||||
@ -11,10 +11,18 @@ maintainers:
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- sophgo,cv1800-clk
|
||||
- sophgo,cv1810-clk
|
||||
- sophgo,sg2000-clk
|
||||
oneOf:
|
||||
- enum:
|
||||
- sophgo,cv1800b-clk
|
||||
- sophgo,cv1812h-clk
|
||||
- sophgo,sg2000-clk
|
||||
- items:
|
||||
- const: sophgo,sg2002-clk
|
||||
- const: sophgo,sg2000-clk
|
||||
- const: sophgo,cv1800-clk
|
||||
deprecated: true
|
||||
- const: sophgo,cv1810-clk
|
||||
deprecated: true
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
99
dts/upstream/Bindings/clock/sophgo,sg2044-clk.yaml
Normal file
99
dts/upstream/Bindings/clock/sophgo,sg2044-clk.yaml
Normal file
@ -0,0 +1,99 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/sophgo,sg2044-clk.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Sophgo SG2044 Clock Controller
|
||||
|
||||
maintainers:
|
||||
- Inochi Amaoto <inochiama@gmail.com>
|
||||
|
||||
description: |
|
||||
The Sophgo SG2044 clock controller requires an external oscillator
|
||||
as input clock.
|
||||
|
||||
All available clocks are defined as preprocessor macros in
|
||||
include/dt-bindings/clock/sophgo,sg2044-clk.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: sophgo,sg2044-clk
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: fpll0
|
||||
- description: fpll1
|
||||
- description: fpll2
|
||||
- description: dpll0
|
||||
- description: dpll1
|
||||
- description: dpll2
|
||||
- description: dpll3
|
||||
- description: dpll4
|
||||
- description: dpll5
|
||||
- description: dpll6
|
||||
- description: dpll7
|
||||
- description: mpll0
|
||||
- description: mpll1
|
||||
- description: mpll2
|
||||
- description: mpll3
|
||||
- description: mpll4
|
||||
- description: mpll5
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: fpll0
|
||||
- const: fpll1
|
||||
- const: fpll2
|
||||
- const: dpll0
|
||||
- const: dpll1
|
||||
- const: dpll2
|
||||
- const: dpll3
|
||||
- const: dpll4
|
||||
- const: dpll5
|
||||
- const: dpll6
|
||||
- const: dpll7
|
||||
- const: mpll0
|
||||
- const: mpll1
|
||||
- const: mpll2
|
||||
- const: mpll3
|
||||
- const: mpll4
|
||||
- const: mpll5
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/sophgo,sg2044-pll.h>
|
||||
|
||||
clock-controller@50002000 {
|
||||
compatible = "sophgo,sg2044-clk";
|
||||
reg = <0x50002000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&syscon CLK_FPLL0>, <&syscon CLK_FPLL1>,
|
||||
<&syscon CLK_FPLL2>, <&syscon CLK_DPLL0>,
|
||||
<&syscon CLK_DPLL1>, <&syscon CLK_DPLL2>,
|
||||
<&syscon CLK_DPLL3>, <&syscon CLK_DPLL4>,
|
||||
<&syscon CLK_DPLL5>, <&syscon CLK_DPLL6>,
|
||||
<&syscon CLK_DPLL7>, <&syscon CLK_MPLL0>,
|
||||
<&syscon CLK_MPLL1>, <&syscon CLK_MPLL2>,
|
||||
<&syscon CLK_MPLL3>, <&syscon CLK_MPLL4>,
|
||||
<&syscon CLK_MPLL5>;
|
||||
clock-names = "fpll0", "fpll1", "fpll2", "dpll0",
|
||||
"dpll1", "dpll2", "dpll3", "dpll4",
|
||||
"dpll5", "dpll6", "dpll7", "mpll0",
|
||||
"mpll1", "mpll2", "mpll3", "mpll4",
|
||||
"mpll5";
|
||||
};
|
||||
50
dts/upstream/Bindings/clock/spacemit,k1-pll.yaml
Normal file
50
dts/upstream/Bindings/clock/spacemit,k1-pll.yaml
Normal file
@ -0,0 +1,50 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/spacemit,k1-pll.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: SpacemiT K1 PLL
|
||||
|
||||
maintainers:
|
||||
- Haylen Chu <heylenay@4d2.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: spacemit,k1-pll
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
description: External 24MHz oscillator
|
||||
|
||||
spacemit,mpmu:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
Phandle to the "Main PMU (MPMU)" syscon. It is used to check PLL
|
||||
lock status.
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
description:
|
||||
See <dt-bindings/clock/spacemit,k1-syscon.h> for valid indices.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- spacemit,mpmu
|
||||
- "#clock-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@d4090000 {
|
||||
compatible = "spacemit,k1-pll";
|
||||
reg = <0xd4090000 0x1000>;
|
||||
clocks = <&vctcxo_24m>;
|
||||
spacemit,mpmu = <&sysctl_mpmu>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
@ -1,71 +0,0 @@
|
||||
STMicroelectronics STM32H7 Reset and Clock Controller
|
||||
=====================================================
|
||||
|
||||
The RCC IP is both a reset and a clock controller.
|
||||
|
||||
Please refer to clock-bindings.txt for common clock controller binding usage.
|
||||
Please also refer to reset.txt for common reset controller binding usage.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be:
|
||||
"st,stm32h743-rcc"
|
||||
|
||||
- reg: should be register base and length as documented in the
|
||||
datasheet
|
||||
|
||||
- #reset-cells: 1, see below
|
||||
|
||||
- #clock-cells : from common clock binding; shall be set to 1
|
||||
|
||||
- clocks: External oscillator clock phandle
|
||||
- high speed external clock signal (HSE)
|
||||
- low speed external clock signal (LSE)
|
||||
- external I2S clock (I2S_CKIN)
|
||||
|
||||
Optional properties:
|
||||
- st,syscfg: phandle for pwrcfg, mandatory to disable/enable backup domain
|
||||
write protection (RTC clock).
|
||||
|
||||
Example:
|
||||
|
||||
rcc: reset-clock-controller@58024400 {
|
||||
compatible = "st,stm32h743-rcc", "st,stm32-rcc";
|
||||
reg = <0x58024400 0x400>;
|
||||
#reset-cells = <1>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s_ckin>;
|
||||
|
||||
st,syscfg = <&pwrcfg>;
|
||||
};
|
||||
|
||||
The peripheral clock consumer should specify the desired clock by
|
||||
having the clock ID in its "clocks" phandle cell.
|
||||
|
||||
Example:
|
||||
|
||||
timer5: timer@40000c00 {
|
||||
compatible = "st,stm32-timer";
|
||||
reg = <0x40000c00 0x400>;
|
||||
interrupts = <50>;
|
||||
clocks = <&rcc TIM5_CK>;
|
||||
};
|
||||
|
||||
Specifying softreset control of devices
|
||||
=======================================
|
||||
|
||||
Device nodes should specify the reset channel required in their "resets"
|
||||
property, containing a phandle to the reset device node and an index specifying
|
||||
which channel to use.
|
||||
The index is the bit number within the RCC registers bank, starting from RCC
|
||||
base address.
|
||||
It is calculated as: index = register_offset / 4 * 32 + bit_offset.
|
||||
Where bit_offset is the bit offset within the register.
|
||||
|
||||
For example, for CRC reset:
|
||||
crc = AHB4RSTR_offset / 4 * 32 + CRCRST_bit_offset = 0x88 / 4 * 32 + 19 = 1107
|
||||
|
||||
Example:
|
||||
|
||||
timer2 {
|
||||
resets = <&rcc STM32H7_APB1L_RESET(TIM2)>;
|
||||
};
|
||||
@ -8,7 +8,8 @@ title: T-HEAD TH1520 AP sub-system clock controller
|
||||
|
||||
description: |
|
||||
The T-HEAD TH1520 AP sub-system clock controller configures the
|
||||
CPU, DPU, GMAC and TEE PLLs.
|
||||
CPU, DPU, GMAC and TEE PLLs. Additionally the VO subsystem configures
|
||||
the clock gates for the HDMI, MIPI and the GPU.
|
||||
|
||||
SoC reference manual
|
||||
https://openbeagle.org/beaglev-ahead/beaglev-ahead/-/blob/main/docs/TH1520%20System%20User%20Manual.pdf
|
||||
@ -20,14 +21,24 @@ maintainers:
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: thead,th1520-clk-ap
|
||||
enum:
|
||||
- thead,th1520-clk-ap
|
||||
- thead,th1520-clk-vo
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: main oscillator (24MHz)
|
||||
- description: |
|
||||
One input clock:
|
||||
- For "thead,th1520-clk-ap": the clock input must be the 24 MHz
|
||||
main oscillator.
|
||||
- For "thead,th1520-clk-vo": the clock input must be the VIDEO_PLL,
|
||||
which is configured by the AP clock controller. According to the
|
||||
TH1520 manual, VIDEO_PLL is a Silicon Creations Sigma-Delta PLL
|
||||
(integer PLL) typically running at 792 MHz (FOUTPOSTDIV), with
|
||||
a maximum FOUTVCO of 2376 MHz.
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
@ -1,41 +0,0 @@
|
||||
* Clock bindings for Freescale Vybrid VF610 SOC
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "fsl,vf610-ccm"
|
||||
- reg: Address and length of the register set
|
||||
- #clock-cells: Should be <1>
|
||||
|
||||
Optional properties:
|
||||
- clocks: list of clock identifiers which are external input clocks to the
|
||||
given clock controller. Please refer the next section to find
|
||||
the input clocks for a given controller.
|
||||
- clock-names: list of names of clocks which are external input clocks to the
|
||||
given clock controller.
|
||||
|
||||
Input clocks for top clock controller:
|
||||
- sxosc (external crystal oscillator 32KHz, recommended)
|
||||
- fxosc (external crystal oscillator 24MHz, recommended)
|
||||
- audio_ext
|
||||
- enet_ext
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/vf610-clock.h
|
||||
for the full list of VF610 clock IDs.
|
||||
|
||||
Examples:
|
||||
|
||||
clks: ccm@4006b000 {
|
||||
compatible = "fsl,vf610-ccm";
|
||||
reg = <0x4006b000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&sxosc>, <&fxosc>;
|
||||
clock-names = "sxosc", "fxosc";
|
||||
};
|
||||
|
||||
uart1: serial@40028000 {
|
||||
compatible = "fsl,vf610-uart";
|
||||
reg = <0x40028000 0x1000>;
|
||||
interrupts = <0 62 0x04>;
|
||||
clocks = <&clks VF610_CLK_UART1>;
|
||||
clock-names = "ipg";
|
||||
};
|
||||
36
dts/upstream/Bindings/counter/fsl,ftm-quaddec.yaml
Normal file
36
dts/upstream/Bindings/counter/fsl,ftm-quaddec.yaml
Normal file
@ -0,0 +1,36 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/counter/fsl,ftm-quaddec.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: FlexTimer Quadrature decoder counter
|
||||
|
||||
description:
|
||||
Exposes a simple counter for the quadrature decoder mode.
|
||||
|
||||
maintainers:
|
||||
- Frank Li <Frank.li@nxp.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: fsl,ftm-quaddec
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
big-endian: true
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
counter@29d0000 {
|
||||
compatible = "fsl,ftm-quaddec";
|
||||
reg = <0x29d0000 0x10000>;
|
||||
big-endian;
|
||||
};
|
||||
@ -1,18 +0,0 @@
|
||||
FlexTimer Quadrature decoder counter
|
||||
|
||||
This driver exposes a simple counter for the quadrature decoder mode.
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be "fsl,ftm-quaddec".
|
||||
- reg: Must be set to the memory region of the flextimer.
|
||||
|
||||
Optional property:
|
||||
- big-endian: Access the device registers in big-endian mode.
|
||||
|
||||
Example:
|
||||
counter0: counter@29d0000 {
|
||||
compatible = "fsl,ftm-quaddec";
|
||||
reg = <0x0 0x29d0000 0x0 0x10000>;
|
||||
big-endian;
|
||||
status = "disabled";
|
||||
};
|
||||
@ -1,553 +0,0 @@
|
||||
===========================================
|
||||
CPU topology binding description
|
||||
===========================================
|
||||
|
||||
===========================================
|
||||
1 - Introduction
|
||||
===========================================
|
||||
|
||||
In a SMP system, the hierarchy of CPUs is defined through three entities that
|
||||
are used to describe the layout of physical CPUs in the system:
|
||||
|
||||
- socket
|
||||
- cluster
|
||||
- core
|
||||
- thread
|
||||
|
||||
The bottom hierarchy level sits at core or thread level depending on whether
|
||||
symmetric multi-threading (SMT) is supported or not.
|
||||
|
||||
For instance in a system where CPUs support SMT, "cpu" nodes represent all
|
||||
threads existing in the system and map to the hierarchy level "thread" above.
|
||||
In systems where SMT is not supported "cpu" nodes represent all cores present
|
||||
in the system and map to the hierarchy level "core" above.
|
||||
|
||||
CPU topology bindings allow one to associate cpu nodes with hierarchical groups
|
||||
corresponding to the system hierarchy; syntactically they are defined as device
|
||||
tree nodes.
|
||||
|
||||
Currently, only ARM/RISC-V intend to use this cpu topology binding but it may be
|
||||
used for any other architecture as well.
|
||||
|
||||
The cpu nodes, as per bindings defined in [4], represent the devices that
|
||||
correspond to physical CPUs and are to be mapped to the hierarchy levels.
|
||||
|
||||
A topology description containing phandles to cpu nodes that are not compliant
|
||||
with bindings standardized in [4] is therefore considered invalid.
|
||||
|
||||
===========================================
|
||||
2 - cpu-map node
|
||||
===========================================
|
||||
|
||||
The ARM/RISC-V CPU topology is defined within the cpu-map node, which is a direct
|
||||
child of the cpus node and provides a container where the actual topology
|
||||
nodes are listed.
|
||||
|
||||
- cpu-map node
|
||||
|
||||
Usage: Optional - On SMP systems provide CPUs topology to the OS.
|
||||
Uniprocessor systems do not require a topology
|
||||
description and therefore should not define a
|
||||
cpu-map node.
|
||||
|
||||
Description: The cpu-map node is just a container node where its
|
||||
subnodes describe the CPU topology.
|
||||
|
||||
Node name must be "cpu-map".
|
||||
|
||||
The cpu-map node's parent node must be the cpus node.
|
||||
|
||||
The cpu-map node's child nodes can be:
|
||||
|
||||
- one or more cluster nodes or
|
||||
- one or more socket nodes in a multi-socket system
|
||||
|
||||
Any other configuration is considered invalid.
|
||||
|
||||
The cpu-map node can only contain 4 types of child nodes:
|
||||
|
||||
- socket node
|
||||
- cluster node
|
||||
- core node
|
||||
- thread node
|
||||
|
||||
whose bindings are described in paragraph 3.
|
||||
|
||||
The nodes describing the CPU topology (socket/cluster/core/thread) can
|
||||
only be defined within the cpu-map node and every core/thread in the
|
||||
system must be defined within the topology. Any other configuration is
|
||||
invalid and therefore must be ignored.
|
||||
|
||||
===========================================
|
||||
2.1 - cpu-map child nodes naming convention
|
||||
===========================================
|
||||
|
||||
cpu-map child nodes must follow a naming convention where the node name
|
||||
must be "socketN", "clusterN", "coreN", "threadN" depending on the node type
|
||||
(ie socket/cluster/core/thread) (where N = {0, 1, ...} is the node number; nodes
|
||||
which are siblings within a single common parent node must be given a unique and
|
||||
sequential N value, starting from 0).
|
||||
cpu-map child nodes which do not share a common parent node can have the same
|
||||
name (ie same number N as other cpu-map child nodes at different device tree
|
||||
levels) since name uniqueness will be guaranteed by the device tree hierarchy.
|
||||
|
||||
===========================================
|
||||
3 - socket/cluster/core/thread node bindings
|
||||
===========================================
|
||||
|
||||
Bindings for socket/cluster/cpu/thread nodes are defined as follows:
|
||||
|
||||
- socket node
|
||||
|
||||
Description: must be declared within a cpu-map node, one node
|
||||
per physical socket in the system. A system can
|
||||
contain single or multiple physical socket.
|
||||
The association of sockets and NUMA nodes is beyond
|
||||
the scope of this bindings, please refer [2] for
|
||||
NUMA bindings.
|
||||
|
||||
This node is optional for a single socket system.
|
||||
|
||||
The socket node name must be "socketN" as described in 2.1 above.
|
||||
A socket node can not be a leaf node.
|
||||
|
||||
A socket node's child nodes must be one or more cluster nodes.
|
||||
|
||||
Any other configuration is considered invalid.
|
||||
|
||||
- cluster node
|
||||
|
||||
Description: must be declared within a cpu-map node, one node
|
||||
per cluster. A system can contain several layers of
|
||||
clustering within a single physical socket and cluster
|
||||
nodes can be contained in parent cluster nodes.
|
||||
|
||||
The cluster node name must be "clusterN" as described in 2.1 above.
|
||||
A cluster node can not be a leaf node.
|
||||
|
||||
A cluster node's child nodes must be:
|
||||
|
||||
- one or more cluster nodes; or
|
||||
- one or more core nodes
|
||||
|
||||
Any other configuration is considered invalid.
|
||||
|
||||
- core node
|
||||
|
||||
Description: must be declared in a cluster node, one node per core in
|
||||
the cluster. If the system does not support SMT, core
|
||||
nodes are leaf nodes, otherwise they become containers of
|
||||
thread nodes.
|
||||
|
||||
The core node name must be "coreN" as described in 2.1 above.
|
||||
|
||||
A core node must be a leaf node if SMT is not supported.
|
||||
|
||||
Properties for core nodes that are leaf nodes:
|
||||
|
||||
- cpu
|
||||
Usage: required
|
||||
Value type: <phandle>
|
||||
Definition: a phandle to the cpu node that corresponds to the
|
||||
core node.
|
||||
|
||||
If a core node is not a leaf node (CPUs supporting SMT) a core node's
|
||||
child nodes can be:
|
||||
|
||||
- one or more thread nodes
|
||||
|
||||
Any other configuration is considered invalid.
|
||||
|
||||
- thread node
|
||||
|
||||
Description: must be declared in a core node, one node per thread
|
||||
in the core if the system supports SMT. Thread nodes are
|
||||
always leaf nodes in the device tree.
|
||||
|
||||
The thread node name must be "threadN" as described in 2.1 above.
|
||||
|
||||
A thread node must be a leaf node.
|
||||
|
||||
A thread node must contain the following property:
|
||||
|
||||
- cpu
|
||||
Usage: required
|
||||
Value type: <phandle>
|
||||
Definition: a phandle to the cpu node that corresponds to
|
||||
the thread node.
|
||||
|
||||
===========================================
|
||||
4 - Example dts
|
||||
===========================================
|
||||
|
||||
Example 1 (ARM 64-bit, 16-cpu system, two clusters of clusters in a single
|
||||
physical socket):
|
||||
|
||||
cpus {
|
||||
#size-cells = <0>;
|
||||
#address-cells = <2>;
|
||||
|
||||
cpu-map {
|
||||
socket0 {
|
||||
cluster0 {
|
||||
cluster0 {
|
||||
core0 {
|
||||
thread0 {
|
||||
cpu = <&CPU0>;
|
||||
};
|
||||
thread1 {
|
||||
cpu = <&CPU1>;
|
||||
};
|
||||
};
|
||||
|
||||
core1 {
|
||||
thread0 {
|
||||
cpu = <&CPU2>;
|
||||
};
|
||||
thread1 {
|
||||
cpu = <&CPU3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cluster1 {
|
||||
core0 {
|
||||
thread0 {
|
||||
cpu = <&CPU4>;
|
||||
};
|
||||
thread1 {
|
||||
cpu = <&CPU5>;
|
||||
};
|
||||
};
|
||||
|
||||
core1 {
|
||||
thread0 {
|
||||
cpu = <&CPU6>;
|
||||
};
|
||||
thread1 {
|
||||
cpu = <&CPU7>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cluster1 {
|
||||
cluster0 {
|
||||
core0 {
|
||||
thread0 {
|
||||
cpu = <&CPU8>;
|
||||
};
|
||||
thread1 {
|
||||
cpu = <&CPU9>;
|
||||
};
|
||||
};
|
||||
core1 {
|
||||
thread0 {
|
||||
cpu = <&CPU10>;
|
||||
};
|
||||
thread1 {
|
||||
cpu = <&CPU11>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cluster1 {
|
||||
core0 {
|
||||
thread0 {
|
||||
cpu = <&CPU12>;
|
||||
};
|
||||
thread1 {
|
||||
cpu = <&CPU13>;
|
||||
};
|
||||
};
|
||||
core1 {
|
||||
thread0 {
|
||||
cpu = <&CPU14>;
|
||||
};
|
||||
thread1 {
|
||||
cpu = <&CPU15>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
CPU0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x0>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
CPU1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x1>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
CPU2: cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x100>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
CPU3: cpu@101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x101>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
CPU4: cpu@10000 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x10000>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
CPU5: cpu@10001 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x10001>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
CPU6: cpu@10100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x10100>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
CPU7: cpu@10101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x10101>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
CPU8: cpu@100000000 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x1 0x0>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
CPU9: cpu@100000001 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x1 0x1>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
CPU10: cpu@100000100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x1 0x100>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
CPU11: cpu@100000101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x1 0x101>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
CPU12: cpu@100010000 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x1 0x10000>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
CPU13: cpu@100010001 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x1 0x10001>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
CPU14: cpu@100010100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x1 0x10100>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
CPU15: cpu@100010101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x1 0x10101>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
};
|
||||
|
||||
Example 2 (ARM 32-bit, dual-cluster, 8-cpu system, no SMT):
|
||||
|
||||
cpus {
|
||||
#size-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
|
||||
cpu-map {
|
||||
cluster0 {
|
||||
core0 {
|
||||
cpu = <&CPU0>;
|
||||
};
|
||||
core1 {
|
||||
cpu = <&CPU1>;
|
||||
};
|
||||
core2 {
|
||||
cpu = <&CPU2>;
|
||||
};
|
||||
core3 {
|
||||
cpu = <&CPU3>;
|
||||
};
|
||||
};
|
||||
|
||||
cluster1 {
|
||||
core0 {
|
||||
cpu = <&CPU4>;
|
||||
};
|
||||
core1 {
|
||||
cpu = <&CPU5>;
|
||||
};
|
||||
core2 {
|
||||
cpu = <&CPU6>;
|
||||
};
|
||||
core3 {
|
||||
cpu = <&CPU7>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
CPU0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x0>;
|
||||
};
|
||||
|
||||
CPU1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x1>;
|
||||
};
|
||||
|
||||
CPU2: cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x2>;
|
||||
};
|
||||
|
||||
CPU3: cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x3>;
|
||||
};
|
||||
|
||||
CPU4: cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x100>;
|
||||
};
|
||||
|
||||
CPU5: cpu@101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x101>;
|
||||
};
|
||||
|
||||
CPU6: cpu@102 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x102>;
|
||||
};
|
||||
|
||||
CPU7: cpu@103 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x103>;
|
||||
};
|
||||
};
|
||||
|
||||
Example 3: HiFive Unleashed (RISC-V 64 bit, 4 core system)
|
||||
|
||||
{
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
compatible = "sifive,fu540g", "sifive,fu500";
|
||||
model = "sifive,hifive-unleashed-a00";
|
||||
|
||||
...
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cpu-map {
|
||||
socket0 {
|
||||
cluster0 {
|
||||
core0 {
|
||||
cpu = <&CPU1>;
|
||||
};
|
||||
core1 {
|
||||
cpu = <&CPU2>;
|
||||
};
|
||||
core2 {
|
||||
cpu0 = <&CPU2>;
|
||||
};
|
||||
core3 {
|
||||
cpu0 = <&CPU3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
CPU1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "sifive,rocket0", "riscv";
|
||||
reg = <0x1>;
|
||||
}
|
||||
|
||||
CPU2: cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "sifive,rocket0", "riscv";
|
||||
reg = <0x2>;
|
||||
}
|
||||
CPU3: cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "sifive,rocket0", "riscv";
|
||||
reg = <0x3>;
|
||||
}
|
||||
CPU4: cpu@4 {
|
||||
device_type = "cpu";
|
||||
compatible = "sifive,rocket0", "riscv";
|
||||
reg = <0x4>;
|
||||
}
|
||||
}
|
||||
};
|
||||
===============================================================================
|
||||
[1] ARM Linux kernel documentation
|
||||
Documentation/devicetree/bindings/arm/cpus.yaml
|
||||
[2] Devicetree NUMA binding description
|
||||
Documentation/devicetree/bindings/numa.txt
|
||||
[3] RISC-V Linux kernel documentation
|
||||
Documentation/devicetree/bindings/riscv/cpus.yaml
|
||||
[4] https://www.devicetree.org/specifications/
|
||||
@ -1,250 +0,0 @@
|
||||
Binding for MediaTek's CPUFreq driver
|
||||
=====================================
|
||||
|
||||
Required properties:
|
||||
- clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names.
|
||||
- clock-names: Should contain the following:
|
||||
"cpu" - The multiplexer for clock input of CPU cluster.
|
||||
"intermediate" - A parent of "cpu" clock which is used as "intermediate" clock
|
||||
source (usually MAINPLL) when the original CPU PLL is under
|
||||
transition and not stable yet.
|
||||
Please refer to Documentation/devicetree/bindings/clock/clock-bindings.txt for
|
||||
generic clock consumer properties.
|
||||
- operating-points-v2: Please refer to Documentation/devicetree/bindings/opp/opp-v2.yaml
|
||||
for detail.
|
||||
- proc-supply: Regulator for Vproc of CPU cluster.
|
||||
|
||||
Optional properties:
|
||||
- sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver
|
||||
needs to do "voltage tracking" to step by step scale up/down Vproc and
|
||||
Vsram to fit SoC specific needs. When absent, the voltage scaling
|
||||
flow is handled by hardware, hence no software "voltage tracking" is
|
||||
needed.
|
||||
- mediatek,cci:
|
||||
Used to confirm the link status between cpufreq and mediatek cci. Because
|
||||
cpufreq and mediatek cci could share the same regulator in some MediaTek SoCs.
|
||||
To prevent the issue of high frequency and low voltage, we need to use this
|
||||
property to make sure mediatek cci is ready.
|
||||
For details of mediatek cci, please refer to
|
||||
Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
|
||||
- #cooling-cells:
|
||||
For details, please refer to
|
||||
Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml
|
||||
|
||||
Example 1 (MT7623 SoC):
|
||||
|
||||
cpu_opp_table: opp_table {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp-598000000 {
|
||||
opp-hz = /bits/ 64 <598000000>;
|
||||
opp-microvolt = <1050000>;
|
||||
};
|
||||
|
||||
opp-747500000 {
|
||||
opp-hz = /bits/ 64 <747500000>;
|
||||
opp-microvolt = <1050000>;
|
||||
};
|
||||
|
||||
opp-1040000000 {
|
||||
opp-hz = /bits/ 64 <1040000000>;
|
||||
opp-microvolt = <1150000>;
|
||||
};
|
||||
|
||||
opp-1196000000 {
|
||||
opp-hz = /bits/ 64 <1196000000>;
|
||||
opp-microvolt = <1200000>;
|
||||
};
|
||||
|
||||
opp-1300000000 {
|
||||
opp-hz = /bits/ 64 <1300000000>;
|
||||
opp-microvolt = <1300000>;
|
||||
};
|
||||
};
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x0>;
|
||||
clocks = <&infracfg CLK_INFRA_CPUSEL>,
|
||||
<&apmixedsys CLK_APMIXED_MAINPLL>;
|
||||
clock-names = "cpu", "intermediate";
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x1>;
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
};
|
||||
cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x2>;
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
};
|
||||
cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x3>;
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
};
|
||||
|
||||
Example 2 (MT8173 SoC):
|
||||
cpu_opp_table_a: opp_table_a {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp-507000000 {
|
||||
opp-hz = /bits/ 64 <507000000>;
|
||||
opp-microvolt = <859000>;
|
||||
};
|
||||
|
||||
opp-702000000 {
|
||||
opp-hz = /bits/ 64 <702000000>;
|
||||
opp-microvolt = <908000>;
|
||||
};
|
||||
|
||||
opp-1001000000 {
|
||||
opp-hz = /bits/ 64 <1001000000>;
|
||||
opp-microvolt = <983000>;
|
||||
};
|
||||
|
||||
opp-1105000000 {
|
||||
opp-hz = /bits/ 64 <1105000000>;
|
||||
opp-microvolt = <1009000>;
|
||||
};
|
||||
|
||||
opp-1183000000 {
|
||||
opp-hz = /bits/ 64 <1183000000>;
|
||||
opp-microvolt = <1028000>;
|
||||
};
|
||||
|
||||
opp-1404000000 {
|
||||
opp-hz = /bits/ 64 <1404000000>;
|
||||
opp-microvolt = <1083000>;
|
||||
};
|
||||
|
||||
opp-1508000000 {
|
||||
opp-hz = /bits/ 64 <1508000000>;
|
||||
opp-microvolt = <1109000>;
|
||||
};
|
||||
|
||||
opp-1573000000 {
|
||||
opp-hz = /bits/ 64 <1573000000>;
|
||||
opp-microvolt = <1125000>;
|
||||
};
|
||||
};
|
||||
|
||||
cpu_opp_table_b: opp_table_b {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp-507000000 {
|
||||
opp-hz = /bits/ 64 <507000000>;
|
||||
opp-microvolt = <828000>;
|
||||
};
|
||||
|
||||
opp-702000000 {
|
||||
opp-hz = /bits/ 64 <702000000>;
|
||||
opp-microvolt = <867000>;
|
||||
};
|
||||
|
||||
opp-1001000000 {
|
||||
opp-hz = /bits/ 64 <1001000000>;
|
||||
opp-microvolt = <927000>;
|
||||
};
|
||||
|
||||
opp-1209000000 {
|
||||
opp-hz = /bits/ 64 <1209000000>;
|
||||
opp-microvolt = <968000>;
|
||||
};
|
||||
|
||||
opp-1404000000 {
|
||||
opp-hz = /bits/ 64 <1007000000>;
|
||||
opp-microvolt = <1028000>;
|
||||
};
|
||||
|
||||
opp-1612000000 {
|
||||
opp-hz = /bits/ 64 <1612000000>;
|
||||
opp-microvolt = <1049000>;
|
||||
};
|
||||
|
||||
opp-1807000000 {
|
||||
opp-hz = /bits/ 64 <1807000000>;
|
||||
opp-microvolt = <1089000>;
|
||||
};
|
||||
|
||||
opp-1989000000 {
|
||||
opp-hz = /bits/ 64 <1989000000>;
|
||||
opp-microvolt = <1125000>;
|
||||
};
|
||||
};
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x000>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_SLEEP_0>;
|
||||
clocks = <&infracfg CLK_INFRA_CA53SEL>,
|
||||
<&apmixedsys CLK_APMIXED_MAINPLL>;
|
||||
clock-names = "cpu", "intermediate";
|
||||
operating-points-v2 = <&cpu_opp_table_a>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x001>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_SLEEP_0>;
|
||||
clocks = <&infracfg CLK_INFRA_CA53SEL>,
|
||||
<&apmixedsys CLK_APMIXED_MAINPLL>;
|
||||
clock-names = "cpu", "intermediate";
|
||||
operating-points-v2 = <&cpu_opp_table_a>;
|
||||
};
|
||||
|
||||
cpu2: cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a72";
|
||||
reg = <0x100>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_SLEEP_0>;
|
||||
clocks = <&infracfg CLK_INFRA_CA72SEL>,
|
||||
<&apmixedsys CLK_APMIXED_MAINPLL>;
|
||||
clock-names = "cpu", "intermediate";
|
||||
operating-points-v2 = <&cpu_opp_table_b>;
|
||||
};
|
||||
|
||||
cpu3: cpu@101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a72";
|
||||
reg = <0x101>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_SLEEP_0>;
|
||||
clocks = <&infracfg CLK_INFRA_CA72SEL>,
|
||||
<&apmixedsys CLK_APMIXED_MAINPLL>;
|
||||
clock-names = "cpu", "intermediate";
|
||||
operating-points-v2 = <&cpu_opp_table_b>;
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
proc-supply = <&mt6397_vpca15_reg>;
|
||||
};
|
||||
|
||||
&cpu1 {
|
||||
proc-supply = <&mt6397_vpca15_reg>;
|
||||
};
|
||||
|
||||
&cpu2 {
|
||||
proc-supply = <&da9211_vcpu_reg>;
|
||||
sram-supply = <&mt6397_vsramca7_reg>;
|
||||
};
|
||||
|
||||
&cpu3 {
|
||||
proc-supply = <&da9211_vcpu_reg>;
|
||||
sram-supply = <&mt6397_vsramca7_reg>;
|
||||
};
|
||||
38
dts/upstream/Bindings/crypto/amd,ccp-seattle-v1a.yaml
Normal file
38
dts/upstream/Bindings/crypto/amd,ccp-seattle-v1a.yaml
Normal file
@ -0,0 +1,38 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/amd,ccp-seattle-v1a.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: AMD Cryptographic Coprocessor (ccp)
|
||||
|
||||
maintainers:
|
||||
- Tom Lendacky <thomas.lendacky@amd.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: amd,ccp-seattle-v1a
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
dma-coherent: true
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
crypto@e0100000 {
|
||||
compatible = "amd,ccp-seattle-v1a";
|
||||
reg = <0xe0100000 0x10000>;
|
||||
interrupts = <0 3 4>;
|
||||
dma-coherent;
|
||||
};
|
||||
@ -1,17 +0,0 @@
|
||||
* AMD Cryptographic Coprocessor driver (ccp)
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "amd,ccp-seattle-v1a"
|
||||
- reg: Address and length of the register set for the device
|
||||
- interrupts: Should contain the CCP interrupt
|
||||
|
||||
Optional properties:
|
||||
- dma-coherent: Present if dma operations are coherent
|
||||
|
||||
Example:
|
||||
ccp@e0100000 {
|
||||
compatible = "amd,ccp-seattle-v1a";
|
||||
reg = <0 0xe0100000 0 0x10000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 3 4>;
|
||||
};
|
||||
@ -1,16 +0,0 @@
|
||||
Axis crypto engine with PDMA interface.
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be one of the following strings:
|
||||
"axis,artpec6-crypto" for the version in the Axis ARTPEC-6 SoC
|
||||
"axis,artpec7-crypto" for the version in the Axis ARTPEC-7 SoC.
|
||||
- reg: Base address and size for the PDMA register area.
|
||||
- interrupts: Interrupt handle for the PDMA interrupt line.
|
||||
|
||||
Example:
|
||||
|
||||
crypto@f4264000 {
|
||||
compatible = "axis,artpec6-crypto";
|
||||
reg = <0xf4264000 0x1000>;
|
||||
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
39
dts/upstream/Bindings/crypto/axis,artpec6-crypto.yaml
Normal file
39
dts/upstream/Bindings/crypto/axis,artpec6-crypto.yaml
Normal file
@ -0,0 +1,39 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/crypto/axis,artpec6-crypto.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Axis ARTPEC6 crypto engine with PDMA interface
|
||||
|
||||
maintainers:
|
||||
- Lars Persson <lars.persson@axis.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- axis,artpec6-crypto
|
||||
- axis,artpec7-crypto
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
crypto@f4264000 {
|
||||
compatible = "axis,artpec6-crypto";
|
||||
reg = <0xf4264000 0x1000>;
|
||||
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
@ -1,22 +0,0 @@
|
||||
The Broadcom Secure Processing Unit (SPU) hardware supports symmetric
|
||||
cryptographic offload for Broadcom SoCs. A SoC may have multiple SPU hardware
|
||||
blocks.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be one of the following:
|
||||
brcm,spum-crypto - for devices with SPU-M hardware
|
||||
brcm,spu2-crypto - for devices with SPU2 hardware
|
||||
brcm,spu2-v2-crypto - for devices with enhanced SPU2 hardware features like SHA3
|
||||
and Rabin Fingerprint support
|
||||
brcm,spum-nsp-crypto - for the Northstar Plus variant of the SPU-M hardware
|
||||
|
||||
- reg: Should contain SPU registers location and length.
|
||||
- mboxes: The mailbox channel to be used to communicate with the SPU.
|
||||
Mailbox channels correspond to DMA rings on the device.
|
||||
|
||||
Example:
|
||||
crypto@612d0000 {
|
||||
compatible = "brcm,spum-crypto";
|
||||
reg = <0 0x612d0000 0 0x900>;
|
||||
mboxes = <&pdc0 0>;
|
||||
};
|
||||
44
dts/upstream/Bindings/crypto/brcm,spum-crypto.yaml
Normal file
44
dts/upstream/Bindings/crypto/brcm,spum-crypto.yaml
Normal file
@ -0,0 +1,44 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/brcm,spum-crypto.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom SPU Crypto Offload
|
||||
|
||||
maintainers:
|
||||
- Rob Rice <rob.rice@broadcom.com>
|
||||
|
||||
description:
|
||||
The Broadcom Secure Processing Unit (SPU) hardware supports symmetric
|
||||
cryptographic offload for Broadcom SoCs. A SoC may have multiple SPU hardware
|
||||
blocks.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- brcm,spum-crypto
|
||||
- brcm,spu2-crypto
|
||||
- brcm,spu2-v2-crypto # enhanced SPU2 hardware features like SHA3 and Rabin Fingerprint support
|
||||
- brcm,spum-nsp-crypto # Northstar Plus variant of the SPU-M hardware
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
mboxes:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- mboxes
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
crypto@612d0000 {
|
||||
compatible = "brcm,spum-crypto";
|
||||
reg = <0x612d0000 0x900>;
|
||||
mboxes = <&pdc0 0>;
|
||||
};
|
||||
@ -83,6 +83,8 @@ properties:
|
||||
by SNVS ONOFF, the driver can report the status of POWER key and wakeup
|
||||
system if pressed after system suspend.
|
||||
|
||||
$ref: /schemas/input/input.yaml
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: fsl,sec-v4.0-pwrkey
|
||||
@ -111,6 +113,9 @@ properties:
|
||||
maxItems: 1
|
||||
default: 116
|
||||
|
||||
power-off-time-sec:
|
||||
enum: [0, 5, 10, 15]
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- interrupts
|
||||
|
||||
@ -38,7 +38,9 @@ properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: fsl,sec-v5.4
|
||||
- enum:
|
||||
- fsl,sec-v5.4
|
||||
- fsl,sec-v6.0
|
||||
- const: fsl,sec-v5.0
|
||||
- const: fsl,sec-v4.0
|
||||
- items:
|
||||
@ -93,6 +95,12 @@ patternProperties:
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: fsl,sec-v6.0-job-ring
|
||||
- const: fsl,sec-v5.2-job-ring
|
||||
- const: fsl,sec-v5.0-job-ring
|
||||
- const: fsl,sec-v4.4-job-ring
|
||||
- const: fsl,sec-v4.0-job-ring
|
||||
- items:
|
||||
- const: fsl,sec-v5.4-job-ring
|
||||
- const: fsl,sec-v5.0-job-ring
|
||||
|
||||
@ -1,157 +0,0 @@
|
||||
SEC 6 is as Freescale's Cryptographic Accelerator and Assurance Module (CAAM).
|
||||
Currently Freescale powerpc chip C29X is embedded with SEC 6.
|
||||
SEC 6 device tree binding include:
|
||||
-SEC 6 Node
|
||||
-Job Ring Node
|
||||
-Full Example
|
||||
|
||||
=====================================================================
|
||||
SEC 6 Node
|
||||
|
||||
Description
|
||||
|
||||
Node defines the base address of the SEC 6 block.
|
||||
This block specifies the address range of all global
|
||||
configuration registers for the SEC 6 block.
|
||||
For example, In C293, we could see three SEC 6 node.
|
||||
|
||||
PROPERTIES
|
||||
|
||||
- compatible
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: Must include "fsl,sec-v6.0".
|
||||
|
||||
- fsl,sec-era
|
||||
Usage: optional
|
||||
Value type: <u32>
|
||||
Definition: A standard property. Define the 'ERA' of the SEC
|
||||
device.
|
||||
|
||||
- #address-cells
|
||||
Usage: required
|
||||
Value type: <u32>
|
||||
Definition: A standard property. Defines the number of cells
|
||||
for representing physical addresses in child nodes.
|
||||
|
||||
- #size-cells
|
||||
Usage: required
|
||||
Value type: <u32>
|
||||
Definition: A standard property. Defines the number of cells
|
||||
for representing the size of physical addresses in
|
||||
child nodes.
|
||||
|
||||
- reg
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: A standard property. Specifies the physical
|
||||
address and length of the SEC 6 configuration registers.
|
||||
|
||||
- ranges
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: A standard property. Specifies the physical address
|
||||
range of the SEC 6.0 register space (-SNVS not included). A
|
||||
triplet that includes the child address, parent address, &
|
||||
length.
|
||||
|
||||
Note: All other standard properties (see the Devicetree Specification)
|
||||
are allowed but are optional.
|
||||
|
||||
EXAMPLE
|
||||
crypto@a0000 {
|
||||
compatible = "fsl,sec-v6.0";
|
||||
fsl,sec-era = <6>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xa0000 0x20000>;
|
||||
ranges = <0 0xa0000 0x20000>;
|
||||
};
|
||||
|
||||
=====================================================================
|
||||
Job Ring (JR) Node
|
||||
|
||||
Child of the crypto node defines data processing interface to SEC 6
|
||||
across the peripheral bus for purposes of processing
|
||||
cryptographic descriptors. The specified address
|
||||
range can be made visible to one (or more) cores.
|
||||
The interrupt defined for this node is controlled within
|
||||
the address range of this node.
|
||||
|
||||
- compatible
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: Must include "fsl,sec-v6.0-job-ring".
|
||||
|
||||
- reg
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: Specifies a two JR parameters: an offset from
|
||||
the parent physical address and the length the JR registers.
|
||||
|
||||
- interrupts
|
||||
Usage: required
|
||||
Value type: <prop_encoded-array>
|
||||
Definition: Specifies the interrupts generated by this
|
||||
device. The value of the interrupts property
|
||||
consists of one interrupt specifier. The format
|
||||
of the specifier is defined by the binding document
|
||||
describing the node's interrupt parent.
|
||||
|
||||
EXAMPLE
|
||||
jr@1000 {
|
||||
compatible = "fsl,sec-v6.0-job-ring";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <49 2 0 0>;
|
||||
};
|
||||
|
||||
===================================================================
|
||||
Full Example
|
||||
|
||||
Since some chips may contain more than one SEC, the dtsi contains
|
||||
only the node contents, not the node itself. A chip using the SEC
|
||||
should include the dtsi inside each SEC node. Example:
|
||||
|
||||
In qoriq-sec6.0.dtsi:
|
||||
|
||||
compatible = "fsl,sec-v6.0";
|
||||
fsl,sec-era = <6>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
jr@1000 {
|
||||
compatible = "fsl,sec-v6.0-job-ring",
|
||||
"fsl,sec-v5.2-job-ring",
|
||||
"fsl,sec-v5.0-job-ring",
|
||||
"fsl,sec-v4.4-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x1000 0x1000>;
|
||||
};
|
||||
|
||||
jr@2000 {
|
||||
compatible = "fsl,sec-v6.0-job-ring",
|
||||
"fsl,sec-v5.2-job-ring",
|
||||
"fsl,sec-v5.0-job-ring",
|
||||
"fsl,sec-v4.4-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x2000 0x1000>;
|
||||
};
|
||||
|
||||
In the C293 device tree, we add the include of public property:
|
||||
|
||||
crypto@a0000 {
|
||||
/include/ "qoriq-sec6.0.dtsi"
|
||||
}
|
||||
|
||||
crypto@a0000 {
|
||||
reg = <0xa0000 0x20000>;
|
||||
ranges = <0 0xa0000 0x20000>;
|
||||
|
||||
jr@1000 {
|
||||
interrupts = <49 2 0 0>;
|
||||
};
|
||||
|
||||
jr@2000 {
|
||||
interrupts = <50 2 0 0>;
|
||||
};
|
||||
};
|
||||
134
dts/upstream/Bindings/crypto/hisilicon,hip06-sec.yaml
Normal file
134
dts/upstream/Bindings/crypto/hisilicon,hip06-sec.yaml
Normal file
@ -0,0 +1,134 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/crypto/hisilicon,hip06-sec.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Hisilicon hip06/hip07 Security Accelerator
|
||||
|
||||
maintainers:
|
||||
- Jonathan Cameron <Jonathan.Cameron@huawei.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- hisilicon,hip06-sec
|
||||
- hisilicon,hip07-sec
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: Registers for backend processing engines
|
||||
- description: Registers for common functionality
|
||||
- description: Registers for queue 0
|
||||
- description: Registers for queue 1
|
||||
- description: Registers for queue 2
|
||||
- description: Registers for queue 3
|
||||
- description: Registers for queue 4
|
||||
- description: Registers for queue 5
|
||||
- description: Registers for queue 6
|
||||
- description: Registers for queue 7
|
||||
- description: Registers for queue 8
|
||||
- description: Registers for queue 9
|
||||
- description: Registers for queue 10
|
||||
- description: Registers for queue 11
|
||||
- description: Registers for queue 12
|
||||
- description: Registers for queue 13
|
||||
- description: Registers for queue 14
|
||||
- description: Registers for queue 15
|
||||
|
||||
interrupts:
|
||||
items:
|
||||
- description: SEC unit error queue interrupt
|
||||
- description: Completion interrupt for queue 0
|
||||
- description: Error interrupt for queue 0
|
||||
- description: Completion interrupt for queue 1
|
||||
- description: Error interrupt for queue 1
|
||||
- description: Completion interrupt for queue 2
|
||||
- description: Error interrupt for queue 2
|
||||
- description: Completion interrupt for queue 3
|
||||
- description: Error interrupt for queue 3
|
||||
- description: Completion interrupt for queue 4
|
||||
- description: Error interrupt for queue 4
|
||||
- description: Completion interrupt for queue 5
|
||||
- description: Error interrupt for queue 5
|
||||
- description: Completion interrupt for queue 6
|
||||
- description: Error interrupt for queue 6
|
||||
- description: Completion interrupt for queue 7
|
||||
- description: Error interrupt for queue 7
|
||||
- description: Completion interrupt for queue 8
|
||||
- description: Error interrupt for queue 8
|
||||
- description: Completion interrupt for queue 9
|
||||
- description: Error interrupt for queue 9
|
||||
- description: Completion interrupt for queue 10
|
||||
- description: Error interrupt for queue 10
|
||||
- description: Completion interrupt for queue 11
|
||||
- description: Error interrupt for queue 11
|
||||
- description: Completion interrupt for queue 12
|
||||
- description: Error interrupt for queue 12
|
||||
- description: Completion interrupt for queue 13
|
||||
- description: Error interrupt for queue 13
|
||||
- description: Completion interrupt for queue 14
|
||||
- description: Error interrupt for queue 14
|
||||
- description: Completion interrupt for queue 15
|
||||
- description: Error interrupt for queue 15
|
||||
|
||||
dma-coherent: true
|
||||
|
||||
iommus:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- dma-coherent
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
bus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
crypto@400d2000000 {
|
||||
compatible = "hisilicon,hip07-sec";
|
||||
reg = <0x400 0xd0000000 0x0 0x10000
|
||||
0x400 0xd2000000 0x0 0x10000
|
||||
0x400 0xd2010000 0x0 0x10000
|
||||
0x400 0xd2020000 0x0 0x10000
|
||||
0x400 0xd2030000 0x0 0x10000
|
||||
0x400 0xd2040000 0x0 0x10000
|
||||
0x400 0xd2050000 0x0 0x10000
|
||||
0x400 0xd2060000 0x0 0x10000
|
||||
0x400 0xd2070000 0x0 0x10000
|
||||
0x400 0xd2080000 0x0 0x10000
|
||||
0x400 0xd2090000 0x0 0x10000
|
||||
0x400 0xd20a0000 0x0 0x10000
|
||||
0x400 0xd20b0000 0x0 0x10000
|
||||
0x400 0xd20c0000 0x0 0x10000
|
||||
0x400 0xd20d0000 0x0 0x10000
|
||||
0x400 0xd20e0000 0x0 0x10000
|
||||
0x400 0xd20f0000 0x0 0x10000
|
||||
0x400 0xd2100000 0x0 0x10000>;
|
||||
interrupts = <576 4>,
|
||||
<577 1>, <578 4>,
|
||||
<579 1>, <580 4>,
|
||||
<581 1>, <582 4>,
|
||||
<583 1>, <584 4>,
|
||||
<585 1>, <586 4>,
|
||||
<587 1>, <588 4>,
|
||||
<589 1>, <590 4>,
|
||||
<591 1>, <592 4>,
|
||||
<593 1>, <594 4>,
|
||||
<595 1>, <596 4>,
|
||||
<597 1>, <598 4>,
|
||||
<599 1>, <600 4>,
|
||||
<601 1>, <602 4>,
|
||||
<603 1>, <604 4>,
|
||||
<605 1>, <606 4>,
|
||||
<607 1>, <608 4>;
|
||||
dma-coherent;
|
||||
iommus = <&p1_smmu_alg_a 0x600>;
|
||||
};
|
||||
};
|
||||
@ -1,67 +0,0 @@
|
||||
* Hisilicon hip07 Security Accelerator (SEC)
|
||||
|
||||
Required properties:
|
||||
- compatible: Must contain one of
|
||||
- "hisilicon,hip06-sec"
|
||||
- "hisilicon,hip07-sec"
|
||||
- reg: Memory addresses and lengths of the memory regions through which
|
||||
this device is controlled.
|
||||
Region 0 has registers to control the backend processing engines.
|
||||
Region 1 has registers for functionality common to all queues.
|
||||
Regions 2-18 have registers for the 16 individual queues which are isolated
|
||||
both in hardware and within the driver.
|
||||
- interrupts: Interrupt specifiers.
|
||||
Refer to interrupt-controller/interrupts.txt for generic interrupt client node
|
||||
bindings.
|
||||
Interrupt 0 is for the SEC unit error queue.
|
||||
Interrupt 2N + 1 is the completion interrupt for queue N.
|
||||
Interrupt 2N + 2 is the error interrupt for queue N.
|
||||
- dma-coherent: The driver assumes coherent dma is possible.
|
||||
|
||||
Optional properties:
|
||||
- iommus: The SEC units are behind smmu-v3 iommus.
|
||||
Refer to iommu/arm,smmu-v3.txt for more information.
|
||||
|
||||
Example:
|
||||
|
||||
p1_sec_a: crypto@400d2000000 {
|
||||
compatible = "hisilicon,hip07-sec";
|
||||
reg = <0x400 0xd0000000 0x0 0x10000
|
||||
0x400 0xd2000000 0x0 0x10000
|
||||
0x400 0xd2010000 0x0 0x10000
|
||||
0x400 0xd2020000 0x0 0x10000
|
||||
0x400 0xd2030000 0x0 0x10000
|
||||
0x400 0xd2040000 0x0 0x10000
|
||||
0x400 0xd2050000 0x0 0x10000
|
||||
0x400 0xd2060000 0x0 0x10000
|
||||
0x400 0xd2070000 0x0 0x10000
|
||||
0x400 0xd2080000 0x0 0x10000
|
||||
0x400 0xd2090000 0x0 0x10000
|
||||
0x400 0xd20a0000 0x0 0x10000
|
||||
0x400 0xd20b0000 0x0 0x10000
|
||||
0x400 0xd20c0000 0x0 0x10000
|
||||
0x400 0xd20d0000 0x0 0x10000
|
||||
0x400 0xd20e0000 0x0 0x10000
|
||||
0x400 0xd20f0000 0x0 0x10000
|
||||
0x400 0xd2100000 0x0 0x10000>;
|
||||
interrupt-parent = <&p1_mbigen_sec_a>;
|
||||
iommus = <&p1_smmu_alg_a 0x600>;
|
||||
dma-coherent;
|
||||
interrupts = <576 4>,
|
||||
<577 1>, <578 4>,
|
||||
<579 1>, <580 4>,
|
||||
<581 1>, <582 4>,
|
||||
<583 1>, <584 4>,
|
||||
<585 1>, <586 4>,
|
||||
<587 1>, <588 4>,
|
||||
<589 1>, <590 4>,
|
||||
<591 1>, <592 4>,
|
||||
<593 1>, <594 4>,
|
||||
<595 1>, <596 4>,
|
||||
<597 1>, <598 4>,
|
||||
<599 1>, <600 4>,
|
||||
<601 1>, <602 4>,
|
||||
<603 1>, <604 4>,
|
||||
<605 1>, <606 4>,
|
||||
<607 1>, <608 4>;
|
||||
};
|
||||
69
dts/upstream/Bindings/crypto/img,hash-accelerator.yaml
Normal file
69
dts/upstream/Bindings/crypto/img,hash-accelerator.yaml
Normal file
@ -0,0 +1,69 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/img,hash-accelerator.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Imagination Technologies hardware hash accelerator
|
||||
|
||||
maintainers:
|
||||
- James Hartley <james.hartley@imgtec.com>
|
||||
|
||||
description:
|
||||
The hash accelerator provides hardware hashing acceleration for
|
||||
SHA1, SHA224, SHA256 and MD5 hashes.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: img,hash-accelerator
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: Register base address and size
|
||||
- description: DMA port specifier
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
dmas:
|
||||
maxItems: 1
|
||||
|
||||
dma-names:
|
||||
items:
|
||||
- const: tx
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: System clock for hash block registers
|
||||
- description: Hash clock for data path
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: sys
|
||||
- const: hash
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- dmas
|
||||
- dma-names
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/mips-gic.h>
|
||||
#include <dt-bindings/clock/pistachio-clk.h>
|
||||
|
||||
hash@18149600 {
|
||||
compatible = "img,hash-accelerator";
|
||||
reg = <0x18149600 0x100>, <0x18101100 0x4>;
|
||||
interrupts = <GIC_SHARED 59 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&dma 8 0xffffffff 0>;
|
||||
dma-names = "tx";
|
||||
clocks = <&cr_periph SYS_CLK_HASH>, <&clk_periph PERIPH_CLK_ROM>;
|
||||
clock-names = "sys", "hash";
|
||||
};
|
||||
@ -1,27 +0,0 @@
|
||||
Imagination Technologies hardware hash accelerator
|
||||
|
||||
The hash accelerator provides hardware hashing acceleration for
|
||||
SHA1, SHA224, SHA256 and MD5 hashes
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : "img,hash-accelerator"
|
||||
- reg : Offset and length of the register set for the module, and the DMA port
|
||||
- interrupts : The designated IRQ line for the hashing module.
|
||||
- dmas : DMA specifier as per Documentation/devicetree/bindings/dma/dma.txt
|
||||
- dma-names : Should be "tx"
|
||||
- clocks : Clock specifiers
|
||||
- clock-names : "sys" Used to clock the hash block registers
|
||||
"hash" Used to clock data through the accelerator
|
||||
|
||||
Example:
|
||||
|
||||
hash: hash@18149600 {
|
||||
compatible = "img,hash-accelerator";
|
||||
reg = <0x18149600 0x100>, <0x18101100 0x4>;
|
||||
interrupts = <GIC_SHARED 59 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&dma 8 0xffffffff 0>;
|
||||
dma-names = "tx";
|
||||
clocks = <&cr_periph SYS_CLK_HASH>, <&clk_periph PERIPH_CLK_ROM>;
|
||||
clock-names = "sys", "hash";
|
||||
};
|
||||
133
dts/upstream/Bindings/crypto/marvell,orion-crypto.yaml
Normal file
133
dts/upstream/Bindings/crypto/marvell,orion-crypto.yaml
Normal file
@ -0,0 +1,133 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/crypto/marvell,orion-crypto.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Marvell Cryptographic Engines And Security Accelerator
|
||||
|
||||
maintainers:
|
||||
- Andrew Lunn <andrew@lunn.ch>
|
||||
- Boris Brezillon <bbrezillon@kernel.org>
|
||||
|
||||
description: |
|
||||
Marvell Cryptographic Engines And Security Accelerator
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- marvell,armada-370-crypto
|
||||
- marvell,armada-xp-crypto
|
||||
- marvell,armada-375-crypto
|
||||
- marvell,armada-38x-crypto
|
||||
- marvell,dove-crypto
|
||||
- marvell,kirkwood-crypto
|
||||
- marvell,orion-crypto
|
||||
|
||||
reg:
|
||||
minItems: 1
|
||||
items:
|
||||
- description: Registers region
|
||||
- description: SRAM region
|
||||
deprecated: true
|
||||
|
||||
reg-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: regs
|
||||
- const: sram
|
||||
deprecated: true
|
||||
|
||||
interrupts:
|
||||
description: One interrupt for each CESA engine
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
clocks:
|
||||
description: One or two clocks for each CESA engine
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: cesa0
|
||||
- const: cesa1
|
||||
- const: cesaz0
|
||||
- const: cesaz1
|
||||
|
||||
marvell,crypto-srams:
|
||||
description: Phandle(s) to crypto SRAM.
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
items:
|
||||
maxItems: 1
|
||||
|
||||
marvell,crypto-sram-size:
|
||||
description: SRAM size reserved for crypto operations.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
default: 0x800
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- interrupts
|
||||
- marvell,crypto-srams
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
not:
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- marvell,kirkwood-crypto
|
||||
- marvell,orion-crypto
|
||||
then:
|
||||
required:
|
||||
- clocks
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- marvell,armada-370-crypto
|
||||
- marvell,armada-375-crypto
|
||||
- marvell,armada-38x-crypto
|
||||
- marvell,armada-xp-crypto
|
||||
then:
|
||||
required:
|
||||
- clock-names
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- marvell,armada-375-crypto
|
||||
- marvell,armada-38x-crypto
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 4
|
||||
clock-names:
|
||||
minItems: 4
|
||||
else:
|
||||
properties:
|
||||
clocks:
|
||||
maxItems: 2
|
||||
clock-names:
|
||||
maxItems: 2
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
crypto@30000 {
|
||||
compatible = "marvell,orion-crypto";
|
||||
reg = <0x30000 0x10000>;
|
||||
reg-names = "regs";
|
||||
interrupts = <22>;
|
||||
marvell,crypto-srams = <&crypto_sram>;
|
||||
marvell,crypto-sram-size = <0x600>;
|
||||
};
|
||||
@ -1,44 +0,0 @@
|
||||
Marvell Cryptographic Engines And Security Accelerator
|
||||
|
||||
Required properties:
|
||||
- compatible: should be one of the following string
|
||||
"marvell,orion-crypto"
|
||||
"marvell,kirkwood-crypto"
|
||||
"marvell,dove-crypto"
|
||||
"marvell,armada-370-crypto"
|
||||
"marvell,armada-xp-crypto"
|
||||
"marvell,armada-375-crypto"
|
||||
"marvell,armada-38x-crypto"
|
||||
- reg: base physical address of the engine and length of memory mapped
|
||||
region. Can also contain an entry for the SRAM attached to the CESA,
|
||||
but this representation is deprecated and marvell,crypto-srams should
|
||||
be used instead
|
||||
- reg-names: "regs". Can contain an "sram" entry, but this representation
|
||||
is deprecated and marvell,crypto-srams should be used instead
|
||||
- interrupts: interrupt number
|
||||
- clocks: reference to the crypto engines clocks. This property is not
|
||||
required for orion and kirkwood platforms
|
||||
- clock-names: "cesaX" and "cesazX", X should be replaced by the crypto engine
|
||||
id.
|
||||
This property is not required for the orion and kirkwoord
|
||||
platforms.
|
||||
"cesazX" clocks are not required on armada-370 platforms
|
||||
- marvell,crypto-srams: phandle to crypto SRAM definitions
|
||||
|
||||
Optional properties:
|
||||
- marvell,crypto-sram-size: SRAM size reserved for crypto operations, if not
|
||||
specified the whole SRAM is used (2KB)
|
||||
|
||||
|
||||
Examples:
|
||||
|
||||
crypto@90000 {
|
||||
compatible = "marvell,armada-xp-crypto";
|
||||
reg = <0x90000 0x10000>;
|
||||
reg-names = "regs";
|
||||
interrupts = <48>, <49>;
|
||||
clocks = <&gateclk 23>, <&gateclk 23>;
|
||||
clock-names = "cesa0", "cesa1";
|
||||
marvell,crypto-srams = <&crypto_sram0>, <&crypto_sram1>;
|
||||
marvell,crypto-sram-size = <0x600>;
|
||||
};
|
||||
@ -1,25 +0,0 @@
|
||||
MediaTek cryptographic accelerators
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "mediatek,eip97-crypto"
|
||||
- reg: Address and length of the register set for the device
|
||||
- interrupts: Should contain the five crypto engines interrupts in numeric
|
||||
order. These are global system and four descriptor rings.
|
||||
- clocks: the clock used by the core
|
||||
- clock-names: Must contain "cryp".
|
||||
- power-domains: Must contain a reference to the PM domain.
|
||||
|
||||
|
||||
Example:
|
||||
crypto: crypto@1b240000 {
|
||||
compatible = "mediatek,eip97-crypto";
|
||||
reg = <0 0x1b240000 0 0x20000>;
|
||||
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <ðsys CLK_ETHSYS_CRYPTO>;
|
||||
clock-names = "cryp";
|
||||
power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
|
||||
};
|
||||
@ -1,32 +0,0 @@
|
||||
Marvell Cryptographic Engines And Security Accelerator
|
||||
|
||||
Required properties:
|
||||
- compatible: should be one of the following string
|
||||
"marvell,orion-crypto"
|
||||
"marvell,kirkwood-crypto"
|
||||
"marvell,dove-crypto"
|
||||
- reg: base physical address of the engine and length of memory mapped
|
||||
region. Can also contain an entry for the SRAM attached to the CESA,
|
||||
but this representation is deprecated and marvell,crypto-srams should
|
||||
be used instead
|
||||
- reg-names: "regs". Can contain an "sram" entry, but this representation
|
||||
is deprecated and marvell,crypto-srams should be used instead
|
||||
- interrupts: interrupt number
|
||||
- clocks: reference to the crypto engines clocks. This property is only
|
||||
required for Dove platforms
|
||||
- marvell,crypto-srams: phandle to crypto SRAM definitions
|
||||
|
||||
Optional properties:
|
||||
- marvell,crypto-sram-size: SRAM size reserved for crypto operations, if not
|
||||
specified the whole SRAM is used (2KB)
|
||||
|
||||
Examples:
|
||||
|
||||
crypto@30000 {
|
||||
compatible = "marvell,orion-crypto";
|
||||
reg = <0x30000 0x10000>;
|
||||
reg-names = "regs";
|
||||
interrupts = <22>;
|
||||
marvell,crypto-srams = <&crypto_sram>;
|
||||
marvell,crypto-sram-size = <0x600>;
|
||||
};
|
||||
@ -45,6 +45,7 @@ properties:
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,qcs615-qce
|
||||
- qcom,qcs8300-qce
|
||||
- qcom,sa8775p-qce
|
||||
- qcom,sc7280-qce
|
||||
|
||||
@ -128,7 +128,7 @@ required:
|
||||
- power-domains
|
||||
- ports
|
||||
|
||||
additionalProperties: false
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
@ -180,4 +180,69 @@ examples:
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
dsi1: dsi@10860000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "renesas,r9a07g044-mipi-dsi", "renesas,rzg2l-mipi-dsi";
|
||||
reg = <0x10860000 0x20000>;
|
||||
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "seq0", "seq1", "vin1", "rcv",
|
||||
"ferr", "ppi", "debug";
|
||||
clocks = <&cpg CPG_MOD R9A07G044_MIPI_DSI_PLLCLK>,
|
||||
<&cpg CPG_MOD R9A07G044_MIPI_DSI_SYSCLK>,
|
||||
<&cpg CPG_MOD R9A07G044_MIPI_DSI_ACLK>,
|
||||
<&cpg CPG_MOD R9A07G044_MIPI_DSI_PCLK>,
|
||||
<&cpg CPG_MOD R9A07G044_MIPI_DSI_VCLK>,
|
||||
<&cpg CPG_MOD R9A07G044_MIPI_DSI_LPCLK>;
|
||||
clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk";
|
||||
resets = <&cpg R9A07G044_MIPI_DSI_CMN_RSTB>,
|
||||
<&cpg R9A07G044_MIPI_DSI_ARESET_N>,
|
||||
<&cpg R9A07G044_MIPI_DSI_PRESET_N>;
|
||||
reset-names = "rst", "arst", "prst";
|
||||
power-domains = <&cpg>;
|
||||
|
||||
panel@0 {
|
||||
compatible = "rocktech,jh057n00900";
|
||||
reg = <0>;
|
||||
vcc-supply = <®_2v8_p>;
|
||||
iovcc-supply = <®_1v8_p>;
|
||||
reset-gpios = <&gpio3 13 GPIO_ACTIVE_LOW>;
|
||||
|
||||
port {
|
||||
panel_in: endpoint {
|
||||
remote-endpoint = <&dsi1_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dsi1_in: endpoint {
|
||||
remote-endpoint = <&du_out_dsi1>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dsi1_out: endpoint {
|
||||
data-lanes = <1 2 3 4>;
|
||||
remote-endpoint = <&panel_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
|
||||
@ -118,15 +118,11 @@ $defs:
|
||||
ti,lvds-vod-swing-clock-microvolt:
|
||||
description: LVDS diferential output voltage <min max> for clock
|
||||
lanes in microvolts.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
|
||||
ti,lvds-vod-swing-data-microvolt:
|
||||
description: LVDS diferential output voltage <min max> for data
|
||||
lanes in microvolts.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
|
||||
allOf:
|
||||
|
||||
@ -1,17 +0,0 @@
|
||||
Device Tree bindings for Freescale TCON Driver
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be one of
|
||||
* "fsl,vf610-tcon".
|
||||
|
||||
- reg: Address and length of the register set for tcon.
|
||||
- clocks: From common clock binding: handle to tcon ipg clock.
|
||||
- clock-names: From common clock binding: Shall be "ipg".
|
||||
|
||||
Examples:
|
||||
timing-controller@4003d000 {
|
||||
compatible = "fsl,vf610-tcon";
|
||||
reg = <0x4003d000 0x1000>;
|
||||
clocks = <&clks VF610_CLK_TCON0>;
|
||||
clock-names = "ipg";
|
||||
};
|
||||
43
dts/upstream/Bindings/display/fsl,vf610-tcon.yaml
Normal file
43
dts/upstream/Bindings/display/fsl,vf610-tcon.yaml
Normal file
@ -0,0 +1,43 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/fsl,vf610-tcon.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Freescale TCON
|
||||
|
||||
maintainers:
|
||||
- Frank Li <Frank.Li@nxp.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: fsl,vf610-tcon
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: ipg
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/vf610-clock.h>
|
||||
|
||||
timing-controller@4003d000 {
|
||||
compatible = "fsl,vf610-tcon";
|
||||
reg = <0x4003d000 0x1000>;
|
||||
clocks = <&clks VF610_CLK_TCON0>;
|
||||
clock-names = "ipg";
|
||||
};
|
||||
@ -0,0 +1,36 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/imx/fsl,imx-display-subsystem.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Freescale i.MX DRM master device
|
||||
|
||||
maintainers:
|
||||
- Frank Li <Frank.Li@nxp.com>
|
||||
|
||||
description:
|
||||
The freescale i.MX DRM master device is a virtual device needed to list all
|
||||
IPU or other display interface nodes that comprise the graphics subsystem.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: fsl,imx-display-subsystem
|
||||
|
||||
ports:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
description:
|
||||
Should contain a list of phandles pointing to camera
|
||||
sensor interface ports of IPU devices.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
display-subsystem {
|
||||
compatible = "fsl,imx-display-subsystem";
|
||||
ports = <&ipu_di0>;
|
||||
};
|
||||
@ -0,0 +1,74 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/imx/fsl,imx-parallel-display.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Parallel display support
|
||||
|
||||
maintainers:
|
||||
- Frank Li <Frank.Li@nxp.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: fsl,imx-parallel-display
|
||||
|
||||
interface-pix-fmt:
|
||||
$ref: /schemas/types.yaml#/definitions/string
|
||||
enum:
|
||||
- rgb24
|
||||
- rgb565
|
||||
- bgr666
|
||||
- lvds666
|
||||
|
||||
ddc:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
phandle describing the i2c bus handling the display data channel
|
||||
|
||||
'#address-cells':
|
||||
const: 1
|
||||
|
||||
'#size-cells':
|
||||
const: 0
|
||||
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/$defs/port-base
|
||||
unevaluatedProperties: false
|
||||
description: input port connected to the IPU display interface
|
||||
|
||||
port@1:
|
||||
$ref: /schemas/graph.yaml#/$defs/port-base
|
||||
unevaluatedProperties: false
|
||||
description: output port connected to a panel
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
display {
|
||||
compatible = "fsl,imx-parallel-display";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interface-pix-fmt = "rgb24";
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
endpoint {
|
||||
remote-endpoint = <&ipu_di0_disp0>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
endpoint {
|
||||
remote-endpoint = <&panel_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
97
dts/upstream/Bindings/display/imx/fsl,imx6q-ipu.yaml
Normal file
97
dts/upstream/Bindings/display/imx/fsl,imx6q-ipu.yaml
Normal file
@ -0,0 +1,97 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/imx/fsl,imx6q-ipu.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Freescale i.MX IPUv3
|
||||
|
||||
maintainers:
|
||||
- Frank Li <Frank.Li@nxp.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- enum:
|
||||
- fsl,imx51-ipu
|
||||
- fsl,imx53-ipu
|
||||
- fsl,imx6q-ipu
|
||||
- items:
|
||||
- const: fsl,imx6qp-ipu
|
||||
- const: fsl,imx6q-ipu
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
clocks:
|
||||
maxItems: 3
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bus
|
||||
- const: di0
|
||||
- const: di1
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
'#address-cells':
|
||||
const: 1
|
||||
|
||||
'#size-cells':
|
||||
const: 0
|
||||
|
||||
fsl,prg:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description: phandle to prg node associated with this IPU instance
|
||||
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/$defs/port-base
|
||||
unevaluatedProperties: false
|
||||
description: CSI0
|
||||
|
||||
port@1:
|
||||
$ref: /schemas/graph.yaml#/$defs/port-base
|
||||
unevaluatedProperties: false
|
||||
description: CSI1
|
||||
|
||||
port@2:
|
||||
$ref: /schemas/graph.yaml#/$defs/port-base
|
||||
unevaluatedProperties: false
|
||||
description: DI0
|
||||
|
||||
port@3:
|
||||
$ref: /schemas/graph.yaml#/$defs/port-base
|
||||
unevaluatedProperties: false
|
||||
description: DI1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- resets
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
display-controller@18000000 {
|
||||
compatible = "fsl,imx53-ipu";
|
||||
reg = <0x18000000 0x080000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <11 10>;
|
||||
resets = <&src 2>;
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
|
||||
endpoint {
|
||||
remote-endpoint = <&display_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
193
dts/upstream/Bindings/display/imx/fsl,imx6q-ldb.yaml
Normal file
193
dts/upstream/Bindings/display/imx/fsl,imx6q-ldb.yaml
Normal file
@ -0,0 +1,193 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/imx/fsl,imx6q-ldb.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Freescale LVDS Display Bridge (ldb)
|
||||
|
||||
description:
|
||||
The LVDS Display Bridge device tree node contains up to two lvds-channel
|
||||
nodes describing each of the two LVDS encoder channels of the bridge.
|
||||
|
||||
maintainers:
|
||||
- Frank Li <Frank.Li@nxp.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- enum:
|
||||
- fsl,imx53-ldb
|
||||
- items:
|
||||
- enum:
|
||||
- fsl,imx6q-ldb
|
||||
- const: fsl,imx53-ldb
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#address-cells':
|
||||
const: 1
|
||||
|
||||
'#size-cells':
|
||||
const: 0
|
||||
|
||||
gpr:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
The phandle points to the iomuxc-gpr region containing the LVDS
|
||||
control register.
|
||||
|
||||
clocks:
|
||||
minItems: 6
|
||||
maxItems: 8
|
||||
|
||||
clock-names:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: di0_pll
|
||||
- const: di1_pll
|
||||
- const: di0_sel
|
||||
- const: di1_sel
|
||||
- const: di0
|
||||
- const: di1
|
||||
- items:
|
||||
- const: di0_pll
|
||||
- const: di1_pll
|
||||
- const: di0_sel
|
||||
- const: di1_sel
|
||||
- const: di2_sel
|
||||
- const: di3_sel
|
||||
- const: di0
|
||||
- const: di1
|
||||
|
||||
fsl,dual-channel:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
if it exists, only LVDS channel 0 should
|
||||
be configured - one input will be distributed on both outputs in dual
|
||||
channel mode
|
||||
|
||||
patternProperties:
|
||||
'^lvds-channel@[0-1]$':
|
||||
type: object
|
||||
description:
|
||||
Each LVDS Channel has to contain either an of graph link to a panel device node
|
||||
or a display-timings node that describes the video timings for the connected
|
||||
LVDS display as well as the fsl,data-mapping and fsl,data-width properties.
|
||||
|
||||
properties:
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#address-cells':
|
||||
const: 1
|
||||
|
||||
'#size-cells':
|
||||
const: 0
|
||||
|
||||
display-timings:
|
||||
$ref: /schemas/display/panel/display-timings.yaml#
|
||||
|
||||
fsl,data-mapping:
|
||||
enum:
|
||||
- spwg
|
||||
- jeida
|
||||
|
||||
fsl,data-width:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: should be <18> or <24>
|
||||
enum:
|
||||
- 18
|
||||
- 24
|
||||
|
||||
fsl,panel:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description: phandle to lcd panel
|
||||
|
||||
patternProperties:
|
||||
'^port@[0-4]$':
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description:
|
||||
On i.MX5, the internal two-input-multiplexer is used. Due to hardware
|
||||
limitations, only one input port (port@[0,1]) can be used for each channel
|
||||
(lvds-channel@[0,1], respectively).
|
||||
On i.MX6, there should be four input ports (port@[0-3]) that correspond
|
||||
to the four LVDS multiplexer inputs.
|
||||
A single output port (port@2 on i.MX5, port@4 on i.MX6) must be connected
|
||||
to a panel input port. Optionally, the output port can be left out if
|
||||
display-timings are used instead.
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- gpr
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/imx5-clock.h>
|
||||
|
||||
ldb@53fa8008 {
|
||||
compatible = "fsl,imx53-ldb";
|
||||
reg = <0x53fa8008 0x4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
gpr = <&gpr>;
|
||||
clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
|
||||
<&clks IMX5_CLK_LDB_DI1_SEL>,
|
||||
<&clks IMX5_CLK_IPU_DI0_SEL>,
|
||||
<&clks IMX5_CLK_IPU_DI1_SEL>,
|
||||
<&clks IMX5_CLK_LDB_DI0_GATE>,
|
||||
<&clks IMX5_CLK_LDB_DI1_GATE>;
|
||||
clock-names = "di0_pll", "di1_pll",
|
||||
"di0_sel", "di1_sel",
|
||||
"di0", "di1";
|
||||
|
||||
/* Using an of-graph endpoint link to connect the panel */
|
||||
lvds-channel@0 {
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
endpoint {
|
||||
remote-endpoint = <&ipu_di0_lvds0>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
|
||||
endpoint {
|
||||
remote-endpoint = <&panel_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* Using display-timings and fsl,data-mapping/width instead */
|
||||
lvds-channel@1 {
|
||||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
fsl,data-mapping = "spwg";
|
||||
fsl,data-width = <24>;
|
||||
|
||||
display-timings {/* ... */
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
endpoint {
|
||||
remote-endpoint = <&ipu_di1_lvds1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
55
dts/upstream/Bindings/display/imx/fsl,imx6qp-pre.yaml
Normal file
55
dts/upstream/Bindings/display/imx/fsl,imx6qp-pre.yaml
Normal file
@ -0,0 +1,55 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/imx/fsl,imx6qp-pre.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Freescale i.MX PRE (Prefetch Resolve Engine)
|
||||
|
||||
maintainers:
|
||||
- Frank Li <Frank.Li@nxp.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: fsl,imx6qp-pre
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: axi
|
||||
fsl,iram:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
phandle pointing to the mmio-sram device node, that should be
|
||||
used for the PRE SRAM double buffer.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/imx6qdl-clock.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
pre@21c8000 {
|
||||
compatible = "fsl,imx6qp-pre";
|
||||
reg = <0x021c8000 0x1000>;
|
||||
interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
|
||||
clocks = <&clks IMX6QDL_CLK_PRE0>;
|
||||
clock-names = "axi";
|
||||
fsl,iram = <&ocram2>;
|
||||
};
|
||||
54
dts/upstream/Bindings/display/imx/fsl,imx6qp-prg.yaml
Normal file
54
dts/upstream/Bindings/display/imx/fsl,imx6qp-prg.yaml
Normal file
@ -0,0 +1,54 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/imx/fsl,imx6qp-prg.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Freescale i.MX PRG (Prefetch Resolve Gasket)
|
||||
|
||||
maintainers:
|
||||
- Frank Li <Frank.Li@nxp.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: fsl,imx6qp-prg
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 2
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: ipg
|
||||
- const: axi
|
||||
|
||||
fsl,pres:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
items:
|
||||
maxItems: 1
|
||||
description:
|
||||
phandles to the PRE units attached to this PRG, with the fixed
|
||||
PRE as the first entry and the muxable PREs following.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/imx6qdl-clock.h>
|
||||
|
||||
prg@21cc000 {
|
||||
compatible = "fsl,imx6qp-prg";
|
||||
reg = <0x021cc000 0x1000>;
|
||||
clocks = <&clks IMX6QDL_CLK_PRG0_APB>, <&clks IMX6QDL_CLK_PRG0_AXI>;
|
||||
clock-names = "ipg", "axi";
|
||||
fsl,pres = <&pre1>, <&pre2>, <&pre3>;
|
||||
};
|
||||
|
||||
@ -1,160 +0,0 @@
|
||||
Freescale i.MX DRM master device
|
||||
================================
|
||||
|
||||
The freescale i.MX DRM master device is a virtual device needed to list all
|
||||
IPU or other display interface nodes that comprise the graphics subsystem.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "fsl,imx-display-subsystem"
|
||||
- ports: Should contain a list of phandles pointing to display interface ports
|
||||
of IPU devices
|
||||
|
||||
example:
|
||||
|
||||
display-subsystem {
|
||||
compatible = "fsl,imx-display-subsystem";
|
||||
ports = <&ipu_di0>;
|
||||
};
|
||||
|
||||
|
||||
Freescale i.MX IPUv3
|
||||
====================
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "fsl,<chip>-ipu" where <chip> is one of
|
||||
- imx51
|
||||
- imx53
|
||||
- imx6q
|
||||
- imx6qp
|
||||
- reg: should be register base and length as documented in the
|
||||
datasheet
|
||||
- interrupts: Should contain sync interrupt and error interrupt,
|
||||
in this order.
|
||||
- resets: phandle pointing to the system reset controller and
|
||||
reset line index, see reset/fsl,imx-src.txt for details
|
||||
Additional required properties for fsl,imx6qp-ipu:
|
||||
- fsl,prg: phandle to prg node associated with this IPU instance
|
||||
Optional properties:
|
||||
- port@[0-3]: Port nodes with endpoint definitions as defined in
|
||||
Documentation/devicetree/bindings/media/video-interfaces.txt.
|
||||
Ports 0 and 1 should correspond to CSI0 and CSI1,
|
||||
ports 2 and 3 should correspond to DI0 and DI1, respectively.
|
||||
|
||||
example:
|
||||
|
||||
ipu: ipu@18000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx53-ipu";
|
||||
reg = <0x18000000 0x080000000>;
|
||||
interrupts = <11 10>;
|
||||
resets = <&src 2>;
|
||||
|
||||
ipu_di0: port@2 {
|
||||
reg = <2>;
|
||||
|
||||
ipu_di0_disp0: endpoint {
|
||||
remote-endpoint = <&display_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
Freescale i.MX PRE (Prefetch Resolve Engine)
|
||||
============================================
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "fsl,imx6qp-pre"
|
||||
- reg: should be register base and length as documented in the
|
||||
datasheet
|
||||
- clocks : phandle to the PRE axi clock input, as described
|
||||
in Documentation/devicetree/bindings/clock/clock-bindings.txt and
|
||||
Documentation/devicetree/bindings/clock/imx6q-clock.yaml.
|
||||
- clock-names: should be "axi"
|
||||
- interrupts: should contain the PRE interrupt
|
||||
- fsl,iram: phandle pointing to the mmio-sram device node, that should be
|
||||
used for the PRE SRAM double buffer.
|
||||
|
||||
example:
|
||||
|
||||
pre@21c8000 {
|
||||
compatible = "fsl,imx6qp-pre";
|
||||
reg = <0x021c8000 0x1000>;
|
||||
interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
|
||||
clocks = <&clks IMX6QDL_CLK_PRE0>;
|
||||
clock-names = "axi";
|
||||
fsl,iram = <&ocram2>;
|
||||
};
|
||||
|
||||
Freescale i.MX PRG (Prefetch Resolve Gasket)
|
||||
============================================
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "fsl,imx6qp-prg"
|
||||
- reg: should be register base and length as documented in the
|
||||
datasheet
|
||||
- clocks : phandles to the PRG ipg and axi clock inputs, as described
|
||||
in Documentation/devicetree/bindings/clock/clock-bindings.txt and
|
||||
Documentation/devicetree/bindings/clock/imx6q-clock.yaml.
|
||||
- clock-names: should be "ipg" and "axi"
|
||||
- fsl,pres: phandles to the PRE units attached to this PRG, with the fixed
|
||||
PRE as the first entry and the muxable PREs following.
|
||||
|
||||
example:
|
||||
|
||||
prg@21cc000 {
|
||||
compatible = "fsl,imx6qp-prg";
|
||||
reg = <0x021cc000 0x1000>;
|
||||
clocks = <&clks IMX6QDL_CLK_PRG0_APB>,
|
||||
<&clks IMX6QDL_CLK_PRG0_AXI>;
|
||||
clock-names = "ipg", "axi";
|
||||
fsl,pres = <&pre1>, <&pre2>, <&pre3>;
|
||||
};
|
||||
|
||||
Parallel display support
|
||||
========================
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "fsl,imx-parallel-display"
|
||||
Optional properties:
|
||||
- interface-pix-fmt: How this display is connected to the
|
||||
display interface. Currently supported types: "rgb24", "rgb565", "bgr666"
|
||||
and "lvds666".
|
||||
- ddc: phandle describing the i2c bus handling the display data
|
||||
channel
|
||||
- port@[0-1]: Port nodes with endpoint definitions as defined in
|
||||
Documentation/devicetree/bindings/media/video-interfaces.txt.
|
||||
Port 0 is the input port connected to the IPU display interface,
|
||||
port 1 is the output port connected to a panel.
|
||||
|
||||
example:
|
||||
|
||||
disp0 {
|
||||
compatible = "fsl,imx-parallel-display";
|
||||
interface-pix-fmt = "rgb24";
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
display_in: endpoint {
|
||||
remote-endpoint = <&ipu_di0_disp0>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
display_out: endpoint {
|
||||
remote-endpoint = <&panel_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
panel {
|
||||
...
|
||||
|
||||
port {
|
||||
panel_in: endpoint {
|
||||
remote-endpoint = <&display_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -1,146 +0,0 @@
|
||||
Device-Tree bindings for LVDS Display Bridge (ldb)
|
||||
|
||||
LVDS Display Bridge
|
||||
===================
|
||||
|
||||
The LVDS Display Bridge device tree node contains up to two lvds-channel
|
||||
nodes describing each of the two LVDS encoder channels of the bridge.
|
||||
|
||||
Required properties:
|
||||
- #address-cells : should be <1>
|
||||
- #size-cells : should be <0>
|
||||
- compatible : should be "fsl,imx53-ldb" or "fsl,imx6q-ldb".
|
||||
Both LDB versions are similar, but i.MX6 has an additional
|
||||
multiplexer in the front to select any of the four IPU display
|
||||
interfaces as input for each LVDS channel.
|
||||
- gpr : should be <&gpr> on i.MX53 and i.MX6q.
|
||||
The phandle points to the iomuxc-gpr region containing the LVDS
|
||||
control register.
|
||||
- clocks, clock-names : phandles to the LDB divider and selector clocks and to
|
||||
the display interface selector clocks, as described in
|
||||
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
The following clocks are expected on i.MX53:
|
||||
"di0_pll" - LDB LVDS channel 0 mux
|
||||
"di1_pll" - LDB LVDS channel 1 mux
|
||||
"di0" - LDB LVDS channel 0 gate
|
||||
"di1" - LDB LVDS channel 1 gate
|
||||
"di0_sel" - IPU1 DI0 mux
|
||||
"di1_sel" - IPU1 DI1 mux
|
||||
On i.MX6q the following additional clocks are needed:
|
||||
"di2_sel" - IPU2 DI0 mux
|
||||
"di3_sel" - IPU2 DI1 mux
|
||||
The needed clock numbers for each are documented in
|
||||
Documentation/devicetree/bindings/clock/imx5-clock.yaml, and in
|
||||
Documentation/devicetree/bindings/clock/imx6q-clock.yaml.
|
||||
|
||||
Optional properties:
|
||||
- pinctrl-names : should be "default" on i.MX53, not used on i.MX6q
|
||||
- pinctrl-0 : a phandle pointing to LVDS pin settings on i.MX53,
|
||||
not used on i.MX6q
|
||||
- fsl,dual-channel : boolean. if it exists, only LVDS channel 0 should
|
||||
be configured - one input will be distributed on both outputs in dual
|
||||
channel mode
|
||||
|
||||
LVDS Channel
|
||||
============
|
||||
|
||||
Each LVDS Channel has to contain either an of graph link to a panel device node
|
||||
or a display-timings node that describes the video timings for the connected
|
||||
LVDS display as well as the fsl,data-mapping and fsl,data-width properties.
|
||||
|
||||
Required properties:
|
||||
- reg : should be <0> or <1>
|
||||
- port: Input and output port nodes with endpoint definitions as defined in
|
||||
Documentation/devicetree/bindings/graph.txt.
|
||||
On i.MX5, the internal two-input-multiplexer is used. Due to hardware
|
||||
limitations, only one input port (port@[0,1]) can be used for each channel
|
||||
(lvds-channel@[0,1], respectively).
|
||||
On i.MX6, there should be four input ports (port@[0-3]) that correspond
|
||||
to the four LVDS multiplexer inputs.
|
||||
A single output port (port@2 on i.MX5, port@4 on i.MX6) must be connected
|
||||
to a panel input port. Optionally, the output port can be left out if
|
||||
display-timings are used instead.
|
||||
|
||||
Optional properties (required if display-timings are used):
|
||||
- display-timings : A node that describes the display timings as defined in
|
||||
Documentation/devicetree/bindings/display/panel/display-timing.txt.
|
||||
- fsl,data-mapping : should be "spwg" or "jeida"
|
||||
This describes how the color bits are laid out in the
|
||||
serialized LVDS signal.
|
||||
- fsl,data-width : should be <18> or <24>
|
||||
|
||||
example:
|
||||
|
||||
gpr: iomuxc-gpr@53fa8000 {
|
||||
/* ... */
|
||||
};
|
||||
|
||||
ldb: ldb@53fa8008 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx53-ldb";
|
||||
gpr = <&gpr>;
|
||||
clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
|
||||
<&clks IMX5_CLK_LDB_DI1_SEL>,
|
||||
<&clks IMX5_CLK_IPU_DI0_SEL>,
|
||||
<&clks IMX5_CLK_IPU_DI1_SEL>,
|
||||
<&clks IMX5_CLK_LDB_DI0_GATE>,
|
||||
<&clks IMX5_CLK_LDB_DI1_GATE>;
|
||||
clock-names = "di0_pll", "di1_pll",
|
||||
"di0_sel", "di1_sel",
|
||||
"di0", "di1";
|
||||
|
||||
/* Using an of-graph endpoint link to connect the panel */
|
||||
lvds-channel@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
lvds0_in: endpoint {
|
||||
remote-endpoint = <&ipu_di0_lvds0>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
|
||||
lvds0_out: endpoint {
|
||||
remote-endpoint = <&panel_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* Using display-timings and fsl,data-mapping/width instead */
|
||||
lvds-channel@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
fsl,data-mapping = "spwg";
|
||||
fsl,data-width = <24>;
|
||||
|
||||
display-timings {
|
||||
/* ... */
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
lvds1_in: endpoint {
|
||||
remote-endpoint = <&ipu_di1_lvds1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
panel: lvds-panel {
|
||||
/* ... */
|
||||
|
||||
port {
|
||||
panel_in: endpoint {
|
||||
remote-endpoint = <&lvds0_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -25,6 +25,10 @@ properties:
|
||||
- mediatek,mt8173-disp-aal
|
||||
- mediatek,mt8183-disp-aal
|
||||
- mediatek,mt8195-mdp3-aal
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8188-mdp3-aal
|
||||
- const: mediatek,mt8195-mdp3-aal
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt2712-disp-aal
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user