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Merge branch '2024-04-13-assorted-fixes' into next

Browse Source 
- Fix bootm_low handling, CONFIG_64BIT usage fixes, RNG fixes, cli
  history fixes, allow bootelf to pass a device tree address, other
  assorted fixes.
This commit is contained in:
Tom Rini 2024-03-13 18:47:16 -04:00
commit 3987e15e88
98 changed files with 166 additions and 4722 deletions
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1
.gitignore vendored
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@ -63,6 +63,7 @@ fit-dtb.blob*
/spl/
/tpl/
/defconfig
/generated_defconfig
#
# Generated include files

7
MAINTAINERS
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@ -683,13 +683,6 @@ F: tools/stm32image.c
N: stm
N: stm32
ARM STM STV0991
M: Vikas Manocha <vikas.manocha@st.com>
S: Maintained
F: arch/arm/cpu/armv7/stv0991/
F: arch/arm/include/asm/arch-stv0991/
ARM SUNXI
M: Jagan Teki <jagan@amarulasolutions.com>
M: Andre Przywara <andre.przywara@arm.com>

1
Makefile
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@ -2233,6 +2233,7 @@ clean: $(clean-dirs)
-o -name modules.builtin -o -name '.tmp_*.o.*' \
-o -name 'dsdt_generated.aml' -o -name 'dsdt_generated.asl.tmp' \
-o -name 'dsdt_generated.c' \
-o -name 'generated_defconfig' \
-o -name '*.efi' -o -name '*.gcno' -o -name '*.so' \) \
-type f -print | xargs rm -f

6
arch/Kconfig
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@ -20,6 +20,12 @@ config SYS_CACHE_SHIFT_6
config SYS_CACHE_SHIFT_7
bool
config 32BIT
bool
config 64BIT
bool
config SYS_CACHELINE_SIZE
int
default 128 if SYS_CACHE_SHIFT_7

16
arch/arm/Kconfig
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@ -6,6 +6,7 @@ config SYS_ARCH
config ARM64
bool
select 64BIT
select PHYS_64BIT
select SYS_CACHE_SHIFT_6
imply SPL_SEPARATE_BSS
@ -631,20 +632,6 @@ config ARCH_ORION5X
select SPL_SEPARATE_BSS if SPL
select TIMER
config TARGET_STV0991
bool "Support stv0991"
select CPU_V7A
select DM
select DM_SERIAL
select DM_SPI
select DM_SPI_FLASH
select GPIO_EXTRA_HEADER
select PL01X_SERIAL
select MTD
select SPI
select SPI_FLASH
imply CMD_DM
config ARCH_BCM283X
bool "Broadcom BCM283X family"
select DM
@ -2358,7 +2345,6 @@ source "board/samsung/common/Kconfig"
source "board/siemens/common/Kconfig"
source "board/seeed/npi_imx6ull/Kconfig"
source "board/socionext/developerbox/Kconfig"
source "board/st/stv0991/Kconfig"
source "board/tcl/sl50/Kconfig"
source "board/traverse/ten64/Kconfig"
source "board/variscite/dart_6ul/Kconfig"

1
arch/arm/cpu/armv7/Makefile
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@ -37,7 +37,6 @@ obj-$(if $(filter bcm281xx,$(SOC)),y) += bcm281xx/
obj-$(if $(filter bcmcygnus,$(SOC)),y) += bcmcygnus/
obj-$(if $(filter bcmnsp,$(SOC)),y) += bcmnsp/
obj-$(if $(filter ls102xa,$(SOC)),y) += ls102xa/
obj-$(if $(filter stv0991,$(SOC)),y) += stv0991/
obj-$(CONFIG_ARCH_SUNXI) += sunxi/
obj-$(CONFIG_VF610) += vf610/
obj-$(CONFIG_ARCH_S5P4418) += s5p4418/

7
arch/arm/cpu/armv7/stv0991/Makefile
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@ -1,7 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2014, STMicroelectronics - All Rights Reserved
# Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
obj-y := timer.o clock.o pinmux.o reset.o
obj-y += lowlevel.o

42
arch/arm/cpu/armv7/stv0991/clock.c
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@ -1,42 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2014, STMicroelectronics - All Rights Reserved
* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*/
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/stv0991_cgu.h>
#include<asm/arch/stv0991_periph.h>
static struct stv0991_cgu_regs *const stv0991_cgu_regs = \
(struct stv0991_cgu_regs *) (CGU_BASE_ADDR);
void enable_pll1(void)
{
/* pll1 already configured for 1000Mhz, just need to enable it */
writel(readl(&stv0991_cgu_regs->pll1_ctrl) & ~(0x01),
&stv0991_cgu_regs->pll1_ctrl);
}
void clock_setup(int peripheral)
{
switch (peripheral) {
case UART_CLOCK_CFG:
writel(UART_CLK_CFG, &stv0991_cgu_regs->uart_freq);
break;
case ETH_CLOCK_CFG:
enable_pll1();
writel(ETH_CLK_CFG, &stv0991_cgu_regs->eth_freq);
/* Clock selection for ethernet tx_clk & rx_clk*/
writel((readl(&stv0991_cgu_regs->eth_ctrl) & ETH_CLK_MASK)
| ETH_CLK_CTRL, &stv0991_cgu_regs->eth_ctrl);
break;
case QSPI_CLOCK_CFG:
writel(QSPI_CLK_CTRL, &stv0991_cgu_regs->qspi_freq);
break;
default:
break;
}
}

11
arch/arm/cpu/armv7/stv0991/lowlevel.S
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@ -1,11 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2014 STMicroelectronics
*/
#include <config.h>
#include <linux/linkage.h>
ENTRY(lowlevel_init)
mov pc, lr
ENDPROC(lowlevel_init)

66
arch/arm/cpu/armv7/stv0991/pinmux.c
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@ -1,66 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2014, STMicroelectronics - All Rights Reserved
* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*/
#include <asm/io.h>
#include <asm/arch/stv0991_creg.h>
#include <asm/arch/stv0991_periph.h>
#include <asm/arch/hardware.h>
static struct stv0991_creg *const stv0991_creg = \
(struct stv0991_creg *)CREG_BASE_ADDR;
int stv0991_pinmux_config(int peripheral)
{
switch (peripheral) {
case UART_GPIOC_30_31:
/* SSDA/SSCL pad muxing to UART Rx/Dx */
writel((readl(&stv0991_creg->mux12) & GPIOC_31_MUX_MASK) |
CFG_GPIOC_31_UART_RX,
&stv0991_creg->mux12);
writel((readl(&stv0991_creg->mux12) & GPIOC_30_MUX_MASK) |
CFG_GPIOC_30_UART_TX,
&stv0991_creg->mux12);
/* SSDA/SSCL pad config to push pull*/
writel((readl(&stv0991_creg->cfg_pad6) & GPIOC_31_MODE_MASK) |
CFG_GPIOC_31_MODE_PP,
&stv0991_creg->cfg_pad6);
writel((readl(&stv0991_creg->cfg_pad6) & GPIOC_30_MODE_MASK) |
CFG_GPIOC_30_MODE_HIGH,
&stv0991_creg->cfg_pad6);
break;
case UART_GPIOB_16_17:
/* ethernet rx_6/7 to UART Rx/Dx */
writel((readl(&stv0991_creg->mux7) & GPIOB_17_MUX_MASK) |
CFG_GPIOB_17_UART_RX,
&stv0991_creg->mux7);
writel((readl(&stv0991_creg->mux7) & GPIOB_16_MUX_MASK) |
CFG_GPIOB_16_UART_TX,
&stv0991_creg->mux7);
break;
case ETH_GPIOB_10_31_C_0_4:
writel(readl(&stv0991_creg->mux6) & 0x000000FF,
&stv0991_creg->mux6);
writel(0x00000000, &stv0991_creg->mux7);
writel(0x00000000, &stv0991_creg->mux8);
writel(readl(&stv0991_creg->mux9) & 0xFFF00000,
&stv0991_creg->mux9);
/* Ethernet Voltage configuration to 1.8V*/
writel((readl(&stv0991_creg->vdd_pad1) & VDD_ETH_PS_MASK) |
ETH_VDD_CFG, &stv0991_creg->vdd_pad1);
writel((readl(&stv0991_creg->vdd_pad1) & VDD_ETH_PS_MASK) |
ETH_M_VDD_CFG, &stv0991_creg->vdd_pad1);
break;
case QSPI_CS_CLK_PAD:
writel((readl(&stv0991_creg->mux13) & FLASH_CS_NC_MASK) |
CFG_FLASH_CS_NC, &stv0991_creg->mux13);
writel((readl(&stv0991_creg->mux13) & FLASH_CLK_MASK) |
CFG_FLASH_CLK, &stv0991_creg->mux13);
default:
break;
}
return 0;
}

27
arch/arm/cpu/armv7/stv0991/reset.c
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@ -1,27 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2014, STMicroelectronics - All Rights Reserved
* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*/
#include <common.h>
#include <cpu_func.h>
#include <asm/io.h>
#include <asm/arch/stv0991_wdru.h>
#include <linux/delay.h>
void reset_cpu(void)
{
puts("System is going to reboot ...\n");
/*
* This 1 second delay will allow the above message
* to be printed before reset
*/
udelay((1000 * 1000));
/* Setting bit 1 of the WDRU unit will reset the SoC */
writel(WDRU_RST_SYS, &stv0991_wd_ru_ptr->wdru_ctrl1);
/* system will restart */
while (1)
;
}

114
arch/arm/cpu/armv7/stv0991/timer.c
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@ -1,114 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2014, STMicroelectronics - All Rights Reserved
* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*/
#include <common.h>
#include <init.h>
#include <time.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch-stv0991/hardware.h>
#include <asm/arch-stv0991/stv0991_cgu.h>
#include <asm/arch-stv0991/stv0991_gpt.h>
#include <linux/delay.h>
static struct stv0991_cgu_regs *const stv0991_cgu_regs = \
(struct stv0991_cgu_regs *) (CGU_BASE_ADDR);
#define READ_TIMER() (readl(&gpt1_regs_ptr->cnt) & GPT_FREE_RUNNING)
#define GPT_RESOLUTION (CFG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)
DECLARE_GLOBAL_DATA_PTR;
#define timestamp gd->arch.tbl
#define lastdec gd->arch.lastinc
static ulong get_timer_masked(void);
int timer_init(void)
{
/* Timer1 clock configuration */
writel(TIMER1_CLK_CFG, &stv0991_cgu_regs->tim_freq);
writel(readl(&stv0991_cgu_regs->cgu_enable_2) |
TIMER1_CLK_EN, &stv0991_cgu_regs->cgu_enable_2);
/* Stop the timer */
writel(readl(&gpt1_regs_ptr->cr1) & ~GPT_CR1_CEN, &gpt1_regs_ptr->cr1);
writel(GPT_PRESCALER_128, &gpt1_regs_ptr->psc);
/* Configure timer for auto-reload */
writel(readl(&gpt1_regs_ptr->cr1) | GPT_MODE_AUTO_RELOAD,
&gpt1_regs_ptr->cr1);
/* load value for free running */
writel(GPT_FREE_RUNNING, &gpt1_regs_ptr->arr);
/* start timer */
writel(readl(&gpt1_regs_ptr->cr1) | GPT_CR1_CEN,
&gpt1_regs_ptr->cr1);
/* Reset the timer */
lastdec = READ_TIMER();
timestamp = 0;
return 0;
}
/*
* timer without interrupts
*/
ulong get_timer(ulong base)
{
return (get_timer_masked() / GPT_RESOLUTION) - base;
}
void __udelay(unsigned long usec)
{
ulong tmo;
ulong start = get_timer_masked();
ulong tenudelcnt = CFG_SYS_HZ_CLOCK / (1000 * 100);
ulong rndoff;
rndoff = (usec % 10) ? 1 : 0;
/* tenudelcnt timer tick gives 10 microsecconds delay */
tmo = ((usec / 10) + rndoff) * tenudelcnt;
while ((ulong) (get_timer_masked() - start) < tmo)
;
}
static ulong get_timer_masked(void)
{
ulong now = READ_TIMER();
if (now >= lastdec) {
/* normal mode */
timestamp += now - lastdec;
} else {
/* we have an overflow ... */
timestamp += now + GPT_FREE_RUNNING - lastdec;
}
lastdec = now;
return timestamp;
}
/*
* This function is derived from PowerPC code (read timebase as long long).
* On ARM it just returns the timer value.
*/
unsigned long long get_ticks(void)
{
return get_timer(0);
}
/*
* This function is derived from PowerPC code (timebase clock frequency).
* On ARM it returns the number of timer ticks per second.
*/
ulong get_tbclk(void)
{
return CONFIG_SYS_HZ;
}

5
arch/arm/dts/Makefile
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@ -569,7 +569,6 @@ dtb-$(CONFIG_TARGET_AM57XX_EVM) += am57xx-beagle-x15.dtb \
am574x-idk.dtb \
am572x-idk.dtb \
am571x-idk.dtb
dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb
dtb-$(CONFIG_ARCH_LS1021A) += ls1021a-qds-duart.dtb \
ls1021a-qds-lpuart.dtb \
@ -1418,9 +1417,7 @@ dtb-$(CONFIG_SOC_K3_J721S2) += k3-am68-sk-base-board.dtb\
dtb-$(CONFIG_SOC_K3_J784S4) += k3-am69-r5-sk.dtb \
k3-j784s4-r5-evm.dtb
dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-evm.dtb \
k3-am642-r5-evm.dtb \
k3-am642-sk.dtb \
dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-r5-evm.dtb \
k3-am642-r5-sk.dtb \
k3-am642-phyboard-electra-rdk.dtb \
k3-am642-r5-phycore-som-2gb.dtb

1546
arch/arm/dts/k3-am64-main.dtsi
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File diff suppressed because it is too large Load Diff

161
arch/arm/dts/k3-am64-mcu.dtsi
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@ -1,161 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for AM64 SoC Family MCU Domain peripherals
*
* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
&cbass_mcu {
/*
* The MCU domain timer interrupts are routed only to the ESM module,
* and not currently available for Linux. The MCU domain timers are
* of limited use without interrupts, and likely reserved by the ESM.
*/
mcu_timer0: timer@4800000 {
compatible = "ti,am654-timer";
reg = <0x00 0x4800000 0x00 0x400>;
clocks = <&k3_clks 35 1>;
clock-names = "fck";
power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
status = "reserved";
};
mcu_timer1: timer@4810000 {
compatible = "ti,am654-timer";
reg = <0x00 0x4810000 0x00 0x400>;
clocks = <&k3_clks 48 1>;
clock-names = "fck";
power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
status = "reserved";
};
mcu_timer2: timer@4820000 {
compatible = "ti,am654-timer";
reg = <0x00 0x4820000 0x00 0x400>;
clocks = <&k3_clks 49 1>;
clock-names = "fck";
power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
status = "reserved";
};
mcu_timer3: timer@4830000 {
compatible = "ti,am654-timer";
reg = <0x00 0x4830000 0x00 0x400>;
clocks = <&k3_clks 50 1>;
clock-names = "fck";
power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
status = "reserved";
};
mcu_uart0: serial@4a00000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x04a00000 0x00 0x100>;
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 149 0>;
clock-names = "fclk";
status = "disabled";
};
mcu_uart1: serial@4a10000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x04a10000 0x00 0x100>;
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 160 0>;
clock-names = "fclk";
status = "disabled";
};
mcu_i2c0: i2c@4900000 {
compatible = "ti,am64-i2c", "ti,omap4-i2c";
reg = <0x00 0x04900000 0x00 0x100>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 106 2>;
clock-names = "fck";
status = "disabled";
};
mcu_i2c1: i2c@4910000 {
compatible = "ti,am64-i2c", "ti,omap4-i2c";
reg = <0x00 0x04910000 0x00 0x100>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 107 2>;
clock-names = "fck";
status = "disabled";
};
mcu_spi0: spi@4b00000 {
compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
reg = <0x00 0x04b00000 0x00 0x400>;
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 147 0>;
status = "disabled";
};
mcu_spi1: spi@4b10000 {
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
reg = <0x00 0x04b10000 0x00 0x400>;
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 148 0>;
status = "disabled";
};
mcu_gpio_intr: interrupt-controller@4210000 {
compatible = "ti,sci-intr";
reg = <0x00 0x04210000 0x00 0x200>;
ti,intr-trigger-type = <1>;
interrupt-controller;
interrupt-parent = <&gic500>;
#interrupt-cells = <1>;
ti,sci = <&dmsc>;
ti,sci-dev-id = <5>;
ti,interrupt-ranges = <0 104 4>;
};
mcu_gpio0: gpio@4201000 {
compatible = "ti,am64-gpio", "ti,keystone-gpio";
reg = <0x0 0x4201000 0x0 0x100>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&mcu_gpio_intr>;
interrupts = <30>, <31>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <23>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 79 0>;
clock-names = "gpio";
};
mcu_pmx0: pinctrl@4084000 {
compatible = "pinctrl-single";
reg = <0x00 0x4084000 0x00 0x84>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
};
mcu_esm: esm@4100000 {
compatible = "ti,j721e-esm";
reg = <0x00 0x4100000 0x00 0x1000>;
ti,esm-pins = <0>, <1>;
};
};

33
arch/arm/dts/k3-am64-thermal.dtsi
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@ -1,33 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/thermal/thermal.h>
thermal_zones: thermal-zones {
main0_thermal: main0-thermal {
polling-delay-passive = <250>; /* milliSeconds */
polling-delay = <500>; /* milliSeconds */
thermal-sensors = <&main_vtm0 0>;
trips {
main0_crit: main0-crit {
temperature = <105000>; /* milliCelsius */
hysteresis = <2000>; /* milliCelsius */
type = "critical";
};
};
};
main1_thermal: main1-thermal {
polling-delay-passive = <250>; /* milliSeconds */
polling-delay = <500>; /* milliSeconds */
thermal-sensors = <&main_vtm0 1>;
trips {
main1_crit: main1-crit {
temperature = <105000>; /* milliCelsius */
hysteresis = <2000>; /* milliCelsius */
type = "critical";
};
};
};
};

100
arch/arm/dts/k3-am64.dtsi
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@ -1,100 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for AM642 SoC Family
*
* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/ti,sci_pm_domain.h>
#include "k3-pinctrl.h"
/ {
model = "Texas Instruments K3 AM642 SoC";
compatible = "ti,am642";
interrupt-parent = <&gic500>;
#address-cells = <2>;
#size-cells = <2>;
chosen { };
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
psci: psci {
compatible = "arm,psci-1.0";
method = "smc";
};
};
a53_timer0: timer-cl0-cpu0 {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
};
pmu: pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
cbass_main: bus@f4000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x000f4000 0x00 0x000f4000 0x00 0x000002d0>, /* PINCTRL */
<0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
<0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
<0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
<0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */
<0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, /* First peripheral window */
<0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
<0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_CORE */
<0x00 0x0e000000 0x00 0x0e000000 0x00 0x00000100>, /* Main RTI0 */
<0x00 0x0e010000 0x00 0x0e010000 0x00 0x00000100>, /* Main RTI1 */
<0x00 0x0f000000 0x00 0x0f000000 0x00 0x00c44200>, /* Second peripheral window */
<0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */
<0x00 0x30000000 0x00 0x30000000 0x00 0x000bc100>, /* ICSSG0/1 */
<0x00 0x37000000 0x00 0x37000000 0x00 0x00040000>, /* TIMERMGR0 TIMERS */
<0x00 0x39000000 0x00 0x39000000 0x00 0x00000400>, /* CPTS0 */
<0x00 0x3b000000 0x00 0x3b000000 0x00 0x00000400>, /* GPMC0_CFG */
<0x00 0x3cd00000 0x00 0x3cd00000 0x00 0x00000200>, /* TIMERMGR0_CONFIG */
<0x00 0x3f004000 0x00 0x3f004000 0x00 0x00000400>, /* GICSS0_REGS */
<0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA2_UL0 */
<0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* CTRL_MMR0 */
<0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
<0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMASS */
<0x00 0x50000000 0x00 0x50000000 0x00 0x08000000>, /* GPMC0 DATA */
<0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */
<0x00 0x68000000 0x00 0x68000000 0x00 0x08000000>, /* PCIe DAT0 */
<0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* OC SRAM */
<0x00 0x78000000 0x00 0x78000000 0x00 0x00800000>, /* Main R5FSS */
<0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */
<0x06 0x00000000 0x06 0x00000000 0x01 0x00000000>, /* PCIe DAT1 */
<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */
/* MCU Domain Range */
<0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>;
cbass_mcu: bus@4000000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral window */
};
};
#include "k3-am64-thermal.dtsi"
};
/* Now include the peripherals for each bus segments */
#include "k3-am64-main.dtsi"
#include "k3-am64-mcu.dtsi"

110
arch/arm/dts/k3-am642-evm-u-boot.dtsi
View File

@ -9,97 +9,27 @@
chosen {
tick-timer = &main_timer0;
};
memory@80000000 {
bootph-all;
};
};
&cbass_main {
bootph-all;
};
&main_timer0 {
bootph-all;
clock-frequency = <200000000>;
};
&main_conf {
bootph-all;
chipid@14 {
bootph-all;
};
};
&main_pmx0 {
bootph-all;
};
&main_i2c0_pins_default {
bootph-all;
};
&main_i2c0 {
bootph-all;
};
&main_uart0_pins_default {
bootph-all;
};
&main_uart0 {
bootph-all;
};
&main_usb0_pins_default {
bootph-all;
};
&usb0 {
dr_mode="peripheral";
bootph-all;
};
&usbss0 {
bootph-all;
};
&main_mmc1_pins_default {
bootph-all;
};
&main_usb0_pins_default {
bootph-all;
};
&dmss {
bootph-all;
};
&secure_proxy_main {
bootph-all;
};
&dmsc {
bootph-all;
k3_sysreset: sysreset-controller {
compatible = "ti,sci-sysreset";
bootph-all;
};
};
&k3_pds {
bootph-all;
};
&k3_clks {
bootph-all;
};
&k3_reset {
bootph-all;
};
&sdhci0 {
bootph-all;
};
@ -108,10 +38,6 @@
bootph-all;
};
&sdhci1 {
bootph-all;
};
&inta_main_dmss {
bootph-all;
};
@ -143,42 +69,6 @@
bootph-all;
};
&mdio1_pins_default {
bootph-all;
};
&cpsw3g_mdio {
bootph-all;
};
&cpsw3g_phy0 {
bootph-all;
};
&rgmii1_pins_default {
bootph-all;
};
&rgmii2_pins_default {
bootph-all;
};
&cpsw3g {
bootph-all;
ethernet-ports {
bootph-all;
};
};
&phy_gmii_sel {
bootph-all;
};
&cpsw_port1 {
bootph-all;
};
&cpsw_port2 {
status = "disabled";
};

690
arch/arm/dts/k3-am642-evm.dts
View File

@ -1,690 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/net/ti-dp83867.h>
#include "k3-am642.dtsi"
#include "k3-serdes.h"
/ {
compatible = "ti,am642-evm", "ti,am642";
model = "Texas Instruments AM642 EVM";
chosen {
stdout-path = &main_uart0;
};
aliases {
serial0 = &mcu_uart0;
serial1 = &main_uart1;
serial2 = &main_uart0;
serial3 = &main_uart3;
i2c0 = &main_i2c0;
i2c1 = &main_i2c1;
mmc0 = &sdhci0;
mmc1 = &sdhci1;
ethernet0 = &cpsw_port1;
ethernet1 = &cpsw_port2;
};
memory@80000000 {
device_type = "memory";
/* 2G RAM */
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
secure_ddr: optee@9e800000 {
reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
alignment = <0x1000>;
no-map;
};
main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa0000000 0x00 0x100000>;
no-map;
};
main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa0100000 0x00 0xf00000>;
no-map;
};
main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa1000000 0x00 0x100000>;
no-map;
};
main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa1100000 0x00 0xf00000>;
no-map;
};
main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa2000000 0x00 0x100000>;
no-map;
};
main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa2100000 0x00 0xf00000>;
no-map;
};
main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa3000000 0x00 0x100000>;
no-map;
};
main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa3100000 0x00 0xf00000>;
no-map;
};
rtos_ipc_memory_region: ipc-memories@a5000000 {
reg = <0x00 0xa5000000 0x00 0x00800000>;
alignment = <0x1000>;
no-map;
};
};
evm_12v0: regulator-0 {
/* main DC jack */
compatible = "regulator-fixed";
regulator-name = "evm_12v0";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
regulator-always-on;
regulator-boot-on;
};
vsys_5v0: regulator-1 {
/* output of LM5140 */
compatible = "regulator-fixed";
regulator-name = "vsys_5v0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&evm_12v0>;
regulator-always-on;
regulator-boot-on;
};
vsys_3v3: regulator-2 {
/* output of LM5140 */
compatible = "regulator-fixed";
regulator-name = "vsys_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&evm_12v0>;
regulator-always-on;
regulator-boot-on;
};
vdd_mmc1: regulator-3 {
/* TPS2051BD */
compatible = "regulator-fixed";
regulator-name = "vdd_mmc1";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
enable-active-high;
vin-supply = <&vsys_3v3>;
gpio = <&exp1 6 GPIO_ACTIVE_HIGH>;
};
vddb: regulator-4 {
compatible = "regulator-fixed";
regulator-name = "vddb_3v3_display";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vsys_3v3>;
regulator-always-on;
regulator-boot-on;
};
vtt_supply: regulator-5 {
compatible = "regulator-fixed";
regulator-name = "vtt";
pinctrl-names = "default";
pinctrl-0 = <&ddr_vtt_pins_default>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&main_gpio0 12 GPIO_ACTIVE_HIGH>;
vin-supply = <&vsys_3v3>;
enable-active-high;
regulator-always-on;
regulator-boot-on;
};
leds {
compatible = "gpio-leds";
led-0 {
label = "am64-evm:red:heartbeat";
gpios = <&exp1 16 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
function = LED_FUNCTION_HEARTBEAT;
default-state = "off";
};
};
mdio_mux: mux-controller {
compatible = "gpio-mux";
#mux-control-cells = <0>;
mux-gpios = <&exp1 12 GPIO_ACTIVE_HIGH>;
};
mdio-mux-1 {
compatible = "mdio-mux-multiplexer";
mux-controls = <&mdio_mux>;
mdio-parent-bus = <&cpsw3g_mdio>;
#address-cells = <1>;
#size-cells = <0>;
mdio@1 {
reg = <0x1>;
#address-cells = <1>;
#size-cells = <0>;
cpsw3g_phy3: ethernet-phy@3 {
reg = <3>;
};
};
};
transceiver1: can-phy0 {
compatible = "ti,tcan1042";
#phy-cells = <0>;
max-bitrate = <5000000>;
standby-gpios = <&exp1 8 GPIO_ACTIVE_HIGH>;
};
transceiver2: can-phy1 {
compatible = "ti,tcan1042";
#phy-cells = <0>;
max-bitrate = <5000000>;
standby-gpios = <&exp1 9 GPIO_ACTIVE_HIGH>;
};
};
&main_pmx0 {
main_mmc1_pins_default: main-mmc1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */
AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */
AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */
AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */
AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */
AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */
AM64X_IOPAD(0x029c, PIN_INPUT, 0) /* (C20) MMC1_SDWP */
AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* MMC1_CLKLB */
>;
};
main_uart1_pins_default: main-uart1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */
AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */
AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */
AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */
>;
};
main_uart0_pins_default: main-uart0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */
AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */
AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
>;
};
main_spi0_pins_default: main-spi0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0210, PIN_INPUT, 0) /* (D13) SPI0_CLK */
AM64X_IOPAD(0x0208, PIN_OUTPUT, 0) /* (D12) SPI0_CS0 */
AM64X_IOPAD(0x0214, PIN_OUTPUT, 0) /* (A13) SPI0_D0 */
AM64X_IOPAD(0x0218, PIN_INPUT, 0) /* (A14) SPI0_D1 */
>;
};
main_i2c0_pins_default: main-i2c0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */
AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */
>;
};
main_i2c1_pins_default: main-i2c1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */
>;
};
mdio1_pins_default: mdio1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
>;
};
rgmii1_pins_default: rgmii1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* (W5) PRG0_PRU1_GPO7.RGMII1_RD0 */
AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* (Y5) PRG0_PRU1_GPO9.RGMII1_RD1 */
AM64X_IOPAD(0x01d8, PIN_INPUT, 4) /* (V6) PRG0_PRU1_GPO10.RGMII1_RD2 */
AM64X_IOPAD(0x01f4, PIN_INPUT, 4) /* (V5) PRG0_PRU1_GPO17.RGMII1_RD3 */
AM64X_IOPAD(0x0188, PIN_INPUT, 4) /* (AA5) PRG0_PRU0_GPO10.RGMII1_RXC */
AM64X_IOPAD(0x0184, PIN_INPUT, 4) /* (W6) PRG0_PRU0_GPO9.RGMII1_RX_CTL */
AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
>;
};
rgmii2_pins_default: rgmii2-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */
AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */
AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */
AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */
AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */
AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
>;
};
main_usb0_pins_default: main-usb0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
>;
};
ospi0_pins_default: ospi0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */
AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */
AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */
AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */
AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */
AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */
AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */
AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */
AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */
AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */
AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */
>;
};
main_ecap0_pins_default: main-ecap0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */
>;
};
main_mcan0_pins_default: main-mcan0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0254, PIN_INPUT, 0) /* (B17) MCAN0_RX */
AM64X_IOPAD(0x0250, PIN_OUTPUT, 0) /* (A17) MCAN0_TX */
>;
};
main_mcan1_pins_default: main-mcan1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x025c, PIN_INPUT, 0) /* (D17) MCAN1_RX */
AM64X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (C17) MCAN1_TX */
>;
};
ddr_vtt_pins_default: ddr-vtt-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0030, PIN_OUTPUT_PULLUP, 7) /* (L18) OSPI0_CSN1.GPIO0_12 */
>;
};
};
&main_uart0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
current-speed = <115200>;
};
/* main_uart1 is reserved for firmware usage */
&main_uart1 {
status = "reserved";
pinctrl-names = "default";
pinctrl-0 = <&main_uart1_pins_default>;
};
&main_i2c0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins_default>;
clock-frequency = <400000>;
eeprom@50 {
/* AT24CM01 */
compatible = "atmel,24c1024";
reg = <0x50>;
};
};
&main_i2c1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c1_pins_default>;
clock-frequency = <400000>;
exp1: gpio@22 {
compatible = "ti,tca6424";
reg = <0x22>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names = "GPIO_eMMC_RSTn", "CAN_MUX_SEL",
"GPIO_CPSW1_RST", "GPIO_RGMII1_RST",
"GPIO_RGMII2_RST", "GPIO_PCIe_RST_OUT",
"MMC1_SD_EN", "FSI_FET_SEL",
"MCAN0_STB_3V3", "MCAN1_STB_3V3",
"CPSW_FET_SEL", "CPSW_FET2_SEL",
"PRG1_RGMII2_FET_SEL", "TEST_GPIO2",
"GPIO_OLED_RESETn", "VPP_LDO_EN",
"TEST_LED1", "TP92", "TP90", "TP88",
"TP87", "TP86", "TP89", "TP91";
};
/* osd9616p0899-10 */
display@3c {
compatible = "solomon,ssd1306fb-i2c";
reg = <0x3c>;
reset-gpios = <&exp1 14 GPIO_ACTIVE_LOW>;
vbat-supply = <&vddb>;
solomon,height = <16>;
solomon,width = <96>;
solomon,com-seq;
solomon,com-invdir;
solomon,page-offset = <0>;
solomon,prechargep1 = <2>;
solomon,prechargep2 = <13>;
};
};
/* mcu_gpio0 is reserved for mcu firmware usage */
&mcu_gpio0 {
status = "reserved";
};
&main_spi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_spi0_pins_default>;
ti,pindir-d0-out-d1-in;
eeprom@0 {
compatible = "microchip,93lc46b";
reg = <0>;
spi-max-frequency = <1000000>;
spi-cs-high;
data-size = <16>;
};
};
&sdhci0 {
/* emmc */
bus-width = <8>;
non-removable;
ti,driver-strength-ohm = <50>;
disable-wp;
};
&sdhci1 {
/* SD/MMC */
vmmc-supply = <&vdd_mmc1>;
pinctrl-names = "default";
bus-width = <4>;
pinctrl-0 = <&main_mmc1_pins_default>;
ti,driver-strength-ohm = <50>;
disable-wp;
};
&usbss0 {
ti,vbus-divider;
ti,usb2-only;
};
&usb0 {
dr_mode = "otg";
maximum-speed = "high-speed";
pinctrl-names = "default";
pinctrl-0 = <&main_usb0_pins_default>;
};
&cpsw3g {
pinctrl-names = "default";
pinctrl-0 = <&rgmii1_pins_default>, <&rgmii2_pins_default>;
};
&cpsw_port1 {
phy-mode = "rgmii-rxid";
phy-handle = <&cpsw3g_phy0>;
};
&cpsw_port2 {
phy-mode = "rgmii-rxid";
phy-handle = <&cpsw3g_phy3>;
};
&cpsw3g_mdio {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mdio1_pins_default>;
cpsw3g_phy0: ethernet-phy@0 {
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
};
};
&tscadc0 {
/* ADC is reserved for R5 usage */
status = "reserved";
};
&ospi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&ospi0_pins_default>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-tx-bus-width = <8>;
spi-rx-bus-width = <8>;
spi-max-frequency = <25000000>;
cdns,tshsl-ns = <60>;
cdns,tsd2d-ns = <60>;
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "ospi.tiboot3";
reg = <0x0 0x100000>;
};
partition@100000 {
label = "ospi.tispl";
reg = <0x100000 0x200000>;
};
partition@300000 {
label = "ospi.u-boot";
reg = <0x300000 0x400000>;
};
partition@700000 {
label = "ospi.env";
reg = <0x700000 0x40000>;
};
partition@740000 {
label = "ospi.env.backup";
reg = <0x740000 0x40000>;
};
partition@800000 {
label = "ospi.rootfs";
reg = <0x800000 0x37c0000>;
};
partition@3fc0000 {
label = "ospi.phypattern";
reg = <0x3fc0000 0x40000>;
};
};
};
};
&mailbox0_cluster2 {
status = "okay";
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
};
mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
ti,mbox-rx = <2 0 2>;
ti,mbox-tx = <3 0 2>;
};
};
&mailbox0_cluster4 {
status = "okay";
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
};
mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
ti,mbox-rx = <2 0 2>;
ti,mbox-tx = <3 0 2>;
};
};
&mailbox0_cluster6 {
status = "okay";
mbox_m4_0: mbox-m4-0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
};
};
&main_r5fss0_core0 {
mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core0>;
memory-region = <&main_r5fss0_core0_dma_memory_region>,
<&main_r5fss0_core0_memory_region>;
};
&main_r5fss0_core1 {
mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core1>;
memory-region = <&main_r5fss0_core1_dma_memory_region>,
<&main_r5fss0_core1_memory_region>;
};
&main_r5fss1_core0 {
mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core0>;
memory-region = <&main_r5fss1_core0_dma_memory_region>,
<&main_r5fss1_core0_memory_region>;
};
&main_r5fss1_core1 {
mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core1>;
memory-region = <&main_r5fss1_core1_dma_memory_region>,
<&main_r5fss1_core1_memory_region>;
};
&serdes_ln_ctrl {
idle-states = <AM64_SERDES0_LANE0_PCIE0>;
};
&serdes0 {
serdes0_pcie_link: phy@0 {
reg = <0>;
cdns,num-lanes = <1>;
#phy-cells = <0>;
cdns,phy-type = <PHY_TYPE_PCIE>;
resets = <&serdes_wiz0 1>;
};
};
&pcie0_rc {
status = "okay";
reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>;
phys = <&serdes0_pcie_link>;
phy-names = "pcie-phy";
num-lanes = <1>;
};
&pcie0_ep {
phys = <&serdes0_pcie_link>;
phy-names = "pcie-phy";
num-lanes = <1>;
};
&ecap0 {
status = "okay";
/* PWM is available on Pin 1 of header J12 */
pinctrl-names = "default";
pinctrl-0 = <&main_ecap0_pins_default>;
};
&main_mcan0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_mcan0_pins_default>;
phys = <&transceiver1>;
};
&main_mcan1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_mcan1_pins_default>;
phys = <&transceiver2>;
};

24
arch/arm/dts/k3-am642-r5-evm.dts
View File

@ -40,10 +40,6 @@
};
};
&vtt_supply {
bootph-pre-ram;
};
&cbass_main {
sysctrler: sysctrler {
compatible = "ti,am654-system-controller";
@ -53,18 +49,6 @@
};
};
&main_esm {
bootph-pre-ram;
};
&cbass_mcu {
bootph-pre-ram;
};
&mcu_esm {
bootph-pre-ram;
};
&dmsc {
mboxes= <&secure_proxy_main 0>,
<&secure_proxy_main 1>,
@ -74,10 +58,6 @@
ti,secure-host;
};
&vtt_supply {
bootph-pre-ram;
};
&memorycontroller {
vtt-supply = <&vtt_supply>;
};
@ -92,10 +72,6 @@
clock-names = "clk_xin";
};
&main_gpio0 {
bootph-pre-ram;
};
/* UART is initialized before SYSFW is started
* so we can't do any power-domain/clock operations.
* Delete clock/power-domain properties to avoid

12
arch/arm/dts/k3-am642-r5-sk.dts
View File

@ -49,18 +49,6 @@
};
};
&main_esm {
bootph-pre-ram;
};
&cbass_mcu {
bootph-pre-ram;
};
&mcu_esm {
bootph-pre-ram;
};
&dmsc {
mboxes= <&secure_proxy_main 0>,
<&secure_proxy_main 1>,

94
arch/arm/dts/k3-am642-sk-u-boot.dtsi
View File

@ -9,87 +9,21 @@
chosen {
tick-timer = &main_timer0;
};
memory@80000000 {
bootph-all;
};
};
&cbass_main{
bootph-all;
};
&main_timer0 {
bootph-all;
clock-frequency = <200000000>;
};
&main_conf {
bootph-all;
chipid@14 {
bootph-all;
};
};
&main_pmx0 {
bootph-all;
};
&main_i2c0_pins_default {
bootph-all;
};
&main_i2c0 {
bootph-all;
};
&main_uart0_pins_default {
bootph-all;
};
&main_uart0 {
bootph-all;
};
&dmss {
bootph-all;
};
&secure_proxy_main {
bootph-all;
};
&dmsc {
bootph-all;
k3_sysreset: sysreset-controller {
compatible = "ti,sci-sysreset";
bootph-all;
};
};
&k3_pds {
bootph-all;
};
&k3_clks {
bootph-all;
};
&k3_reset {
bootph-all;
};
&sdhci0 {
status = "disabled";
bootph-all;
};
&sdhci1 {
bootph-all;
};
&main_mmc1_pins_default {
bootph-all;
};
&inta_main_dmss {
@ -180,38 +114,10 @@
bootph-all;
};
&main_usb0_pins_default {
bootph-all;
};
&serdes_ln_ctrl {
bootph-all;
};
&usbss0 {
bootph-all;
};
&usb0 {
bootph-all;
};
&serdes_wiz0 {
bootph-all;
};
&serdes0_usb_link {
bootph-all;
};
&serdes0 {
bootph-all;
};
&serdes_refclk {
bootph-all;
};
&ospi0_pins_default {
bootph-all;
};

642
arch/arm/dts/k3-am642-sk.dts
View File

@ -1,642 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/net/ti-dp83867.h>
#include <dt-bindings/leds/common.h>
#include "k3-am642.dtsi"
#include "k3-serdes.h"
/ {
compatible = "ti,am642-sk", "ti,am642";
model = "Texas Instruments AM642 SK";
chosen {
stdout-path = &main_uart0;
};
aliases {
serial0 = &mcu_uart0;
serial1 = &main_uart1;
serial2 = &main_uart0;
i2c0 = &main_i2c0;
i2c1 = &main_i2c1;
mmc0 = &sdhci0;
mmc1 = &sdhci1;
ethernet0 = &cpsw_port1;
ethernet1 = &cpsw_port2;
};
memory@80000000 {
device_type = "memory";
/* 2G RAM */
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
secure_ddr: optee@9e800000 {
reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
alignment = <0x1000>;
no-map;
};
main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa0000000 0x00 0x100000>;
no-map;
};
main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa0100000 0x00 0xf00000>;
no-map;
};
main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa1000000 0x00 0x100000>;
no-map;
};
main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa1100000 0x00 0xf00000>;
no-map;
};
main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa2000000 0x00 0x100000>;
no-map;
};
main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa2100000 0x00 0xf00000>;
no-map;
};
main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa3000000 0x00 0x100000>;
no-map;
};
main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa3100000 0x00 0xf00000>;
no-map;
};
rtos_ipc_memory_region: ipc-memories@a5000000 {
reg = <0x00 0xa5000000 0x00 0x00800000>;
alignment = <0x1000>;
no-map;
};
};
vusb_main: regulator-0 {
/* USB MAIN INPUT 5V DC */
compatible = "regulator-fixed";
regulator-name = "vusb_main5v0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
regulator-boot-on;
};
vcc_3v3_sys: regulator-1 {
/* output of LP8733xx */
compatible = "regulator-fixed";
regulator-name = "vcc_3v3_sys";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vusb_main>;
regulator-always-on;
regulator-boot-on;
};
vdd_mmc1: regulator-2 {
/* TPS2051BD */
compatible = "regulator-fixed";
regulator-name = "vdd_mmc1";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
enable-active-high;
vin-supply = <&vcc_3v3_sys>;
gpio = <&exp1 3 GPIO_ACTIVE_HIGH>;
};
com8_ls_en: regulator-3 {
compatible = "regulator-fixed";
regulator-name = "com8_ls_en";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
pinctrl-0 = <&main_com8_ls_en_pins_default>;
pinctrl-names = "default";
gpio = <&main_gpio0 62 GPIO_ACTIVE_LOW>;
};
wlan_en: regulator-4 {
/* output of SN74AVC4T245RSVR */
compatible = "regulator-fixed";
regulator-name = "wlan_en";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
enable-active-high;
pinctrl-0 = <&main_wlan_en_pins_default>;
pinctrl-names = "default";
vin-supply = <&com8_ls_en>;
gpio = <&main_gpio0 48 GPIO_ACTIVE_HIGH>;
};
led-controller {
compatible = "gpio-leds";
led-0 {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_INDICATOR;
function-enumerator = <1>;
gpios = <&exp2 0 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-1 {
color = <LED_COLOR_ID_RED>;
function = LED_FUNCTION_INDICATOR;
function-enumerator = <2>;
gpios = <&exp2 1 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-2 {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_INDICATOR;
function-enumerator = <3>;
gpios = <&exp2 2 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-3 {
color = <LED_COLOR_ID_AMBER>;
function = LED_FUNCTION_INDICATOR;
function-enumerator = <4>;
gpios = <&exp2 3 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-4 {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_INDICATOR;
function-enumerator = <5>;
gpios = <&exp2 4 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-5 {
color = <LED_COLOR_ID_RED>;
function = LED_FUNCTION_INDICATOR;
function-enumerator = <6>;
gpios = <&exp2 5 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-6 {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_INDICATOR;
function-enumerator = <7>;
gpios = <&exp2 6 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-7 {
color = <LED_COLOR_ID_AMBER>;
function = LED_FUNCTION_HEARTBEAT;
function-enumerator = <8>;
linux,default-trigger = "heartbeat";
gpios = <&exp2 7 GPIO_ACTIVE_HIGH>;
};
};
};
&main_pmx0 {
main_mmc1_pins_default: main-mmc1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x029c, PIN_INPUT_PULLUP, 0) /* (C20) MMC1_SDWP */
AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */
AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* (#N/A) MMC1_CLKLB */
AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */
AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */
AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */
AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */
AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */
>;
};
main_uart0_pins_default: main-uart0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */
AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */
AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
>;
};
main_uart1_pins_default: main-uart1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */
AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */
AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */
AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */
>;
};
main_usb0_pins_default: main-usb0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
>;
};
main_i2c0_pins_default: main-i2c0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */
AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */
>;
};
main_i2c1_pins_default: main-i2c1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */
>;
};
mdio1_pins_default: mdio1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
>;
};
rgmii1_pins_default: rgmii1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x011c, PIN_INPUT, 4) /* (AA13) PRG1_PRU1_GPO5.RGMII1_RD0 */
AM64X_IOPAD(0x0128, PIN_INPUT, 4) /* (U12) PRG1_PRU1_GPO8.RGMII1_RD1 */
AM64X_IOPAD(0x0150, PIN_INPUT, 4) /* (Y13) PRG1_PRU1_GPO18.RGMII1_RD2 */
AM64X_IOPAD(0x0154, PIN_INPUT, 4) /* (V12) PRG1_PRU1_GPO19.RGMII1_RD3 */
AM64X_IOPAD(0x00d8, PIN_INPUT, 4) /* (W13) PRG1_PRU0_GPO8.RGMII1_RXC */
AM64X_IOPAD(0x00cc, PIN_INPUT, 4) /* (V13) PRG1_PRU0_GPO5.RGMII1_RX_CTL */
AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
>;
};
rgmii2_pins_default: rgmii2-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */
AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */
AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */
AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */
AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */
AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
>;
};
ospi0_pins_default: ospi0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */
AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */
AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */
AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */
AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */
AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */
AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */
AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */
AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */
AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */
AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */
>;
};
main_ecap0_pins_default: main-ecap0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */
>;
};
main_wlan_en_pins_default: main-wlan-en-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x00c4, PIN_OUTPUT_PULLUP, 7) /* (V8) GPIO0_48 */
>;
};
main_com8_ls_en_pins_default: main-com8-ls-en-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x00fc, PIN_OUTPUT, 7) /* (U7) PRG1_PRU0_GPO17.GPIO0_62 */
>;
};
main_wlan_pins_default: main-wlan-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x00bc, PIN_INPUT, 7) /* (U8) GPIO0_46 */
>;
};
};
&main_uart0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
current-speed = <115200>;
};
&main_uart1 {
/* main_uart1 is reserved for firmware usage */
status = "reserved";
pinctrl-names = "default";
pinctrl-0 = <&main_uart1_pins_default>;
};
&main_i2c0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins_default>;
clock-frequency = <400000>;
eeprom@51 {
compatible = "atmel,24c512";
reg = <0x51>;
};
};
&main_i2c1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c1_pins_default>;
clock-frequency = <400000>;
exp1: gpio@70 {
compatible = "nxp,pca9538";
reg = <0x70>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST",
"PRU_DETECT", "MMC1_SD_EN",
"VPP_LDO_EN", "RPI_PS_3V3_En",
"RPI_PS_5V0_En", "RPI_HAT_DETECT";
};
exp2: gpio@60 {
compatible = "ti,tpic2810";
reg = <0x60>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names = "LED1","LED2","LED3","LED4","LED5","LED6","LED7","LED8";
};
};
/* mcu_gpio0 is reserved for mcu firmware usage */
&mcu_gpio0 {
status = "reserved";
};
&sdhci0 {
vmmc-supply = <&wlan_en>;
bus-width = <4>;
non-removable;
cap-power-off-card;
keep-power-in-suspend;
ti,driver-strength-ohm = <50>;
#address-cells = <1>;
#size-cells = <0>;
wlcore: wlcore@2 {
compatible = "ti,wl1837";
reg = <2>;
pinctrl-0 = <&main_wlan_pins_default>;
pinctrl-names = "default";
interrupt-parent = <&main_gpio0>;
interrupts = <46 IRQ_TYPE_EDGE_FALLING>;
};
};
&sdhci1 {
/* SD/MMC */
vmmc-supply = <&vdd_mmc1>;
pinctrl-names = "default";
bus-width = <4>;
pinctrl-0 = <&main_mmc1_pins_default>;
ti,driver-strength-ohm = <50>;
disable-wp;
};
&serdes_ln_ctrl {
idle-states = <AM64_SERDES0_LANE0_USB>;
};
&serdes0 {
serdes0_usb_link: phy@0 {
reg = <0>;
cdns,num-lanes = <1>;
#phy-cells = <0>;
cdns,phy-type = <PHY_TYPE_USB3>;
resets = <&serdes_wiz0 1>;
};
};
&usbss0 {
ti,vbus-divider;
};
&usb0 {
dr_mode = "host";
maximum-speed = "super-speed";
pinctrl-names = "default";
pinctrl-0 = <&main_usb0_pins_default>;
phys = <&serdes0_usb_link>;
phy-names = "cdns3,usb3-phy";
};
&cpsw3g {
pinctrl-names = "default";
pinctrl-0 = <&rgmii1_pins_default>, <&rgmii2_pins_default>;
};
&cpsw_port1 {
phy-mode = "rgmii-rxid";
phy-handle = <&cpsw3g_phy0>;
};
&cpsw_port2 {
phy-mode = "rgmii-rxid";
phy-handle = <&cpsw3g_phy1>;
};
&cpsw3g_mdio {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mdio1_pins_default>;
cpsw3g_phy0: ethernet-phy@0 {
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
};
cpsw3g_phy1: ethernet-phy@1 {
reg = <1>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
};
};
&ospi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&ospi0_pins_default>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-tx-bus-width = <8>;
spi-rx-bus-width = <8>;
spi-max-frequency = <25000000>;
cdns,tshsl-ns = <60>;
cdns,tsd2d-ns = <60>;
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "ospi.tiboot3";
reg = <0x0 0x100000>;
};
partition@100000 {
label = "ospi.tispl";
reg = <0x100000 0x200000>;
};
partition@300000 {
label = "ospi.u-boot";
reg = <0x300000 0x400000>;
};
partition@700000 {
label = "ospi.env";
reg = <0x700000 0x40000>;
};
partition@740000 {
label = "ospi.env.backup";
reg = <0x740000 0x40000>;
};
partition@800000 {
label = "ospi.rootfs";
reg = <0x800000 0x37c0000>;
};
partition@3fc0000 {
label = "ospi.phypattern";
reg = <0x3fc0000 0x40000>;
};
};
};
};
&mailbox0_cluster2 {
status = "okay";
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
};
mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
ti,mbox-rx = <2 0 2>;
ti,mbox-tx = <3 0 2>;
};
};
&mailbox0_cluster4 {
status = "okay";
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
};
mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
ti,mbox-rx = <2 0 2>;
ti,mbox-tx = <3 0 2>;
};
};
&mailbox0_cluster6 {
status = "okay";
mbox_m4_0: mbox-m4-0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
};
};
&main_r5fss0_core0 {
mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core0>;
memory-region = <&main_r5fss0_core0_dma_memory_region>,
<&main_r5fss0_core0_memory_region>;
};
&main_r5fss0_core1 {
mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core1>;
memory-region = <&main_r5fss0_core1_dma_memory_region>,
<&main_r5fss0_core1_memory_region>;
};
&main_r5fss1_core0 {
mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core0>;
memory-region = <&main_r5fss1_core0_dma_memory_region>,
<&main_r5fss1_core0_memory_region>;
};
&main_r5fss1_core1 {
mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core1>;
memory-region = <&main_r5fss1_core1_dma_memory_region>,
<&main_r5fss1_core1_memory_region>;
};
&ecap0 {
status = "okay";
/* PWM is available on Pin 1 of header J3 */
pinctrl-names = "default";
pinctrl-0 = <&main_ecap0_pins_default>;
};

66
arch/arm/dts/k3-am642.dtsi
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@ -1,66 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for AM642 SoC family in Dual core configuration
*
* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
#include "k3-am64.dtsi"
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu-map {
cluster0: cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
};
};
cpu0: cpu@0 {
compatible = "arm,cortex-a53";
reg = <0x000>;
device_type = "cpu";
enable-method = "psci";
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&L2_0>;
};
cpu1: cpu@1 {
compatible = "arm,cortex-a53";
reg = <0x001>;
device_type = "cpu";
enable-method = "psci";
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&L2_0>;
};
};
L2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
cache-size = <0x40000>;
cache-line-size = <64>;
cache-sets = <256>;
};
};

6
arch/arm/dts/k3-am64x-binman.dtsi
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@ -118,11 +118,11 @@
#ifdef CONFIG_TARGET_AM642_A53_EVM
#define SPL_AM642_EVM_DTB "spl/dts/k3-am642-evm.dtb"
#define SPL_AM642_SK_DTB "spl/dts/k3-am642-sk.dtb"
#define SPL_AM642_EVM_DTB "spl/dts/ti/k3-am642-evm.dtb"
#define SPL_AM642_SK_DTB "spl/dts/ti/k3-am642-sk.dtb"
#define AM642_EVM_DTB "u-boot.dtb"
#define AM642_SK_DTB "arch/arm/dts/k3-am642-sk.dtb"
#define AM642_SK_DTB "dts/upstream/src/arm64/ti/k3-am642-sk.dtb"
&binman {
ti-spl {

55
arch/arm/dts/stv0991.dts
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@ -1,55 +0,0 @@
/dts-v1/;
/ {
model = "ST STV0991 application board";
compatible = "st,stv0991";
#address-cells = <1>;
#size-cells = <1>;
chosen {
stdout-path = &uart0;
};
memory {
device_type="memory";
reg = <0x0 0x198000>;
};
uart0: serial@0x80406000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x80406000 0x1000>;
clock = <2700000>;
};
aliases {
spi0 = "/spi@80203000"; /* QSPI */
};
qspi: spi@80203000 {
compatible = "cdns,qspi-nor";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x80203000 0x100>,
<0x40000000 0x1000000>;
clocks = <3750000>;
cdns,fifo-depth = <256>;
cdns,fifo-width = <4>;
cdns,trigger-address = <0x40000000>;
status = "okay";
flash0: n25q32@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>; /* chip select */
spi-max-frequency = <50000000>;
m25p,fast-read;
page-size = <256>;
block-size = <16>; /* 2^16, 64KB */
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
cdns,tchsh-ns = <4>;
cdns,tslch-ns = <4>;
};
};
};

21
arch/arm/include/asm/arch-stv0991/gpio.h
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@ -1,21 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2014, STMicroelectronics - All Rights Reserved
* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*/
#ifndef __ASM_ARCH_STV0991_GPIO_H
#define __ASM_ARCH_STV0991_GPIO_H
enum gpio_direction {
GPIO_DIRECTION_IN,
GPIO_DIRECTION_OUT,
};
struct gpio_regs {
u32 data; /* offset 0x0 */
u32 reserved[0xff]; /* 0x4--0x3fc */
u32 dir; /* offset 0x400 */
};
#endif /* __ASM_ARCH_STV0991_GPIO_H */

72
arch/arm/include/asm/arch-stv0991/hardware.h
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@ -1,72 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2014, STMicroelectronics - All Rights Reserved
* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*/
#ifndef _ASM_ARCH_HARDWARE_H
#define _ASM_ARCH_HARDWARE_H
/* STV0991 */
#define SRAM0_BASE_ADDR 0x00000000UL
#define SRAM1_BASE_ADDR 0x00068000UL
#define SRAM2_BASE_ADDR 0x000D0000UL
#define SRAM3_BASE_ADDR 0x00138000UL
#define CFS_SRAM0_BASE_ADDR 0x00198000UL
#define CFS_SRAM1_BASE_ADDR 0x001B8000UL
#define FAST_SRAM_BASE_ADDR 0x001D8000UL
#define FLASH_BASE_ADDR 0x40000000UL
#define PL310_BASE_ADDR 0x70000000UL
#define HSAXIM_BASE_ADDR 0x70100000UL
#define IMGSS_BASE_ADDR 0x70200000UL
#define ADC_BASE_ADDR 0x80000000UL
#define GPIOA_BASE_ADDR 0x80001000UL
#define GPIOB_BASE_ADDR 0x80002000UL
#define GPIOC_BASE_ADDR 0x80003000UL
#define HDM_BASE_ADDR 0x80004000UL
#define THSENS_BASE_ADDR 0x80200000UL
#define GPTIMER2_BASE_ADDR 0x80201000UL
#define GPTIMER1_BASE_ADDR 0x80202000UL
#define QSPI_BASE_ADDR 0x80203000UL
#define CGU_BASE_ADDR 0x80204000UL
#define CREG_BASE_ADDR 0x80205000UL
#define PEC_BASE_ADDR 0x80206000UL
#define WDRU_BASE_ADDR 0x80207000UL
#define BSEC_BASE_ADDR 0x80208000UL
#define DAP_ROM_BASE_ADDR 0x80210000UL
#define SOC_CTI_BASE_ADDR 0x80211000UL
#define TPIU_BASE_ADDR 0x80212000UL
#define TMC_ETF_BASE_ADDR 0x80213000UL
#define R4_ETM_BASE_ADDR 0x80214000UL
#define R4_CTI_BASE_ADDR 0x80215000UL
#define R4_DBG_BASE_ADDR 0x80216000UL
#define GMAC_BASE_ADDR 0x80300000UL
#define RNSS_BASE_ADDR 0x80302000UL
#define CRYP_BASE_ADDR 0x80303000UL
#define HASH_BASE_ADDR 0x80304000UL
#define GPDMA_BASE_ADDR 0x80305000UL
#define ISA_BASE_ADDR 0x8032A000UL
#define HCI_BASE_ADDR 0x80400000UL
#define I2C1_BASE_ADDR 0x80401000UL
#define I2C2_BASE_ADDR 0x80402000UL
#define SAI_BASE_ADDR 0x80403000UL
#define USI_BASE_ADDR 0x80404000UL
#define SPI1_BASE_ADDR 0x80405000UL
#define UART_BASE_ADDR 0x80406000UL
#define SPI2_BASE_ADDR 0x80500000UL
#define CAN_BASE_ADDR 0x80501000UL
#define USART1_BASE_ADDR 0x80502000UL
#define USART2_BASE_ADDR 0x80503000UL
#define USART3_BASE_ADDR 0x80504000UL
#define USART4_BASE_ADDR 0x80505000UL
#define USART5_BASE_ADDR 0x80506000UL
#define USART6_BASE_ADDR 0x80507000UL
#define SDI2_BASE_ADDR 0x80600000UL
#define SDI1_BASE_ADDR 0x80601000UL
#define VICA_BASE_ADDR 0x81000000UL
#define VICB_BASE_ADDR 0x81001000UL
#define STM_CHANNELS_BASE_ADDR 0x81100000UL
#define STM_BASE_ADDR 0x81110000UL
#define SROM_BASE_ADDR 0xFFFF0000UL
#endif /* _ASM_ARCH_HARDWARE_H */

130
arch/arm/include/asm/arch-stv0991/stv0991_cgu.h
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@ -1,130 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2014, STMicroelectronics - All Rights Reserved
* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*/
#ifndef _STV0991_CGU_H
#define _STV0991_CGU_H
struct stv0991_cgu_regs {
u32 cpu_freq; /* offset 0x0 */
u32 icn2_freq; /* offset 0x4 */
u32 dma_freq; /* offset 0x8 */
u32 isp_freq; /* offset 0xc */
u32 h264_freq; /* offset 0x10 */
u32 osif_freq; /* offset 0x14 */
u32 ren_freq; /* offset 0x18 */
u32 tim_freq; /* offset 0x1c */
u32 sai_freq; /* offset 0x20 */
u32 eth_freq; /* offset 0x24 */
u32 i2c_freq; /* offset 0x28 */
u32 spi_freq; /* offset 0x2c */
u32 uart_freq; /* offset 0x30 */
u32 qspi_freq; /* offset 0x34 */
u32 sdio_freq; /* offset 0x38 */
u32 usi_freq; /* offset 0x3c */
u32 can_line_freq; /* offset 0x40 */
u32 debug_freq; /* offset 0x44 */
u32 trace_freq; /* offset 0x48 */
u32 stm_freq; /* offset 0x4c */
u32 eth_ctrl; /* offset 0x50 */
u32 reserved[3]; /* offset 0x54 */
u32 osc_ctrl; /* offset 0x60 */
u32 pll1_ctrl; /* offset 0x64 */
u32 pll1_freq; /* offset 0x68 */
u32 pll1_fract; /* offset 0x6c */
u32 pll1_spread; /* offset 0x70 */
u32 pll1_status; /* offset 0x74 */
u32 pll2_ctrl; /* offset 0x78 */
u32 pll2_freq; /* offset 0x7c */
u32 pll2_fract; /* offset 0x80 */
u32 pll2_spread; /* offset 0x84 */
u32 pll2_status; /* offset 0x88 */
u32 cgu_enable_1; /* offset 0x8c */
u32 cgu_enable_2; /* offset 0x90 */
u32 cgu_isp_pulse; /* offset 0x94 */
u32 cgu_h264_pulse; /* offset 0x98 */
u32 cgu_osif_pulse; /* offset 0x9c */
u32 cgu_ren_pulse; /* offset 0xa0 */
};
/* CGU Timer */
#define CLK_TMR_OSC 0
#define CLK_TMR_MCLK 1
#define CLK_TMR_PLL1 2
#define CLK_TMR_PLL2 3
#define MDIV_SHIFT_TMR 3
#define DIV_SHIFT_TMR 6
#define TIMER1_CLK_CFG (0 << DIV_SHIFT_TMR \
| 0 << MDIV_SHIFT_TMR | CLK_TMR_MCLK)
/* Clock Enable/Disable */
#define TIMER1_CLK_EN (1 << 15)
/* CGU Uart config */
#define CLK_UART_MCLK 0
#define CLK_UART_PLL1 1
#define CLK_UART_PLL2 2
#define MDIV_SHIFT_UART 3
#define DIV_SHIFT_UART 6
#define UART_CLK_CFG (4 << DIV_SHIFT_UART \
| 1 << MDIV_SHIFT_UART | CLK_UART_MCLK)
/* CGU Ethernet clock config */
#define CLK_ETH_MCLK 0
#define CLK_ETH_PLL1 1
#define CLK_ETH_PLL2 2
#define MDIV_SHIFT_ETH 3
#define DIV_SHIFT_ETH 6
#define DIV_ETH_125 9
#define DIV_ETH_50 12
#define DIV_ETH_P2P 15
#define ETH_CLK_CFG (4 << DIV_ETH_P2P | 4 << DIV_ETH_50 \
| 1 << DIV_ETH_125 \
| 0 << DIV_SHIFT_ETH \
| 3 << MDIV_SHIFT_ETH | CLK_ETH_PLL1)
/* CGU Ethernet control */
#define ETH_CLK_TX_EXT_PHY 0
#define ETH_CLK_TX_125M 1
#define ETH_CLK_TX_25M 2
#define ETH_CLK_TX_2M5 3
#define ETH_CLK_TX_DIS 7
#define ETH_CLK_RX_EXT_PHY 0
#define ETH_CLK_RX_25M 1
#define ETH_CLK_RX_2M5 2
#define ETH_CLK_RX_DIS 3
#define RX_CLK_SHIFT 3
#define ETH_CLK_MASK ~(0x1F)
#define ETH_PHY_MODE_GMII 0
#define ETH_PHY_MODE_RMII 1
#define ETH_PHY_CLK_DIS 1
#define ETH_CLK_CTRL (ETH_CLK_RX_EXT_PHY << RX_CLK_SHIFT \
| ETH_CLK_TX_EXT_PHY)
/* CGU qspi clock */
#define DIV_HCLK1_SHIFT 9
#define DIV_CRYP_SHIFT 6
#define MDIV_QSPI_SHIFT 3
#define CLK_QSPI_OSC 0
#define CLK_QSPI_MCLK 1
#define CLK_QSPI_PLL1 2
#define CLK_QSPI_PLL2 3
#define QSPI_CLK_CTRL (3 << DIV_HCLK1_SHIFT \
| 1 << DIV_CRYP_SHIFT \
| 0 << MDIV_QSPI_SHIFT \
| CLK_QSPI_OSC)
#endif

103
arch/arm/include/asm/arch-stv0991/stv0991_creg.h
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@ -1,103 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2014, STMicroelectronics - All Rights Reserved
* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*/
#ifndef _STV0991_CREG_H
#define _STV0991_CREG_H
struct stv0991_creg {
u32 version; /* offset 0x0 */
u32 hdpctl; /* offset 0x4 */
u32 hdpval; /* offset 0x8 */
u32 hdpgposet; /* offset 0xc */
u32 hdpgpoclr; /* offset 0x10 */
u32 hdpgpoval; /* offset 0x14 */
u32 stm_mux; /* offset 0x18 */
u32 sysctrl_1; /* offset 0x1c */
u32 sysctrl_2; /* offset 0x20 */
u32 sysctrl_3; /* offset 0x24 */
u32 sysctrl_4; /* offset 0x28 */
u32 reserved_1[0x35]; /* offset 0x2C-0xFC */
u32 mux1; /* offset 0x100 */
u32 mux2; /* offset 0x104 */
u32 mux3; /* offset 0x108 */
u32 mux4; /* offset 0x10c */
u32 mux5; /* offset 0x110 */
u32 mux6; /* offset 0x114 */
u32 mux7; /* offset 0x118 */
u32 mux8; /* offset 0x11c */
u32 mux9; /* offset 0x120 */
u32 mux10; /* offset 0x124 */
u32 mux11; /* offset 0x128 */
u32 mux12; /* offset 0x12c */
u32 mux13; /* offset 0x130 */
u32 reserved_2[0x33]; /* offset 0x134-0x1FC */
u32 cfg_pad1; /* offset 0x200 */
u32 cfg_pad2; /* offset 0x204 */
u32 cfg_pad3; /* offset 0x208 */
u32 cfg_pad4; /* offset 0x20c */
u32 cfg_pad5; /* offset 0x210 */
u32 cfg_pad6; /* offset 0x214 */
u32 cfg_pad7; /* offset 0x218 */
u32 reserved_3[0x39]; /* offset 0x21C-0x2FC */
u32 vdd_pad1; /* offset 0x300 */
u32 vdd_pad2; /* offset 0x304 */
u32 reserved_4[0x3e]; /* offset 0x308-0x3FC */
u32 vdd_comp1; /* offset 0x400 */
};
/* CREG MUX 13 register */
#define FLASH_CS_NC_SHIFT 4
#define FLASH_CS_NC_MASK ~(7 << FLASH_CS_NC_SHIFT)
#define CFG_FLASH_CS_NC (0 << FLASH_CS_NC_SHIFT)
#define FLASH_CLK_SHIFT 0
#define FLASH_CLK_MASK ~(7 << FLASH_CLK_SHIFT)
#define CFG_FLASH_CLK (0 << FLASH_CLK_SHIFT)
/* CREG MUX 12 register */
#define GPIOC_30_MUX_SHIFT 24
#define GPIOC_30_MUX_MASK ~(1 << GPIOC_30_MUX_SHIFT)
#define CFG_GPIOC_30_UART_TX (1 << GPIOC_30_MUX_SHIFT)
#define GPIOC_31_MUX_SHIFT 28
#define GPIOC_31_MUX_MASK ~(1 << GPIOC_31_MUX_SHIFT)
#define CFG_GPIOC_31_UART_RX (1 << GPIOC_31_MUX_SHIFT)
/* CREG MUX 7 register */
#define GPIOB_16_MUX_SHIFT 0
#define GPIOB_16_MUX_MASK ~(1 << GPIOB_16_MUX_SHIFT)
#define CFG_GPIOB_16_UART_TX (1 << GPIOB_16_MUX_SHIFT)
#define GPIOB_17_MUX_SHIFT 4
#define GPIOB_17_MUX_MASK ~(1 << GPIOB_17_MUX_SHIFT)
#define CFG_GPIOB_17_UART_RX (1 << GPIOB_17_MUX_SHIFT)
/* CREG CFG_PAD6 register */
#define GPIOC_31_MODE_SHIFT 30
#define GPIOC_31_MODE_MASK ~(1 << GPIOC_31_MODE_SHIFT)
#define CFG_GPIOC_31_MODE_OD (0 << GPIOC_31_MODE_SHIFT)
#define CFG_GPIOC_31_MODE_PP (1 << GPIOC_31_MODE_SHIFT)
#define GPIOC_30_MODE_SHIFT 28
#define GPIOC_30_MODE_MASK ~(1 << GPIOC_30_MODE_SHIFT)
#define CFG_GPIOC_30_MODE_LOW (0 << GPIOC_30_MODE_SHIFT)
#define CFG_GPIOC_30_MODE_HIGH (1 << GPIOC_30_MODE_SHIFT)
/* CREG Ethernet pad config */
#define VDD_ETH_PS_1V8 0
#define VDD_ETH_PS_2V5 2
#define VDD_ETH_PS_3V3 3
#define VDD_ETH_PS_MASK 0x3
#define VDD_ETH_PS_SHIFT 12
#define ETH_VDD_CFG (VDD_ETH_PS_1V8 << VDD_ETH_PS_SHIFT)
#define VDD_ETH_M_PS_SHIFT 28
#define ETH_M_VDD_CFG (VDD_ETH_PS_1V8 << VDD_ETH_M_PS_SHIFT)
#endif

14
arch/arm/include/asm/arch-stv0991/stv0991_defs.h
View File

@ -1,14 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2014, STMicroelectronics - All Rights Reserved
* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*/
#ifndef __STV0991_DEFS_H__
#define __STV0991_DEFS_H__
#include <asm/arch/stv0991_periph.h>
extern int stv0991_pinmux_config(enum periph_id);
extern int clock_setup(enum periph_clock);
#endif

41
arch/arm/include/asm/arch-stv0991/stv0991_gpt.h
View File

@ -1,41 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2014, STMicroelectronics - All Rights Reserved
* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*/
#ifndef _STV0991_GPT_H
#define _STV0991_GPT_H
#include <asm/arch-stv0991/hardware.h>
struct gpt_regs {
u32 cr1;
u32 cr2;
u32 reserved_1;
u32 dier; /* dma_int_en */
u32 sr; /* status reg */
u32 egr; /* event gen */
u32 reserved_2[3]; /* offset 0x18--0x20*/
u32 cnt;
u32 psc;
u32 arr;
};
struct gpt_regs *const gpt1_regs_ptr =
(struct gpt_regs *) GPTIMER1_BASE_ADDR;
/* Timer control1 register */
#define GPT_CR1_CEN 0x0001
#define GPT_MODE_AUTO_RELOAD (1 << 7)
/* Timer prescalar reg */
#define GPT_PRESCALER_128 0x128
/* Auto reload register for free running config */
#define GPT_FREE_RUNNING 0xFFFF
/* Timer, HZ specific defines */
#define CFG_SYS_HZ_CLOCK ((27 * 1000 * 1000) / GPT_PRESCALER_128)
#endif

45
arch/arm/include/asm/arch-stv0991/stv0991_periph.h
View File

@ -1,45 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2014, STMicroelectronics - All Rights Reserved
* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*/
#ifndef __ASM_ARM_ARCH_PERIPH_H
#define __ASM_ARM_ARCH_PERIPH_H
/*
* Peripherals required for pinmux configuration. List will
* grow with support for more devices getting added.
* Numbering based on interrupt table.
*
*/
enum periph_id {
UART_GPIOC_30_31 = 0,
UART_GPIOB_16_17,
ETH_GPIOB_10_31_C_0_4,
QSPI_CS_CLK_PAD,
PERIPH_ID_I2C0,
PERIPH_ID_I2C1,
PERIPH_ID_I2C2,
PERIPH_ID_I2C3,
PERIPH_ID_I2C4,
PERIPH_ID_I2C5,
PERIPH_ID_I2C6,
PERIPH_ID_I2C7,
PERIPH_ID_SPI0,
PERIPH_ID_SPI1,
PERIPH_ID_SPI2,
PERIPH_ID_SDMMC0,
PERIPH_ID_SDMMC1,
PERIPH_ID_SDMMC2,
PERIPH_ID_SDMMC3,
PERIPH_ID_I2S1,
};
enum periph_clock {
UART_CLOCK_CFG = 0,
ETH_CLOCK_CFG,
QSPI_CLOCK_CFG,
};
#endif /* __ASM_ARM_ARCH_PERIPH_H */

27
arch/arm/include/asm/arch-stv0991/stv0991_wdru.h
View File

@ -1,27 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2014, STMicroelectronics - All Rights Reserved
* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*/
#ifndef _STV0991_WD_RST_H
#define _STV0991_WD_RST_H
#include <asm/arch-stv0991/hardware.h>
struct stv0991_wd_ru {
u32 wdru_config;
u32 wdru_ctrl1;
u32 wdru_ctrl2;
u32 wdru_tim;
u32 wdru_count;
u32 wdru_stat;
u32 wdru_wrlock;
};
struct stv0991_wd_ru *const stv0991_wd_ru_ptr = \
(struct stv0991_wd_ru *)WDRU_BASE_ADDR;
/* Watchdog control register */
#define WDRU_RST_SYS 0x1
#endif

6
arch/mips/Kconfig
View File

@ -473,12 +473,6 @@ config MIPS_TUNE_74KC
config MIPS_TUNE_OCTEON3
bool
config 32BIT
bool
config 64BIT
bool
config SWAP_IO_SPACE
bool

6
arch/riscv/Kconfig
View File

@ -288,12 +288,6 @@ endmenu
config RISCV_ISA_A
def_bool y
config 32BIT
bool
config 64BIT
bool
config DMA_ADDR_T_64BIT
bool
default y if 64BIT

3
board/anbernic/rgxx3_rk3566/Kconfig
View File

@ -9,7 +9,4 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "anbernic-rgxx3-rk3566"
config BOARD_SPECIFIC_OPTIONS
def_bool y
endif

3
board/chipspark/popmetal_rk3288/Kconfig
View File

@ -9,7 +9,4 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "popmetal_rk3288"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif

3
board/edgeble/neural-compute-module-6/Kconfig
View File

@ -9,7 +9,4 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "neural-compute-module-6"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif

3
board/elgin/elgin_rv1108/Kconfig
View File

@ -9,7 +9,4 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "elgin_rv1108"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif

3
board/firefly/firefly-rk3288/Kconfig
View File

@ -9,7 +9,4 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "firefly-rk3288"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif

3
board/firefly/firefly-rk3308/Kconfig
View File

@ -9,7 +9,4 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "firefly_rk3308"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif

3
board/firefly/roc-pc-rk3399/Kconfig
View File

@ -9,8 +9,5 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "roc-pc-rk3399"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif

3
board/friendlyelec/nanopc-t6-rk3588/Kconfig
View File

@ -9,7 +9,4 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "nanopc-t6-rk3588"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif

3
board/geekbuying/geekbox/Kconfig
View File

@ -9,7 +9,4 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "geekbox"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif

6
board/google/gru/Kconfig
View File

@ -9,9 +9,6 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "gru"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif
if TARGET_CHROMEBOOK_KEVIN
@ -25,7 +22,4 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "gru"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif

12
board/google/veyron/Kconfig
View File

@ -9,9 +9,6 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "veyron"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif
if TARGET_CHROMEBIT_MICKEY
@ -25,9 +22,6 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "veyron"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif
if TARGET_CHROMEBOOK_MINNIE
@ -41,9 +35,6 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "veyron"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif
if TARGET_CHROMEBOOK_SPEEDY
@ -57,7 +48,4 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "veyron"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif

3
board/hardkernel/odroid_go2/Kconfig
View File

@ -9,7 +9,4 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "odroid_go2"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif

3
board/hardkernel/odroid_m1/Kconfig
View File

@ -9,7 +9,4 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "odroid_m1"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif

3
board/mqmaker/miqi_rk3288/Kconfig
View File

@ -9,7 +9,4 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "miqi_rk3288"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif

3
board/phytec/phycore_rk3288/Kconfig
View File

@ -9,7 +9,4 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "phycore_rk3288"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif

3
board/pine64/pinebook-pro-rk3399/Kconfig
View File

@ -9,7 +9,4 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "pinebook-pro-rk3399"
config BOARD_SPECIFIC_OPTIONS
def_bool y
endif

3
board/pine64/pinephone-pro-rk3399/Kconfig
View File

@ -9,7 +9,4 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "pinephone-pro-rk3399"
config BOARD_SPECIFIC_OPTIONS
def_bool y
endif

3
board/pine64/quartz64_rk3566/Kconfig
View File

@ -9,7 +9,4 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "quartz64_rk3566"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif

3
board/pine64/quartzpro64-rk3588/Kconfig
View File

@ -9,7 +9,4 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "quartzpro64-rk3588"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif

3
board/pine64/rockpro64_rk3399/Kconfig
View File

@ -9,7 +9,4 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "rockpro64_rk3399"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif

3
board/radxa/rock/Kconfig
View File

@ -9,7 +9,4 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "rock"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif

3
board/radxa/rock2/Kconfig
View File

@ -9,7 +9,4 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "rock2"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif

3
board/radxa/rock5a-rk3588s/Kconfig
View File

@ -9,7 +9,4 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "rock5a-rk3588s"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif

3
board/radxa/rock5b-rk3588/Kconfig
View File

@ -9,7 +9,4 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "rock5b-rk3588"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif

3
board/rikomagic/mk808/Kconfig
View File

@ -9,7 +9,4 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "mk808"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif

3
board/rockchip/evb_px30/Kconfig
View File

@ -9,7 +9,4 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "evb_px30"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif

3
board/rockchip/evb_px5/Kconfig
View File

@ -9,7 +9,4 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "evb_px5"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif

3
board/rockchip/evb_rk3036/Kconfig
View File

@ -9,7 +9,4 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "evb_rk3036"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif

3
board/rockchip/evb_rk3128/Kconfig
View File

@ -9,7 +9,4 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "evb_rk3128"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif

3
board/rockchip/evb_rk3229/Kconfig
View File

@ -9,7 +9,4 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "evb_rk3229"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif

3
board/rockchip/evb_rk3288/Kconfig
View File

@ -9,7 +9,4 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "evb_rk3288"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif

3
board/rockchip/evb_rk3308/Kconfig
View File

@ -9,7 +9,4 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "evb_rk3308"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif

3
board/rockchip/evb_rk3328/Kconfig
View File

@ -9,7 +9,4 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "evb_rk3328"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif

3
board/rockchip/evb_rk3399/Kconfig
View File

@ -9,7 +9,4 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "evb_rk3399"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif

3
board/rockchip/evb_rk3568/Kconfig
View File

@ -9,7 +9,4 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "evb_rk3568"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif

3
board/rockchip/evb_rk3588/Kconfig
View File

@ -9,7 +9,4 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "evb_rk3588"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif

3
board/rockchip/evb_rv1108/Kconfig
View File

@ -9,7 +9,4 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "evb_rv1108"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif

3
board/rockchip/kylin_rk3036/Kconfig
View File

@ -9,7 +9,4 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "kylin_rk3036"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif

3
board/rockchip/sheep_rk3368/Kconfig
View File

@ -9,7 +9,4 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "sheep_rk3368"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif

3
board/rockchip/tinker_rk3288/Kconfig
View File

@ -9,7 +9,4 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "tinker_rk3288"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif

60
board/socionext/developerbox/developerbox.c
View File

@ -125,10 +125,29 @@ int dram_init(void)
struct draminfo *synquacer_draminfo = (void *)SQ_DRAMINFO_BASE;
struct draminfo_entry *ent = synquacer_draminfo->entry;
unsigned long size = 0;
int i;
struct mm_region *mr;
int i, ri;
for (i = 0; i < synquacer_draminfo->nr_regions; i++)
if (synquacer_draminfo->nr_regions < 1) {
log_err("Failed to get correct DRAM information\n");
return -EINVAL;
}
for (i = 0; i < synquacer_draminfo->nr_regions; i++) {
if (i >= MAX_DDR_REGIONS)
break;
ri = DDR_REGION_INDEX(i);
mem_map[ri].phys = ent[i].base;
mem_map[ri].size = ent[i].size;
mem_map[ri].virt = mem_map[ri].phys;
size += ent[i].size;
if (i == 0)
continue;
mr = &mem_map[DDR_REGION_INDEX(0)];
mem_map[ri].attrs = mr->attrs;
}
gd->ram_size = size;
gd->ram_base = ent[0].base;
@ -162,43 +181,6 @@ int dram_init_banksize(void)
return 0;
}
void build_mem_map(void)
{
struct draminfo *synquacer_draminfo = (void *)SQ_DRAMINFO_BASE;
struct draminfo_entry *ent = synquacer_draminfo->entry;
struct mm_region *mr;
int i, ri;
if (synquacer_draminfo->nr_regions < 1) {
log_err("Failed to get correct DRAM information\n");
return;
}
/* Update memory region maps */
for (i = 0; i < synquacer_draminfo->nr_regions; i++) {
if (i >= MAX_DDR_REGIONS)
break;
ri = DDR_REGION_INDEX(i);
mem_map[ri].phys = ent[i].base;
mem_map[ri].size = ent[i].size;
mem_map[ri].virt = mem_map[ri].phys;
if (i == 0)
continue;
mr = &mem_map[DDR_REGION_INDEX(0)];
mem_map[ri].attrs = mr->attrs;
}
}
void enable_caches(void)
{
build_mem_map();
icache_enable();
dcache_enable();
}
int print_cpuinfo(void)
{
printf("CPU: SC2A11:Cortex-A53 MPCore 24cores\n");

15
board/st/stv0991/Kconfig
View File

@ -1,15 +0,0 @@
if TARGET_STV0991
config SYS_BOARD
default "stv0991"
config SYS_VENDOR
default "st"
config SYS_SOC
default "stv0991"
config SYS_CONFIG_NAME
default "stv0991"
endif

6
board/st/stv0991/MAINTAINERS
View File

@ -1,6 +0,0 @@
STV0991 APPLICATION BOARD
M: Vikas Manocha <vikas.manocha@st.com>
S: Maintained
F: board/st/stv0991/
F: include/configs/stv0991.h
F: configs/stv0991_defconfig

6
board/st/stv0991/Makefile
View File

@ -1,6 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2014, STMicroelectronics - All Rights Reserved
# Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
obj-y := stv0991.o

119
board/st/stv0991/stv0991.c
View File

@ -1,119 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2014, STMicroelectronics - All Rights Reserved
* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*/
#include <common.h>
#include <bootstage.h>
#include <dm.h>
#include <init.h>
#include <miiphy.h>
#include <net.h>
#include <asm/arch/stv0991_periph.h>
#include <asm/arch/stv0991_defs.h>
#include <asm/arch/hardware.h>
#include <asm/arch/gpio.h>
#include <netdev.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <dm/platform_data/serial_pl01x.h>
DECLARE_GLOBAL_DATA_PTR;
struct gpio_regs *const gpioa_regs =
(struct gpio_regs *) GPIOA_BASE_ADDR;
#ifndef CONFIG_OF_CONTROL
static const struct pl01x_serial_plat serial_plat = {
.base = 0x80406000,
.type = TYPE_PL011,
.clock = 2700 * 1000,
};
U_BOOT_DRVINFO(stv09911_serials) = {
.name = "serial_pl01x",
.plat = &serial_plat,
};
#endif
#if CONFIG_IS_ENABLED(BOOTSTAGE)
void show_boot_progress(int progress)
{
printf("%i\n", progress);
}
#endif
void enable_eth_phy(void)
{
/* Set GPIOA_06 pad HIGH (Appli board)*/
writel(readl(&gpioa_regs->dir) | 0x40, &gpioa_regs->dir);
writel(readl(&gpioa_regs->data) | 0x40, &gpioa_regs->data);
}
int board_eth_enable(void)
{
stv0991_pinmux_config(ETH_GPIOB_10_31_C_0_4);
clock_setup(ETH_CLOCK_CFG);
enable_eth_phy();
return 0;
}
int board_qspi_enable(void)
{
stv0991_pinmux_config(QSPI_CS_CLK_PAD);
clock_setup(QSPI_CLOCK_CFG);
return 0;
}
/*
* Miscellaneous platform dependent initialisations
*/
int board_init(void)
{
board_eth_enable();
board_qspi_enable();
return 0;
}
int board_uart_init(void)
{
stv0991_pinmux_config(UART_GPIOC_30_31);
clock_setup(UART_CLOCK_CFG);
return 0;
}
#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_early_init_f(void)
{
board_uart_init();
return 0;
}
#endif
int dram_init(void)
{
gd->ram_size = PHYS_SDRAM_1_SIZE;
return 0;
}
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
return 0;
}
#ifdef CONFIG_CMD_NET
int board_eth_init(struct bd_info *bis)
{
int ret = 0;
#if defined(CONFIG_ETH_DESIGNWARE)
u32 interface = PHY_INTERFACE_MODE_MII;
if (designware_initialize(GMAC_BASE_ADDR, interface) >= 0)
ret++;
#endif
return ret;
}
#endif

3
board/theobroma-systems/lion_rk3368/Kconfig
View File

@ -9,9 +9,6 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "lion_rk3368"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
config ENV_SIZE
default 0x2000

3
board/turing/turing-rk1-rk3588/Kconfig
View File

@ -9,7 +9,4 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "turing-rk1-rk3588"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif

3
board/vamrs/rock960_rk3399/Kconfig
View File

@ -9,7 +9,4 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "rock960_rk3399"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif

4
boot/image-fdt.c
View File

@ -217,14 +217,14 @@ int boot_relocate_fdt(struct lmb *lmb, char **of_flat_tree, ulong *of_size)
if (start + size < low)
continue;
usable = min(size, (u64)mapsize);
usable = min(start + size, (u64)(low + mapsize));
/*
* At least part of this DRAM bank is usable, try
* using it for LMB allocation.
*/
of_start = map_sysmem((ulong)lmb_alloc_base(lmb,
of_len, 0x1000, start + usable), of_len);
of_len, 0x1000, usable), of_len);
/* Allocation succeeded, use this block. */
if (of_start != NULL)
break;

22
cmd/Kconfig
View File

@ -189,6 +189,17 @@ config CMD_HISTORY
Show the command-line history, i.e. a list of commands that are in
the history buffer.
config CMD_HISTORY_USE_CALLOC
bool "dynamically allocate memory"
default y
depends on CMD_HISTORY
help
Saying Y to this will use calloc to get the space for history
storing. Otherwise the history buffer will be an uninitialized
static array directly, without the memory allocation, and it is
writable after relocation to RAM. If u-boot is running from ROM
all the time or unsure, say Y to this.
config CMD_LICENSE
bool "license"
select BUILD_BIN2C
@ -479,6 +490,17 @@ config CMD_ELF
help
Boot an ELF/vxWorks image from the memory.
config CMD_ELF_FDT_SETUP
bool "Flattened Device Tree setup in bootelf cmd"
default n
depends on CMD_ELF
select LIB_LIBFDT
select LMB
help
Do FDT setup in bootelf command optionally by param -d, which
allows to bring additional system info (e.g. /memory node) to
the Operating System or application.
config CMD_FDT
bool "Flattened Device Tree utility commands"
default y

39
cmd/elf.c
View File

@ -38,6 +38,10 @@ static unsigned long do_bootelf_exec(ulong (*entry)(int, char * const[]),
/* Interpreter command to boot an arbitrary ELF image from memory */
int do_bootelf(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
#if CONFIG_IS_ENABLED(CMD_ELF_FDT_SETUP)
struct bootm_headers img = {0};
unsigned long fdt_addr = 0; /* Address of the FDT */
#endif
unsigned long addr; /* Address of the ELF image */
unsigned long rc; /* Return value from user code */
char *sload = NULL;
@ -46,13 +50,25 @@ int do_bootelf(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
/* Consume 'bootelf' */
argc--; argv++;
/* Check for flag. */
/* Check for [-p|-s] flag. */
if (argc >= 1 && (argv[0][0] == '-' && \
(argv[0][1] == 'p' || argv[0][1] == 's'))) {
sload = argv[0];
/* Consume flag. */
argc--; argv++;
}
#if CONFIG_IS_ENABLED(CMD_ELF_FDT_SETUP)
/* Check for [-d fdt_addr_r] option. */
if ((argc >= 2) && (argv[0][0] == '-') && (argv[0][1] == 'd')) {
if (strict_strtoul(argv[1], 16, &fdt_addr) != 0)
return CMD_RET_USAGE;
/* Consume option. */
argc -= 2;
argv += 2;
}
#endif
/* Check for address. */
if (argc >= 1 && strict_strtoul(argv[0], 16, &addr) != -EINVAL) {
/* Consume address */
@ -68,6 +84,16 @@ int do_bootelf(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
else
addr = load_elf_image_shdr(addr);
#if CONFIG_IS_ENABLED(CMD_ELF_FDT_SETUP)
if (fdt_addr) {
printf("## Setting up FDT at 0x%08lx ...\n", fdt_addr);
flush();
if (image_setup_libfdt(&img, (void *)fdt_addr, NULL))
return 1;
}
#endif
if (!env_get_autostart())
return rcode;
@ -298,9 +324,16 @@ int do_bootvx(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
U_BOOT_CMD(
bootelf, CONFIG_SYS_MAXARGS, 0, do_bootelf,
"Boot from an ELF image in memory",
"[-p|-s] [address]\n"
"[-p|-s] "
#if CONFIG_IS_ENABLED(CMD_ELF_FDT_SETUP)
"[-d fdt_addr_r] "
#endif
"[address]\n"
"\t- load ELF image at [address] via program headers (-p)\n"
"\t or via section headers (-s)"
"\t or via section headers (-s)\n"
#if CONFIG_IS_ENABLED(CMD_ELF_FDT_SETUP)
"\t- setup FDT image at [fdt_addr_r] (-d)"
#endif
);
U_BOOT_CMD(

23
cmd/rng.c
View File

@ -19,6 +19,22 @@ static int do_rng(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
struct udevice *dev;
int ret = CMD_RET_SUCCESS;
if (argc == 2 && !strcmp(argv[1], "list")) {
int idx = 0;
uclass_foreach_dev_probe(UCLASS_RNG, dev) {
idx++;
printf("RNG #%d - %s\n", dev->seq_, dev->name);
}
if (!idx) {
log_err("No RNG device\n");
return CMD_RET_FAILURE;
}
return CMD_RET_SUCCESS;
}
switch (argc) {
case 1:
devnum = 0;
@ -56,12 +72,9 @@ static int do_rng(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
return ret;
}
U_BOOT_LONGHELP(rng,
"[dev [n]]\n"
" - print n random bytes(max 64) read from dev\n");
U_BOOT_CMD(
rng, 3, 0, do_rng,
"print bytes from the hardware random number generator",
rng_help_text
"list - list all the probed rng devices\n"
"rng [dev] [n] - print n random bytes(max 64) read from dev\n"
);

38
common/cli_readline.c
View File

@ -86,6 +86,9 @@ static int hist_add_idx;
static int hist_cur = -1;
static unsigned hist_num;
#ifndef CONFIG_CMD_HISTORY_USE_CALLOC
static char hist_data[HIST_MAX][HIST_SIZE + 1];
#endif
static char *hist_list[HIST_MAX];
#define add_idx_minus_one() ((hist_add_idx == 0) ? hist_max : hist_add_idx-1)
@ -100,21 +103,27 @@ static void getcmd_putchars(int count, int ch)
static int hist_init(void)
{
unsigned char *hist;
int i;
#ifndef CONFIG_CMD_HISTORY_USE_CALLOC
for (i = 0; i < HIST_MAX; i++) {
hist_list[i] = hist_data[i];
hist_list[i][0] = '\0';
}
#else
unsigned char *hist = calloc(HIST_MAX, HIST_SIZE + 1);
if (!hist)
panic("%s: calloc: out of memory!\n", __func__);
for (i = 0; i < HIST_MAX; i++)
hist_list[i] = hist + (i * (HIST_SIZE + 1));
#endif
hist_max = 0;
hist_add_idx = 0;
hist_cur = -1;
hist_num = 0;
hist = calloc(HIST_MAX, HIST_SIZE + 1);
if (!hist)
return -ENOMEM;
for (i = 0; i < HIST_MAX; i++)
hist_list[i] = hist + (i * (HIST_SIZE + 1));
return 0;
}
@ -643,10 +652,15 @@ int cli_readline_into_buffer(const char *const prompt, char *buffer,
static int initted;
/*
* History uses a global array which is not
* writable until after relocation to RAM.
* Revert to non-history version if still
* running from flash.
* Say N to CMD_HISTORY_USE_CALLOC will skip runtime
* allocation for the history buffer and directly
* use an uninitialized static array as the buffer.
* Doing this might have better performance and not
* increase the binary file's size, as it only marks
* the size. However, the array is only writable after
* relocation to RAM. If u-boot is running from ROM
* all the time, consider say Y to CMD_HISTORY_USE_CALLOC
* or disable CMD_HISTORY.
*/
if (IS_ENABLED(CONFIG_CMDLINE_EDITING) && (gd->flags & GD_FLG_RELOC)) {
if (!initted) {

5
configs/am64x_evm_a53_defconfig
View File

@ -16,7 +16,7 @@ CONFIG_SF_DEFAULT_SPEED=25000000
CONFIG_ENV_SIZE=0x20000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="k3-am642-evm"
CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am642-evm"
CONFIG_SPL_TEXT_BASE=0x80080000
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
@ -74,7 +74,7 @@ CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIST="k3-am642-evm k3-am642-sk"
CONFIG_OF_LIST="ti/k3-am642-evm ti/k3-am642-sk"
CONFIG_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
@ -170,3 +170,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_FUNCTION_MASS_STORAGE=y
CONFIG_SPL_DFU=y
CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
CONFIG_OF_UPSTREAM=y

44
configs/stv0991_defconfig
View File

@ -1,44 +0,0 @@
CONFIG_ARM=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_TARGET_STV0991=y
CONFIG_TEXT_BASE=0x00010000
CONFIG_SYS_MALLOC_LEN=0x14000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x30000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DEFAULT_DEVICE_TREE="stv0991"
CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_ENV_ADDR=0x188000
CONFIG_SYS_MEMTEST_START=0x00000000
CONFIG_SYS_MEMTEST_END=0x00100000
CONFIG_BOOTDELAY=3
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="go 0x40040000"
CONFIG_SYS_PBSIZE=1050
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PROMPT="STV0991> "
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_SPI=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_PING=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_PHY_RESET_DELAY=10000
CONFIG_ETH_DESIGNWARE=y
CONFIG_DW_ALTDESCRIPTOR=y
CONFIG_MII=y
CONFIG_CADENCE_QSPI=y
CONFIG_HAS_CQSPI_REF_CLK=y
CONFIG_CQSPI_REF_CLK=3000000

14
doc/usage/cmd/rng.rst
View File

@ -11,16 +11,22 @@ Synopsis
::
rng [devnum [n]]
rng list
rng [dev] [n]
Description
-----------
rng list
--------
List all the probed rng devices.
rng [dev] [n]
-------------
The *rng* command reads the random number generator(RNG) device and
prints the random bytes read on the console. A maximum of 64 bytes can
be read in one invocation of the command.
devnum
dev
The RNG device from which the random bytes are to be
read. Defaults to 0.

5
drivers/firmware/psci.c
View File

@ -135,10 +135,13 @@ static int bind_smccc_features(struct udevice *dev, int psci_method)
PSCI_VERSION_MAJOR(psci_0_2_get_version()) == 0)
return 0;
if (request_psci_features(ARM_SMCCC_ARCH_FEATURES) ==
if (request_psci_features(ARM_SMCCC_VERSION) ==
PSCI_RET_NOT_SUPPORTED)
return 0;
if (invoke_psci_fn(ARM_SMCCC_VERSION, 0, 0, 0) < ARM_SMCCC_VERSION_1_1)
return 0;
if (psci_method == PSCI_METHOD_HVC)
pdata->invoke_fn = smccc_invoke_hvc;
else

2
drivers/rng/smccc_trng.c
View File

@ -165,7 +165,7 @@ static int smccc_trng_probe(struct udevice *dev)
struct smccc_trng_priv *priv = dev_get_priv(dev);
struct arm_smccc_res res;
if (!(smccc_trng_is_supported(smccc->invoke_fn)))
if (!smccc || !(smccc_trng_is_supported(smccc->invoke_fn)))
return -ENODEV;
/* At least one of 64bit and 32bit interfaces is available */

25
include/configs/stv0991.h
View File

@ -1,25 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2014, STMicroelectronics - All Rights Reserved
* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*/
#ifndef __CONFIG_STV0991_H
#define __CONFIG_STV0991_H
#define CFG_SYS_EXCEPTION_VECTORS_HIGH
/* ram memory-related information */
#define PHYS_SDRAM_1 0x00000000
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define PHYS_SDRAM_1_SIZE 0x00198000
/* user interface */
/* MISC */
#define CFG_SYS_INIT_RAM_SIZE 0x8000
#define CFG_SYS_INIT_RAM_ADDR 0x00190000
/* U-Boot Load Address */
/* Misc configuration */
#endif /* __CONFIG_H */

6
include/linux/arm-smccc.h
View File

@ -55,8 +55,14 @@
#define ARM_SMCCC_QUIRK_NONE 0
#define ARM_SMCCC_QUIRK_QCOM_A6 1 /* Save/restore register a6 */
#define ARM_SMCCC_VERSION 0x80000000
#define ARM_SMCCC_ARCH_FEATURES 0x80000001
#define ARM_SMCCC_VERSION_1_0 0x10000
#define ARM_SMCCC_VERSION_1_1 0x10001
#define ARM_SMCCC_VERSION_1_2 0x10002
#define ARM_SMCCC_VERSION_1_3 0x10003
#define ARM_SMCCC_RET_NOT_SUPPORTED ((unsigned long)-1)
#ifndef __ASSEMBLY__

4
lib/initcall.c
View File

@ -55,7 +55,7 @@ int initcall_run_list(const init_fnc_t init_sequence[])
init_fnc_t func;
int ret = 0;
for (ptr = init_sequence; func = *ptr, !ret && func; ptr++) {
for (ptr = init_sequence; func = *ptr, func; ptr++) {
type = initcall_is_event(func);
if (type) {
@ -71,6 +71,8 @@ int initcall_run_list(const init_fnc_t init_sequence[])
}
ret = type ? event_notify_null(type) : func();
if (ret)
break;
}
if (ret) {

2
scripts/kconfig/Makefile
View File

@ -93,7 +93,7 @@ endif
endif
%_defconfig: $(obj)/conf
$(Q)$(CPP) -nostdinc -I $(srctree) -undef -x assembler-with-cpp $(srctree)/arch/$(SRCARCH)/configs/$@ -o generated_defconfig
$(Q)$(CPP) -nostdinc -P -I $(srctree) -undef -x assembler-with-cpp $(srctree)/arch/$(SRCARCH)/configs/$@ -o generated_defconfig
$(Q)$< $(silent) --defconfig=generated_defconfig $(Kconfig)
# Added for U-Boot (backward compatibility)