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For 2023.04

Browse Source 
-----------
 
 - several conversion to DM_SERIAL and DM_I2C
 - fixes for Toradex boards
 - PSCI
 
 CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/14965
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Merge tag 'u-boot-imx-20230201' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

For 2023.04
-----------

- several conversion to DM_SERIAL and DM_I2C
- fixes for Toradex boards
- PSCI

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/14965
This commit is contained in:
Tom Rini 2023-02-01 09:30:52 -05:00
commit 3592a61fa8
155 changed files with 4678 additions and 598 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/cpu/armv8/fwcall.c
View File

@ -103,7 +103,7 @@ void __noreturn psci_system_reset2(u32 reset_level, u32 cookie)
{
struct pt_regs regs;
regs.regs[0] = ARM_PSCI_0_2_FN64_SYSTEM_RESET2;
regs.regs[0] = ARM_PSCI_1_1_FN64_SYSTEM_RESET2;
regs.regs[1] = PSCI_RESET2_TYPE_VENDOR | reset_level;
regs.regs[2] = cookie;
if (use_smc_for_psci)

2
arch/arm/cpu/armv8/psci.S
View File

@ -81,6 +81,7 @@ PSCI_DEFAULT(psci_node_hw_state_64)
PSCI_DEFAULT(psci_system_suspend_64)
PSCI_DEFAULT(psci_stat_residency_64)
PSCI_DEFAULT(psci_stat_count_64)
PSCI_DEFAULT(psci_system_reset2_64)
.align 3
_psci_64_table:
@ -94,6 +95,7 @@ PSCI_TABLE(ARM_PSCI_1_0_FN64_NODE_HW_STATE, psci_node_hw_state_64)
PSCI_TABLE(ARM_PSCI_1_0_FN64_SYSTEM_SUSPEND, psci_system_suspend_64)
PSCI_TABLE(ARM_PSCI_1_0_FN64_STAT_RESIDENCY, psci_stat_residency_64)
PSCI_TABLE(ARM_PSCI_1_0_FN64_STAT_COUNT, psci_stat_count_64)
PSCI_TABLE(ARM_PSCI_1_1_FN64_SYSTEM_RESET2, psci_system_reset2_64)
PSCI_TABLE(0, 0)
.macro psci_enter

1
arch/arm/dts/Makefile
View File

@ -962,6 +962,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mm-kontron-bl.dtb \
imx8mm-kontron-bl-osm-s.dtb \
imx8mm-mx8menlo.dtb \
imx8mm-phg.dtb \
imx8mm-venice.dtb \
imx8mm-venice-gw71xx-0x.dtb \
imx8mm-venice-gw72xx-0x.dtb \

8
arch/arm/dts/fsl-imx8qm-apalis.dts
View File

@ -589,8 +589,10 @@
/* eMMC */
&usdhc1 {
pinctrl-names = "default";
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1>;
pinctrl-2 = <&pinctrl_usdhc1>;
bus-width = <8>;
non-removable;
status = "okay";
@ -598,8 +600,10 @@
/* Apalis MMC1 */
&usdhc2 {
pinctrl-names = "default";
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_mmc1_cd>;
pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_mmc1_cd>;
pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_mmc1_cd>;
bus-width = <8>;
cd-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; /* Apalis MMC1_CD# */
status = "okay";

13
arch/arm/dts/imx6q-sabrelite-u-boot.dtsi Normal file
View File

@ -0,0 +1,13 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2022 Collabora
*/
#include "imx6qdl-u-boot.dtsi"
/ {
aliases {
mmc0 = &usdhc3;
mmc1 = &usdhc4;
};
};

16
arch/arm/dts/imx6qdl-icore-u-boot.dtsi
View File

@ -5,6 +5,22 @@
#include "imx6qdl-u-boot.dtsi"
&soc {
u-boot,dm-pre-reloc;
};
&aips1 {
u-boot,dm-pre-reloc;
};
&pinctrl_uart4 {
u-boot,dm-pre-reloc;
};
&uart4 {
u-boot,dm-pre-reloc;
};
&usdhc1 {
u-boot,dm-spl;
};

6
arch/arm/dts/imx6qdl-sabresd-u-boot.dtsi
View File

@ -5,6 +5,12 @@
#include "imx6qdl-u-boot.dtsi"
/ {
aliases {
mmc1 = &usdhc3;
};
};
&usdhc3 {
u-boot,dm-spl;
};

8
arch/arm/dts/imx6sll-evk-u-boot.dtsi Normal file
View File

@ -0,0 +1,8 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019, 2021 NXP
*/
&pinctrl_uart1 {
u-boot,dm-pre-reloc;
};

4
arch/arm/dts/imx6sx-sabreauto-u-boot.dtsi
View File

@ -14,3 +14,7 @@
compatible = "jedec,spi-nor";
};
};
&pinctrl_uart1 {
u-boot,dm-pre-reloc;
};

16
arch/arm/dts/imx6ul-isiot-u-boot.dtsi
View File

@ -5,6 +5,22 @@
#include "imx6ul-u-boot.dtsi"
&soc {
u-boot,dm-pre-reloc;
};
&aips1 {
u-boot,dm-pre-reloc;
};
&pinctrl_uart1 {
u-boot,dm-pre-reloc;
};
&uart1 {
u-boot,dm-pre-reloc;
};
&usdhc1 {
u-boot,dm-spl;
};

8
arch/arm/dts/imx6ull-14x14-evk-u-boot.dtsi Normal file
View File

@ -0,0 +1,8 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2022 NXP
*/
&pinctrl_uart1 {
u-boot,dm-pre-reloc;
};

1
arch/arm/dts/imx6ull-colibri-eval-v3-u-boot.dtsi
View File

@ -6,7 +6,6 @@
/ {
aliases {
u-boot,dm-pre-reloc;
mmc0 = &usdhc1;
usb0 = &usbotg1; /* required for ums */
display0 = &lcdif;
};

8
arch/arm/dts/imx6ulz-14x14-evk-u-boot.dtsi Normal file
View File

@ -0,0 +1,8 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2022 NXP
*/
&pinctrl_uart1 {
u-boot,dm-pre-reloc;
};

4
arch/arm/dts/imx8mm-kontron-bl.dts
View File

@ -13,6 +13,8 @@
aliases {
ethernet1 = &usbnet;
rtc0 = &rx8900;
rtc1 = &snvs_rtc;
};
/* fixed crystal dedicated to mcp2515 */
@ -136,7 +138,7 @@
pinctrl-0 = <&pinctrl_i2c4>;
status = "okay";
rtc@32 {
rx8900: rtc@32 {
compatible = "epson,rx8900";
reg = <0x32>;
};

7
arch/arm/dts/imx8mm-kontron-osm-s.dtsi
View File

@ -10,6 +10,11 @@
model = "Kontron OSM-S i.MX8MM (N802X SOM)";
compatible = "kontron,imx8mm-osm-s", "fsl,imx8mm";
aliases {
rtc0 = &rv3028;
rtc1 = &snvs_rtc;
};
memory@40000000 {
device_type = "memory";
/*
@ -200,7 +205,7 @@
};
};
rtc@52 {
rv3028: rtc@52 {
compatible = "microcrystal,rv3028";
reg = <0x52>;
pinctrl-names = "default";

137
arch/arm/dts/imx8mm-phg-u-boot.dtsi Normal file
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@ -0,0 +1,137 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019 NXP
*/
#include "imx8mm-u-boot.dtsi"
/ {
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
u-boot,dm-spl;
};
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
};
};
&aips4 {
u-boot,dm-spl;
};
&reg_usdhc2_vmmc {
u-boot,off-on-delay-us = <20000>;
};
&pinctrl_reg_usdhc2_vmmc {
u-boot,dm-spl;
};
&pinctrl_uart2 {
u-boot,dm-spl;
};
&pinctrl_usdhc2_gpio {
u-boot,dm-spl;
};
&pinctrl_usdhc2 {
u-boot,dm-spl;
};
&pinctrl_usdhc3 {
u-boot,dm-spl;
};
&gpio1 {
u-boot,dm-spl;
};
&gpio2 {
u-boot,dm-spl;
};
&gpio3 {
u-boot,dm-spl;
};
&gpio4 {
u-boot,dm-spl;
};
&gpio5 {
u-boot,dm-spl;
};
&uart2 {
u-boot,dm-spl;
};
&usbmisc1 {
u-boot,dm-spl;
};
&usbphynop1 {
u-boot,dm-spl;
};
&usbotg1 {
u-boot,dm-spl;
};
&usdhc1 {
u-boot,dm-spl;
};
&usdhc2 {
u-boot,dm-spl;
sd-uhs-sdr104;
sd-uhs-ddr50;
assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
assigned-clock-rates = <400000000>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_400M>;
};
&usdhc3 {
u-boot,dm-spl;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
/*
* prevents voltage switch warn: driver will switch even at
* fixed voltage
*/
/delete-property/ vmmc-supply;
/delete-property/ vqmmc-supply;
assigned-clocks = <&clk IMX8MM_CLK_USDHC3>;
assigned-clock-rates = <400000000>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_400M>;
};
&i2c1 {
u-boot,dm-spl;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@25} {
u-boot,dm-spl;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} {
u-boot,dm-spl;
};
&pinctrl_i2c1 {
u-boot,dm-spl;
};
&pinctrl_pmic {
u-boot,dm-spl;
};
&wdog1 {
u-boot,dm-spl;
};

266
arch/arm/dts/imx8mm-phg.dts Normal file
View File

@ -0,0 +1,266 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 Fabio Estevam <festevam@denx.de>
*/
/dts-v1/;
#include "imx8mm-tqma8mqml.dtsi"
/ {
model = "Cloos i.MX8MM PHG board";
compatible = "cloos,imx8mm-phg", "tq,imx8mm-tqma8mqml", "fsl,imx8mm";
aliases {
mmc0 = &usdhc3;
mmc1 = &usdhc2;
};
chosen {
stdout-path = &uart2;
};
beeper {
compatible = "gpio-beeper";
pinctrl-0 = <&pinctrl_beeper>;
gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_led>;
led-0 {
label = "status1";
gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
};
led-1 {
label = "status2";
gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
};
led-2 {
label = "status3";
gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
};
led-3 {
label = "run";
gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
};
led-4 {
label = "powerled";
gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
};
};
reg_usb_otg_vbus: regulator-usb-otg-vbus {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_otg_vbus_ctrl>;
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio2 2 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usdhc2_vmmc: regulator-vmmc {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
startup-delay-us = <100>;
off-on-delay-us = <12000>;
};
};
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
status = "okay";
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
reg = <0>;
compatible = "ethernet-phy-ieee802.3-c22";
};
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&usbphynop1 {
power-domains = <&pgc_otg1>;
};
&usbphynop2 {
power-domains = <&pgc_otg2>;
};
&usbotg1 {
dr_mode = "host";
vbus-supply = <&reg_usb_otg_vbus>;
status = "okay";
};
&usbotg2 {
dr_mode = "host";
status = "okay";
};
&usdhc2 {
assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
assigned-clock-rates = <400000000>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_400M>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
bus-width = <4>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
disable-wp;
no-mmc;
no-sdio;
sd-uhs-sdr104;
sd-uhs-ddr50;
vmmc-supply = <&reg_usdhc2_vmmc>;
status = "okay";
};
&iomuxc {
pinctrl_beeper: beepergrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x19
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x40000002
MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x40000002
MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x14
MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x14
MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x14
MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x14
MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x90
MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x90
MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x90
MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x90
MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x14
MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x90
MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x90
MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x14
MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x10
>;
};
pinctrl_gpio_led: gpioledgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19
MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19
MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19
MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19
MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x19
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
>;
};
pinctrl_otg_vbus_ctrl: otgvbusctrlgrp {
fsl,pins = <
MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x119
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
>;
};
pinctrl_usdhc2_gpio: usdhc2grpgpiogrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
>;
};
};

341
arch/arm/dts/imx8mm-tqma8mqml.dtsi Normal file
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@ -0,0 +1,341 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright 2020-2021 TQ-Systems GmbH
*/
#include <dt-bindings/phy/phy-imx8-pcie.h>
#include "imx8mm.dtsi"
/ {
model = "TQ-Systems GmbH i.MX8MM TQMa8MxML";
compatible = "tq,imx8mm-tqma8mqml", "fsl,imx8mm";
memory@40000000 {
device_type = "memory";
/* our minimum RAM config will be 1024 MiB */
reg = <0x00000000 0x40000000 0 0x40000000>;
};
/* e-MMC IO, needed for HS modes */
reg_vcc1v8: regulator-vcc1v8 {
compatible = "regulator-fixed";
regulator-name = "TQMA8MXML_VCC1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
/* identical to buck4_reg, but should never change */
reg_vcc3v3: regulator-vcc3v3 {
compatible = "regulator-fixed";
regulator-name = "TQMA8MXML_VCC3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/* global autoconfigured region for contiguous allocations */
linux,cma {
compatible = "shared-dma-pool";
reusable;
/* 640 MiB */
size = <0 0x28000000>;
/* 1024 - 128 MiB, our minimum RAM config will be 1024 MiB */
alloc-ranges = <0 0x40000000 0 0x78000000>;
linux,cma-default;
};
};
};
&A53_0 {
cpu-supply = <&buck2_reg>;
};
&flexspi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexspi>;
status = "okay";
flash0: flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <84000000>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
};
};
&gpu_2d {
status = "okay";
};
&gpu_3d {
status = "okay";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
sensor0: temperature-sensor-eeprom@1b {
compatible = "nxp,se97", "jedec,jc-42.4-temp";
reg = <0x1b>;
};
pca9450: pmic@25 {
compatible = "nxp,pca9450a";
reg = <0x25>;
/* PMIC PCA9450 PMIC_nINT GPIO1_IO08 */
pinctrl-0 = <&pinctrl_pmic>;
pinctrl-names = "default";
interrupt-parent = <&gpio1>;
interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
regulators {
/* V_0V85_SOC: 0.85 */
buck1_reg: BUCK1 {
regulator-name = "BUCK1";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <850000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
};
/* VDD_ARM */
buck2_reg: BUCK2 {
regulator-name = "BUCK2";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1000000>;
regulator-boot-on;
regulator-always-on;
nxp,dvs-run-voltage = <950000>;
nxp,dvs-standby-voltage = <850000>;
regulator-ramp-delay = <3125>;
};
/* V_0V85_GPU / DRAM / VPU */
buck3_reg: BUCK3 {
regulator-name = "BUCK3";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <950000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
};
/* VCC3V3 -> VMMC, ... must not be changed */
buck4_reg: BUCK4 {
regulator-name = "BUCK4";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
/* V_1V8 -> VQMMC, SPI-NOR, ... must not be changed */
buck5_reg: BUCK5 {
regulator-name = "BUCK5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
/* V_1V1 -> RAM, ... must not be changed */
buck6_reg: BUCK6 {
regulator-name = "BUCK6";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-boot-on;
regulator-always-on;
};
/* V_1V8_SNVS */
ldo1_reg: LDO1 {
regulator-name = "LDO1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
/* V_0V8_SNVS */
ldo2_reg: LDO2 {
regulator-name = "LDO2";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <850000>;
regulator-boot-on;
regulator-always-on;
};
/* V_1V8_ANA */
ldo3_reg: LDO3 {
regulator-name = "LDO3";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
/* V_0V9_MIPI */
ldo4_reg: LDO4 {
regulator-name = "LDO4";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-boot-on;
regulator-always-on;
};
/* VCC SD IO - switched using SD2 VSELECT */
ldo5_reg: LDO5 {
regulator-name = "LDO5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
};
};
pcf85063: rtc@51 {
compatible = "nxp,pcf85063a";
reg = <0x51>;
quartz-load-femtofarads = <7000>;
};
eeprom1: eeprom@53 {
compatible = "nxp,se97b", "atmel,24c02";
read-only;
reg = <0x53>;
pagesize = <16>;
};
eeprom0: eeprom@57 {
compatible = "atmel,24c64";
reg = <0x57>;
pagesize = <32>;
};
};
&pcie_phy {
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
fsl,clkreq-unsupported;
};
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
bus-width = <8>;
non-removable;
no-sd;
no-sdio;
vmmc-supply = <&reg_vcc3v3>;
vqmmc-supply = <&reg_vcc1v8>;
status = "okay";
};
/*
* Attention:
* wdog reset is routed to PMIC, PMIC must be preconfigured to force POR
* without LDO for SNVS. GPIO1_IO02 must not be used as GPIO.
*/
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl_flexspi: flexspigrp {
fsl,pins = <MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82>,
<MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82>,
<MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82>,
<MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82>,
<MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82>,
<MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000004>,
<MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000004>;
};
pinctrl_i2c1_gpio: i2c1gpiogrp {
fsl,pins = <MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x40000004>,
<MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x40000004>;
};
pinctrl_pmic: pmicgrp {
fsl,pins = <MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x94>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x84>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d4>,
<MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>,
<MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>,
<MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>,
<MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>,
<MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>,
<MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4>,
<MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4>,
<MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4>,
<MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4>,
<MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x84>,
/* option USDHC3_RESET_B not defined, only in RM */
<MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x84>;
};
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d2>,
<MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>,
<MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>,
<MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>,
<MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>,
<MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>,
<MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4>,
<MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4>,
<MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4>,
<MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4>,
<MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x84>,
/* option USDHC3_RESET_B not defined, only in RM */
<MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x84>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d6>,
<MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>,
<MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>,
<MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>,
<MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>,
<MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>,
<MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4>,
<MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4>,
<MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4>,
<MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4>,
<MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x84>,
/* option USDHC3_RESET_B not defined, only in RM */
<MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x84>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x84>;
};
};

4
arch/arm/dts/imx8mm-u-boot.dtsi
View File

@ -99,6 +99,7 @@
};
};
#ifndef CONFIG_ARMV8_PSCI
atf {
arch = "arm64";
compression = "none";
@ -112,6 +113,7 @@
type = "atf-bl31";
};
};
#endif
binman_fip: fip {
arch = "arm64";
@ -140,7 +142,9 @@
description = "NAME";
fdt = "fdt-SEQ";
firmware = "uboot";
#ifndef CONFIG_ARMV8_PSCI
loadables = "atf";
#endif
};
};
};

24
arch/arm/dts/imx8mm-venice-gw700x.dtsi
View File

@ -119,8 +119,11 @@
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
gsc: gsc@20 {
@ -365,8 +368,11 @@
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
eeprom@52 {
@ -435,6 +441,13 @@
>;
};
pinctrl_i2c1_gpio: i2c1gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3
MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
@ -442,6 +455,13 @@
>;
};
pinctrl_i2c2_gpio: i2c2gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3
MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140

48
arch/arm/dts/imx8mm-venice-gw7901.dts
View File

@ -326,8 +326,11 @@
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
gsc: gsc@20 {
@ -477,8 +480,11 @@
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
pmic@4b {
@ -600,8 +606,11 @@
&i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
pinctrl-1 = <&pinctrl_i2c3_gpio>;
scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
leds_gpio: gpio@20 {
@ -673,8 +682,11 @@
&i2c4 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c4>;
pinctrl-1 = <&pinctrl_i2c4_gpio>;
scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
@ -852,6 +864,13 @@
>;
};
pinctrl_i2c1_gpio: i2c1gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3
MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
@ -859,6 +878,13 @@
>;
};
pinctrl_i2c2_gpio: i2c2gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3
MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
@ -866,6 +892,13 @@
>;
};
pinctrl_i2c3_gpio: i2c3gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3
MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
@ -873,6 +906,13 @@
>;
};
pinctrl_i2c4_gpio: i2c4gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c3
MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c3
>;
};
pinctrl_ksz: kszgrp {
fsl,pins = <
MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x41

14
arch/arm/dts/imx8mm-venice-gw7902-u-boot.dtsi
View File

@ -6,6 +6,13 @@
#include "imx8mm-venice-u-boot.dtsi"
&gpio1 {
m2pwren {
gpio-hog;
output-low;
gpios = <8 GPIO_ACTIVE_HIGH>;
line-name = "m2_pwren";
};
m2rst {
gpio-hog;
output-low;
@ -96,6 +103,13 @@
line-name = "app_gpio1";
};
vdd4p0en {
gpio-hog;
output-low;
gpios = <22 GPIO_ACTIVE_HIGH>;
line-name = "vdd_4p0_en";
};
uart1rs485 {
gpio-hog;
output-low;

60
arch/arm/dts/imx8mm-venice-gw7902.dts
View File

@ -261,7 +261,7 @@
&gpio1 {
gpio-line-names = "", "", "", "", "", "", "", "",
"", "", "", "", "", "m2_reset", "", "m2_wdis#",
"m2_pwr_en", "", "", "", "", "m2_reset", "", "m2_wdis#",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
@ -283,7 +283,8 @@
&gpio4 {
gpio-line-names = "", "", "", "", "", "", "", "",
"", "", "", "amp_gpio3", "amp_gpio2", "", "amp_gpio1", "",
"", "", "", "", "amp_gpio4", "app_gpio1", "", "uart1_rs485",
"lte_pwr#", "lte_rst", "lte_int", "",
"amp_gpio4", "app_gpio1", "vdd_4p0_en", "uart1_rs485",
"", "uart1_term", "uart1_half", "app_gpio2",
"mipi_gpio1", "", "", "";
};
@ -298,8 +299,11 @@
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
gsc: gsc@20 {
@ -566,8 +570,11 @@
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
accelerometer@19 {
@ -585,16 +592,22 @@
/* off-board header */
&i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
pinctrl-1 = <&pinctrl_i2c3_gpio>;
scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
/* off-board header */
&i2c4 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c4>;
pinctrl-1 = <&pinctrl_i2c4_gpio>;
scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
@ -738,14 +751,19 @@
pinctrl_hog: hoggrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */
MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x40000041 /* M2_PWR_EN */
MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RESET */
MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */
MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */
MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x40000041 /* LTE_INT */
MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x40000041 /* LTE_RST# */
MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x40000041 /* LTE_PWR */
MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x40000041 /* AMP GPIO1 */
MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x40000041 /* AMP GPIO2 */
MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x40000041 /* AMP GPIO3 */
MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x40000041 /* AMP_GPIO4 */
MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 /* APP GPIO1 */
MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x40000041 /* VDD_4P0_EN */
MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* APP GPIO2 */
MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* UART2_EN# */
MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x40000041 /* MIPI_GPIO1 */
@ -779,8 +797,6 @@
MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* RST# */
MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* IRQ# */
MX8MM_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x141
MX8MM_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x141
>;
};
@ -797,6 +813,13 @@
>;
};
pinctrl_i2c1_gpio: i2c1gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3
MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
@ -804,6 +827,13 @@
>;
};
pinctrl_i2c2_gpio: i2c2gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3
MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
@ -811,6 +841,13 @@
>;
};
pinctrl_i2c3_gpio: i2c3gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3
MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
@ -818,6 +855,13 @@
>;
};
pinctrl_i2c4_gpio: i2c4gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c3
MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c3
>;
};
pinctrl_gpio_leds: gpioledgrp {
fsl,pins = <
MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19

36
arch/arm/dts/imx8mm-venice-gw7903.dts
View File

@ -265,8 +265,11 @@
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
gsc: gsc@20 {
@ -397,8 +400,11 @@
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
pmic@4b {
@ -520,8 +526,11 @@
&i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
pinctrl-1 = <&pinctrl_i2c3_gpio>;
scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
accelerometer@19 {
@ -681,6 +690,13 @@
>;
};
pinctrl_i2c1_gpio: i2c1gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3
MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
@ -688,6 +704,13 @@
>;
};
pinctrl_i2c2_gpio: i2c2gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3
MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
@ -695,6 +718,13 @@
>;
};
pinctrl_i2c3_gpio: i2c3gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3
MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3
>;
};
pinctrl_gpio_leds: gpioledgrp {
fsl,pins = <
MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19

48
arch/arm/dts/imx8mm-venice-gw7904.dts
View File

@ -315,8 +315,11 @@
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
gsc: gsc@20 {
@ -441,8 +444,11 @@
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
pmic@4b {
@ -564,8 +570,11 @@
&i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
pinctrl-1 = <&pinctrl_i2c3_gpio>;
scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
accelerometer@19 {
@ -582,8 +591,11 @@
&i2c4 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c4>;
pinctrl-1 = <&pinctrl_i2c4_gpio>;
scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
gpioled: gpio@27 {
@ -738,6 +750,13 @@
>;
};
pinctrl_i2c1_gpio: i2c1gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3
MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
@ -745,6 +764,13 @@
>;
};
pinctrl_i2c2_gpio: i2c2gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3
MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
@ -752,6 +778,13 @@
>;
};
pinctrl_i2c3_gpio: i2c3gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3
MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
@ -759,6 +792,13 @@
>;
};
pinctrl_i2c4_gpio: i2c4gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c3
MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c3
>;
};
pinctrl_pcie0: pciegrp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x41

4
arch/arm/dts/imx8mm-venice-u-boot.dtsi
View File

@ -57,6 +57,10 @@
u-boot,dm-spl;
};
&pinctrl_i2c1_gpio {
u-boot,dm-spl;
};
&gsc {
u-boot,dm-spl;
};

12
arch/arm/dts/imx8mm-venice.dts
View File

@ -23,8 +23,11 @@
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
status = "okay";
gsc: gsc@20 {
@ -89,6 +92,13 @@
>;
};
pinctrl_i2c1_gpio: i2c1grp-gpio-grp {
fsl,pins = <
MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3
MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3

18
arch/arm/dts/imx8mn-u-boot.dtsi
View File

@ -85,7 +85,7 @@
#ifdef CONFIG_IMX8M_LPDDR4
filename = "lpddr4_pmu_train_1d_imem.bin";
#elif CONFIG_IMX8M_DDR4
filename = "ddr4_imem_1d.bin";
filename = "ddr4_imem_1d_201810.bin";
#else
filename = "ddr3_imem_1d.bin";
#endif
@ -97,7 +97,7 @@
#ifdef CONFIG_IMX8M_LPDDR4
filename = "lpddr4_pmu_train_1d_dmem.bin";
#elif CONFIG_IMX8M_DDR4
filename = "ddr4_dmem_1d.bin";
filename = "ddr4_dmem_1d_201810.bin";
#else
filename = "ddr3_dmem_1d.bin";
#endif
@ -105,11 +105,12 @@
align-end = <4>;
};
#if defined(CONFIG_IMX8M_LPDDR4) || defined(CONFIG_IMX8M_DDR4)
ddr-2d-imem-fw {
#ifdef CONFIG_IMX8M_LPDDR4
filename = "lpddr4_pmu_train_2d_imem.bin";
#elif CONFIG_IMX8M_DDR4
filename = "ddr4_imem_2d.bin";
#else
filename = "ddr4_imem_2d_201810.bin";
#endif
type = "blob-ext";
align-end = <4>;
@ -118,12 +119,13 @@
ddr-2d-dmem-fw {
#ifdef CONFIG_IMX8M_LPDDR4
filename = "lpddr4_pmu_train_2d_dmem.bin";
#elif CONFIG_IMX8M_DDR4
filename = "ddr4_dmem_2d.bin";
#else
filename = "ddr4_dmem_2d_201810.bin";
#endif
type = "blob-ext";
align-end = <4>;
};
#endif
};
spl {
@ -161,6 +163,7 @@
};
};
#ifndef CONFIG_ARMV8_PSCI
atf {
arch = "arm64";
compression = "none";
@ -174,6 +177,7 @@
type = "atf-bl31";
};
};
#endif
binman_fip: fip {
arch = "arm64";
@ -202,7 +206,9 @@
description = "NAME";
fdt = "fdt-SEQ";
firmware = "uboot";
#ifndef CONFIG_ARMV8_PSCI
loadables = "atf";
#endif
};
};
};

14
arch/arm/dts/imx8mn-venice-gw7902-u-boot.dtsi
View File

@ -6,6 +6,13 @@
#include "imx8mn-venice-u-boot.dtsi"
&gpio1 {
m2pwren {
gpio-hog;
output-low;
gpios = <8 GPIO_ACTIVE_HIGH>;
line-name = "m2_pwren";
};
m2rst {
gpio-hog;
output-low;
@ -54,6 +61,13 @@
line-name = "app_gpio1";
};
vdd4p0en {
gpio-hog;
output-low;
gpios = <22 GPIO_ACTIVE_HIGH>;
line-name = "vdd_4p0_en";
};
uart1rs485 {
gpio-hog;
output-low;

56
arch/arm/dts/imx8mn-venice-gw7902.dts
View File

@ -256,7 +256,7 @@
&gpio1 {
gpio-line-names = "", "", "", "", "", "", "", "",
"", "", "", "", "", "m2_reset", "", "m2_wdis#",
"m2_pwr_en", "", "", "", "", "m2_reset", "", "m2_wdis#",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
@ -278,7 +278,7 @@
&gpio4 {
gpio-line-names = "", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "app_gpio1", "", "uart1_rs485",
"", "", "", "", "", "app_gpio1", "vdd_4p0_en", "uart1_rs485",
"", "uart1_term", "uart1_half", "app_gpio2",
"mipi_gpio1", "", "", "";
};
@ -297,8 +297,11 @@
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
gsc: gsc@20 {
@ -565,8 +568,11 @@
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
accelerometer@19 {
@ -584,16 +590,22 @@
/* off-board header */
&i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
pinctrl-1 = <&pinctrl_i2c3_gpio>;
scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
/* off-board header */
&i2c4 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c4>;
pinctrl-1 = <&pinctrl_i2c4_gpio>;
scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
@ -689,10 +701,12 @@
pinctrl_hog: hoggrp {
fsl,pins = <
MX8MN_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */
MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x40000041 /* M2_PWR_EN */
MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RESET */
MX8MN_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */
MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */
MX8MN_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 /* APP GPIO1 */
MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x40000041 /* VDD_4P0_EN */
MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* APP GPIO2 */
MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* UART2_EN# */
MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x40000041 /* MIPI_GPIO1 */
@ -726,8 +740,6 @@
MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* RST# */
MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* IRQ# */
MX8MN_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x141
MX8MN_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x141
>;
};
@ -744,6 +756,13 @@
>;
};
pinctrl_i2c1_gpio: i2c1gpiogrp {
fsl,pins = <
MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3
MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
@ -751,6 +770,13 @@
>;
};
pinctrl_i2c2_gpio: i2c2gpiogrp {
fsl,pins = <
MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3
MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
@ -758,6 +784,13 @@
>;
};
pinctrl_i2c3_gpio: i2c3gpiogrp {
fsl,pins = <
MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3
MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
@ -765,6 +798,13 @@
>;
};
pinctrl_i2c4_gpio: i2c4gpiogrp {
fsl,pins = <
MX8MN_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c3
MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c3
>;
};
pinctrl_gpio_leds: gpioledgrp {
fsl,pins = <
MX8MN_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19

4
arch/arm/dts/imx8mn-venice-u-boot.dtsi
View File

@ -49,6 +49,10 @@
u-boot,dm-spl;
};
&pinctrl_i2c1_gpio {
u-boot,dm-spl;
};
&gsc {
u-boot,dm-spl;
};

12
arch/arm/dts/imx8mn-venice.dts
View File

@ -23,8 +23,11 @@
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
status = "okay";
gsc: gsc@20 {
@ -89,6 +92,13 @@
>;
};
pinctrl_i2c1_gpio: i2c1grp-gpio-grp {
fsl,pins = <
MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3
MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3

10
arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi
View File

@ -158,12 +158,10 @@
};
};
};
configurations {
conf {
loadables = "atf", "fip";
};
};
};
};
};
&binman_configuration {
loadables = "atf", "fip";
};

6
arch/arm/dts/imx8mp-u-boot.dtsi
View File

@ -120,6 +120,7 @@
};
};
#ifndef CONFIG_ARMV8_PSCI
atf {
description = "ARM Trusted Firmware";
type = "firmware";
@ -133,6 +134,7 @@
type = "atf-bl31";
};
};
#endif
@fdt-SEQ {
description = "NAME";
@ -148,11 +150,13 @@
configurations {
default = "@config-DEFAULT-SEQ";
@config-SEQ {
binman_configuration: @config-SEQ {
description = "NAME";
fdt = "fdt-SEQ";
firmware = "uboot";
#ifndef CONFIG_ARMV8_PSCI
loadables = "atf";
#endif
};
};
};

48
arch/arm/dts/imx8mp-venice-gw74xx.dts
View File

@ -253,8 +253,11 @@
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
gsc: gsc@20 {
@ -477,8 +480,11 @@
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
accelerometer@19 {
@ -556,16 +562,22 @@
/* off-board header */
&i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
pinctrl-1 = <&pinctrl_i2c3_gpio>;
scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
/* off-board header */
&i2c4 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c4>;
pinctrl-1 = <&pinctrl_i2c4_gpio>;
scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
@ -800,6 +812,13 @@
>;
};
pinctrl_i2c1_gpio: i2c1gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c2
MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c2
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
@ -807,6 +826,13 @@
>;
};
pinctrl_i2c2_gpio: i2c2gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c3
MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c3
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
@ -814,6 +840,13 @@
>;
};
pinctrl_i2c3_gpio: i2c3gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c3
MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c3
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c2
@ -821,6 +854,13 @@
>;
};
pinctrl_i2c4_gpio: i2c4gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x400001c3
MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001c3
>;
};
pinctrl_ksz: kszgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x150 /* IRQ# */

4
arch/arm/dts/imx8mp-venice-u-boot.dtsi
View File

@ -57,6 +57,10 @@
u-boot,dm-spl;
};
&pinctrl_i2c1_gpio {
u-boot,dm-spl;
};
&gsc {
u-boot,dm-spl;
};

12
arch/arm/dts/imx8mp-venice.dts
View File

@ -23,8 +23,11 @@
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
status = "okay";
gsc: gsc@20 {
@ -89,6 +92,13 @@
>;
};
pinctrl_i2c1_gpio: i2c1grp-gpio-grp {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c3
MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c3
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3

4
arch/arm/dts/imx8mq-u-boot.dtsi
View File

@ -114,6 +114,7 @@
};
};
#ifndef CONFIG_ARMV8_PSCI
atf {
arch = "arm64";
compression = "none";
@ -127,6 +128,7 @@
type = "blob-ext";
};
};
#endif
fdt {
compression = "none";
@ -147,7 +149,9 @@
description = "NAME";
fdt = "fdt";
firmware = "uboot";
#ifndef CONFIG_ARMV8_PSCI
loadables = "atf";
#endif
};
};
};

1
arch/arm/dts/imx8ulp-evk-u-boot.dtsi
View File

@ -26,6 +26,7 @@
&iomuxc1 {
u-boot,dm-spl;
fsl,mux_mask = <0xf00>;
};
&pinctrl_lpuart5 {

2
arch/arm/include/asm/arch-imx8/sci/rpc.h
View File

@ -11,7 +11,7 @@
/* Defines */
#define SCFW_API_VERSION_MAJOR 1U
#define SCFW_API_VERSION_MINOR 15U
#define SCFW_API_VERSION_MINOR 21U
#define SC_RPC_VERSION 1U

8
arch/arm/include/asm/arch-imx8m/imx-regs.h
View File

@ -31,6 +31,7 @@
#define CCM_BASE_ADDR 0x30380000
#define SRC_BASE_ADDR 0x30390000
#define GPC_BASE_ADDR 0x303A0000
#define CSU_BASE_ADDR 0x303E0000
#define SYSCNT_RD_BASE_ADDR 0x306A0000
#define SYSCNT_CMP_BASE_ADDR 0x306B0000
@ -81,6 +82,9 @@
#define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000)
#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
#define GICD_BASE 0x38800000
#define GICR_BASE 0x38880000
#define DDRC_DDR_SS_GPR0 0x3d000000
#define DDRC_IPS_BASE_ADDR(X) (0x3d400000 + ((X) * 0x2000000))
#define DDR_CSD1_BASE_ADDR 0x40000000
@ -88,6 +92,10 @@
#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK 0x70000
#define FEC_QUIRK_ENET_MAC
#ifdef CONFIG_ARMV8_PSCI /* Final jump location */
#define CPU_RELEASE_ADDR 0x900000
#endif
#define CAAM_ARB_BASE_ADDR (0x00100000)
#define CAAM_ARB_END_ADDR (0x00107FFF)
#define CAAM_IPS_BASE_ADDR (0x30900000)

2
arch/arm/include/asm/arch-imx8m/imx8mq_pins.h
View File

@ -538,7 +538,7 @@ enum {
IMX8MQ_PAD_ECSPI2_SCLK__GPIO5_IO10 = IOMUX_PAD(0x046C, 0x0204, 5, 0x0000, 0, 0),
IMX8MQ_PAD_ECSPI2_MOSI__ECSPI2_MOSI = IOMUX_PAD(0x0470, 0x0208, 0, 0x0000, 0, 0),
IMX8MQ_PAD_ECSPI2_MOSI__UART4_TX = IOMUX_PAD(0x0470, 0x0208, 1, 0x050C, 1, 0),
IMX8MQ_PAD_ECSPI2_MOSI__UART4_TX = IOMUX_PAD(0x0470, 0x0208, 1, 0x0000, 0, 0),
IMX8MQ_PAD_ECSPI2_MOSI__GPIO5_IO11 = IOMUX_PAD(0x0470, 0x0208, 5, 0x0000, 0, 0),
IMX8MQ_PAD_ECSPI2_MISO__ECSPI2_MISO = IOMUX_PAD(0x0474, 0x020C, 0, 0x0000, 0, 0),

2
arch/arm/include/asm/mach-imx/sys_proto.h
View File

@ -149,6 +149,8 @@ struct rproc_att {
u32 size; /* size of reg range */
};
const struct rproc_att *imx_bootaux_get_hostmap(void);
struct rom_api {
u16 ver;
u16 tag;

5
arch/arm/include/asm/psci.h
View File

@ -22,6 +22,7 @@
#include <linux/bitops.h>
#endif
#define ARM_PSCI_VER_1_1 (0x00010001)
#define ARM_PSCI_VER_1_0 (0x00010000)
#define ARM_PSCI_VER_0_2 (0x00000002)
@ -68,7 +69,6 @@
#define ARM_PSCI_0_2_FN64_AFFINITY_INFO ARM_PSCI_0_2_FN64(4)
#define ARM_PSCI_0_2_FN64_MIGRATE ARM_PSCI_0_2_FN64(5)
#define ARM_PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU ARM_PSCI_0_2_FN64(7)
#define ARM_PSCI_0_2_FN64_SYSTEM_RESET2 ARM_PSCI_0_2_FN64(18)
/* PSCI 1.0 interface */
#define ARM_PSCI_1_0_FN_PSCI_FEATURES ARM_PSCI_0_2_FN(10)
@ -86,6 +86,9 @@
#define ARM_PSCI_1_0_FN64_STAT_RESIDENCY ARM_PSCI_0_2_FN64(16)
#define ARM_PSCI_1_0_FN64_STAT_COUNT ARM_PSCI_0_2_FN64(17)
/* PSCI 1.1 interface */
#define ARM_PSCI_1_1_FN64_SYSTEM_RESET2 ARM_PSCI_0_2_FN64(18)
/* 1KB stack per core */
#define ARM_PSCI_STACK_SHIFT 10
#define ARM_PSCI_STACK_SIZE (1 << ARM_PSCI_STACK_SHIFT)

2
arch/arm/mach-imx/Makefile
View File

@ -235,8 +235,6 @@ endif
targets += $(addprefix ../../../,SPL spl/u-boot-spl.cfgout u-boot-dtb.cfgout u-boot.cfgout u-boot.uim spl/u-boot-nand-spl.imx)
obj-$(CONFIG_ARM64) += lowlevel.o
obj-$(CONFIG_MX5) += mx5/
obj-$(CONFIG_MX6) += mx6/
obj-$(CONFIG_MX7) += mx7/

23
arch/arm/mach-imx/imx8m/Kconfig
View File

@ -2,6 +2,7 @@ if ARCH_IMX8M
config IMX8M
bool
select GICV3 if ARMV8_PSCI
select HAS_CAAM
select ROM_UNIFIED_SECTIONS
select ARMV8_CRYPTO
@ -26,6 +27,14 @@ config IMX8MP
config SYS_SOC
default "imx8m"
config SYS_HAS_ARMV8_SECURE_BASE
bool "Enable secure address for PSCI image"
depends on ARMV8_PSCI
help
PSCI image can be re-located to secure RAM.
If enabled, please also define the value for ARMV8_SECURE_BASE,
for i.MX8M, it could be some address in OCRAM.
choice
prompt "NXP i.MX8M board select"
optional
@ -94,6 +103,13 @@ config TARGET_IMX8MM_MX8MENLO
select SUPPORT_SPL
select IMX8M_LPDDR4
config TARGET_IMX8MM_PHG
bool "i.MX8MM PHG board"
select BINMAN
select IMX8MM
select SUPPORT_SPL
select IMX8M_LPDDR4
config TARGET_IMX8MM_VENICE
bool "Support Gateworks Venice iMX8M Mini module"
select BINMAN
@ -233,6 +249,9 @@ config TARGET_IMX8MM_BEACON
select IMX8MM
select SUPPORT_SPL
select IMX8M_LPDDR4
select FSL_CAAM
select ARCH_MISC_INIT
select SPL_CRYPTO if SPL
config TARGET_IMX8MN_BEACON
bool "imx8mn Beacon Embedded devkit"
@ -240,6 +259,9 @@ config TARGET_IMX8MN_BEACON
select IMX8MN
select SUPPORT_SPL
select IMX8M_LPDDR4
select FSL_CAAM
select ARCH_MISC_INIT
select SPL_CRYPTO if SPL
config TARGET_PHYCORE_IMX8MM
bool "PHYTEC PHYCORE i.MX8MM"
@ -305,6 +327,7 @@ source "board/advantech/imx8mp_rsb3720a1/Kconfig"
source "board/beacon/imx8mm/Kconfig"
source "board/beacon/imx8mn/Kconfig"
source "board/bsh/imx8mn_smm_s2/Kconfig"
source "board/cloos/imx8mm_phg/Kconfig"
source "board/compulab/imx8mm-cl-iot-gate/Kconfig"
source "board/data_modul/imx8mm_edm_sbc/Kconfig"
source "board/dhelectronics/dh_imx8mp/Kconfig"

1
arch/arm/mach-imx/imx8m/Makefile
View File

@ -4,5 +4,6 @@
obj-y += lowlevel_init.o
obj-y += clock_slice.o soc.o
obj-$(CONFIG_ARMV8_PSCI) += psci.o
obj-$(CONFIG_IMX8MQ) += clock_imx8mq.o
obj-$(CONFIG_IMX8MM)$(CONFIG_IMX8MN)$(CONFIG_IMX8MP) += clock_imx8mm.o

288
arch/arm/mach-imx/imx8m/psci.c Normal file
View File

@ -0,0 +1,288 @@
// SPDX-License-Identifier: GPL-2.0
/*
* This file implements basic PSCI support for i.MX8M
*
* Copyright (C) 2022 Marek Vasut <marex@denx.de>
*/
#include <asm/arch/imx-regs.h>
#include <asm/cache.h>
#include <asm/gic.h>
#include <asm/io.h>
#include <asm/psci.h>
#include <asm/secure.h>
#include <common.h>
#include <cpu_func.h>
#include <debug_uart.h>
#include <fsl_wdog.h>
#include <linux/bitops.h>
#define SNVS_LPCR 0x38
#define SNVS_LPCR_TOP BIT(6)
#define SNVS_LPCR_DP_EN BIT(5)
#define SNVS_LPCR_SRTC_ENV BIT(0)
#define MPIDR_AFF0 GENMASK(7, 0)
#define GPC_LPCR_A53_AD 0x4
#define EN_Cn_WFI_PDN(cpu) BIT(((((cpu) & 1) * 2) + (((cpu) & 2) * 8)))
#define GPC_PGC_nCTRL(cpu) (0x800 + ((cpu) * 0x40))
#define PGC_PCR BIT(0)
#define GPC_CPU_PGC_SW_PUP_REQ (IS_ENABLED(CONFIG_IMX8MP) ? 0xd0 : 0xf0)
#define COREn_A53_SW_PUP_REQ(cpu) BIT(cpu)
#define SRC_A53RCR1 0x8
#define A53_COREn_ENABLE(n) BIT(n)
#define SRC_GPR(n) (0x74 + ((n) * 4))
/*
* Helper code
*/
static u8 psci_state[CONFIG_ARMV8_PSCI_NR_CPUS] __secure_data = {
PSCI_AFFINITY_LEVEL_ON,
PSCI_AFFINITY_LEVEL_OFF,
PSCI_AFFINITY_LEVEL_OFF,
PSCI_AFFINITY_LEVEL_OFF
};
int psci_update_dt(void *fdt)
{
return 0;
}
__secure static void psci_set_state(int cpu, u8 state)
{
psci_state[cpu] = state;
dsb();
isb();
}
__secure static s32 psci_cpu_on_validate_mpidr(u64 mpidr, u32 *cpu)
{
*cpu = mpidr & MPIDR_AFF0;
if (mpidr & ~MPIDR_AFF0)
return ARM_PSCI_RET_INVAL;
if (*cpu >= CONFIG_ARMV8_PSCI_NR_CPUS)
return ARM_PSCI_RET_INVAL;
if (psci_state[*cpu] == PSCI_AFFINITY_LEVEL_ON)
return ARM_PSCI_RET_ALREADY_ON;
if (psci_state[*cpu] == PSCI_AFFINITY_LEVEL_ON_PENDING)
return ARM_PSCI_RET_ON_PENDING;
return ARM_PSCI_RET_SUCCESS;
}
__secure static void psci_cpu_on_write_entry_point(const u32 cpu, u64 entry_point)
{
const u64 ep = CONFIG_SPL_TEXT_BASE;
/* Trampoline target */
writeq(entry_point, CPU_RELEASE_ADDR);
/* RVBAR address HI */
writel((u32)(ep >> 24) & 0xffff,
(void *)SRC_BASE_ADDR + SRC_GPR(cpu * 2));
/* RVBAR address LO */
writel((u32)(ep >> 2) & 0x3fffff,
(void *)SRC_BASE_ADDR + SRC_GPR(cpu * 2 + 1));
}
__secure static void psci_cpu_on_power_on(const u32 cpu)
{
int i;
clrbits_le32((void *)GPC_BASE_ADDR + GPC_LPCR_A53_AD, EN_Cn_WFI_PDN(cpu));
clrbits_le32((void *)SRC_BASE_ADDR + SRC_A53RCR1, A53_COREn_ENABLE(cpu));
setbits_le32((void *)GPC_BASE_ADDR + GPC_PGC_nCTRL(cpu), PGC_PCR);
setbits_le32((void *)GPC_BASE_ADDR + GPC_CPU_PGC_SW_PUP_REQ, COREn_A53_SW_PUP_REQ(cpu));
/* If we fail here, the core gets power cycled, hang is OK */
while (readl(GPC_BASE_ADDR + GPC_CPU_PGC_SW_PUP_REQ) & COREn_A53_SW_PUP_REQ(cpu))
;
clrbits_le32((void *)GPC_BASE_ADDR + GPC_PGC_nCTRL(cpu), PGC_PCR);
setbits_le32((void *)SRC_BASE_ADDR + SRC_A53RCR1, A53_COREn_ENABLE(cpu));
/* Give the core a bit of time to boot and start executing code */
for (i = 0; i < 100000; i++)
asm volatile("nop");
}
__secure static void psci_cpu_on_power_off(const u32 cpu)
{
setbits_le32((void *)GPC_BASE_ADDR + GPC_LPCR_A53_AD, EN_Cn_WFI_PDN(cpu));
setbits_le32((void *)GPC_BASE_ADDR + GPC_PGC_nCTRL(cpu), PGC_PCR);
}
/*
* Common PSCI code
*/
/* Return supported PSCI version */
__secure u32 psci_version(void)
{
return ARM_PSCI_VER_1_0;
}
/*
* 64bit PSCI code
*/
__secure s32 psci_cpu_on_64(u32 __always_unused function_id, u64 mpidr,
u64 entry_point_address, u64 context_id)
{
u32 cpu = 0;
int ret;
ret = psci_cpu_on_validate_mpidr(mpidr, &cpu);
if (ret != ARM_PSCI_RET_SUCCESS)
return ret;
psci_cpu_on_write_entry_point(cpu, entry_point_address);
psci_set_state(cpu, PSCI_AFFINITY_LEVEL_ON);
psci_cpu_on_power_on(cpu);
smp_kick_all_cpus();
return ARM_PSCI_RET_SUCCESS;
}
__secure s32 psci_affinity_info_64(u32 __always_unused function_id,
u64 target_affinity, u32 lowest_affinity_level)
{
u32 cpu = target_affinity & MPIDR_AFF0;
if (lowest_affinity_level > 0)
return ARM_PSCI_RET_INVAL;
if (target_affinity & ~MPIDR_AFF0)
return ARM_PSCI_RET_INVAL;
if (cpu >= CONFIG_ARMV8_PSCI_NR_CPUS)
return ARM_PSCI_RET_INVAL;
return psci_state[cpu];
}
__secure s32 psci_system_reset2_64(u32 __always_unused function_id,
u32 reset_type, u64 cookie)
{
psci_system_reset();
return 0; /* Not reached */
}
/*
* 32bit PSCI code
*/
__secure s32 psci_affinity_info(u32 __always_unused function_id,
u32 target_affinity, u32 lowest_affinity_level)
{
return psci_affinity_info_64(function_id, target_affinity, lowest_affinity_level);
}
__secure s32 psci_cpu_on(u32 __always_unused function_id, u32 mpidr,
u32 entry_point_address, u32 context_id)
{
return psci_cpu_on_64(function_id, mpidr, entry_point_address, context_id);
}
__secure s32 psci_cpu_off(void)
{
u32 cpu = psci_get_cpu_id();
psci_cpu_on_power_off(cpu);
psci_set_state(cpu, PSCI_AFFINITY_LEVEL_OFF);
while (1)
wfi();
}
__secure u32 psci_migrate_info_type(void)
{
/* Trusted OS is either not present or does not require migration */
return 2;
}
__secure void psci_system_reset(void)
{
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
bool ext_reset = true;
u16 wcr = WCR_WDE;
if (ext_reset)
wcr |= WCR_SRS; /* do not assert internal reset */
else
wcr |= WCR_WDA; /* do not assert external reset */
/* Write 3 times to ensure it works, due to IMX6Q errata ERR004346 */
writew(wcr, &wdog->wcr);
writew(wcr, &wdog->wcr);
writew(wcr, &wdog->wcr);
while (1)
wfi();
}
__secure void psci_system_off(void)
{
writel(SNVS_LPCR_TOP | SNVS_LPCR_DP_EN | SNVS_LPCR_SRTC_ENV,
SNVS_BASE_ADDR + SNVS_LPCR);
while (1)
wfi();
}
/*
* PSCI jump table
*/
__secure s32 psci_features(u32 __always_unused function_id, u32 psci_fid)
{
switch (psci_fid) {
case ARM_PSCI_0_2_FN_PSCI_VERSION:
case ARM_PSCI_0_2_FN_CPU_OFF:
case ARM_PSCI_0_2_FN_CPU_ON:
case ARM_PSCI_0_2_FN_AFFINITY_INFO:
case ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE:
case ARM_PSCI_0_2_FN_SYSTEM_OFF:
case ARM_PSCI_0_2_FN_SYSTEM_RESET:
case ARM_PSCI_0_2_FN64_CPU_ON:
case ARM_PSCI_0_2_FN64_AFFINITY_INFO:
/* PSCI 1.0 interface */
case ARM_PSCI_1_0_FN_PSCI_FEATURES:
/* PSCI 1.1 interface */
case ARM_PSCI_1_1_FN64_SYSTEM_RESET2:
return 0x0;
/*
* Not implemented:
* ARM_PSCI_0_2_FN_CPU_SUSPEND
* ARM_PSCI_1_0_FN_CPU_FREEZE
* ARM_PSCI_1_0_FN_CPU_DEFAULT_SUSPEND
* ARM_PSCI_1_0_FN_NODE_HW_STATE
* ARM_PSCI_1_0_FN_SYSTEM_SUSPEND
* ARM_PSCI_1_0_FN_SET_SUSPEND_MODE
* ARM_PSCI_1_0_FN_STAT_RESIDENCY
* ARM_PSCI_1_0_FN_STAT_COUNT
* ARM_PSCI_0_2_FN64_CPU_SUSPEND
* ARM_PSCI_1_0_FN64_CPU_DEFAULT_SUSPEND
* ARM_PSCI_1_0_FN64_NODE_HW_STATE
* ARM_PSCI_1_0_FN64_SYSTEM_SUSPEND
* ARM_PSCI_1_0_FN64_STAT_RESIDENCY
* ARM_PSCI_1_0_FN64_STAT_COUNT
*/
/* Not required, ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE returns 2 */
case ARM_PSCI_0_2_FN_MIGRATE:
case ARM_PSCI_0_2_FN64_MIGRATE:
/* Not required */
case ARM_PSCI_0_2_FN_MIGRATE_INFO_UP_CPU:
case ARM_PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU:
default:
return ARM_PSCI_RET_NI;
}
}

55
arch/arm/mach-imx/imx8m/soc.c
View File

@ -100,6 +100,12 @@ void set_wdog_reset(struct wdog_regs *wdog)
setbits_le16(&wdog->wcr, WDOG_WDT_MASK | WDOG_WDZST_MASK);
}
#ifdef CONFIG_ARMV8_PSCI
#define PTE_MAP_NS PTE_BLOCK_NS
#else
#define PTE_MAP_NS 0
#endif
static struct mm_region imx8m_mem_map[] = {
{
/* ROM */
@ -122,7 +128,7 @@ static struct mm_region imx8m_mem_map[] = {
.phys = 0x180000UL,
.size = 0x8000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE
PTE_BLOCK_OUTER_SHARE | PTE_MAP_NS
}, {
/* TCM */
.virt = 0x7C0000UL,
@ -130,14 +136,14 @@ static struct mm_region imx8m_mem_map[] = {
.size = 0x80000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_MAP_NS
}, {
/* OCRAM */
.virt = 0x900000UL,
.phys = 0x900000UL,
.size = 0x200000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE
PTE_BLOCK_OUTER_SHARE | PTE_MAP_NS
}, {
/* AIPS */
.virt = 0xB00000UL,
@ -152,7 +158,7 @@ static struct mm_region imx8m_mem_map[] = {
.phys = 0x40000000UL,
.size = PHYS_SDRAM_SIZE,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE
PTE_BLOCK_OUTER_SHARE | PTE_MAP_NS
#ifdef PHYS_SDRAM_2_SIZE
}, {
/* DRAM2 */
@ -160,7 +166,7 @@ static struct mm_region imx8m_mem_map[] = {
.phys = 0x100000000UL,
.size = PHYS_SDRAM_2_SIZE,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE
PTE_BLOCK_OUTER_SHARE | PTE_MAP_NS
#endif
}, {
/* empty entrie to split table entry 5 if needed when TEEs are used */
@ -238,7 +244,7 @@ int dram_init(void)
return ret;
/* rom_pointer[1] contains the size of TEE occupies */
if (rom_pointer[1])
if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && rom_pointer[1])
gd->ram_size = sdram_size - rom_pointer[1];
else
gd->ram_size = sdram_size;
@ -267,7 +273,7 @@ int dram_init_banksize(void)
}
gd->bd->bi_dram[bank].start = PHYS_SDRAM;
if (rom_pointer[1]) {
if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && rom_pointer[1]) {
phys_addr_t optee_start = (phys_addr_t)rom_pointer[0];
phys_size_t optee_size = (size_t)rom_pointer[1];
@ -312,7 +318,7 @@ phys_size_t get_effective_memsize(void)
sdram_b1_size = sdram_size;
}
if (rom_pointer[1]) {
if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && rom_pointer[1]) {
/* We will relocate u-boot to Top of dram1. Tee position has two cases:
* 1. At the top of dram1, Then return the size removed optee size.
* 2. In the middle of dram1, return the size of dram1.
@ -344,7 +350,8 @@ phys_size_t board_get_usable_ram_top(phys_size_t total_size)
* rom_pointer[1] stores the size TEE uses.
* We need to reserve the memory region for TEE.
*/
if (rom_pointer[0] && rom_pointer[1] && top_addr > rom_pointer[0])
if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && rom_pointer[0] &&
rom_pointer[1] && top_addr > rom_pointer[0])
top_addr = rom_pointer[0];
return top_addr;
@ -554,6 +561,29 @@ static void imx8m_setup_snvs(void)
writel(0xffffffff, SNVS_BASE_ADDR + SNVS_LPSR);
}
static void imx8m_setup_csu_tzasc(void)
{
const uintptr_t tzasc_base[4] = {
0x301f0000, 0x301f0000, 0x301f0000, 0x301f0000
};
int i, j;
if (!IS_ENABLED(CONFIG_ARMV8_PSCI))
return;
/* CSU */
for (i = 0; i < 64; i++)
writel(0x00ff00ff, (void *)CSU_BASE_ADDR + (4 * i));
/* TZASC */
for (j = 0; j < 4; j++) {
writel(0x77777777, (void *)(tzasc_base[j]));
writel(0x77777777, (void *)(tzasc_base[j]) + 0x4);
for (i = 0; i <= 0x10; i += 4)
writel(0, (void *)(tzasc_base[j]) + 0x40 + i);
}
}
int arch_cpu_init(void)
{
struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
@ -606,6 +636,8 @@ int arch_cpu_init(void)
imx8m_setup_snvs();
imx8m_setup_csu_tzasc();
return 0;
}
@ -1610,4 +1642,9 @@ const struct rproc_att hostmap[] = {
{ 0x40000000, 0x40000000, 0x80000000 },
{ /* sentinel */ }
};
const struct rproc_att *imx_bootaux_get_hostmap(void)
{
return hostmap;
}
#endif

15
arch/arm/mach-imx/imx_bootaux.c
View File

@ -15,17 +15,20 @@
#include <cpu_func.h>
/* Just to avoid build error */
#if CONFIG_IS_ENABLED(IMX8M)
#if IS_ENABLED(CONFIG_IMX8M)
#define SRC_M4C_NON_SCLR_RST_MASK BIT(0)
#define SRC_M4_ENABLE_MASK BIT(0)
#define SRC_M4_REG_OFFSET 0
#endif
const __weak struct rproc_att hostmap[] = { };
__weak const struct rproc_att *imx_bootaux_get_hostmap(void)
{
return NULL;
}
static const struct rproc_att *get_host_mapping(unsigned long auxcore)
{
const struct rproc_att *mmap = hostmap;
const struct rproc_att *mmap = imx_bootaux_get_hostmap();
while (mmap && mmap->size) {
if (mmap->da <= auxcore &&
@ -106,7 +109,7 @@ int arch_auxiliary_core_up(u32 core_id, ulong addr)
if (!pc)
return CMD_RET_FAILURE;
if (!CONFIG_IS_ENABLED(ARM64))
if (!IS_ENABLED(CONFIG_ARM64))
stack = 0x0;
} else {
/*
@ -128,7 +131,7 @@ int arch_auxiliary_core_up(u32 core_id, ulong addr)
flush_dcache_all();
/* Enable M4 */
if (CONFIG_IS_ENABLED(IMX8M)) {
if (IS_ENABLED(CONFIG_IMX8M)) {
arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0, 0, 0, 0, 0, NULL);
} else {
clrsetbits_le32(SRC_BASE_ADDR + SRC_M4_REG_OFFSET,
@ -143,7 +146,7 @@ int arch_auxiliary_core_check_up(u32 core_id)
struct arm_smccc_res res;
unsigned int val;
if (CONFIG_IS_ENABLED(IMX8M)) {
if (IS_ENABLED(CONFIG_IMX8M)) {
arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, 0, 0, 0, 0, 0, &res);
return res.a0;
}

22
arch/arm/mach-imx/lowlevel.S
View File

@ -1,22 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2019 NXP
*/
#include <linux/linkage.h>
ENTRY(lowlevel_init)
mrs x0, CurrentEL
cmp x0, #8
b.eq 1f
ret
1:
msr daifclr, #4
/* set HCR_EL2.AMO to catch SERROR */
mrs x0, hcr_el2
orr x0, x0, #0x20
msr hcr_el2, x0
isb
ret
ENDPROC(lowlevel_init)

2
arch/arm/mach-imx/mx7/clock.c
View File

@ -502,7 +502,7 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
case MXC_IPG_CLK:
return get_ipg_clk();
case MXC_I2C_CLK:
return get_root_clk(I2C1_CLK_ROOT);
return 60000000;
case MXC_UART_CLK:
return get_root_clk(UART1_CLK_ROOT);
case MXC_CSPI_CLK:

5
arch/arm/mach-imx/mx7/soc.c
View File

@ -224,6 +224,11 @@ const struct rproc_att hostmap[] = {
{ 0x80000000, 0x80000000, 0x60000000 }, /* DDRC */
{ /* sentinel */ }
};
const struct rproc_att *imx_bootaux_get_hostmap(void)
{
return hostmap;
}
#endif
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)

3
arch/arm/mach-imx/romapi.c
View File

@ -66,6 +66,9 @@ enum boot_device get_boot_device(void)
case BT_DEV_TYPE_FLEXSPINOR:
boot_dev = QSPI_BOOT;
break;
case BT_DEV_TYPE_SPI_NOR:
boot_dev = SPI_NOR_BOOT;
break;
case BT_DEV_TYPE_USB:
boot_dev = boot_instance + USB_BOOT;
break;

3
board/advantech/imx8mp_rsb3720a1/spl.c
View File

@ -209,9 +209,6 @@ int power_init_board(void)
/* To avoid timing risk from SOC to ARM,increase VDD_ARM to OD voltage 0.95v */
pmic_reg_write(pdev, PCA9450_BUCK2OUT_DVS0, 0x1C);
/* set WDOG_B_CFG to cold reset */
pmic_reg_write(pdev, PCA9450_RESET_CTRL, 0xA1);
/* Forced enable the I2C level translator*/
pmic_reg_write(pdev, PCA9450_CONFIG2, 0x03);

2
board/beacon/imx8mm/README
View File

@ -11,7 +11,7 @@ Get and Build the ARM Trusted firmware
======================================
Note: $(srctree) is U-Boot source directory
$ git clone https://source.codeaurora.org/external/imx/imx-atf
$ git clone https://github.com/nxp-imx/imx-atf
$ git lf-5.10.72-2.2.0
$ make PLAT=imx8mm bl31 CROSS_COMPILE=aarch64-linux-gnu-
$ cp build/imx8mm/release/bl31.bin $(srctree)

2
board/beacon/imx8mn/README
View File

@ -11,7 +11,7 @@ Get and Build the ARM Trusted firmware
======================================
Note: $(srctree) is U-Boot source directory
$ git clone https://source.codeaurora.org/external/imx/imx-atf
$ git clone https://github.com/nxp-imx/imx-atf
$ git lf-5.10.72-2.2.0
$ make PLAT=imx8mn bl31 CROSS_COMPILE=aarch64-linux-gnu-
$ cp build/imx8mn/release/bl31.bin $(srctree)

15
board/cloos/imx8mm_phg/Kconfig Normal file
View File

@ -0,0 +1,15 @@
if TARGET_IMX8MM_PHG
config SYS_BOARD
default "imx8mm_phg"
config SYS_VENDOR
default "cloos"
config SYS_CONFIG_NAME
default "imx8mm_phg"
config IMX_CONFIG
default "board/cloos/imx8mm_phg/imximage-8mm-lpddr4.cfg"
endif

6
board/cloos/imx8mm_phg/MAINTAINERS Normal file
View File

@ -0,0 +1,6 @@
i.MX8MM PHG BOARD
M: Fabio Estevam <festevam@denx.de>
S: Maintained
F: board/cloos/imx8mm_phg/
F: include/configs/imx8mm_phg.h
F: configs/imx8mm_phg_defconfig

12
board/cloos/imx8mm_phg/Makefile Normal file
View File

@ -0,0 +1,12 @@
#
# Copyright 2018 NXP
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += imx8mm_phg.o
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
endif

50
board/cloos/imx8mm_phg/imx8mm_phg.c Normal file
View File

@ -0,0 +1,50 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018 NXP
*/
#include <common.h>
#include <env.h>
#include <init.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/global_data.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
static int setup_fec(void)
{
struct iomuxc_gpr_base_regs *gpr =
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
/* Use 125MHz anatop REF_CLK1 for ENET1, not from external */
clrsetbits_le32(&gpr->gpr[1], 0x2000, 0);
return 0;
}
int board_init(void)
{
setup_fec();
return 0;
}
int board_late_init(void)
{
if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) {
env_set("board_name", "PHG");
env_set("board_rev", "iMX8MM");
}
if (is_usb_boot()) {
env_set("bootcmd", "ums 0 mmc 0");
env_set("bootdelay", "0");
}
return 0;
}

8
board/cloos/imx8mm_phg/imx8mm_phg.env Normal file
View File

@ -0,0 +1,8 @@
fdt_addr_r=0x43000000
mmcdev=0
fdtfile=imx8mm-phg.dtb
mmcargs=setenv bootargs console=ttymxc1,115200 root=/dev/mmcblk${mmcdev}p${mmcpart} rw rootwait quiet
bootcmd=env exists mmcpart || setenv mmcpart 1; run mmcargs; \
mmc dev ${mmcdev}; load mmc ${mmcdev}:${mmcpart} ${loadaddr} boot/Image; \
load mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} boot/${fdtfile}; \
booti ${loadaddr} - ${fdt_addr_r}

8
board/cloos/imx8mm_phg/imximage-8mm-lpddr4.cfg Normal file
View File

@ -0,0 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2021 NXP
*/
BOOT_FROM sd
LOADER u-boot-spl-ddr.bin 0x7E1000

1846
board/cloos/imx8mm_phg/lpddr4_timing.c Normal file
View File

File diff suppressed because it is too large Load Diff

147
board/cloos/imx8mm_phg/spl.c Normal file
View File

@ -0,0 +1,147 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019 NXP
*/
#include <common.h>
#include <command.h>
#include <cpu_func.h>
#include <hang.h>
#include <image.h>
#include <init.h>
#include <log.h>
#include <spl.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx8mm_pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/arch/ddr.h>
#include <dm/uclass.h>
#include <dm/device.h>
#include <dm/uclass-internal.h>
#include <dm/device-internal.h>
#include <power/pmic.h>
#include <power/pca9450.h>
DECLARE_GLOBAL_DATA_PTR;
int spl_board_boot_device(enum boot_device boot_dev_spl)
{
switch (boot_dev_spl) {
case USB_BOOT:
return BOOT_DEVICE_BOARD;
case SD2_BOOT:
case MMC2_BOOT:
return BOOT_DEVICE_MMC1;
case SD3_BOOT:
case MMC3_BOOT:
return BOOT_DEVICE_MMC2;
default:
return BOOT_DEVICE_NONE;
}
}
static void spl_dram_init(void)
{
ddr_init(&dram_timing);
}
void spl_board_init(void)
{
if (is_usb_boot())
puts("USB Boot\n");
else
puts("Normal Boot\n");
}
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
/* Just empty function now - can't decide what to choose */
debug("%s: %s\n", __func__, name);
return 0;
}
#endif
static int power_init_board(void)
{
struct udevice *dev;
int ret;
ret = pmic_get("pmic@25", &dev);
if (ret == -ENODEV) {
puts("No pmic\n");
return 0;
}
if (ret != 0)
return ret;
/* BUCKxOUT_DVS0/1 control BUCK123 output */
pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
/* Buck 1 DVS control through PMIC_STBY_REQ */
pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
/* Set DVS1 to 0.8V for suspend */
pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x10);
/* increase VDD_DRAM to 0.95V for 3GHz DDR */
pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x1C);
/* VDD_DRAM needs off in suspend, set B1_ENMODE=10 (ON by PMIC_ON_REQ = H && PMIC_STBY_REQ = L) */
pmic_reg_write(dev, PCA9450_BUCK3CTRL, 0x4a);
/* set VDD_SNVS_0V8 from default 0.85V */
pmic_reg_write(dev, PCA9450_LDO2CTRL, 0xC0);
/* set WDOG_B_CFG to cold reset */
pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1);
return 0;
}
void board_init_f(ulong dummy)
{
struct udevice *dev;
int ret;
arch_cpu_init();
init_uart_clk(1);
timer_init();
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
ret = spl_early_init();
if (ret) {
debug("spl_early_init() failed: %d\n", ret);
hang();
}
ret = uclass_get_device_by_name(UCLASS_CLK,
"clock-controller@30380000",
&dev);
if (ret < 0) {
printf("Failed to find clock node. Check device tree\n");
hang();
}
preloader_console_init();
enable_tzc380();
power_init_board();
/* DDR initialization */
spl_dram_init();
board_init_r(NULL, 0);
}

194
board/data_modul/common/common.c Normal file
View File

@ -0,0 +1,194 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2022 Marek Vasut <marex@denx.de>
*/
#include <common.h>
#include <asm-generic/gpio.h>
#include <asm-generic/sections.h>
#include <asm/arch/clock.h>
#include <asm/arch/ddr.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/iomux-v3.h>
#include <common.h>
#include <dm/uclass.h>
#include <hang.h>
#include <i2c_eeprom.h>
#include <image.h>
#include <init.h>
#include <net.h>
#include <spl.h>
#include <dm/uclass.h>
#include <dm/device.h>
#include <dm/uclass-internal.h>
#include <dm/device-internal.h>
DECLARE_GLOBAL_DATA_PTR;
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
u8 dmo_get_memcfg(void)
{
struct gpio_desc gpio[4];
u8 memcfg = 0;
ofnode node;
int i, ret;
node = ofnode_path("/config");
if (!ofnode_valid(node)) {
printf("%s: no /config node?\n", __func__);
return BIT(2) | BIT(0);
}
ret = gpio_request_list_by_name_nodev(node,
"dmo,ram-coding-gpios",
gpio, ARRAY_SIZE(gpio),
GPIOD_IS_IN);
for (i = 0; i < ret; i++)
memcfg |= !!dm_gpio_get_value(&(gpio[i])) << i;
gpio_free_list_nodev(gpio, ret);
return memcfg;
}
int board_phys_sdram_size(phys_size_t *size)
{
u8 memcfg = dmo_get_memcfg();
*size = (4ULL >> ((memcfg >> 1) & 0x3)) * SZ_1G;
return 0;
}
#ifdef CONFIG_SPL_BUILD
static void data_modul_imx_edm_sbc_early_init_f(const iomux_v3_cfg_t wdog_pad)
{
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
imx_iomux_v3_setup_pad(wdog_pad | MUX_PAD_CTRL(WDOG_PAD_CTRL));
set_wdog_reset(wdog);
}
__weak int data_modul_imx_edm_sbc_board_power_init(void)
{
return 0;
}
static void spl_dram_init(struct dram_timing_info *dram_timing_info[8])
{
u8 memcfg = dmo_get_memcfg();
int i;
printf("DDR: %d GiB x%d [0x%x]\n",
/* 0..4 GiB, 1..2 GiB, 0..1 GiB */
4 >> ((memcfg >> 1) & 0x3),
/* 0..x32, 1..x16 */
32 >> (memcfg & BIT(0)),
memcfg);
if (!dram_timing_info[memcfg]) {
printf("Unsupported DRAM strapping, trying lowest supported. MEMCFG=0x%x\n",
memcfg);
for (i = 7; i >= 0; i--)
if (dram_timing_info[i]) /* Configuration found */
break;
}
ddr_init(dram_timing_info[memcfg]);
}
void dmo_board_init_f(const iomux_v3_cfg_t wdog_pad,
struct dram_timing_info *dram_timing_info[8])
{
struct udevice *dev;
int ret;
icache_enable();
arch_cpu_init();
init_uart_clk(2);
data_modul_imx_edm_sbc_early_init_f(wdog_pad);
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
ret = spl_early_init();
if (ret) {
debug("spl_early_init() failed: %d\n", ret);
hang();
}
preloader_console_init();
ret = uclass_get_device_by_name(UCLASS_CLK,
"clock-controller@30380000",
&dev);
if (ret < 0) {
printf("Failed to find clock node. Check device tree\n");
hang();
}
enable_tzc380();
data_modul_imx_edm_sbc_board_power_init();
/* DDR initialization */
spl_dram_init(dram_timing_info);
board_init_r(NULL, 0);
}
#else
void dmo_setup_boot_device(void)
{
int boot_device = get_boot_device();
char *devnum;
devnum = env_get("devnum");
if (devnum) /* devnum is already set */
return;
if (boot_device == MMC3_BOOT) /* eMMC */
env_set_ulong("devnum", 0);
else
env_set_ulong("devnum", 1);
}
void dmo_setup_mac_address(void)
{
unsigned char enetaddr[6];
struct udevice *dev;
int off, ret;
ret = eth_env_get_enetaddr("ethaddr", enetaddr);
if (ret) /* ethaddr is already set */
return;
off = fdt_path_offset(gd->fdt_blob, "eeprom0");
if (off < 0) {
printf("%s: No eeprom0 path offset\n", __func__);
return;
}
ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev);
if (ret) {
printf("Cannot find EEPROM!\n");
return;
}
ret = i2c_eeprom_read(dev, 0xb0, enetaddr, 0x6);
if (ret) {
printf("Error reading configuration EEPROM!\n");
return;
}
if (is_valid_ethaddr(enetaddr))
eth_env_set_enetaddr("ethaddr", enetaddr);
}
#endif

18
board/data_modul/common/common.h Normal file
View File

@ -0,0 +1,18 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2022 Marek Vasut <marex@denx.de>
*/
#ifndef __EDM_SBC_COMMON_H__
#define __EDM_SBC_COMMON_H__
#include <asm/arch/ddr.h>
#include <asm/mach-imx/iomux-v3.h>
u8 dmo_get_memcfg(void);
void dmo_board_init_f(const iomux_v3_cfg_t wdog_pad,
struct dram_timing_info *dram_timing_info[8]);
void dmo_setup_boot_device(void);
void dmo_setup_mac_address(void);
#endif /* __EDM_SBC_COMMON_H__ */

2
board/data_modul/imx8mm_edm_sbc/Makefile
View File

@ -10,4 +10,4 @@ else
obj-y += imx8mm_data_modul_edm_sbc.o
endif
obj-y += common.o
obj-y += ../common/common.o

37
board/data_modul/imx8mm_edm_sbc/common.c
View File

@ -1,37 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2022 Marek Vasut <marex@denx.de>
*/
#include <common.h>
#include <asm/io.h>
#include <asm-generic/gpio.h>
#include "lpddr4_timing.h"
DECLARE_GLOBAL_DATA_PTR;
u8 dmo_get_memcfg(void)
{
struct gpio_desc gpio[4];
u8 memcfg = 0;
ofnode node;
int i, ret;
node = ofnode_path("/config");
if (!ofnode_valid(node)) {
printf("%s: no /config node?\n", __func__);
return BIT(2) | BIT(0);
}
ret = gpio_request_list_by_name_nodev(node,
"dmo,ram-coding-gpios",
gpio, ARRAY_SIZE(gpio),
GPIOD_IS_IN);
for (i = 0; i < ret; i++)
memcfg |= !!dm_gpio_get_value(&(gpio[i])) << i;
gpio_free_list_nodev(gpio, ret);
return memcfg;
}

72
board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c
View File

@ -5,82 +5,16 @@
#include <common.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
#include <asm/mach-imx/boot_mode.h>
#include <dm.h>
#include <dm/device-internal.h>
#include <i2c_eeprom.h>
#include <malloc.h>
#include <net.h>
#include <spl.h>
#include "lpddr4_timing.h"
#include "../common/common.h"
DECLARE_GLOBAL_DATA_PTR;
int mach_cpu_init(void)
{
icache_enable();
return 0;
}
int board_phys_sdram_size(phys_size_t *size)
{
u8 memcfg = dmo_get_memcfg();
*size = (4ULL >> ((memcfg >> 1) & 0x3)) * SZ_1G;
return 0;
}
static void setup_mac_address(void)
{
unsigned char enetaddr[6];
struct udevice *dev;
int off, ret;
ret = eth_env_get_enetaddr("ethaddr", enetaddr);
if (ret) /* ethaddr is already set */
return;
off = fdt_path_offset(gd->fdt_blob, "eeprom0");
if (off < 0) {
printf("%s: No eeprom0 path offset\n", __func__);
return;
}
ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev);
if (ret) {
printf("Cannot find EEPROM!\n");
return;
}
ret = i2c_eeprom_read(dev, 0xb0, enetaddr, 0x6);
if (ret) {
printf("Error reading configuration EEPROM!\n");
return;
}
if (is_valid_ethaddr(enetaddr))
eth_env_set_enetaddr("ethaddr", enetaddr);
}
static void setup_boot_device(void)
{
int boot_device = get_boot_device();
char *devnum;
devnum = env_get("devnum");
if (devnum) /* devnum is already set */
return;
if (boot_device == MMC3_BOOT) /* eMMC */
env_set_ulong("devnum", 0);
else
env_set_ulong("devnum", 1);
}
int board_init(void)
{
return 0;
@ -91,8 +25,8 @@ int board_late_init(void)
struct udevice *dev;
int ret;
setup_boot_device();
setup_mac_address();
dmo_setup_boot_device();
dmo_setup_mac_address();
ret = uclass_get_device_by_name(UCLASS_MISC, "usb-hub@2c", &dev);
if (ret)

2
board/data_modul/imx8mm_edm_sbc/lpddr4_timing.h
View File

@ -9,6 +9,4 @@
extern struct dram_timing_info dmo_imx8mm_sbc_dram_timing_16_32;
extern struct dram_timing_info dmo_imx8mm_sbc_dram_timing_32_32;
u8 dmo_get_memcfg(void);
#endif /* __LPDDR4_TIMING_H__ */

81
board/data_modul/imx8mm_edm_sbc/spl.c
View File

@ -26,24 +26,11 @@
#include "lpddr4_timing.h"
#include "../common/common.h"
DECLARE_GLOBAL_DATA_PTR;
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
static const iomux_v3_cfg_t wdog_pads[] = {
IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
static void data_modul_imx8mm_edm_sbc_early_init_f(void)
{
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
set_wdog_reset(wdog);
}
static int data_modul_imx8mm_edm_sbc_board_power_init(void)
int data_modul_imx_edm_sbc_board_power_init(void)
{
struct udevice *dev;
int ret;
@ -105,67 +92,7 @@ static struct dram_timing_info *dram_timing_info[8] = {
NULL, /* INVALID */
};
static void spl_dram_init(void)
{
u8 memcfg = dmo_get_memcfg();
int i;
printf("DDR: %d GiB x%d [0x%x]\n",
/* 0..4 GiB, 1..2 GiB, 0..1 GiB */
4 >> ((memcfg >> 1) & 0x3),
/* 0..x32, 1..x16 */
32 >> (memcfg & BIT(0)),
memcfg);
if (!dram_timing_info[memcfg]) {
printf("Unsupported DRAM strapping, trying lowest supported. MEMCFG=0x%x\n",
memcfg);
for (i = ARRAY_SIZE(dram_timing_info) - 1; i >= 0; i--)
if (dram_timing_info[i]) /* Configuration found */
break;
}
ddr_init(dram_timing_info[memcfg]);
}
void board_init_f(ulong dummy)
{
struct udevice *dev;
int ret;
icache_enable();
arch_cpu_init();
init_uart_clk(2);
data_modul_imx8mm_edm_sbc_early_init_f();
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
ret = spl_early_init();
if (ret) {
debug("spl_early_init() failed: %d\n", ret);
hang();
}
preloader_console_init();
ret = uclass_get_device_by_name(UCLASS_CLK,
"clock-controller@30380000",
&dev);
if (ret < 0) {
printf("Failed to find clock node. Check device tree\n");
hang();
}
enable_tzc380();
data_modul_imx8mm_edm_sbc_board_power_init();
/* DDR initialization */
spl_dram_init();
board_init_r(NULL, 0);
dmo_board_init_f(IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B, dram_timing_info);
}

3
board/dhelectronics/dh_imx8mp/spl.c
View File

@ -88,9 +88,6 @@ static int dh_imx8mp_board_power_init(void)
/* To avoid timing risk from SoC to ARM, increase VDD_ARM to OD voltage 0.95V */
pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1c);
/* Set WDOG_B_CFG to cold reset. */
pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1);
/* Set LDO4 and CONFIG2 to enable the I2C level translator. */
pmic_reg_write(dev, PCA9450_LDO4CTRL, 0x59);
pmic_reg_write(dev, PCA9450_CONFIG2, 0x1);

20
board/engicam/common/spl.c
View File

@ -26,20 +26,6 @@
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/video.h>
#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
static iomux_v3_cfg_t const uart_pads[] = {
#ifdef CONFIG_MX6QDL
IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
#elif CONFIG_MX6UL
IOMUX_PADS(PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL)),
IOMUX_PADS(PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL)),
#endif
};
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
@ -421,12 +407,12 @@ void board_init_f(ulong dummy)
if (!(is_mx6ul()))
gpr_init();
/* iomux */
SETUP_IOMUX_PADS(uart_pads);
/* setup GP timer */
timer_init();
/* Enable device tree and early DM support*/
spl_early_init();
/* UART clocks enabled and gd valid - init serial console */
preloader_console_init();

3
board/engicam/imx8mp/spl.c
View File

@ -95,9 +95,6 @@ int power_init_board(void)
pmic_reg_write(p, PCA9450_BUCK6OUT, 0x18);
#endif
/* set WDOG_B_CFG to cold reset */
pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1);
return 0;
}
#endif

3
board/freescale/imx8mm_evk/spl.c
View File

@ -99,9 +99,6 @@ static int power_init_board(void)
/* set VDD_SNVS_0V8 from default 0.85V */
pmic_reg_write(dev, PCA9450_LDO2CTRL, 0xC0);
/* set WDOG_B_CFG to cold reset */
pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1);
return 0;
}

3
board/freescale/imx8mn_evk/spl.c
View File

@ -95,9 +95,6 @@ int power_init_board(void)
/* enable LDO4 to 1.2v */
pmic_reg_write(dev, PCA9450_LDO4CTRL, 0x44);
/* set WDOG_B_CFG to cold reset */
pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1);
return 0;
}
#endif

3
board/freescale/imx8mp_evk/spl.c
View File

@ -102,9 +102,6 @@ int power_init_board(void)
/* To avoid timing risk from SOC to ARM,increase VDD_ARM to OD voltage 0.95v */
pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C);
/* set WDOG_B_CFG to cold reset */
pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1);
return 0;
}
#endif

2
board/freescale/imx8qm_mek/README
View File

@ -12,7 +12,7 @@ Quick Start
Get and Build the ARM Trusted firmware
======================================
$ git clone https://source.codeaurora.org/external/imx/imx-atf
$ git clone https://github.com/nxp-imx/imx-atf
$ cd imx-atf/
$ git checkout origin/imx_4.14.78_1.0.0_ga -b imx_4.14.78_1.0.0_ga
$ make PLAT=imx8qm bl31

3
board/freescale/imx93_evk/spl.c
View File

@ -74,9 +74,6 @@ int power_init_board(void)
/* I2C_LT_EN*/
pmic_reg_write(dev, 0xa, 0x3);
/* set WDOG_B_CFG to cold reset */
pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1);
return 0;
}
#endif

18
board/freescale/mx6sllevk/mx6sllevk.c
View File

@ -24,10 +24,6 @@
DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
int dram_init(void)
{
gd->ram_size = imx_ddr_size();
@ -35,20 +31,10 @@ int dram_init(void)
return 0;
}
static iomux_v3_cfg_t const uart1_pads[] = {
MX6_PAD_UART1_TXD__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_UART1_RXD__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static iomux_v3_cfg_t const wdog_pads[] = {
MX6_PAD_WDOG_B__WDOG1_B | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static void setup_iomux_uart(void)
{
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
}
#ifdef CONFIG_DM_PMIC_PFUZE100
int power_init_board(void)
{
@ -58,7 +44,7 @@ int power_init_board(void)
u32 switch_num = 6;
u32 offset = PFUZE100_SW1CMODE;
ret = pmic_get("pfuze100@08", &dev);
ret = pmic_get("pfuze100@8", &dev);
if (ret == -ENODEV)
return 0;
@ -94,8 +80,6 @@ int power_init_board(void)
int board_early_init_f(void)
{
setup_iomux_uart();
return 0;
}

16
board/freescale/mx6sxsabreauto/mx6sxsabreauto.c
View File

@ -33,10 +33,6 @@
DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
PAD_CTL_SPEED_HIGH | \
PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
@ -59,11 +55,6 @@ int dram_init(void)
return 0;
}
static iomux_v3_cfg_t const uart1_pads[] = {
MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static iomux_v3_cfg_t const fec2_pads[] = {
MX6_PAD_ENET1_MDC__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET1_MDIO__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
@ -81,11 +72,6 @@ static iomux_v3_cfg_t const fec2_pads[] = {
MX6_PAD_RGMII2_TXC__ENET2_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
};
static void setup_iomux_uart(void)
{
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
}
static int setup_fec(void)
{
struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
@ -216,8 +202,6 @@ int board_ehci_hcd_init(int port)
int board_early_init_f(void)
{
setup_iomux_uart();
return 0;
}

16
board/freescale/mx6ullevk/mx6ullevk.c
View File

@ -24,10 +24,6 @@
DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
int dram_init(void)
{
gd->ram_size = imx_ddr_size();
@ -35,16 +31,6 @@ int dram_init(void)
return 0;
}
static iomux_v3_cfg_t const uart1_pads[] = {
MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static void setup_iomux_uart(void)
{
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
}
int board_mmc_get_env_dev(int devno)
{
return devno;
@ -57,8 +43,6 @@ int mmc_map_to_kernel_blk(int devno)
int board_early_init_f(void)
{
setup_iomux_uart();
return 0;
}

2
board/gateworks/venice/README
View File

@ -10,7 +10,7 @@ Quick Start
Get and Build the ARM Trusted firmware
======================================
$ git clone https://source.codeaurora.org/external/imx/imx-atf
$ git clone https://github.com/nxp-imx/imx-atf
$ git checkout imx_5.4.47_2.2.0
$ make PLAT=imx8mm CROSS_COMPILE=aarch64-linux-gnu- bl31
$ cp build/imx8mm/release/bl31.bin .

42
board/gateworks/venice/spl.c
View File

@ -16,10 +16,12 @@
#include <asm/arch/imx8mp_pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/arch/ddr.h>
#include <asm-generic/gpio.h>
#include <dm/uclass.h>
#include <dm/device.h>
#include <dm/pinctrl.h>
#include <linux/delay.h>
#include <power/bd71837.h>
#include <power/mp5416.h>
@ -165,9 +167,6 @@ static int power_init_board(void)
/* Kernel uses OD/OD freq for SOC */
/* To avoid timing risk from SOC to ARM, increase VDD_ARM to OD voltage 0.95v */
dm_i2c_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1C);
/* set WDOG_B_CFG to cold reset */
dm_i2c_reg_write(dev, PCA9450_RESET_CTRL, 0xA1);
}
else if ((!strncmp(model, "GW7901", 6)) ||
@ -218,8 +217,8 @@ static int power_init_board(void)
void board_init_f(ulong dummy)
{
struct udevice *dev;
int ret;
struct udevice *bus, *dev;
int i, ret;
int dram_sz;
arch_cpu_init();
@ -250,19 +249,28 @@ void board_init_f(ulong dummy)
*
* On a board with a missing/depleted backup battery for GSC, the
* board may be ready to probe the GSC before its firmware is
* running. We will wait here indefinately for the GSC EEPROM.
* running. Wait here for 50ms for the GSC firmware to let go of
* the SCL/SDA lines to avoid the i2c driver spamming
* 'Arbitration lost' I2C errors
*/
#ifdef CONFIG_IMX8MN
/*
* IMX8MN boots quicker than IMX8MM and exposes issue
* where because GSC I2C state machine isn't running and its
* SCL/SDA are driven low the I2C driver spams 'Arbitration lost'
* I2C errors.
*
* TODO: Put a loop here that somehow waits for I2C CLK/DAT to be high
*/
mdelay(50);
#endif
if (!uclass_get_device_by_seq(UCLASS_I2C, 0, &bus)) {
if (!pinctrl_select_state(bus, "gpio")) {
struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
struct gpio_desc *scl_gpio = &i2c_bus->scl_gpio;
struct gpio_desc *sda_gpio = &i2c_bus->sda_gpio;
dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN);
dm_gpio_set_dir_flags(sda_gpio, GPIOD_IS_IN);
for (i = 0; i < 5; i++) {
if (dm_gpio_get_value(scl_gpio) &&
dm_gpio_get_value(sda_gpio))
break;
mdelay(10);
}
pinctrl_select_state(bus, "default");
}
}
/* Wait indefiniately until the GSC probes */
while (1) {
if (!uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(gsc), &dev))
break;

2
board/google/imx8mq_phanbell/README
View File

@ -10,7 +10,7 @@ Quick Start
Get and Build the ARM Trusted firmware
======================================
Note: srctree is U-Boot source directory
Get ATF from: https://source.codeaurora.org/external/imx/imx-atf
Get ATF from: https://github.com/nxp-imx/imx-atf
branch: imx_4.19.35_1.0.0
$ make PLAT=imx8mq bl31
$ cp build/imx8mq/release/bl31.bin $(builddir)

3
board/kontron/sl-mx8mm/spl.c
View File

@ -193,9 +193,6 @@ static int power_init_board(void)
/* set VDD_SNVS_0V8 from default 0.85V to 0.8V */
pmic_reg_write(dev, PCA9450_LDO2CTRL, 0xC0);
/* set WDOG_B_CFG to cold reset */
pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1);
return 0;
}

2
board/ronetix/imx8mq-cm/README
View File

@ -9,7 +9,7 @@ Quick Start
Get and Build the ARM Trusted firmware
======================================
$ git clone https://source.codeaurora.org/external/imx/imx-atf
$ git clone https://github.com/nxp-imx/imx-atf
$ cd imx-atf
$ git checkout imx_4.19.35_1.0.0
$ make PLAT=imx8mq bl31

70
board/technexion/pico-imx7d/pico-imx7d.c
View File

@ -13,10 +13,8 @@
#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/io.h>
#include <common.h>
#include <i2c.h>
#include <miiphy.h>
#include <power/pmic.h>
#include <power/pfuze3000_pmic.h>
@ -27,27 +25,6 @@ DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
#define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)
#ifdef CONFIG_SYS_I2C_MXC
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
/* I2C4 for PMIC */
static struct i2c_pads_info i2c_pad_info4 = {
.scl = {
.i2c_mode = MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL | PC,
.gpio_mode = MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 | PC,
.gp = IMX_GPIO_NR(6, 16),
},
.sda = {
.i2c_mode = MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA | PC,
.gpio_mode = MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 | PC,
.gp = IMX_GPIO_NR(6, 17),
},
};
#endif
int dram_init(void)
{
gd->ram_size = imx_ddr_size();
@ -60,50 +37,43 @@ int dram_init(void)
return 0;
}
#if CONFIG_IS_ENABLED(POWER_LEGACY)
#define I2C_PMIC 3
#if CONFIG_IS_ENABLED(DM_PMIC)
int power_init_board(void)
{
struct pmic *p;
struct udevice *dev;
int reg, rev_id;
int ret;
unsigned int reg, rev_id;
ret = power_pfuze3000_init(I2C_PMIC);
if (ret)
ret = pmic_get("pfuze3000@8", &dev);
if (ret == -ENODEV)
return 0;
if (ret != 0)
return ret;
p = pmic_get("PFUZE3000");
ret = pmic_probe(p);
if (ret) {
printf("Warning: Cannot find PMIC PFUZE3000\n");
printf("\tPower consumption is not optimized.\n");
return 0;
}
pmic_reg_read(p, PFUZE3000_DEVICEID, &reg);
pmic_reg_read(p, PFUZE3000_REVID, &rev_id);
printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
reg = pmic_reg_read(dev, PFUZE3000_DEVICEID);
rev_id = pmic_reg_read(dev, PFUZE3000_REVID);
printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
/* disable Low Power Mode during standby mode */
pmic_reg_read(p, PFUZE3000_LDOGCTL, &reg);
reg = pmic_reg_read(dev, PFUZE3000_LDOGCTL);
reg |= 0x1;
pmic_reg_write(p, PFUZE3000_LDOGCTL, reg);
pmic_reg_write(dev, PFUZE3000_LDOGCTL, reg);
/* SW1A/1B mode set to APS/APS */
reg = 0x8;
pmic_reg_write(p, PFUZE3000_SW1AMODE, reg);
pmic_reg_write(p, PFUZE3000_SW1BMODE, reg);
pmic_reg_write(dev, PFUZE3000_SW1AMODE, reg);
pmic_reg_write(dev, PFUZE3000_SW1BMODE, reg);
/* SW1A/1B standby voltage set to 1.025V */
reg = 0xd;
pmic_reg_write(p, PFUZE3000_SW1ASTBY, reg);
pmic_reg_write(p, PFUZE3000_SW1BSTBY, reg);
pmic_reg_write(dev, PFUZE3000_SW1ASTBY, reg);
pmic_reg_write(dev, PFUZE3000_SW1BSTBY, reg);
/* decrease SW1B normal voltage to 0.975V */
pmic_reg_read(p, PFUZE3000_SW1BVOLT, &reg);
reg = pmic_reg_read(dev, PFUZE3000_SW1BVOLT);
reg &= ~0x1f;
reg |= PFUZE3000_SW1AB_SETP(975);
pmic_reg_write(p, PFUZE3000_SW1BVOLT, reg);
pmic_reg_write(dev, PFUZE3000_SW1BVOLT, reg);
return 0;
}
@ -168,10 +138,6 @@ int board_early_init_f(void)
{
setup_iomux_uart();
#ifdef CONFIG_SYS_I2C_MXC
setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info4);
#endif
return 0;
}

30
board/technexion/pico-imx7d/spl.c
View File

@ -61,6 +61,8 @@ static struct ddrc ddrc_regs_val = {
.dramtmg0 = 0x09081109,
.addrmap0 = 0x0000001f,
.addrmap1 = 0x00080808,
.addrmap2 = 0x00000000,
.addrmap3 = 0x00000000,
.addrmap4 = 0x00000f0f,
.addrmap5 = 0x07070707,
.addrmap6 = 0x0f0f0707,
@ -100,16 +102,38 @@ static void gpr_init(void)
writel(0x4F400005, &gpr_regs->gpr[1]);
}
static bool is_1g(void)
/*
* Revision Detection
*
* GPIO1_12 GPIO1_13
* 0 0 1GB DDR3
* 0 1 2GB DDR3
* 1 0 512MB DDR3
*/
static int imx7d_pico_detect_board(void)
{
gpio_direction_input(IMX_GPIO_NR(1, 12));
return !gpio_get_value(IMX_GPIO_NR(1, 12));
gpio_direction_input(IMX_GPIO_NR(1, 13));
return gpio_get_value(IMX_GPIO_NR(1, 12)) << 1 |
gpio_get_value(IMX_GPIO_NR(1, 13));
}
static void ddr_init(void)
{
if (is_1g())
switch (imx7d_pico_detect_board()) {
case 0:
ddrc_regs_val.addrmap6 = 0x0f070707;
break;
case 1:
ddrc_regs_val.addrmap0 = 0x0000001f;
ddrc_regs_val.addrmap1 = 0x00181818;
ddrc_regs_val.addrmap4 = 0x00000f0f;
ddrc_regs_val.addrmap5 = 0x04040404;
ddrc_regs_val.addrmap6 = 0x04040404;
break;
}
mx7_dram_cfg(&ddrc_regs_val, &ddrc_mp_val, &ddr_phy_regs_val,
&calib_param);

3
board/toradex/apalis-imx8/Kconfig
View File

@ -12,6 +12,9 @@ config SYS_CONFIG_NAME
config TDX_CFG_BLOCK
default y
config TDX_CFG_BLOCK_2ND_ETHADDR
default y
config TDX_HAVE_MMC
default y

148
board/toradex/apalis-imx8/apalis-imx8.c
View File

@ -12,13 +12,16 @@
#include <asm/arch/imx8-pins.h>
#include <asm/arch/iomux.h>
#include <asm/arch/sci/sci.h>
#include <asm/arch/snvs_security_sc.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <command.h>
#include <env.h>
#include <errno.h>
#include <linux/libfdt.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/libfdt.h>
#include "../common/tdx-cfg-block.h"
@ -29,11 +32,41 @@ DECLARE_GLOBAL_DATA_PTR;
(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
#define PCB_VERS_DETECT ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
#define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
#define PCB_VERS_DEFAULT ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
(SC_PAD_28FDSOI_PS_PD << PADRING_PULL_SHIFT) | \
(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT))
#define TDX_USER_FUSE_BLOCK1_A 276
#define TDX_USER_FUSE_BLOCK1_B 277
#define TDX_USER_FUSE_BLOCK2_A 278
#define TDX_USER_FUSE_BLOCK2_B 279
enum pcb_rev_t {
PCB_VERSION_1_0,
PCB_VERSION_1_1
};
static iomux_cfg_t pcb_vers_detect[] = {
SC_P_MIPI_DSI0_GPIO0_00 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(PCB_VERS_DETECT),
SC_P_MIPI_DSI0_GPIO0_01 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(PCB_VERS_DETECT),
};
static iomux_cfg_t pcb_vers_default[] = {
SC_P_MIPI_DSI0_GPIO0_00 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(PCB_VERS_DEFAULT),
SC_P_MIPI_DSI0_GPIO0_01 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(PCB_VERS_DEFAULT),
};
static iomux_cfg_t uart1_pads[] = {
SC_P_UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
SC_P_UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
@ -137,12 +170,12 @@ void board_mem_get_layout(u64 *phys_sdram_1_start,
int board_early_init_f(void)
{
sc_pm_clock_rate_t rate = SC_80MHZ;
sc_err_t err = 0;
int ret;
/* Set UART1 clock root to 80 MHz and enable it */
err = sc_pm_setup_uart(SC_R_UART_1, rate);
if (err != SC_ERR_NONE)
return 0;
ret = sc_pm_setup_uart(SC_R_UART_1, rate);
if (ret)
return ret;
setup_iomux_uart();
@ -150,25 +183,30 @@ int board_early_init_f(void)
}
#if CONFIG_IS_ENABLED(DM_GPIO)
#define BKL1_GPIO IMX_GPIO_NR(1, 10)
static iomux_cfg_t board_gpios[] = {
SC_P_LVDS1_GPIO00 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL),
};
static void board_gpio_init(void)
{
/* TODO */
imx8_iomux_setup_multiple_pads(board_gpios, ARRAY_SIZE(board_gpios));
gpio_request(BKL1_GPIO, "BKL1_GPIO");
}
#else
static inline void board_gpio_init(void) {}
#endif
#if IS_ENABLED(CONFIG_FEC_MXC)
#include <miiphy.h>
int board_phy_config(struct phy_device *phydev)
/*
* Backlight off before OS handover
*/
void board_preboot_os(void)
{
if (phydev->drv->config)
phydev->drv->config(phydev);
return 0;
gpio_direction_output(BKL1_GPIO, 0);
}
#endif
int checkboard(void)
{
@ -180,10 +218,86 @@ int checkboard(void)
return 0;
}
static enum pcb_rev_t get_pcb_revision(void)
{
unsigned int pcb_vers = 0;
imx8_iomux_setup_multiple_pads(pcb_vers_detect,
ARRAY_SIZE(pcb_vers_detect));
gpio_request(IMX_GPIO_NR(1, 18),
"PCB version detection on PAD SC_P_MIPI_DSI0_GPIO0_00");
gpio_request(IMX_GPIO_NR(1, 19),
"PCB version detection on PAD SC_P_MIPI_DSI0_GPIO0_01");
gpio_direction_input(IMX_GPIO_NR(1, 18));
gpio_direction_input(IMX_GPIO_NR(1, 19));
udelay(1000);
pcb_vers = gpio_get_value(IMX_GPIO_NR(1, 18));
pcb_vers |= gpio_get_value(IMX_GPIO_NR(1, 19)) << 1;
/* Set muxing back to default values for saving energy */
imx8_iomux_setup_multiple_pads(pcb_vers_default,
ARRAY_SIZE(pcb_vers_default));
switch (pcb_vers) {
case 0b11:
return PCB_VERSION_1_0;
case 0b10:
return PCB_VERSION_1_1;
default:
printf("Unknown PCB version=0x%x, default to V1.1\n", pcb_vers);
return PCB_VERSION_1_1;
}
}
static void select_dt_from_module_version(void)
{
env_set("soc", "imx8qm");
env_set("variant", "-v1.1");
switch (tdx_hw_tag.prodid) {
/* Select Apalis iMX8QM device trees */
case APALIS_IMX8QM_IT:
case APALIS_IMX8QM_WIFI_BT_IT:
case APALIS_IMX8QM_8GB_WIFI_BT_IT:
if (get_pcb_revision() == PCB_VERSION_1_0)
env_set("variant", "");
break;
/* Select Apalis iMX8QP device trees */
case APALIS_IMX8QP_WIFI_BT:
case APALIS_IMX8QP:
env_set("soc", "imx8qp");
break;
default:
printf("Unknown Apalis iMX8 module\n");
return;
}
}
static int do_select_dt_from_module_version(struct cmd_tbl *cmdtp, int flag,
int argc, char * const argv[])
{
select_dt_from_module_version();
return 0;
}
U_BOOT_CMD(select_dt_from_module_version, CONFIG_SYS_MAXARGS, 1, do_select_dt_from_module_version,
"\n", " - select devicetree from module version"
);
int board_init(void)
{
board_gpio_init();
if (IS_ENABLED(CONFIG_IMX_SNVS_SEC_SC_AUTO)) {
int ret = snvs_security_sc_init();
if (ret)
return ret;
}
return 0;
}
@ -215,5 +329,9 @@ int board_late_init(void)
env_set("board_rev", "v1.0");
#endif
build_info();
select_dt_from_module_version();
return 0;
}

3
board/toradex/verdin-imx8mm/spl.c
View File

@ -92,9 +92,6 @@ int power_init_board(void)
/* increase VDD_DRAM to 0.975v for 1.5Ghz DDR */
pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x1c);
/* set WDOG_B_CFG to cold reset */
pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1);
pmic_reg_write(dev, PCA9450_CONFIG2, 0x1);
return 0;

3
board/toradex/verdin-imx8mp/spl.c
View File

@ -116,9 +116,6 @@ int power_init_board(void)
/* To avoid timing risk from SoC to ARM, increase VDD_ARM to OD voltage 0.95v */
pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1c);
/* set WDOG_B_CFG to cold reset */
pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1);
/* set LDO4 and CONFIG2 to enable the I2C level translator */
pmic_reg_write(p, PCA9450_LDO4CTRL, 0x59);
pmic_reg_write(p, PCA9450_CONFIG2, 0x1);

11
configs/apalis-imx8_defconfig
View File

@ -8,8 +8,11 @@ CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFDE00
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-apalis"
CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
CONFIG_TARGET_APALIS_IMX8=y
CONFIG_SYS_LOAD_ADDR=0x80280000
CONFIG_SYS_PROMPT="Apalis iMX8 # "
CONFIG_SYS_LOAD_ADDR=0x95400000
CONFIG_SYS_MEMTEST_START=0x88000000
CONFIG_SYS_MEMTEST_END=0x89000000
CONFIG_DISTRO_DEFAULTS=y
@ -19,6 +22,9 @@ CONFIG_REMAKE_ELF=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOOTDELAY=1
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile ${soc}-apalis${variant}-${fdt_board}.dtb"
CONFIG_LOG=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
@ -48,6 +54,8 @@ CONFIG_VERSION_VARIABLE=y
CONFIG_IP_DEFRAG=y
CONFIG_TFTP_BLOCKSIZE=4096
CONFIG_TFTP_TSIZE=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_ENV=y
CONFIG_USE_IPADDR=y
CONFIG_IPADDR="192.168.10.2"
CONFIG_USE_NETMASK=y
@ -81,4 +89,5 @@ CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
CONFIG_DM_THERMAL=y
CONFIG_IMX_SCU_THERMAL=y
CONFIG_OF_LIBFDT_OVERLAY=y
# CONFIG_EFI_LOADER is not set

1
configs/colibri-imx8x_defconfig
View File

@ -80,4 +80,5 @@ CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
CONFIG_DM_THERMAL=y
CONFIG_IMX_SCU_THERMAL=y
CONFIG_OF_LIBFDT_OVERLAY=y
# CONFIG_EFI_LOADER is not set

1
configs/imx6dl_icore_nand_defconfig
View File

@ -66,6 +66,7 @@ CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_IMX_THERMAL=y
CONFIG_VIDEO=y

1
configs/imx6q_icore_nand_defconfig
View File

@ -67,6 +67,7 @@ CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_IMX_THERMAL=y
CONFIG_VIDEO=y

1
configs/imx6qdl_icore_mipi_defconfig
View File

@ -74,5 +74,6 @@ CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_IMX_THERMAL=y

1
configs/imx6qdl_icore_mmc_defconfig
View File

@ -90,6 +90,7 @@ CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_IMX_THERMAL=y
CONFIG_VIDEO=y

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