From 6629e1590495a476c05ce113c2b1f9e3e0b11da3 Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Sat, 28 Jan 2023 17:04:04 +0100 Subject: [PATCH 01/87] arm: dts: imx8mn-u-boot: fix DDR3 only support In case the CONFIG_IMX8M_LPDDR4 and CONFIG_IMX8M_DDR4 options are both disabled (i. e. BSH boards), binmain fails because DDR4 bin files are missing. Fixes: 93c4c0e4dd1e75 ("arm: dts: imx8mn-u-boot: Create common imx8mn-u-boot.dtsi") Signed-off-by: Dario Binacchi Reviewed-by: Michael Trimarchi Reviewed-by: Fabio Estevam --- arch/arm/dts/imx8mn-u-boot.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/imx8mn-u-boot.dtsi b/arch/arm/dts/imx8mn-u-boot.dtsi index 95f45ad2522..ec53390afb3 100644 --- a/arch/arm/dts/imx8mn-u-boot.dtsi +++ b/arch/arm/dts/imx8mn-u-boot.dtsi @@ -105,10 +105,11 @@ align-end = <4>; }; +#if defined(CONFIG_IMX8M_LPDDR4) || defined(CONFIG_IMX8M_DDR4) ddr-2d-imem-fw { #ifdef CONFIG_IMX8M_LPDDR4 filename = "lpddr4_pmu_train_2d_imem.bin"; -#elif CONFIG_IMX8M_DDR4 +#else filename = "ddr4_imem_2d.bin"; #endif type = "blob-ext"; @@ -118,12 +119,13 @@ ddr-2d-dmem-fw { #ifdef CONFIG_IMX8M_LPDDR4 filename = "lpddr4_pmu_train_2d_dmem.bin"; -#elif CONFIG_IMX8M_DDR4 +#else filename = "ddr4_dmem_2d.bin"; #endif type = "blob-ext"; align-end = <4>; }; +#endif }; spl { From fe7b2b322ec49ab3c78494054f15e23ad5256fc9 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Mon, 16 Jan 2023 20:04:56 +0100 Subject: [PATCH 02/87] apalis-imx8: implement pcb version and soc variant handling Implement PCB version and SoC variant handling which automatically loads the correct device tree for the Linux kernel. Signed-off-by: Marcel Ziswiler Signed-off-by: Andrejs Cainikovs Signed-off-by: Francesco Dolcini Reviewed-by: Fabio Estevam --- board/toradex/apalis-imx8/apalis-imx8.c | 105 +++++++++++++++++++++++- configs/apalis-imx8_defconfig | 2 + include/configs/apalis-imx8.h | 3 +- 3 files changed, 107 insertions(+), 3 deletions(-) diff --git a/board/toradex/apalis-imx8/apalis-imx8.c b/board/toradex/apalis-imx8/apalis-imx8.c index 408198843fd..6f28367cf03 100644 --- a/board/toradex/apalis-imx8/apalis-imx8.c +++ b/board/toradex/apalis-imx8/apalis-imx8.c @@ -15,10 +15,12 @@ #include #include #include +#include #include #include -#include #include +#include +#include #include "../common/tdx-cfg-block.h" @@ -29,11 +31,41 @@ DECLARE_GLOBAL_DATA_PTR; (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) +#define PCB_VERS_DETECT ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define PCB_VERS_DEFAULT ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PD << PADRING_PULL_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT)) + #define TDX_USER_FUSE_BLOCK1_A 276 #define TDX_USER_FUSE_BLOCK1_B 277 #define TDX_USER_FUSE_BLOCK2_A 278 #define TDX_USER_FUSE_BLOCK2_B 279 +enum pcb_rev_t { + PCB_VERSION_1_0, + PCB_VERSION_1_1 +}; + +static iomux_cfg_t pcb_vers_detect[] = { + SC_P_MIPI_DSI0_GPIO0_00 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(PCB_VERS_DETECT), + SC_P_MIPI_DSI0_GPIO0_01 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(PCB_VERS_DETECT), +}; + +static iomux_cfg_t pcb_vers_default[] = { + SC_P_MIPI_DSI0_GPIO0_00 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(PCB_VERS_DEFAULT), + SC_P_MIPI_DSI0_GPIO0_01 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(PCB_VERS_DEFAULT), +}; + static iomux_cfg_t uart1_pads[] = { SC_P_UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), SC_P_UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), @@ -180,6 +212,75 @@ int checkboard(void) return 0; } +static enum pcb_rev_t get_pcb_revision(void) +{ + unsigned int pcb_vers = 0; + + imx8_iomux_setup_multiple_pads(pcb_vers_detect, + ARRAY_SIZE(pcb_vers_detect)); + + gpio_request(IMX_GPIO_NR(1, 18), + "PCB version detection on PAD SC_P_MIPI_DSI0_GPIO0_00"); + gpio_request(IMX_GPIO_NR(1, 19), + "PCB version detection on PAD SC_P_MIPI_DSI0_GPIO0_01"); + gpio_direction_input(IMX_GPIO_NR(1, 18)); + gpio_direction_input(IMX_GPIO_NR(1, 19)); + + udelay(1000); + + pcb_vers = gpio_get_value(IMX_GPIO_NR(1, 18)); + pcb_vers |= gpio_get_value(IMX_GPIO_NR(1, 19)) << 1; + + /* Set muxing back to default values for saving energy */ + imx8_iomux_setup_multiple_pads(pcb_vers_default, + ARRAY_SIZE(pcb_vers_default)); + + switch (pcb_vers) { + case 0b11: + return PCB_VERSION_1_0; + case 0b10: + return PCB_VERSION_1_1; + default: + printf("Unknown PCB version=0x%x, default to V1.1\n", pcb_vers); + return PCB_VERSION_1_1; + } +} + +static void select_dt_from_module_version(void) +{ + env_set("soc", "imx8qm"); + env_set("variant", "-v1.1"); + + switch (tdx_hw_tag.prodid) { + /* Select Apalis iMX8QM device trees */ + case APALIS_IMX8QM_IT: + case APALIS_IMX8QM_WIFI_BT_IT: + case APALIS_IMX8QM_8GB_WIFI_BT_IT: + if (get_pcb_revision() == PCB_VERSION_1_0) + env_set("variant", ""); + break; + /* Select Apalis iMX8QP device trees */ + case APALIS_IMX8QP_WIFI_BT: + case APALIS_IMX8QP: + env_set("soc", "imx8qp"); + break; + default: + printf("Unknown Apalis iMX8 module\n"); + return; + } +} + +static int do_select_dt_from_module_version(struct cmd_tbl *cmdtp, int flag, + int argc, char * const argv[]) +{ + select_dt_from_module_version(); + return 0; +} + +U_BOOT_CMD(select_dt_from_module_version, CONFIG_SYS_MAXARGS, 1, do_select_dt_from_module_version, + "\n", " - select devicetree from module version" +); + int board_init(void) { board_gpio_init(); @@ -215,5 +316,7 @@ int board_late_init(void) env_set("board_rev", "v1.0"); #endif + select_dt_from_module_version(); + return 0; } diff --git a/configs/apalis-imx8_defconfig b/configs/apalis-imx8_defconfig index 395202bc29f..de33b25cefa 100644 --- a/configs/apalis-imx8_defconfig +++ b/configs/apalis-imx8_defconfig @@ -19,6 +19,8 @@ CONFIG_REMAKE_ELF=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_SYSTEM_SETUP=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile ${soc}-apalis${variant}-${fdt_board}.dtb" CONFIG_LOG=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y diff --git a/include/configs/apalis-imx8.h b/include/configs/apalis-imx8.h index 73d8d245a96..a8b2b0774fe 100644 --- a/include/configs/apalis-imx8.h +++ b/include/configs/apalis-imx8.h @@ -38,8 +38,7 @@ "boot_script_dhcp=boot.scr\0" \ "console=ttyLP1 earlycon\0" \ "fdt_addr=0x83000000\0" \ - "fdt_file=fsl-imx8qm-apalis-eval.dtb\0" \ - "fdtfile=fsl-imx8qm-apalis-eval.dtb\0" \ + "fdt_board=eval\0" \ "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \ "initrd_addr=0x83800000\0" \ "initrd_high=0xffffffffffffffff\0" \ From 717783ecdcb19534f8d34baaf5cb2b9e415fdf23 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Mon, 16 Jan 2023 20:04:57 +0100 Subject: [PATCH 03/87] apalis-imx8: turn off lcd backlight before os handover U-Boot typically tears down the display controller before handing control over to Linux. On LCD displays disabling pixel clock leads to a fading out effect with vertical/horizontal lines. Make sure to disable back light GPIO Apalis BKL1 before booting Linux. Signed-off-by: Marcel Ziswiler Signed-off-by: Francesco Dolcini Reviewed-by: Fabio Estevam --- board/toradex/apalis-imx8/apalis-imx8.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/board/toradex/apalis-imx8/apalis-imx8.c b/board/toradex/apalis-imx8/apalis-imx8.c index 6f28367cf03..1622900bd1d 100644 --- a/board/toradex/apalis-imx8/apalis-imx8.c +++ b/board/toradex/apalis-imx8/apalis-imx8.c @@ -182,9 +182,18 @@ int board_early_init_f(void) } #if CONFIG_IS_ENABLED(DM_GPIO) + +#define BKL1_GPIO IMX_GPIO_NR(1, 10) + +static iomux_cfg_t board_gpios[] = { + SC_P_LVDS1_GPIO00 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), +}; + static void board_gpio_init(void) { - /* TODO */ + imx8_iomux_setup_multiple_pads(board_gpios, ARRAY_SIZE(board_gpios)); + + gpio_request(BKL1_GPIO, "BKL1_GPIO"); } #else static inline void board_gpio_init(void) {} @@ -202,6 +211,14 @@ int board_phy_config(struct phy_device *phydev) } #endif +/* + * Backlight off before OS handover + */ +void board_preboot_os(void) +{ + gpio_direction_output(BKL1_GPIO, 0); +} + int checkboard(void) { puts("Model: Toradex Apalis iMX8\n"); From 37630e0f86c4f85b0ded7169e047b37b989d5b27 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Mon, 16 Jan 2023 20:04:58 +0100 Subject: [PATCH 04/87] apalis-imx8: display build info Display build info with information about the version of SCFW, SECO and TF-A (ATF). Signed-off-by: Marcel Ziswiler Signed-off-by: Francesco Dolcini Reviewed-by: Fabio Estevam --- board/toradex/apalis-imx8/apalis-imx8.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/board/toradex/apalis-imx8/apalis-imx8.c b/board/toradex/apalis-imx8/apalis-imx8.c index 1622900bd1d..743d015b836 100644 --- a/board/toradex/apalis-imx8/apalis-imx8.c +++ b/board/toradex/apalis-imx8/apalis-imx8.c @@ -333,6 +333,8 @@ int board_late_init(void) env_set("board_rev", "v1.0"); #endif + build_info(); + select_dt_from_module_version(); return 0; From 1511ebf9f38d305392bd4898948a5a864420376c Mon Sep 17 00:00:00 2001 From: Igor Opaniuk Date: Mon, 16 Jan 2023 20:04:59 +0100 Subject: [PATCH 05/87] apalis-imx8: provide proper config_sys_prompt This provides correct system prompt for U-Boot console. Signed-off-by: Igor Opaniuk Signed-off-by: Marcel Ziswiler Signed-off-by: Francesco Dolcini Reviewed-by: Fabio Estevam --- configs/apalis-imx8_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/apalis-imx8_defconfig b/configs/apalis-imx8_defconfig index de33b25cefa..125cd7435e7 100644 --- a/configs/apalis-imx8_defconfig +++ b/configs/apalis-imx8_defconfig @@ -9,6 +9,7 @@ CONFIG_ENV_OFFSET=0xFFFFDE00 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-apalis" CONFIG_TARGET_APALIS_IMX8=y +CONFIG_SYS_PROMPT="Apalis iMX8 # " CONFIG_SYS_LOAD_ADDR=0x80280000 CONFIG_SYS_MEMTEST_START=0x88000000 CONFIG_SYS_MEMTEST_END=0x89000000 From 41eac82bbd8785975b2bb83742f3b87aec7c2259 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Mon, 16 Jan 2023 20:05:00 +0100 Subject: [PATCH 06/87] apalis-imx8: set bootdelay Set the boot delay to one second. Signed-off-by: Marcel Ziswiler Signed-off-by: Francesco Dolcini Reviewed-by: Fabio Estevam --- configs/apalis-imx8_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/apalis-imx8_defconfig b/configs/apalis-imx8_defconfig index 125cd7435e7..dba320ad3e8 100644 --- a/configs/apalis-imx8_defconfig +++ b/configs/apalis-imx8_defconfig @@ -20,6 +20,7 @@ CONFIG_REMAKE_ELF=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_SYSTEM_SETUP=y +CONFIG_BOOTDELAY=1 CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile ${soc}-apalis${variant}-${fdt_board}.dtb" CONFIG_LOG=y From a8f197dfd33cb01efe8bc2f3ab91e52f399bb056 Mon Sep 17 00:00:00 2001 From: Oleksandr Suvorov Date: Mon, 16 Jan 2023 20:05:01 +0100 Subject: [PATCH 07/87] apalis/colibri-imx8/8x: add overlay support for i.mx 8/8x-based soms There is no "apply" command enabled for "fdt". Enable "apply" command to allow overlays to be applied. Signed-off-by: Oleksandr Suvorov Signed-off-by: Marcel Ziswiler Signed-off-by: Francesco Dolcini Reviewed-by: Fabio Estevam --- configs/apalis-imx8_defconfig | 1 + configs/colibri-imx8x_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/apalis-imx8_defconfig b/configs/apalis-imx8_defconfig index dba320ad3e8..72bc4fd847b 100644 --- a/configs/apalis-imx8_defconfig +++ b/configs/apalis-imx8_defconfig @@ -85,4 +85,5 @@ CONFIG_DM_SERIAL=y CONFIG_FSL_LPUART=y CONFIG_DM_THERMAL=y CONFIG_IMX_SCU_THERMAL=y +CONFIG_OF_LIBFDT_OVERLAY=y # CONFIG_EFI_LOADER is not set diff --git a/configs/colibri-imx8x_defconfig b/configs/colibri-imx8x_defconfig index e4c418958b2..83f39996b1a 100644 --- a/configs/colibri-imx8x_defconfig +++ b/configs/colibri-imx8x_defconfig @@ -80,4 +80,5 @@ CONFIG_DM_SERIAL=y CONFIG_FSL_LPUART=y CONFIG_DM_THERMAL=y CONFIG_IMX_SCU_THERMAL=y +CONFIG_OF_LIBFDT_OVERLAY=y # CONFIG_EFI_LOADER is not set From 73b8c05221aae5c0fac978909bf263d77673754e Mon Sep 17 00:00:00 2001 From: Oleksandr Suvorov Date: Mon, 16 Jan 2023 20:05:02 +0100 Subject: [PATCH 08/87] apalis/colibri-imx8/8x: remove global variable script The distroboot script system scans boot_scripts variable and try to find and use to boot each script name mentioned there. Setting global variable "script" breaks this general mechanism of searching and running a distro boot script. Remove global variables "script" to fix working the general distro boot script mechanism. Signed-off-by: Oleksandr Suvorov Signed-off-by: Marcel Ziswiler Signed-off-by: Francesco Dolcini Reviewed-by: Fabio Estevam --- include/configs/apalis-imx8.h | 1 - include/configs/colibri-imx8x.h | 1 - 2 files changed, 2 deletions(-) diff --git a/include/configs/apalis-imx8.h b/include/configs/apalis-imx8.h index a8b2b0774fe..df431261306 100644 --- a/include/configs/apalis-imx8.h +++ b/include/configs/apalis-imx8.h @@ -47,7 +47,6 @@ "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ "mmcpart=1\0" \ "panel=NULL\0" \ - "script=boot.scr\0" \ "update_uboot=askenv confirm Did you load u-boot-dtb.imx (y/N)?; " \ "if test \"$confirm\" = \"y\"; then " \ "setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \ diff --git a/include/configs/colibri-imx8x.h b/include/configs/colibri-imx8x.h index 2de116c59da..3ec36aa773e 100644 --- a/include/configs/colibri-imx8x.h +++ b/include/configs/colibri-imx8x.h @@ -77,7 +77,6 @@ "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ "mmcpart=1\0" \ "panel=NULL\0" \ - "script=boot.scr\0" \ "update_uboot=askenv confirm Did you load u-boot-dtb.imx (y/N)?; " \ "if test \"$confirm\" = \"y\"; then " \ "setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \ From 2540965f69a29c66fc7ecdfb12efd6b923632735 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Mon, 16 Jan 2023 20:05:03 +0100 Subject: [PATCH 09/87] apalis-imx8: enable environment bootcount limit Enable optional environment bootcount limit functionality. Signed-off-by: Marcel Ziswiler Signed-off-by: Francesco Dolcini Reviewed-by: Fabio Estevam --- configs/apalis-imx8_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/apalis-imx8_defconfig b/configs/apalis-imx8_defconfig index 72bc4fd847b..b562e90af66 100644 --- a/configs/apalis-imx8_defconfig +++ b/configs/apalis-imx8_defconfig @@ -52,6 +52,8 @@ CONFIG_VERSION_VARIABLE=y CONFIG_IP_DEFRAG=y CONFIG_TFTP_BLOCKSIZE=4096 CONFIG_TFTP_TSIZE=y +CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_BOOTCOUNT_ENV=y CONFIG_USE_IPADDR=y CONFIG_IPADDR="192.168.10.2" CONFIG_USE_NETMASK=y From b3d41fb8aea8069a8a0dedf6072cb658dc591015 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Mon, 16 Jan 2023 20:05:06 +0100 Subject: [PATCH 10/87] apalis-imx8: introduce setup setting setupargs Introduce setup setting setupargs and move earlycon there. Signed-off-by: Marcel Ziswiler Signed-off-by: Francesco Dolcini Reviewed-by: Fabio Estevam --- include/configs/apalis-imx8.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/include/configs/apalis-imx8.h b/include/configs/apalis-imx8.h index df431261306..4043a8c7d42 100644 --- a/include/configs/apalis-imx8.h +++ b/include/configs/apalis-imx8.h @@ -36,7 +36,7 @@ MEM_LAYOUT_ENV_SETTINGS \ "boot_file=Image\0" \ "boot_script_dhcp=boot.scr\0" \ - "console=ttyLP1 earlycon\0" \ + "console=ttyLP1\0" \ "fdt_addr=0x83000000\0" \ "fdt_board=eval\0" \ "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \ @@ -47,6 +47,8 @@ "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ "mmcpart=1\0" \ "panel=NULL\0" \ + "setup=setenv setupargs console=tty1 console=${console},${baudrate} " \ + "consoleblank=0 earlycon\0" \ "update_uboot=askenv confirm Did you load u-boot-dtb.imx (y/N)?; " \ "if test \"$confirm\" = \"y\"; then " \ "setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \ From 63b6193f3f9dc0ce73466a6c412563d91d55906c Mon Sep 17 00:00:00 2001 From: Philippe Schenker Date: Mon, 16 Jan 2023 20:05:10 +0100 Subject: [PATCH 11/87] board: apalis-imx8: get rid of sc_err_t type sc_pm_setup_uart() returns int, not sc_err_t. Signed-off-by: Philippe Schenker Signed-off-by: Francesco Dolcini Reviewed-by: Fabio Estevam --- board/toradex/apalis-imx8/apalis-imx8.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/board/toradex/apalis-imx8/apalis-imx8.c b/board/toradex/apalis-imx8/apalis-imx8.c index 743d015b836..43456e8af99 100644 --- a/board/toradex/apalis-imx8/apalis-imx8.c +++ b/board/toradex/apalis-imx8/apalis-imx8.c @@ -169,12 +169,12 @@ void board_mem_get_layout(u64 *phys_sdram_1_start, int board_early_init_f(void) { sc_pm_clock_rate_t rate = SC_80MHZ; - sc_err_t err = 0; + int ret; /* Set UART1 clock root to 80 MHz and enable it */ - err = sc_pm_setup_uart(SC_R_UART_1, rate); - if (err != SC_ERR_NONE) - return 0; + ret = sc_pm_setup_uart(SC_R_UART_1, rate); + if (ret) + return ret; setup_iomux_uart(); From 9607d8b17dc3f583a137a238afc2a5ffc8f82674 Mon Sep 17 00:00:00 2001 From: Andrejs Cainikovs Date: Mon, 16 Jan 2023 20:05:11 +0100 Subject: [PATCH 12/87] board: apalis-imx8: remove board_phy_config duplicate Remove a duplicate of weak board_phy_config() implementation in drivers/net/phy/phy.c. Signed-off-by: Andrejs Cainikovs Signed-off-by: Francesco Dolcini Reviewed-by: Fabio Estevam --- board/toradex/apalis-imx8/apalis-imx8.c | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/board/toradex/apalis-imx8/apalis-imx8.c b/board/toradex/apalis-imx8/apalis-imx8.c index 43456e8af99..ad0986eebfc 100644 --- a/board/toradex/apalis-imx8/apalis-imx8.c +++ b/board/toradex/apalis-imx8/apalis-imx8.c @@ -199,18 +199,6 @@ static void board_gpio_init(void) static inline void board_gpio_init(void) {} #endif -#if IS_ENABLED(CONFIG_FEC_MXC) -#include - -int board_phy_config(struct phy_device *phydev) -{ - if (phydev->drv->config) - phydev->drv->config(phydev); - - return 0; -} -#endif - /* * Backlight off before OS handover */ From 382e89ca40f195810d061c3235578e538fef51f9 Mon Sep 17 00:00:00 2001 From: Andrejs Cainikovs Date: Mon, 16 Jan 2023 20:05:12 +0100 Subject: [PATCH 13/87] board: apalis-imx8: initialize snvs Initialize Secure Non-Volatile Storage, aka SNVS. Signed-off-by: Andrejs Cainikovs Signed-off-by: Francesco Dolcini Reviewed-by: Fabio Estevam --- board/toradex/apalis-imx8/apalis-imx8.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/board/toradex/apalis-imx8/apalis-imx8.c b/board/toradex/apalis-imx8/apalis-imx8.c index ad0986eebfc..6b43b587007 100644 --- a/board/toradex/apalis-imx8/apalis-imx8.c +++ b/board/toradex/apalis-imx8/apalis-imx8.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -290,6 +291,13 @@ int board_init(void) { board_gpio_init(); + if (IS_ENABLED(CONFIG_IMX_SNVS_SEC_SC_AUTO)) { + int ret = snvs_security_sc_init(); + + if (ret) + return ret; + } + return 0; } From 352c4023979e834ca98bba69121d3b14e97bc5d7 Mon Sep 17 00:00:00 2001 From: Andrejs Cainikovs Date: Mon, 16 Jan 2023 20:05:15 +0100 Subject: [PATCH 14/87] apalis-imx8: add emmc/mmc card pinctrl's for different speeds Add pinctrl's for high speed eMMC and MMC cards. Signed-off-by: Andrejs Cainikovs Signed-off-by: Philippe Schenker Signed-off-by: Francesco Dolcini Reviewed-by: Fabio Estevam --- arch/arm/dts/fsl-imx8qm-apalis.dts | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/fsl-imx8qm-apalis.dts b/arch/arm/dts/fsl-imx8qm-apalis.dts index 0d8d3b3e8e8..bc7c75d3372 100644 --- a/arch/arm/dts/fsl-imx8qm-apalis.dts +++ b/arch/arm/dts/fsl-imx8qm-apalis.dts @@ -589,8 +589,10 @@ /* eMMC */ &usdhc1 { - pinctrl-names = "default"; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1>; bus-width = <8>; non-removable; status = "okay"; @@ -598,8 +600,10 @@ /* Apalis MMC1 */ &usdhc2 { - pinctrl-names = "default"; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_mmc1_cd>; + pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_mmc1_cd>; + pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_mmc1_cd>; bus-width = <8>; cd-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; /* Apalis MMC1_CD# */ status = "okay"; From 6e0ca0658ee318e143ceae143f19550745ad5c5a Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 23 Jan 2023 17:53:19 +0100 Subject: [PATCH 15/87] ddr: imx: Handle both 3733 and 3732 MTps rates The DDR calibration tool for i.MX8M currently produces 3732 MTps rate in lpddr4_timing.c , while the PHY code expects 3733 MTps rate. Support both variants to avoid surprises where the system fails to boot. Signed-off-by: Marek Vasut --- drivers/ddr/imx/phy/ddrphy_utils.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/ddr/imx/phy/ddrphy_utils.c b/drivers/ddr/imx/phy/ddrphy_utils.c index b852c870f90..6a8b6be42b2 100644 --- a/drivers/ddr/imx/phy/ddrphy_utils.c +++ b/drivers/ddr/imx/phy/ddrphy_utils.c @@ -112,6 +112,7 @@ void ddrphy_init_set_dfi_clk(unsigned int drate) dram_disable_bypass(); break; case 3733: + case 3732: dram_pll_init(MHZ(933)); dram_disable_bypass(); break; From d48827e323465bb0524a2b9ece2307bd34d77288 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Mon, 16 Jan 2023 20:05:04 +0100 Subject: [PATCH 16/87] apalis-imx8: remove obsolete sdhc related config defines Remove obsolete SDHC related config defines. Nowadays, all SDHC related hardware configuration comes from the device tree. Signed-off-by: Marcel Ziswiler Signed-off-by: Francesco Dolcini Reviewed-by: Fabio Estevam --- include/configs/apalis-imx8.h | 9 --------- 1 file changed, 9 deletions(-) diff --git a/include/configs/apalis-imx8.h b/include/configs/apalis-imx8.h index 4043a8c7d42..6b0541f1d84 100644 --- a/include/configs/apalis-imx8.h +++ b/include/configs/apalis-imx8.h @@ -9,10 +9,6 @@ #include #include -#define CFG_SYS_FSL_ESDHC_ADDR 0 -#define USDHC1_BASE_ADDR 0x5b010000 -#define USDHC2_BASE_ADDR 0x5b020000 - /* Networking */ #define MEM_LAYOUT_ENV_SETTINGS \ @@ -55,11 +51,6 @@ "${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x0 " \ "${blkcnt}; fi\0" -/* Link Definitions */ - -/* On Apalis iMX8 USDHC1 is eMMC, USDHC2 is 8-bit and USDHC3 is 4-bit MMC/SD */ -#define CFG_SYS_FSL_USDHC_NUM 3 - #define CFG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_2 0x880000000 From b2f2ee3e7ba5c9c7060648f1c19fb15b1deca547 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Mon, 16 Jan 2023 20:05:05 +0100 Subject: [PATCH 17/87] apalis-imx8: remove obsolete net usb start Remove obsolete net USB start. While at it also add a comment about enabling distro-boot. Signed-off-by: Marcel Ziswiler Signed-off-by: Francesco Dolcini Reviewed-by: Fabio Estevam --- include/configs/apalis-imx8.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/include/configs/apalis-imx8.h b/include/configs/apalis-imx8.h index 6b0541f1d84..5d1ee490fb0 100644 --- a/include/configs/apalis-imx8.h +++ b/include/configs/apalis-imx8.h @@ -17,14 +17,13 @@ "ramdisk_addr_r=0x94400000\0" \ "scriptaddr=0x87000000\0" +/* Enable Distro Boot */ #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 2) \ func(MMC, mmc, 0) \ func(DHCP, dhcp, na) #include -#undef BOOTENV_RUN_NET_USB_START -#define BOOTENV_RUN_NET_USB_START "" /* Initial environment variables */ #define CFG_EXTRA_ENV_SETTINGS \ From 49db56852f01dcd1dc92127389b3ca16de664e8f Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Mon, 16 Jan 2023 20:05:07 +0100 Subject: [PATCH 18/87] apalis-imx8: drop obsolete environment variables Drop obsolete environment variables fdt_addr, finduuid, boot_file, mmcargs, mmcdev, mmcpart and panel. Signed-off-by: Marcel Ziswiler Signed-off-by: Andrejs Cainikovs Signed-off-by: Francesco Dolcini Reviewed-by: Fabio Estevam --- include/configs/apalis-imx8.h | 8 -------- 1 file changed, 8 deletions(-) diff --git a/include/configs/apalis-imx8.h b/include/configs/apalis-imx8.h index 5d1ee490fb0..a54e0185552 100644 --- a/include/configs/apalis-imx8.h +++ b/include/configs/apalis-imx8.h @@ -29,19 +29,11 @@ #define CFG_EXTRA_ENV_SETTINGS \ BOOTENV \ MEM_LAYOUT_ENV_SETTINGS \ - "boot_file=Image\0" \ "boot_script_dhcp=boot.scr\0" \ "console=ttyLP1\0" \ - "fdt_addr=0x83000000\0" \ "fdt_board=eval\0" \ - "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \ "initrd_addr=0x83800000\0" \ "initrd_high=0xffffffffffffffff\0" \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=PARTUUID=${uuid} rootwait " \ - "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ - "mmcpart=1\0" \ - "panel=NULL\0" \ "setup=setenv setupargs console=tty1 console=${console},${baudrate} " \ "consoleblank=0 earlycon\0" \ "update_uboot=askenv confirm Did you load u-boot-dtb.imx (y/N)?; " \ From 8930143e87c607af7430f871fa1c8e249e2fe6a4 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Mon, 16 Jan 2023 20:05:08 +0100 Subject: [PATCH 19/87] apalis-imx8: update update_uboot confirmation message Update update_uboot confirmation message. Signed-off-by: Marcel Ziswiler Signed-off-by: Francesco Dolcini Reviewed-by: Fabio Estevam --- include/configs/apalis-imx8.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/apalis-imx8.h b/include/configs/apalis-imx8.h index a54e0185552..0c37aa7e384 100644 --- a/include/configs/apalis-imx8.h +++ b/include/configs/apalis-imx8.h @@ -36,7 +36,7 @@ "initrd_high=0xffffffffffffffff\0" \ "setup=setenv setupargs console=tty1 console=${console},${baudrate} " \ "consoleblank=0 earlycon\0" \ - "update_uboot=askenv confirm Did you load u-boot-dtb.imx (y/N)?; " \ + "update_uboot=askenv confirm Did you load flash.bin resp. u-boot-dtb.imx (y/N)?; " \ "if test \"$confirm\" = \"y\"; then " \ "setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \ "${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x0 " \ From a9f1e35bedc4ed0ce62b3eceddfe8ffbef12a44f Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Mon, 16 Jan 2023 20:05:09 +0100 Subject: [PATCH 20/87] apalis-imx8: update env memory layout Update the distro config env memory layout for the Apalis iMX8 aka QuadMax: - kernel_comp_addr_r=0xf0000000 temporary area for uncompressing (ie FIT images or Image.gz booted using booti) - kernel_comp_size=0x08000000 - loadaddr=0x95400000 avoiding any reserved areas located before that - fdt_addr_r = loadaddr + 128MB - allows for 128MB kernel - scriptaddr = fdt_addr_r + 512KB - allows for 512KB fdt - ramdisk_addr_r = scriptaddr + 512KB - allows for 512KB script Basic idea of memory layout taken from commit fd5c7173ade4 ("imx8m{m,n}_venice: update env memory layout"). However, moved past any reserved areas to avoid any kind of conflicts. Note that for our regular BSP Layers and Reference Images for Yocto Project an updated distro boot script is required (see meta-toradex-bsp-common/recipes-bsp/u-boot/u-boot-distro-boot). Signed-off-by: Marcel Ziswiler Signed-off-by: Francesco Dolcini Reviewed-by: Fabio Estevam --- configs/apalis-imx8_defconfig | 2 +- include/configs/apalis-imx8.h | 10 ++++++---- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/configs/apalis-imx8_defconfig b/configs/apalis-imx8_defconfig index b562e90af66..d459e007319 100644 --- a/configs/apalis-imx8_defconfig +++ b/configs/apalis-imx8_defconfig @@ -10,7 +10,7 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-apalis" CONFIG_TARGET_APALIS_IMX8=y CONFIG_SYS_PROMPT="Apalis iMX8 # " -CONFIG_SYS_LOAD_ADDR=0x80280000 +CONFIG_SYS_LOAD_ADDR=0x95400000 CONFIG_SYS_MEMTEST_START=0x88000000 CONFIG_SYS_MEMTEST_END=0x89000000 CONFIG_DISTRO_DEFAULTS=y diff --git a/include/configs/apalis-imx8.h b/include/configs/apalis-imx8.h index 0c37aa7e384..9eedf36b41e 100644 --- a/include/configs/apalis-imx8.h +++ b/include/configs/apalis-imx8.h @@ -12,10 +12,12 @@ /* Networking */ #define MEM_LAYOUT_ENV_SETTINGS \ - "fdt_addr_r=0x84000000\0" \ - "kernel_addr_r=0x82000000\0" \ - "ramdisk_addr_r=0x94400000\0" \ - "scriptaddr=0x87000000\0" + "fdt_addr_r=0x9d400000\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "kernel_comp_addr_r=0xf0000000\0" \ + "kernel_comp_size=0x08000000\0" \ + "ramdisk_addr_r=0x9d500000\0" \ + "scriptaddr=0x9d480000\0" /* Enable Distro Boot */ #define BOOT_TARGET_DEVICES(func) \ From 242abc869387ca250149e225e3360277e7ac7836 Mon Sep 17 00:00:00 2001 From: Andrejs Cainikovs Date: Mon, 16 Jan 2023 20:05:13 +0100 Subject: [PATCH 21/87] apalis-imx8: set bootaux memory base and size Set i.MX auxiliary core memory base and size. Signed-off-by: Andrejs Cainikovs Signed-off-by: Francesco Dolcini Reviewed-by: Fabio Estevam --- configs/apalis-imx8_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/apalis-imx8_defconfig b/configs/apalis-imx8_defconfig index d459e007319..55f9e76dffa 100644 --- a/configs/apalis-imx8_defconfig +++ b/configs/apalis-imx8_defconfig @@ -8,6 +8,8 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xFFFFDE00 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-apalis" +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 CONFIG_TARGET_APALIS_IMX8=y CONFIG_SYS_PROMPT="Apalis iMX8 # " CONFIG_SYS_LOAD_ADDR=0x95400000 From baa7550c14156f9dda65e0c3267f35a0dfc3cf10 Mon Sep 17 00:00:00 2001 From: Andrejs Cainikovs Date: Mon, 16 Jan 2023 20:05:14 +0100 Subject: [PATCH 22/87] apalis-imx8: add M4 boot environment helpers Add M4 boot environment functions for reference. Signed-off-by: Andrejs Cainikovs Signed-off-by: Francesco Dolcini Reviewed-by: Fabio Estevam --- include/configs/apalis-imx8.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/include/configs/apalis-imx8.h b/include/configs/apalis-imx8.h index 9eedf36b41e..845705c86db 100644 --- a/include/configs/apalis-imx8.h +++ b/include/configs/apalis-imx8.h @@ -19,6 +19,15 @@ "ramdisk_addr_r=0x9d500000\0" \ "scriptaddr=0x9d480000\0" +/* Boot M4 */ +#define M4_BOOT_ENV \ + "m4_0_image=m4_0.bin\0" \ + "m4_1_image=m4_1.bin\0" \ + "loadm4image_0=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \ + "loadm4image_1=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_1_image}\0" \ + "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \ + "m4boot_1=run loadm4image_1; dcache flush; bootaux ${loadaddr} 1\0" \ + /* Enable Distro Boot */ #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ @@ -30,6 +39,7 @@ /* Initial environment variables */ #define CFG_EXTRA_ENV_SETTINGS \ BOOTENV \ + M4_BOOT_ENV \ MEM_LAYOUT_ENV_SETTINGS \ "boot_script_dhcp=boot.scr\0" \ "console=ttyLP1\0" \ From 507a70b1447ae389c614ac3d04ae853922935898 Mon Sep 17 00:00:00 2001 From: Mikhail Ilin Date: Tue, 22 Nov 2022 12:34:26 +0300 Subject: [PATCH 23/87] tools: imximage: Fix check array index The struct dcd_v1_t is initialized to MAX_HW_CFG_SIZE_V1 (60) structs 'dcd_type_addr_data_t', so the indexes to use on its elements are [0,59]. But on line 478, the variable 'length' can take on the value 60, which applies to array overflow: cd_v1->addr_data[length].type Thus, it is necessary to tighten the check on the 'size' variable on line 463. Fixes: 0b0c6af38738 ("Prepare v2020.01") Signed-off-by: Mikhail Ilin --- tools/imximage.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/imximage.c b/tools/imximage.c index 5c23fba3b12..354ee34c14a 100644 --- a/tools/imximage.c +++ b/tools/imximage.c @@ -460,7 +460,7 @@ static void print_hdr_v1(struct imx_header *imx_hdr) uint32_t size, length, ver; size = dcd_v1->preamble.length; - if (size > (MAX_HW_CFG_SIZE_V1 * sizeof(dcd_type_addr_data_t))) { + if (size >= (MAX_HW_CFG_SIZE_V1 * sizeof(dcd_type_addr_data_t))) { fprintf(stderr, "Error: Image corrupt DCD size %d exceed maximum %d\n", (uint32_t)(size / sizeof(dcd_type_addr_data_t)), From 9017785acd247c6ba60d0f0c0e9722201f0b184c Mon Sep 17 00:00:00 2001 From: Mikhail Ilin Date: Wed, 23 Nov 2022 13:48:44 +0300 Subject: [PATCH 24/87] tools: imx8mimage: Fix handle leak The handle "fd" was created in imx8mimage.c:178 by calling the "fopen" function and is lost in imx8mimage.c:210. Should close the 'fd' file descriptor before exiting the parse_cfg_file(char *name) function. Fixes: 6609c2663c9c ("tools: add i.MX8M image support") Signed-off-by: Mikhail Ilin --- tools/imx8mimage.c | 1 + 1 file changed, 1 insertion(+) diff --git a/tools/imx8mimage.c b/tools/imx8mimage.c index 35d0a92bfdf..3ca79d865aa 100644 --- a/tools/imx8mimage.c +++ b/tools/imx8mimage.c @@ -207,6 +207,7 @@ static uint32_t parse_cfg_file(char *name) } } + fclose(fd); return 0; } From f75e92f7f7bffe724dccd6769b37f95e0aa7842c Mon Sep 17 00:00:00 2001 From: Mikhail Ilin Date: Wed, 23 Nov 2022 13:59:49 +0300 Subject: [PATCH 25/87] tools: imx8image: Fix handle leak The handle "fd" was created in imx8image.c:249 by calling the "fopen" function and is lost in imx8image.c:282. Should close the 'fd' file descriptor before exiting the parse_cfg_file(image_t *param_stack, char *name) function. Fixes: a2b96ece5be1 ("tools: add i.MX8/8X image support") Signed-off-by: Mikhail Ilin Reviewed-by: Simon Glass --- tools/imx8image.c | 1 + 1 file changed, 1 insertion(+) diff --git a/tools/imx8image.c b/tools/imx8image.c index 01e14869114..395d5c64bdf 100644 --- a/tools/imx8image.c +++ b/tools/imx8image.c @@ -279,6 +279,7 @@ static uint32_t parse_cfg_file(image_t *param_stack, char *name) } } + fclose(fd); return 0; } From 910c7a881f5b64dc92d3ba9232ce59ae54fd6486 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 9 Dec 2022 20:35:46 +0100 Subject: [PATCH 26/87] pmic: pca9450: Make warm reset on WDOG_B assertion The default configuration of the PMIC behavior makes the PMIC power cycle most regulators on WDOG_B assertion. This power cycling causes the memory contents of OCRAM to be lost. Some systems neeeds some memory that survives reset and reboot, therefore this patch is created. The implementation is taken almost verbatim from Linux commit 2364a64d0673f ("regulator: pca9450: Make warm reset on WDOG_B assertion") Signed-off-by: Marek Vasut Reviewed-by: Fabio Estevam Reviewed-by: Peng Fan --- drivers/power/pmic/pca9450.c | 11 ++++++++++- include/power/pca9450.h | 4 ++++ 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/power/pmic/pca9450.c b/drivers/power/pmic/pca9450.c index a186edc08da..2427abfb7a5 100644 --- a/drivers/power/pmic/pca9450.c +++ b/drivers/power/pmic/pca9450.c @@ -86,6 +86,7 @@ static int pca9450_bind(struct udevice *dev) static int pca9450_probe(struct udevice *dev) { struct pca9450_priv *priv = dev_get_priv(dev); + unsigned int reset_ctrl; int ret = 0; if (CONFIG_IS_ENABLED(DM_GPIO) && CONFIG_IS_ENABLED(DM_REGULATOR_PCA9450)) { @@ -95,10 +96,18 @@ static int pca9450_probe(struct udevice *dev) if (IS_ERR(priv->sd_vsel_gpio)) { ret = PTR_ERR(priv->sd_vsel_gpio); dev_err(dev, "Failed to request SD_VSEL GPIO: %d\n", ret); + if (ret) + return ret; } } - return ret; + if (ofnode_read_bool(dev_ofnode(dev), "nxp,wdog_b-warm-reset")) + reset_ctrl = PCA9450_PMIC_RESET_WDOG_B_CFG_WARM; + else + reset_ctrl = PCA9450_PMIC_RESET_WDOG_B_CFG_COLD_LDO12; + + return pmic_clrsetbits(dev, PCA9450_RESET_CTRL, + PCA9450_PMIC_RESET_WDOG_B_CFG_MASK, reset_ctrl); } static struct dm_pmic_ops pca9450_ops = { diff --git a/include/power/pca9450.h b/include/power/pca9450.h index fa0405fcb87..6efecee96c8 100644 --- a/include/power/pca9450.h +++ b/include/power/pca9450.h @@ -67,4 +67,8 @@ enum { #define PCA9450_LDO34_MASK 0x1f #define PCA9450_LDO5_MASK 0x0f +#define PCA9450_PMIC_RESET_WDOG_B_CFG_MASK 0xc0 +#define PCA9450_PMIC_RESET_WDOG_B_CFG_WARM 0x40 +#define PCA9450_PMIC_RESET_WDOG_B_CFG_COLD_LDO12 0x80 + #endif From a20be24cd4854fb829384f9b45742f7f5d9046c8 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 9 Dec 2022 20:35:47 +0100 Subject: [PATCH 27/87] ARM: imx: Remove PMIC reset configuration from board files The PCA9450 reset configuration can now be performed by the PCA9450 PMIC driver itself, remove the hard-coded variant from board code and let the PMIC driver perform this task using one-liner: ``` $ sed -i '/set WDOG_B_CFG to cold reset/,+2 d' $(git grep -l PCA9450_RESET_CTRL.*0xA1 board/) ``` Venice and i.MX93 EVK required slight manual fix up. Signed-off-by: Marek Vasut Reviewed-by: Fabio Estevam Reviewed-by: Peng Fan --- board/advantech/imx8mp_rsb3720a1/spl.c | 3 --- board/dhelectronics/dh_imx8mp/spl.c | 3 --- board/engicam/imx8mp/spl.c | 3 --- board/freescale/imx8mm_evk/spl.c | 3 --- board/freescale/imx8mn_evk/spl.c | 3 --- board/freescale/imx8mp_evk/spl.c | 3 --- board/freescale/imx93_evk/spl.c | 3 --- board/gateworks/venice/spl.c | 3 --- board/kontron/sl-mx8mm/spl.c | 3 --- board/toradex/verdin-imx8mm/spl.c | 3 --- board/toradex/verdin-imx8mp/spl.c | 3 --- 11 files changed, 33 deletions(-) diff --git a/board/advantech/imx8mp_rsb3720a1/spl.c b/board/advantech/imx8mp_rsb3720a1/spl.c index 6cc8c23ecf8..f4257bc993d 100644 --- a/board/advantech/imx8mp_rsb3720a1/spl.c +++ b/board/advantech/imx8mp_rsb3720a1/spl.c @@ -209,9 +209,6 @@ int power_init_board(void) /* To avoid timing risk from SOC to ARM,increase VDD_ARM to OD voltage 0.95v */ pmic_reg_write(pdev, PCA9450_BUCK2OUT_DVS0, 0x1C); - /* set WDOG_B_CFG to cold reset */ - pmic_reg_write(pdev, PCA9450_RESET_CTRL, 0xA1); - /* Forced enable the I2C level translator*/ pmic_reg_write(pdev, PCA9450_CONFIG2, 0x03); diff --git a/board/dhelectronics/dh_imx8mp/spl.c b/board/dhelectronics/dh_imx8mp/spl.c index 312e4b96984..95de74556af 100644 --- a/board/dhelectronics/dh_imx8mp/spl.c +++ b/board/dhelectronics/dh_imx8mp/spl.c @@ -88,9 +88,6 @@ static int dh_imx8mp_board_power_init(void) /* To avoid timing risk from SoC to ARM, increase VDD_ARM to OD voltage 0.95V */ pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1c); - /* Set WDOG_B_CFG to cold reset. */ - pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1); - /* Set LDO4 and CONFIG2 to enable the I2C level translator. */ pmic_reg_write(dev, PCA9450_LDO4CTRL, 0x59); pmic_reg_write(dev, PCA9450_CONFIG2, 0x1); diff --git a/board/engicam/imx8mp/spl.c b/board/engicam/imx8mp/spl.c index 6a16d58ae5a..36b83aace39 100644 --- a/board/engicam/imx8mp/spl.c +++ b/board/engicam/imx8mp/spl.c @@ -95,9 +95,6 @@ int power_init_board(void) pmic_reg_write(p, PCA9450_BUCK6OUT, 0x18); #endif - /* set WDOG_B_CFG to cold reset */ - pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1); - return 0; } #endif diff --git a/board/freescale/imx8mm_evk/spl.c b/board/freescale/imx8mm_evk/spl.c index b5a2faf3a18..6e9513805cd 100644 --- a/board/freescale/imx8mm_evk/spl.c +++ b/board/freescale/imx8mm_evk/spl.c @@ -99,9 +99,6 @@ static int power_init_board(void) /* set VDD_SNVS_0V8 from default 0.85V */ pmic_reg_write(dev, PCA9450_LDO2CTRL, 0xC0); - /* set WDOG_B_CFG to cold reset */ - pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1); - return 0; } diff --git a/board/freescale/imx8mn_evk/spl.c b/board/freescale/imx8mn_evk/spl.c index 380abecd746..ec0378b5b76 100644 --- a/board/freescale/imx8mn_evk/spl.c +++ b/board/freescale/imx8mn_evk/spl.c @@ -95,9 +95,6 @@ int power_init_board(void) /* enable LDO4 to 1.2v */ pmic_reg_write(dev, PCA9450_LDO4CTRL, 0x44); - /* set WDOG_B_CFG to cold reset */ - pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1); - return 0; } #endif diff --git a/board/freescale/imx8mp_evk/spl.c b/board/freescale/imx8mp_evk/spl.c index f1b285417d0..246826a0d48 100644 --- a/board/freescale/imx8mp_evk/spl.c +++ b/board/freescale/imx8mp_evk/spl.c @@ -102,9 +102,6 @@ int power_init_board(void) /* To avoid timing risk from SOC to ARM,increase VDD_ARM to OD voltage 0.95v */ pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C); - /* set WDOG_B_CFG to cold reset */ - pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1); - return 0; } #endif diff --git a/board/freescale/imx93_evk/spl.c b/board/freescale/imx93_evk/spl.c index 38cfbac6ea6..1aa2977b409 100644 --- a/board/freescale/imx93_evk/spl.c +++ b/board/freescale/imx93_evk/spl.c @@ -74,9 +74,6 @@ int power_init_board(void) /* I2C_LT_EN*/ pmic_reg_write(dev, 0xa, 0x3); - - /* set WDOG_B_CFG to cold reset */ - pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1); return 0; } #endif diff --git a/board/gateworks/venice/spl.c b/board/gateworks/venice/spl.c index e06de8bb54c..60830766ca9 100644 --- a/board/gateworks/venice/spl.c +++ b/board/gateworks/venice/spl.c @@ -165,9 +165,6 @@ static int power_init_board(void) /* Kernel uses OD/OD freq for SOC */ /* To avoid timing risk from SOC to ARM, increase VDD_ARM to OD voltage 0.95v */ dm_i2c_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1C); - - /* set WDOG_B_CFG to cold reset */ - dm_i2c_reg_write(dev, PCA9450_RESET_CTRL, 0xA1); } else if ((!strncmp(model, "GW7901", 6)) || diff --git a/board/kontron/sl-mx8mm/spl.c b/board/kontron/sl-mx8mm/spl.c index 25ee925ceb0..3a919d0a9c3 100644 --- a/board/kontron/sl-mx8mm/spl.c +++ b/board/kontron/sl-mx8mm/spl.c @@ -193,9 +193,6 @@ static int power_init_board(void) /* set VDD_SNVS_0V8 from default 0.85V to 0.8V */ pmic_reg_write(dev, PCA9450_LDO2CTRL, 0xC0); - /* set WDOG_B_CFG to cold reset */ - pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1); - return 0; } diff --git a/board/toradex/verdin-imx8mm/spl.c b/board/toradex/verdin-imx8mm/spl.c index 210665bd6a9..9d54d60bb17 100644 --- a/board/toradex/verdin-imx8mm/spl.c +++ b/board/toradex/verdin-imx8mm/spl.c @@ -92,9 +92,6 @@ int power_init_board(void) /* increase VDD_DRAM to 0.975v for 1.5Ghz DDR */ pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x1c); - /* set WDOG_B_CFG to cold reset */ - pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1); - pmic_reg_write(dev, PCA9450_CONFIG2, 0x1); return 0; diff --git a/board/toradex/verdin-imx8mp/spl.c b/board/toradex/verdin-imx8mp/spl.c index 1838b464a0d..ea99e370850 100644 --- a/board/toradex/verdin-imx8mp/spl.c +++ b/board/toradex/verdin-imx8mp/spl.c @@ -116,9 +116,6 @@ int power_init_board(void) /* To avoid timing risk from SoC to ARM, increase VDD_ARM to OD voltage 0.95v */ pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1c); - /* set WDOG_B_CFG to cold reset */ - pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1); - /* set LDO4 and CONFIG2 to enable the I2C level translator */ pmic_reg_write(p, PCA9450_LDO4CTRL, 0x59); pmic_reg_write(p, PCA9450_CONFIG2, 0x1); From d51b38762dc679ba5a0bc8a69750d0a9ce6072fb Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 10 Dec 2022 02:29:52 +0100 Subject: [PATCH 28/87] ARM: imx: Reinstate decode ECSPI env location from i.MX8M ROMAPI tables Decode ECSPI boot device in env_get_location() from i.MX8M ROMAPI tables. This is necessary to correctly identify env is in SPI NOR when the system boots from SPI NOR attached to ECSPI. This reinstates change from commit: e26d0152d61 ("ARM: imx: Decode ECSPI env location from i.MX8M ROMAPI tables") which has been dropped in commit: b0a284a7c94 ("imx: move get_boot_device to common file") Fixes: b0a284a7c94 ("imx: move get_boot_device to common file") Signed-off-by: Marek Vasut Reviewed-by: Fabio Estevam --- arch/arm/mach-imx/romapi.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/mach-imx/romapi.c b/arch/arm/mach-imx/romapi.c index c8accdb04db..b49e7f80a28 100644 --- a/arch/arm/mach-imx/romapi.c +++ b/arch/arm/mach-imx/romapi.c @@ -66,6 +66,9 @@ enum boot_device get_boot_device(void) case BT_DEV_TYPE_FLEXSPINOR: boot_dev = QSPI_BOOT; break; + case BT_DEV_TYPE_SPI_NOR: + boot_dev = SPI_NOR_BOOT; + break; case BT_DEV_TYPE_USB: boot_dev = boot_instance + USB_BOOT; break; From d939c5e0f576551fb1a300e5aba6d3fabfbfbb6b Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sat, 10 Dec 2022 18:31:19 -0300 Subject: [PATCH 29/87] imx6qdl-sabresd: Pass mmc alias Originally, the mmc aliases node was present in imx6qdl-sabresd.dtsi. After the sync with Linux in commit d0399a46e7cd ("imx6dl/imx6qdl: synchronise device trees with linux"), the aliases node is gone as the upstream version does not have it. This causes a regression in which the SD card cannot be found anymore. Fix it by passing the alias node in the u-boot.dtsi file to restore the original behaviour where the SD card (esdhc3) was mapped to mmc1. Fixes: d0399a46e7cd ("imx6dl/imx6qdl: synchronise device trees with linux") Reported-by: Carlos Rafael Giani Signed-off-by: Fabio Estevam --- arch/arm/dts/imx6qdl-sabresd-u-boot.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/dts/imx6qdl-sabresd-u-boot.dtsi b/arch/arm/dts/imx6qdl-sabresd-u-boot.dtsi index 45f02b19c7e..cbb856fba3f 100644 --- a/arch/arm/dts/imx6qdl-sabresd-u-boot.dtsi +++ b/arch/arm/dts/imx6qdl-sabresd-u-boot.dtsi @@ -5,6 +5,12 @@ #include "imx6qdl-u-boot.dtsi" +/ { + aliases { + mmc1 = &usdhc3; + }; +}; + &usdhc3 { u-boot,dm-spl; }; From 868f754db86120bf3baf9697f017e740a98b2cf1 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 11 Dec 2022 21:16:11 +0100 Subject: [PATCH 30/87] ARM: imx: Enable LTO for Data Modul i.MX8M Mini eDM SBC Enable LTO to reduce the size of SPL. Signed-off-by: Marek Vasut --- configs/imx8mm_data_modul_edm_sbc_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/imx8mm_data_modul_edm_sbc_defconfig b/configs/imx8mm_data_modul_edm_sbc_defconfig index 3ccd26817ba..d9821885c3a 100644 --- a/configs/imx8mm_data_modul_edm_sbc_defconfig +++ b/configs/imx8mm_data_modul_edm_sbc_defconfig @@ -24,6 +24,7 @@ CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y CONFIG_ENV_OFFSET_REDUND=0xFFFC0000 CONFIG_IMX_BOOTAUX=y CONFIG_SYS_LOAD_ADDR=0x60000000 +CONFIG_LTO=y CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_FIT=y From 3bb15941ffb46323332f9dcc7810ff6f3e55a258 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 11 Dec 2022 21:16:36 +0100 Subject: [PATCH 31/87] ARM: imx: Drop board side icache enable on Data Modul i.MX8M Mini eDM SBC The icache is enabled in common architecture code since commit: 2fa763baa1c ("ARM: imx: Enable instruction cache early on on i.MX8M") Drop the board side duplicate code. Signed-off-by: Marek Vasut --- board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c b/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c index dc0883002c8..82856f7a08c 100644 --- a/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c +++ b/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c @@ -19,12 +19,6 @@ DECLARE_GLOBAL_DATA_PTR; -int mach_cpu_init(void) -{ - icache_enable(); - return 0; -} - int board_phys_sdram_size(phys_size_t *size) { u8 memcfg = dmo_get_memcfg(); From 5cae28c3b109c016c1527f857f584c1e962d075b Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 11 Dec 2022 21:17:14 +0100 Subject: [PATCH 32/87] ARM: imx: Factor common code out of Data Modul i.MX8M Mini eDM SBC Pull common.c into common subdirectory of the board file, since this code can be reused by other Data Modul SBCs. Drop the include of lpddr4_timing.h, which is unneeded. Signed-off-by: Marek Vasut --- board/data_modul/common/common.c | 194 ++++++++++++++++++ board/data_modul/common/common.h | 18 ++ board/data_modul/imx8mm_edm_sbc/Makefile | 2 +- board/data_modul/imx8mm_edm_sbc/common.c | 37 ---- .../imx8mm_data_modul_edm_sbc.c | 66 +----- .../data_modul/imx8mm_edm_sbc/lpddr4_timing.h | 2 - board/data_modul/imx8mm_edm_sbc/spl.c | 81 +------- 7 files changed, 220 insertions(+), 180 deletions(-) create mode 100644 board/data_modul/common/common.c create mode 100644 board/data_modul/common/common.h delete mode 100644 board/data_modul/imx8mm_edm_sbc/common.c diff --git a/board/data_modul/common/common.c b/board/data_modul/common/common.c new file mode 100644 index 00000000000..bf9a11472d1 --- /dev/null +++ b/board/data_modul/common/common.c @@ -0,0 +1,194 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 Marek Vasut + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) + +u8 dmo_get_memcfg(void) +{ + struct gpio_desc gpio[4]; + u8 memcfg = 0; + ofnode node; + int i, ret; + + node = ofnode_path("/config"); + if (!ofnode_valid(node)) { + printf("%s: no /config node?\n", __func__); + return BIT(2) | BIT(0); + } + + ret = gpio_request_list_by_name_nodev(node, + "dmo,ram-coding-gpios", + gpio, ARRAY_SIZE(gpio), + GPIOD_IS_IN); + for (i = 0; i < ret; i++) + memcfg |= !!dm_gpio_get_value(&(gpio[i])) << i; + + gpio_free_list_nodev(gpio, ret); + + return memcfg; +} + +int board_phys_sdram_size(phys_size_t *size) +{ + u8 memcfg = dmo_get_memcfg(); + + *size = (4ULL >> ((memcfg >> 1) & 0x3)) * SZ_1G; + + return 0; +} + +#ifdef CONFIG_SPL_BUILD +static void data_modul_imx_edm_sbc_early_init_f(const iomux_v3_cfg_t wdog_pad) +{ + struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; + + imx_iomux_v3_setup_pad(wdog_pad | MUX_PAD_CTRL(WDOG_PAD_CTRL)); + + set_wdog_reset(wdog); +} + +__weak int data_modul_imx_edm_sbc_board_power_init(void) +{ + return 0; +} + +static void spl_dram_init(struct dram_timing_info *dram_timing_info[8]) +{ + u8 memcfg = dmo_get_memcfg(); + int i; + + printf("DDR: %d GiB x%d [0x%x]\n", + /* 0..4 GiB, 1..2 GiB, 0..1 GiB */ + 4 >> ((memcfg >> 1) & 0x3), + /* 0..x32, 1..x16 */ + 32 >> (memcfg & BIT(0)), + memcfg); + + if (!dram_timing_info[memcfg]) { + printf("Unsupported DRAM strapping, trying lowest supported. MEMCFG=0x%x\n", + memcfg); + for (i = 7; i >= 0; i--) + if (dram_timing_info[i]) /* Configuration found */ + break; + } + + ddr_init(dram_timing_info[memcfg]); +} + +void dmo_board_init_f(const iomux_v3_cfg_t wdog_pad, + struct dram_timing_info *dram_timing_info[8]) +{ + struct udevice *dev; + int ret; + + icache_enable(); + + arch_cpu_init(); + + init_uart_clk(2); + + data_modul_imx_edm_sbc_early_init_f(wdog_pad); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + ret = spl_early_init(); + if (ret) { + debug("spl_early_init() failed: %d\n", ret); + hang(); + } + + preloader_console_init(); + + ret = uclass_get_device_by_name(UCLASS_CLK, + "clock-controller@30380000", + &dev); + if (ret < 0) { + printf("Failed to find clock node. Check device tree\n"); + hang(); + } + + enable_tzc380(); + + data_modul_imx_edm_sbc_board_power_init(); + + /* DDR initialization */ + spl_dram_init(dram_timing_info); + + board_init_r(NULL, 0); +} +#else +void dmo_setup_boot_device(void) +{ + int boot_device = get_boot_device(); + char *devnum; + + devnum = env_get("devnum"); + if (devnum) /* devnum is already set */ + return; + + if (boot_device == MMC3_BOOT) /* eMMC */ + env_set_ulong("devnum", 0); + else + env_set_ulong("devnum", 1); +} + +void dmo_setup_mac_address(void) +{ + unsigned char enetaddr[6]; + struct udevice *dev; + int off, ret; + + ret = eth_env_get_enetaddr("ethaddr", enetaddr); + if (ret) /* ethaddr is already set */ + return; + + off = fdt_path_offset(gd->fdt_blob, "eeprom0"); + if (off < 0) { + printf("%s: No eeprom0 path offset\n", __func__); + return; + } + + ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev); + if (ret) { + printf("Cannot find EEPROM!\n"); + return; + } + + ret = i2c_eeprom_read(dev, 0xb0, enetaddr, 0x6); + if (ret) { + printf("Error reading configuration EEPROM!\n"); + return; + } + + if (is_valid_ethaddr(enetaddr)) + eth_env_set_enetaddr("ethaddr", enetaddr); +} +#endif diff --git a/board/data_modul/common/common.h b/board/data_modul/common/common.h new file mode 100644 index 00000000000..4f6b2bc17d4 --- /dev/null +++ b/board/data_modul/common/common.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2022 Marek Vasut + */ + +#ifndef __EDM_SBC_COMMON_H__ +#define __EDM_SBC_COMMON_H__ + +#include +#include + +u8 dmo_get_memcfg(void); +void dmo_board_init_f(const iomux_v3_cfg_t wdog_pad, + struct dram_timing_info *dram_timing_info[8]); +void dmo_setup_boot_device(void); +void dmo_setup_mac_address(void); + +#endif /* __EDM_SBC_COMMON_H__ */ diff --git a/board/data_modul/imx8mm_edm_sbc/Makefile b/board/data_modul/imx8mm_edm_sbc/Makefile index eaba85d65b8..6d72e930fca 100644 --- a/board/data_modul/imx8mm_edm_sbc/Makefile +++ b/board/data_modul/imx8mm_edm_sbc/Makefile @@ -10,4 +10,4 @@ else obj-y += imx8mm_data_modul_edm_sbc.o endif -obj-y += common.o +obj-y += ../common/common.o diff --git a/board/data_modul/imx8mm_edm_sbc/common.c b/board/data_modul/imx8mm_edm_sbc/common.c deleted file mode 100644 index 713f789da67..00000000000 --- a/board/data_modul/imx8mm_edm_sbc/common.c +++ /dev/null @@ -1,37 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2022 Marek Vasut - */ - -#include -#include -#include - -#include "lpddr4_timing.h" - -DECLARE_GLOBAL_DATA_PTR; - -u8 dmo_get_memcfg(void) -{ - struct gpio_desc gpio[4]; - u8 memcfg = 0; - ofnode node; - int i, ret; - - node = ofnode_path("/config"); - if (!ofnode_valid(node)) { - printf("%s: no /config node?\n", __func__); - return BIT(2) | BIT(0); - } - - ret = gpio_request_list_by_name_nodev(node, - "dmo,ram-coding-gpios", - gpio, ARRAY_SIZE(gpio), - GPIOD_IS_IN); - for (i = 0; i < ret; i++) - memcfg |= !!dm_gpio_get_value(&(gpio[i])) << i; - - gpio_free_list_nodev(gpio, ret); - - return memcfg; -} diff --git a/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c b/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c index 82856f7a08c..ff89333b732 100644 --- a/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c +++ b/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c @@ -5,76 +5,16 @@ #include #include -#include #include -#include #include #include -#include #include -#include #include -#include "lpddr4_timing.h" +#include "../common/common.h" DECLARE_GLOBAL_DATA_PTR; -int board_phys_sdram_size(phys_size_t *size) -{ - u8 memcfg = dmo_get_memcfg(); - - *size = (4ULL >> ((memcfg >> 1) & 0x3)) * SZ_1G; - - return 0; -} - -static void setup_mac_address(void) -{ - unsigned char enetaddr[6]; - struct udevice *dev; - int off, ret; - - ret = eth_env_get_enetaddr("ethaddr", enetaddr); - if (ret) /* ethaddr is already set */ - return; - - off = fdt_path_offset(gd->fdt_blob, "eeprom0"); - if (off < 0) { - printf("%s: No eeprom0 path offset\n", __func__); - return; - } - - ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev); - if (ret) { - printf("Cannot find EEPROM!\n"); - return; - } - - ret = i2c_eeprom_read(dev, 0xb0, enetaddr, 0x6); - if (ret) { - printf("Error reading configuration EEPROM!\n"); - return; - } - - if (is_valid_ethaddr(enetaddr)) - eth_env_set_enetaddr("ethaddr", enetaddr); -} - -static void setup_boot_device(void) -{ - int boot_device = get_boot_device(); - char *devnum; - - devnum = env_get("devnum"); - if (devnum) /* devnum is already set */ - return; - - if (boot_device == MMC3_BOOT) /* eMMC */ - env_set_ulong("devnum", 0); - else - env_set_ulong("devnum", 1); -} - int board_init(void) { return 0; @@ -85,8 +25,8 @@ int board_late_init(void) struct udevice *dev; int ret; - setup_boot_device(); - setup_mac_address(); + dmo_setup_boot_device(); + dmo_setup_mac_address(); ret = uclass_get_device_by_name(UCLASS_MISC, "usb-hub@2c", &dev); if (ret) diff --git a/board/data_modul/imx8mm_edm_sbc/lpddr4_timing.h b/board/data_modul/imx8mm_edm_sbc/lpddr4_timing.h index 1fab9b14051..8b5368a104d 100644 --- a/board/data_modul/imx8mm_edm_sbc/lpddr4_timing.h +++ b/board/data_modul/imx8mm_edm_sbc/lpddr4_timing.h @@ -9,6 +9,4 @@ extern struct dram_timing_info dmo_imx8mm_sbc_dram_timing_16_32; extern struct dram_timing_info dmo_imx8mm_sbc_dram_timing_32_32; -u8 dmo_get_memcfg(void); - #endif /* __LPDDR4_TIMING_H__ */ diff --git a/board/data_modul/imx8mm_edm_sbc/spl.c b/board/data_modul/imx8mm_edm_sbc/spl.c index f5063eb8c19..4a9c62fb86f 100644 --- a/board/data_modul/imx8mm_edm_sbc/spl.c +++ b/board/data_modul/imx8mm_edm_sbc/spl.c @@ -26,24 +26,11 @@ #include "lpddr4_timing.h" +#include "../common/common.h" + DECLARE_GLOBAL_DATA_PTR; -#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) - -static const iomux_v3_cfg_t wdog_pads[] = { - IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), -}; - -static void data_modul_imx8mm_edm_sbc_early_init_f(void) -{ - struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; - - imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); - - set_wdog_reset(wdog); -} - -static int data_modul_imx8mm_edm_sbc_board_power_init(void) +int data_modul_imx_edm_sbc_board_power_init(void) { struct udevice *dev; int ret; @@ -105,67 +92,7 @@ static struct dram_timing_info *dram_timing_info[8] = { NULL, /* INVALID */ }; -static void spl_dram_init(void) -{ - u8 memcfg = dmo_get_memcfg(); - int i; - - printf("DDR: %d GiB x%d [0x%x]\n", - /* 0..4 GiB, 1..2 GiB, 0..1 GiB */ - 4 >> ((memcfg >> 1) & 0x3), - /* 0..x32, 1..x16 */ - 32 >> (memcfg & BIT(0)), - memcfg); - - if (!dram_timing_info[memcfg]) { - printf("Unsupported DRAM strapping, trying lowest supported. MEMCFG=0x%x\n", - memcfg); - for (i = ARRAY_SIZE(dram_timing_info) - 1; i >= 0; i--) - if (dram_timing_info[i]) /* Configuration found */ - break; - } - - ddr_init(dram_timing_info[memcfg]); -} - void board_init_f(ulong dummy) { - struct udevice *dev; - int ret; - - icache_enable(); - - arch_cpu_init(); - - init_uart_clk(2); - - data_modul_imx8mm_edm_sbc_early_init_f(); - - /* Clear the BSS. */ - memset(__bss_start, 0, __bss_end - __bss_start); - - ret = spl_early_init(); - if (ret) { - debug("spl_early_init() failed: %d\n", ret); - hang(); - } - - preloader_console_init(); - - ret = uclass_get_device_by_name(UCLASS_CLK, - "clock-controller@30380000", - &dev); - if (ret < 0) { - printf("Failed to find clock node. Check device tree\n"); - hang(); - } - - enable_tzc380(); - - data_modul_imx8mm_edm_sbc_board_power_init(); - - /* DDR initialization */ - spl_dram_init(); - - board_init_r(NULL, 0); + dmo_board_init_f(IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B, dram_timing_info); } From 4408cd6641175b6f7a10d4456d51495426ae4cd9 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 13 Dec 2022 05:46:06 +0100 Subject: [PATCH 33/87] ARM: imx: bootaux: Fix macro misuse There are no CONFIG_{TOOLS_,SPL_,TPL_,}IMX8M macros, nor is there one for ARM64. Use plain IS_ENABLED(CONFIG_IMX8M) and IS_ENABLED(CONFIG_ARM64) to avoid expanding the {TOOLS_,SPL_,TPL_,} part. Fixes: 56c2dbdabab5 ("imx: bootaux: cleanup code") Signed-off-by: Marek Vasut Reviewed-by: Peng Fan --- arch/arm/mach-imx/imx_bootaux.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-imx/imx_bootaux.c b/arch/arm/mach-imx/imx_bootaux.c index 8115bf40f1a..433c1f80cee 100644 --- a/arch/arm/mach-imx/imx_bootaux.c +++ b/arch/arm/mach-imx/imx_bootaux.c @@ -15,7 +15,7 @@ #include /* Just to avoid build error */ -#if CONFIG_IS_ENABLED(IMX8M) +#if IS_ENABLED(CONFIG_IMX8M) #define SRC_M4C_NON_SCLR_RST_MASK BIT(0) #define SRC_M4_ENABLE_MASK BIT(0) #define SRC_M4_REG_OFFSET 0 @@ -106,7 +106,7 @@ int arch_auxiliary_core_up(u32 core_id, ulong addr) if (!pc) return CMD_RET_FAILURE; - if (!CONFIG_IS_ENABLED(ARM64)) + if (!IS_ENABLED(CONFIG_ARM64)) stack = 0x0; } else { /* @@ -128,7 +128,7 @@ int arch_auxiliary_core_up(u32 core_id, ulong addr) flush_dcache_all(); /* Enable M4 */ - if (CONFIG_IS_ENABLED(IMX8M)) { + if (IS_ENABLED(CONFIG_IMX8M)) { arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0, 0, 0, 0, 0, NULL); } else { clrsetbits_le32(SRC_BASE_ADDR + SRC_M4_REG_OFFSET, @@ -143,7 +143,7 @@ int arch_auxiliary_core_check_up(u32 core_id) struct arm_smccc_res res; unsigned int val; - if (CONFIG_IS_ENABLED(IMX8M)) { + if (IS_ENABLED(CONFIG_IMX8M)) { arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, 0, 0, 0, 0, 0, &res); return res.a0; } From 3f7afddc9cbdcbbc47a0b814a132b76593cf8b28 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 13 Dec 2022 05:46:07 +0100 Subject: [PATCH 34/87] ARM: imx: bootaux: Fix LTO -Wlto-type-mismatch MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Commit 56c2dbdabab5 ("imx: bootaux: cleanup code") introduces the following LTO related warning: " arch/arm/mach-imx/imx_bootaux.c:24:31: warning: type of ‘hostmap’ does not match original declaration [-Wlto-type-mismatch] 24 | const __weak struct rproc_att hostmap[] = { }; | ^ arch/arm/mach-imx/imx8m/soc.c:1590:24: note: array types have different bounds 1590 | const struct rproc_att hostmap[] = { | ^ arch/arm/mach-imx/imx8m/soc.c:1590:24: note: ‘hostmap’ was previously declared here ../aarch64-linux-gnu/bin/ld: warning: u-boot has a LOAD segment with RWX permissions " This is because the weak empty array of structures "hostmap" is eventually replaced by non-empty array of structures with different number of elements. Fix this by avoiding weak variable size array, instead use a weak function which returns single pointer to the array. Fixes: 56c2dbdabab5 ("imx: bootaux: cleanup code") Signed-off-by: Marek Vasut Reviewed-by: Peng Fan --- arch/arm/include/asm/mach-imx/sys_proto.h | 2 ++ arch/arm/mach-imx/imx8m/soc.c | 5 +++++ arch/arm/mach-imx/imx_bootaux.c | 7 +++++-- arch/arm/mach-imx/mx7/soc.c | 5 +++++ 4 files changed, 17 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h index dd0d3f29333..27fdc16cd50 100644 --- a/arch/arm/include/asm/mach-imx/sys_proto.h +++ b/arch/arm/include/asm/mach-imx/sys_proto.h @@ -149,6 +149,8 @@ struct rproc_att { u32 size; /* size of reg range */ }; +const struct rproc_att *imx_bootaux_get_hostmap(void); + struct rom_api { u16 ver; u16 tag; diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 8050406613d..90a59bd4398 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -1610,4 +1610,9 @@ const struct rproc_att hostmap[] = { { 0x40000000, 0x40000000, 0x80000000 }, { /* sentinel */ } }; + +const struct rproc_att *imx_bootaux_get_hostmap(void) +{ + return hostmap; +} #endif diff --git a/arch/arm/mach-imx/imx_bootaux.c b/arch/arm/mach-imx/imx_bootaux.c index 433c1f80cee..888c53d6901 100644 --- a/arch/arm/mach-imx/imx_bootaux.c +++ b/arch/arm/mach-imx/imx_bootaux.c @@ -21,11 +21,14 @@ #define SRC_M4_REG_OFFSET 0 #endif -const __weak struct rproc_att hostmap[] = { }; +__weak const struct rproc_att *imx_bootaux_get_hostmap(void) +{ + return NULL; +} static const struct rproc_att *get_host_mapping(unsigned long auxcore) { - const struct rproc_att *mmap = hostmap; + const struct rproc_att *mmap = imx_bootaux_get_hostmap(); while (mmap && mmap->size) { if (mmap->da <= auxcore && diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c index 02af0d568f2..689dbefe8ee 100644 --- a/arch/arm/mach-imx/mx7/soc.c +++ b/arch/arm/mach-imx/mx7/soc.c @@ -224,6 +224,11 @@ const struct rproc_att hostmap[] = { { 0x80000000, 0x80000000, 0x60000000 }, /* DDRC */ { /* sentinel */ } }; + +const struct rproc_att *imx_bootaux_get_hostmap(void) +{ + return hostmap; +} #endif #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) From c4d79448b095b4f792556f361c1a3667c3375673 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 3 Jan 2023 10:19:39 -0300 Subject: [PATCH 35/87] mx7: clock: Use 60MHz for the I2C clocks When an I2C clock is enabled inside enable_i2c_clk() the clock rate is configured as PLL_SYS_MAIN_120M_CLK / 2 = 60MHz. Currently, the I2C clock is retrieved from I2C1_CLK_ROOT, which may not be the one that was enabled. As there is no clock driver for the imx7d, it is better to return 60MHz for the I2C clock. This provides a workaround for the imx7d-pico board, where I2C4 is connected to the PMIC. With this change, it is possible to convert the imx7d-pico board to DM_I2C and DM_PMIC. Signed-off-by: Fabio Estevam --- arch/arm/mach-imx/mx7/clock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/mx7/clock.c b/arch/arm/mach-imx/mx7/clock.c index 88f6fe02748..4e232385afc 100644 --- a/arch/arm/mach-imx/mx7/clock.c +++ b/arch/arm/mach-imx/mx7/clock.c @@ -502,7 +502,7 @@ unsigned int mxc_get_clock(enum mxc_clock clk) case MXC_IPG_CLK: return get_ipg_clk(); case MXC_I2C_CLK: - return get_root_clk(I2C1_CLK_ROOT); + return 60000000; case MXC_UART_CLK: return get_root_clk(UART1_CLK_ROOT); case MXC_CSPI_CLK: From 14d3c8fd0a2df70e7101b5e77290daeec146cc0c Mon Sep 17 00:00:00 2001 From: Philippe Schenker Date: Wed, 4 Jan 2023 20:02:16 +0100 Subject: [PATCH 36/87] configs: verdin-imx8mm: Add bootaux command The i.MX 8M Mini SoC does incorporate an additional M-Core. To be able to load it with a firmware, enable bootaux command as other Toradex modules also have it enabled to be consistent. Signed-off-by: Philippe Schenker --- configs/verdin-imx8mm_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/verdin-imx8mm_defconfig b/configs/verdin-imx8mm_defconfig index 62f85883cb2..5b5f7c051e5 100644 --- a/configs/verdin-imx8mm_defconfig +++ b/configs/verdin-imx8mm_defconfig @@ -16,6 +16,7 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y +CONFIG_IMX_BOOTAUX=y CONFIG_SYS_LOAD_ADDR=0x48200000 CONFIG_SYS_MEMTEST_START=0x40000000 CONFIG_SYS_MEMTEST_END=0x80000000 From 6e91c06a73547d165bdede2b57af4acd66c0d40f Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Mon, 9 Jan 2023 12:42:18 +0100 Subject: [PATCH 37/87] arm64: dts: imx8mm-kontron: Add RTC aliases Add aliases for the RTCs on the board and on the SoC. This ensures that the primary RTC is always the one on the board that has a buffered supply and maximum accuracy. This is a direct port of the pending commit from linux-next. Signed-off-by: Frieder Schrempf Signed-off-by: Shawn Guo Reviewed-by: Fabio Estevam --- arch/arm/dts/imx8mm-kontron-bl.dts | 4 +++- arch/arm/dts/imx8mm-kontron-osm-s.dtsi | 7 ++++++- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/imx8mm-kontron-bl.dts b/arch/arm/dts/imx8mm-kontron-bl.dts index a079322a379..dcec57c2039 100644 --- a/arch/arm/dts/imx8mm-kontron-bl.dts +++ b/arch/arm/dts/imx8mm-kontron-bl.dts @@ -13,6 +13,8 @@ aliases { ethernet1 = &usbnet; + rtc0 = &rx8900; + rtc1 = &snvs_rtc; }; /* fixed crystal dedicated to mcp2515 */ @@ -136,7 +138,7 @@ pinctrl-0 = <&pinctrl_i2c4>; status = "okay"; - rtc@32 { + rx8900: rtc@32 { compatible = "epson,rx8900"; reg = <0x32>; }; diff --git a/arch/arm/dts/imx8mm-kontron-osm-s.dtsi b/arch/arm/dts/imx8mm-kontron-osm-s.dtsi index 8d10f5b4129..695da2fa7c4 100644 --- a/arch/arm/dts/imx8mm-kontron-osm-s.dtsi +++ b/arch/arm/dts/imx8mm-kontron-osm-s.dtsi @@ -10,6 +10,11 @@ model = "Kontron OSM-S i.MX8MM (N802X SOM)"; compatible = "kontron,imx8mm-osm-s", "fsl,imx8mm"; + aliases { + rtc0 = &rv3028; + rtc1 = &snvs_rtc; + }; + memory@40000000 { device_type = "memory"; /* @@ -200,7 +205,7 @@ }; }; - rtc@52 { + rv3028: rtc@52 { compatible = "microcrystal,rv3028"; reg = <0x52>; pinctrl-names = "default"; From d12618b9279647e10055b9d086e454823496b0ff Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 10 Jan 2023 17:18:08 -0300 Subject: [PATCH 38/87] imx8mm-phg: Add board support Add the board support for the i.MX8MM Cloos PHG board. This board uses a imx8mm-tqma8mqml SoM from TQ-Group. imx8mm-phg.dts and imx8mm-tqma8mqml.dtsi are taken directly from Linux 6.2-rc3. Signed-off-by: Fabio Estevam Reviewed-by: Tom Rini --- arch/arm/dts/Makefile | 1 + arch/arm/dts/imx8mm-phg-u-boot.dtsi | 137 ++ arch/arm/dts/imx8mm-phg.dts | 266 +++ arch/arm/dts/imx8mm-tqma8mqml.dtsi | 341 +++ arch/arm/mach-imx/imx8m/Kconfig | 8 + board/cloos/imx8mm_phg/Kconfig | 15 + board/cloos/imx8mm_phg/MAINTAINERS | 6 + board/cloos/imx8mm_phg/Makefile | 12 + board/cloos/imx8mm_phg/imx8mm_phg.c | 50 + board/cloos/imx8mm_phg/imx8mm_phg.env | 8 + .../cloos/imx8mm_phg/imximage-8mm-lpddr4.cfg | 8 + board/cloos/imx8mm_phg/lpddr4_timing.c | 1846 +++++++++++++++++ board/cloos/imx8mm_phg/spl.c | 147 ++ configs/imx8mm_phg_defconfig | 120 ++ doc/board/cloos/imx8mm_phg.rst | 55 + doc/board/cloos/index.rst | 9 + doc/board/index.rst | 1 + include/configs/imx8mm_phg.h | 41 + 18 files changed, 3071 insertions(+) create mode 100644 arch/arm/dts/imx8mm-phg-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mm-phg.dts create mode 100644 arch/arm/dts/imx8mm-tqma8mqml.dtsi create mode 100644 board/cloos/imx8mm_phg/Kconfig create mode 100644 board/cloos/imx8mm_phg/MAINTAINERS create mode 100644 board/cloos/imx8mm_phg/Makefile create mode 100644 board/cloos/imx8mm_phg/imx8mm_phg.c create mode 100644 board/cloos/imx8mm_phg/imx8mm_phg.env create mode 100644 board/cloos/imx8mm_phg/imximage-8mm-lpddr4.cfg create mode 100644 board/cloos/imx8mm_phg/lpddr4_timing.c create mode 100644 board/cloos/imx8mm_phg/spl.c create mode 100644 configs/imx8mm_phg_defconfig create mode 100644 doc/board/cloos/imx8mm_phg.rst create mode 100644 doc/board/cloos/index.rst create mode 100644 include/configs/imx8mm_phg.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 3ecd6a86e95..48de9ab3ca9 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -960,6 +960,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mm-kontron-bl.dtb \ imx8mm-kontron-bl-osm-s.dtb \ imx8mm-mx8menlo.dtb \ + imx8mm-phg.dtb \ imx8mm-venice.dtb \ imx8mm-venice-gw71xx-0x.dtb \ imx8mm-venice-gw72xx-0x.dtb \ diff --git a/arch/arm/dts/imx8mm-phg-u-boot.dtsi b/arch/arm/dts/imx8mm-phg-u-boot.dtsi new file mode 100644 index 00000000000..3bf45ef4a64 --- /dev/null +++ b/arch/arm/dts/imx8mm-phg-u-boot.dtsi @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include "imx8mm-u-boot.dtsi" + +/ { + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + u-boot,dm-spl; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; +}; + +&aips4 { + u-boot,dm-spl; +}; + +®_usdhc2_vmmc { + u-boot,off-on-delay-us = <20000>; +}; + +&pinctrl_reg_usdhc2_vmmc { + u-boot,dm-spl; +}; + +&pinctrl_uart2 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2_gpio { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc3 { + u-boot,dm-spl; +}; + +&gpio1 { + u-boot,dm-spl; +}; + +&gpio2 { + u-boot,dm-spl; +}; + +&gpio3 { + u-boot,dm-spl; +}; + +&gpio4 { + u-boot,dm-spl; +}; + +&gpio5 { + u-boot,dm-spl; +}; + +&uart2 { + u-boot,dm-spl; +}; + +&usbmisc1 { + u-boot,dm-spl; +}; + +&usbphynop1 { + u-boot,dm-spl; +}; + +&usbotg1 { + u-boot,dm-spl; +}; + +&usdhc1 { + u-boot,dm-spl; +}; + +&usdhc2 { + u-boot,dm-spl; + sd-uhs-sdr104; + sd-uhs-ddr50; + assigned-clocks = <&clk IMX8MM_CLK_USDHC2>; + assigned-clock-rates = <400000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_400M>; +}; + +&usdhc3 { + u-boot,dm-spl; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + /* + * prevents voltage switch warn: driver will switch even at + * fixed voltage + */ + /delete-property/ vmmc-supply; + /delete-property/ vqmmc-supply; + assigned-clocks = <&clk IMX8MM_CLK_USDHC3>; + assigned-clock-rates = <400000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_400M>; +}; + +&i2c1 { + u-boot,dm-spl; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pmic@25} { + u-boot,dm-spl; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} { + u-boot,dm-spl; +}; + +&pinctrl_i2c1 { + u-boot,dm-spl; +}; + +&pinctrl_pmic { + u-boot,dm-spl; +}; + +&wdog1 { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/imx8mm-phg.dts b/arch/arm/dts/imx8mm-phg.dts new file mode 100644 index 00000000000..e9447738b10 --- /dev/null +++ b/arch/arm/dts/imx8mm-phg.dts @@ -0,0 +1,266 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Fabio Estevam + */ + +/dts-v1/; + +#include "imx8mm-tqma8mqml.dtsi" + +/ { + model = "Cloos i.MX8MM PHG board"; + compatible = "cloos,imx8mm-phg", "tq,imx8mm-tqma8mqml", "fsl,imx8mm"; + + aliases { + mmc0 = &usdhc3; + mmc1 = &usdhc2; + }; + + chosen { + stdout-path = &uart2; + }; + + beeper { + compatible = "gpio-beeper"; + pinctrl-0 = <&pinctrl_beeper>; + gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_led>; + + led-0 { + label = "status1"; + gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + }; + + led-1 { + label = "status2"; + gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + }; + + led-2 { + label = "status3"; + gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; + }; + + led-3 { + label = "run"; + gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + }; + + led-4 { + label = "powerled"; + gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + }; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_otg_vbus_ctrl>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio2 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: regulator-vmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + off-on-delay-us = <12000>; + }; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + reg = <0>; + compatible = "ethernet-phy-ieee802.3-c22"; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usbphynop1 { + power-domains = <&pgc_otg1>; +}; + +&usbphynop2 { + power-domains = <&pgc_otg2>; +}; + +&usbotg1 { + dr_mode = "host"; + vbus-supply = <®_usb_otg_vbus>; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + status = "okay"; +}; + +&usdhc2 { + assigned-clocks = <&clk IMX8MM_CLK_USDHC2>; + assigned-clock-rates = <400000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_400M>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + disable-wp; + no-mmc; + no-sdio; + sd-uhs-sdr104; + sd-uhs-ddr50; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&iomuxc { + pinctrl_beeper: beepergrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x19 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 + MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 + MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 + MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x40000002 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x40000002 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x14 + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x14 + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x14 + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x14 + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x90 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x90 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x90 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x90 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x14 + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x90 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x90 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x14 + MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x10 + >; + }; + + pinctrl_gpio_led: gpioledgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 + MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 + MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x19 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_otg_vbus_ctrl: otgvbusctrlgrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x119 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpiogrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + >; + }; +}; diff --git a/arch/arm/dts/imx8mm-tqma8mqml.dtsi b/arch/arm/dts/imx8mm-tqma8mqml.dtsi new file mode 100644 index 00000000000..f649dfacb4b --- /dev/null +++ b/arch/arm/dts/imx8mm-tqma8mqml.dtsi @@ -0,0 +1,341 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2020-2021 TQ-Systems GmbH + */ + +#include +#include "imx8mm.dtsi" + +/ { + model = "TQ-Systems GmbH i.MX8MM TQMa8MxML"; + compatible = "tq,imx8mm-tqma8mqml", "fsl,imx8mm"; + + memory@40000000 { + device_type = "memory"; + /* our minimum RAM config will be 1024 MiB */ + reg = <0x00000000 0x40000000 0 0x40000000>; + }; + + /* e-MMC IO, needed for HS modes */ + reg_vcc1v8: regulator-vcc1v8 { + compatible = "regulator-fixed"; + regulator-name = "TQMA8MXML_VCC1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + /* identical to buck4_reg, but should never change */ + reg_vcc3v3: regulator-vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "TQMA8MXML_VCC3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + /* 640 MiB */ + size = <0 0x28000000>; + /* 1024 - 128 MiB, our minimum RAM config will be 1024 MiB */ + alloc-ranges = <0 0x40000000 0 0x78000000>; + linux,cma-default; + }; + }; +}; + +&A53_0 { + cpu-supply = <&buck2_reg>; +}; + +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi>; + status = "okay"; + + flash0: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <84000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + }; +}; + +&gpu_2d { + status = "okay"; +}; + +&gpu_3d { + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + sensor0: temperature-sensor-eeprom@1b { + compatible = "nxp,se97", "jedec,jc-42.4-temp"; + reg = <0x1b>; + }; + + pca9450: pmic@25 { + compatible = "nxp,pca9450a"; + reg = <0x25>; + + /* PMIC PCA9450 PMIC_nINT GPIO1_IO08 */ + pinctrl-0 = <&pinctrl_pmic>; + pinctrl-names = "default"; + interrupt-parent = <&gpio1>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + + regulators { + /* V_0V85_SOC: 0.85 */ + buck1_reg: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + /* VDD_ARM */ + buck2_reg: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + regulator-ramp-delay = <3125>; + }; + + /* V_0V85_GPU / DRAM / VPU */ + buck3_reg: BUCK3 { + regulator-name = "BUCK3"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <950000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + /* VCC3V3 -> VMMC, ... must not be changed */ + buck4_reg: BUCK4 { + regulator-name = "BUCK4"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_1V8 -> VQMMC, SPI-NOR, ... must not be changed */ + buck5_reg: BUCK5 { + regulator-name = "BUCK5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_1V1 -> RAM, ... must not be changed */ + buck6_reg: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_1V8_SNVS */ + ldo1_reg: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_0V8_SNVS */ + ldo2_reg: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_1V8_ANA */ + ldo3_reg: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_0V9_MIPI */ + ldo4_reg: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VCC SD IO - switched using SD2 VSELECT */ + ldo5_reg: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; + + + pcf85063: rtc@51 { + compatible = "nxp,pcf85063a"; + reg = <0x51>; + quartz-load-femtofarads = <7000>; + }; + + eeprom1: eeprom@53 { + compatible = "nxp,se97b", "atmel,24c02"; + read-only; + reg = <0x53>; + pagesize = <16>; + }; + + eeprom0: eeprom@57 { + compatible = "atmel,24c64"; + reg = <0x57>; + pagesize = <32>; + }; +}; + +&pcie_phy { + fsl,refclk-pad-mode = ; + fsl,clkreq-unsupported; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + no-sd; + no-sdio; + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc1v8>; + status = "okay"; +}; + +/* + * Attention: + * wdog reset is routed to PMIC, PMIC must be preconfigured to force POR + * without LDO for SNVS. GPIO1_IO02 must not be used as GPIO. + */ +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_flexspi: flexspigrp { + fsl,pins = , + , + , + , + , + ; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = , + ; + }; + + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = , + ; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = ; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = ; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + /* option USDHC3_RESET_B not defined, only in RM */ + ; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + /* option USDHC3_RESET_B not defined, only in RM */ + ; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + /* option USDHC3_RESET_B not defined, only in RM */ + ; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = ; + }; +}; diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index a0715e80911..64e6b49f46b 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -94,6 +94,13 @@ config TARGET_IMX8MM_MX8MENLO select SUPPORT_SPL select IMX8M_LPDDR4 +config TARGET_IMX8MM_PHG + bool "i.MX8MM PHG board" + select BINMAN + select IMX8MM + select SUPPORT_SPL + select IMX8M_LPDDR4 + config TARGET_IMX8MM_VENICE bool "Support Gateworks Venice iMX8M Mini module" select BINMAN @@ -305,6 +312,7 @@ source "board/advantech/imx8mp_rsb3720a1/Kconfig" source "board/beacon/imx8mm/Kconfig" source "board/beacon/imx8mn/Kconfig" source "board/bsh/imx8mn_smm_s2/Kconfig" +source "board/cloos/imx8mm_phg/Kconfig" source "board/compulab/imx8mm-cl-iot-gate/Kconfig" source "board/data_modul/imx8mm_edm_sbc/Kconfig" source "board/dhelectronics/dh_imx8mp/Kconfig" diff --git a/board/cloos/imx8mm_phg/Kconfig b/board/cloos/imx8mm_phg/Kconfig new file mode 100644 index 00000000000..04680d93b5b --- /dev/null +++ b/board/cloos/imx8mm_phg/Kconfig @@ -0,0 +1,15 @@ +if TARGET_IMX8MM_PHG + +config SYS_BOARD + default "imx8mm_phg" + +config SYS_VENDOR + default "cloos" + +config SYS_CONFIG_NAME + default "imx8mm_phg" + +config IMX_CONFIG + default "board/cloos/imx8mm_phg/imximage-8mm-lpddr4.cfg" + +endif diff --git a/board/cloos/imx8mm_phg/MAINTAINERS b/board/cloos/imx8mm_phg/MAINTAINERS new file mode 100644 index 00000000000..476f23061bc --- /dev/null +++ b/board/cloos/imx8mm_phg/MAINTAINERS @@ -0,0 +1,6 @@ +i.MX8MM PHG BOARD +M: Fabio Estevam +S: Maintained +F: board/cloos/imx8mm_phg/ +F: include/configs/imx8mm_phg.h +F: configs/imx8mm_phg_defconfig diff --git a/board/cloos/imx8mm_phg/Makefile b/board/cloos/imx8mm_phg/Makefile new file mode 100644 index 00000000000..2b36931fcf7 --- /dev/null +++ b/board/cloos/imx8mm_phg/Makefile @@ -0,0 +1,12 @@ +# +# Copyright 2018 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx8mm_phg.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o +endif diff --git a/board/cloos/imx8mm_phg/imx8mm_phg.c b/board/cloos/imx8mm_phg/imx8mm_phg.c new file mode 100644 index 00000000000..bc4e984d505 --- /dev/null +++ b/board/cloos/imx8mm_phg/imx8mm_phg.c @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static int setup_fec(void) +{ + struct iomuxc_gpr_base_regs *gpr = + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + + /* Use 125MHz anatop REF_CLK1 for ENET1, not from external */ + clrsetbits_le32(&gpr->gpr[1], 0x2000, 0); + + return 0; +} + +int board_init(void) +{ + setup_fec(); + + return 0; +} + +int board_late_init(void) +{ + if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) { + env_set("board_name", "PHG"); + env_set("board_rev", "iMX8MM"); + } + + if (is_usb_boot()) { + env_set("bootcmd", "ums 0 mmc 0"); + env_set("bootdelay", "0"); + } + + return 0; +} diff --git a/board/cloos/imx8mm_phg/imx8mm_phg.env b/board/cloos/imx8mm_phg/imx8mm_phg.env new file mode 100644 index 00000000000..9cfb3d34584 --- /dev/null +++ b/board/cloos/imx8mm_phg/imx8mm_phg.env @@ -0,0 +1,8 @@ +fdt_addr_r=0x43000000 +mmcdev=0 +fdtfile=imx8mm-phg.dtb +mmcargs=setenv bootargs console=ttymxc1,115200 root=/dev/mmcblk${mmcdev}p${mmcpart} rw rootwait quiet +bootcmd=env exists mmcpart || setenv mmcpart 1; run mmcargs; \ + mmc dev ${mmcdev}; load mmc ${mmcdev}:${mmcpart} ${loadaddr} boot/Image; \ + load mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} boot/${fdtfile}; \ + booti ${loadaddr} - ${fdt_addr_r} diff --git a/board/cloos/imx8mm_phg/imximage-8mm-lpddr4.cfg b/board/cloos/imx8mm_phg/imximage-8mm-lpddr4.cfg new file mode 100644 index 00000000000..20061521f22 --- /dev/null +++ b/board/cloos/imx8mm_phg/imximage-8mm-lpddr4.cfg @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021 NXP + */ + + +BOOT_FROM sd +LOADER u-boot-spl-ddr.bin 0x7E1000 diff --git a/board/cloos/imx8mm_phg/lpddr4_timing.c b/board/cloos/imx8mm_phg/lpddr4_timing.c new file mode 100644 index 00000000000..ba961ebad4d --- /dev/null +++ b/board/cloos/imx8mm_phg/lpddr4_timing.c @@ -0,0 +1,1846 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2019 NXP + * + * Generated code from MX8M_DDR_tool + * TQMa8MQML.2GByte.RAM-Timing.0153.xlsx / K4F6E3S4HM-GFCL03V + * (HW REV.020x) + * from MX8MM_LPDDR4_RPA_v18.xlsx + */ + +#include +#include + +static struct dram_cfg_param ddr_ddrc_cfg[] = { + /* Initialize DDRC registers */ + { 0x3d400304, 0x1 }, + { 0x3d400030, 0x1 }, + { 0x3d400000, 0xa1080020 }, + { 0x3d400020, 0x203 }, + { 0x3d400024, 0x3a980 }, + { 0x3d400064, 0x5b00d2 }, + { 0x3d4000d0, 0xc00305ba }, + { 0x3d4000d4, 0x940000 }, + { 0x3d4000dc, 0xd4002d }, + { 0x3d4000e0, 0x310000 }, + { 0x3d4000e8, 0x66004d }, + { 0x3d4000ec, 0x6004d }, + { 0x3d400100, 0x191e1920 }, + { 0x3d400104, 0x60630 }, + { 0x3d40010c, 0xb0b000 }, + { 0x3d400110, 0xe04080e }, + { 0x3d400114, 0x2040c0c }, + { 0x3d400118, 0x1010007 }, + { 0x3d40011c, 0x401 }, + { 0x3d400130, 0x20600 }, + { 0x3d400134, 0xc100002 }, + { 0x3d400138, 0xd8 }, + { 0x3d400144, 0x96004b }, + { 0x3d400180, 0x2ee0017 }, + { 0x3d400184, 0x2605b8e }, + { 0x3d400188, 0x0 }, + { 0x3d400190, 0x497820a }, + { 0x3d400194, 0x80303 }, + { 0x3d4001b4, 0x170a }, + { 0x3d4001a0, 0xe0400018 }, + { 0x3d4001a4, 0xdf00e4 }, + { 0x3d4001a8, 0x80000000 }, + { 0x3d4001b0, 0x11 }, + { 0x3d4001c0, 0x1 }, + { 0x3d4001c4, 0x1 }, + { 0x3d4000f4, 0xc99 }, + { 0x3d400108, 0x70e1617 }, + { 0x3d400200, 0x1f }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400204, 0x80808 }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0x7070707 }, + { 0x3d400250, 0x29001701 }, + { 0x3d400254, 0x2c }, + { 0x3d40025c, 0x4000030 }, + { 0x3d400264, 0x900093e7 }, + { 0x3d40026c, 0x2005574 }, + { 0x3d400400, 0x111 }, + { 0x3d400408, 0x72ff }, + { 0x3d400494, 0x2100e07 }, + { 0x3d400498, 0x620096 }, + { 0x3d40049c, 0x1100e07 }, + { 0x3d4004a0, 0xc8012c }, + { 0x3d402020, 0x1 }, + { 0x3d402024, 0x7d00 }, + { 0x3d402050, 0x20d040 }, + { 0x3d402064, 0xc001c }, + { 0x3d4020dc, 0x840000 }, + { 0x3d4020e0, 0x310000 }, + { 0x3d4020e8, 0x66004d }, + { 0x3d4020ec, 0x6004d }, + { 0x3d402100, 0xa040305 }, + { 0x3d402104, 0x30407 }, + { 0x3d402108, 0x203060b }, + { 0x3d40210c, 0x505000 }, + { 0x3d402110, 0x2040202 }, + { 0x3d402114, 0x2030202 }, + { 0x3d402118, 0x1010004 }, + { 0x3d40211c, 0x301 }, + { 0x3d402130, 0x20300 }, + { 0x3d402134, 0xa100002 }, + { 0x3d402138, 0x1d }, + { 0x3d402144, 0x14000a }, + { 0x3d402180, 0x640004 }, + { 0x3d402190, 0x3818200 }, + { 0x3d402194, 0x80303 }, + { 0x3d4021b4, 0x100 }, + { 0x3d4020f4, 0xc99 }, + { 0x3d403020, 0x1 }, + { 0x3d403024, 0x1f40 }, + { 0x3d403050, 0x20d040 }, + { 0x3d403064, 0x30007 }, + { 0x3d4030dc, 0x840000 }, + { 0x3d4030e0, 0x310000 }, + { 0x3d4030e8, 0x66004d }, + { 0x3d4030ec, 0x6004d }, + { 0x3d403100, 0xa010102 }, + { 0x3d403104, 0x30404 }, + { 0x3d403108, 0x203060b }, + { 0x3d40310c, 0x505000 }, + { 0x3d403110, 0x2040202 }, + { 0x3d403114, 0x2030202 }, + { 0x3d403118, 0x1010004 }, + { 0x3d40311c, 0x301 }, + { 0x3d403130, 0x20300 }, + { 0x3d403134, 0xa100002 }, + { 0x3d403138, 0x8 }, + { 0x3d403144, 0x50003 }, + { 0x3d403180, 0x190004 }, + { 0x3d403190, 0x3818200 }, + { 0x3d403194, 0x80303 }, + { 0x3d4031b4, 0x100 }, + { 0x3d4030f4, 0xc99 }, + { 0x3d400028, 0x0 }, +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + { 0x100a0, 0x0 }, + { 0x100a1, 0x1 }, + { 0x100a2, 0x2 }, + { 0x100a3, 0x3 }, + { 0x100a4, 0x4 }, + { 0x100a5, 0x5 }, + { 0x100a6, 0x6 }, + { 0x100a7, 0x7 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x1 }, + { 0x110a2, 0x2 }, + { 0x110a3, 0x3 }, + { 0x110a4, 0x4 }, + { 0x110a5, 0x5 }, + { 0x110a6, 0x6 }, + { 0x110a7, 0x7 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x1 }, + { 0x120a2, 0x2 }, + { 0x120a3, 0x5 }, + { 0x120a4, 0x4 }, + { 0x120a5, 0x3 }, + { 0x120a6, 0x6 }, + { 0x120a7, 0x7 }, + { 0x130a0, 0x7 }, + { 0x130a1, 0x1 }, + { 0x130a2, 0x2 }, + { 0x130a3, 0x5 }, + { 0x130a4, 0x4 }, + { 0x130a5, 0x3 }, + { 0x130a6, 0x6 }, + { 0x130a7, 0x0 }, + { 0x1005f, 0x1ff }, + { 0x1015f, 0x1ff }, + { 0x1105f, 0x1ff }, + { 0x1115f, 0x1ff }, + { 0x1205f, 0x1ff }, + { 0x1215f, 0x1ff }, + { 0x1305f, 0x1ff }, + { 0x1315f, 0x1ff }, + { 0x11005f, 0x1ff }, + { 0x11015f, 0x1ff }, + { 0x11105f, 0x1ff }, + { 0x11115f, 0x1ff }, + { 0x11205f, 0x1ff }, + { 0x11215f, 0x1ff }, + { 0x11305f, 0x1ff }, + { 0x11315f, 0x1ff }, + { 0x21005f, 0x1ff }, + { 0x21015f, 0x1ff }, + { 0x21105f, 0x1ff }, + { 0x21115f, 0x1ff }, + { 0x21205f, 0x1ff }, + { 0x21215f, 0x1ff }, + { 0x21305f, 0x1ff }, + { 0x21315f, 0x1ff }, + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x3055, 0x1ff }, + { 0x4055, 0x1ff }, + { 0x5055, 0x1ff }, + { 0x6055, 0x1ff }, + { 0x7055, 0x1ff }, + { 0x8055, 0x1ff }, + { 0x9055, 0x1ff }, + { 0x200c5, 0x19 }, + { 0x1200c5, 0x7 }, + { 0x2200c5, 0x7 }, + { 0x2002e, 0x2 }, + { 0x12002e, 0x2 }, + { 0x22002e, 0x2 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x20024, 0x1ab }, + { 0x2003a, 0x0 }, + { 0x120024, 0x1ab }, + { 0x2003a, 0x0 }, + { 0x220024, 0x1ab }, + { 0x2003a, 0x0 }, + { 0x20056, 0x3 }, + { 0x120056, 0x3 }, + { 0x220056, 0x3 }, + { 0x1004d, 0xe00 }, + { 0x1014d, 0xe00 }, + { 0x1104d, 0xe00 }, + { 0x1114d, 0xe00 }, + { 0x1204d, 0xe00 }, + { 0x1214d, 0xe00 }, + { 0x1304d, 0xe00 }, + { 0x1314d, 0xe00 }, + { 0x11004d, 0xe00 }, + { 0x11014d, 0xe00 }, + { 0x11104d, 0xe00 }, + { 0x11114d, 0xe00 }, + { 0x11204d, 0xe00 }, + { 0x11214d, 0xe00 }, + { 0x11304d, 0xe00 }, + { 0x11314d, 0xe00 }, + { 0x21004d, 0xe00 }, + { 0x21014d, 0xe00 }, + { 0x21104d, 0xe00 }, + { 0x21114d, 0xe00 }, + { 0x21204d, 0xe00 }, + { 0x21214d, 0xe00 }, + { 0x21304d, 0xe00 }, + { 0x21314d, 0xe00 }, + { 0x10049, 0xeba }, + { 0x10149, 0xeba }, + { 0x11049, 0xeba }, + { 0x11149, 0xeba }, + { 0x12049, 0xeba }, + { 0x12149, 0xeba }, + { 0x13049, 0xeba }, + { 0x13149, 0xeba }, + { 0x110049, 0xeba }, + { 0x110149, 0xeba }, + { 0x111049, 0xeba }, + { 0x111149, 0xeba }, + { 0x112049, 0xeba }, + { 0x112149, 0xeba }, + { 0x113049, 0xeba }, + { 0x113149, 0xeba }, + { 0x210049, 0xeba }, + { 0x210149, 0xeba }, + { 0x211049, 0xeba }, + { 0x211149, 0xeba }, + { 0x212049, 0xeba }, + { 0x212149, 0xeba }, + { 0x213049, 0xeba }, + { 0x213149, 0xeba }, + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + { 0x20018, 0x3 }, + { 0x20075, 0x4 }, + { 0x20050, 0x0 }, + { 0x20008, 0x2ee }, + { 0x120008, 0x64 }, + { 0x220008, 0x19 }, + { 0x20088, 0x9 }, + { 0x200b2, 0xdc }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x12043, 0x5a1 }, + { 0x12143, 0x5a1 }, + { 0x13043, 0x5a1 }, + { 0x13143, 0x5a1 }, + { 0x1200b2, 0xdc }, + { 0x110043, 0x5a1 }, + { 0x110143, 0x5a1 }, + { 0x111043, 0x5a1 }, + { 0x111143, 0x5a1 }, + { 0x112043, 0x5a1 }, + { 0x112143, 0x5a1 }, + { 0x113043, 0x5a1 }, + { 0x113143, 0x5a1 }, + { 0x2200b2, 0xdc }, + { 0x210043, 0x5a1 }, + { 0x210143, 0x5a1 }, + { 0x211043, 0x5a1 }, + { 0x211143, 0x5a1 }, + { 0x212043, 0x5a1 }, + { 0x212143, 0x5a1 }, + { 0x213043, 0x5a1 }, + { 0x213143, 0x5a1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x2200fa, 0x1 }, + { 0x20019, 0x1 }, + { 0x120019, 0x1 }, + { 0x220019, 0x1 }, + { 0x200f0, 0x660 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5665 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x22002d, 0x0 }, + { 0x200c7, 0x21 }, + { 0x1200c7, 0x21 }, + { 0x2200c7, 0x21 }, + { 0x200ca, 0x24 }, + { 0x1200ca, 0x24 }, + { 0x2200ca, 0x24 }, +}; + +/* ddr phy trained csr */ +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + { 0x200b2, 0x0 }, + { 0x1200b2, 0x0 }, + { 0x2200b2, 0x0 }, + { 0x200cb, 0x0 }, + { 0x10043, 0x0 }, + { 0x110043, 0x0 }, + { 0x210043, 0x0 }, + { 0x10143, 0x0 }, + { 0x110143, 0x0 }, + { 0x210143, 0x0 }, + { 0x11043, 0x0 }, + { 0x111043, 0x0 }, + { 0x211043, 0x0 }, + { 0x11143, 0x0 }, + { 0x111143, 0x0 }, + { 0x211143, 0x0 }, + { 0x12043, 0x0 }, + { 0x112043, 0x0 }, + { 0x212043, 0x0 }, + { 0x12143, 0x0 }, + { 0x112143, 0x0 }, + { 0x212143, 0x0 }, + { 0x13043, 0x0 }, + { 0x113043, 0x0 }, + { 0x213043, 0x0 }, + { 0x13143, 0x0 }, + { 0x113143, 0x0 }, + { 0x213143, 0x0 }, + { 0x80, 0x0 }, + { 0x100080, 0x0 }, + { 0x200080, 0x0 }, + { 0x1080, 0x0 }, + { 0x101080, 0x0 }, + { 0x201080, 0x0 }, + { 0x2080, 0x0 }, + { 0x102080, 0x0 }, + { 0x202080, 0x0 }, + { 0x3080, 0x0 }, + { 0x103080, 0x0 }, + { 0x203080, 0x0 }, + { 0x4080, 0x0 }, + { 0x104080, 0x0 }, + { 0x204080, 0x0 }, + { 0x5080, 0x0 }, + { 0x105080, 0x0 }, + { 0x205080, 0x0 }, + { 0x6080, 0x0 }, + { 0x106080, 0x0 }, + { 0x206080, 0x0 }, + { 0x7080, 0x0 }, + { 0x107080, 0x0 }, + { 0x207080, 0x0 }, + { 0x8080, 0x0 }, + { 0x108080, 0x0 }, + { 0x208080, 0x0 }, + { 0x9080, 0x0 }, + { 0x109080, 0x0 }, + { 0x209080, 0x0 }, + { 0x10080, 0x0 }, + { 0x110080, 0x0 }, + { 0x210080, 0x0 }, + { 0x10180, 0x0 }, + { 0x110180, 0x0 }, + { 0x210180, 0x0 }, + { 0x11080, 0x0 }, + { 0x111080, 0x0 }, + { 0x211080, 0x0 }, + { 0x11180, 0x0 }, + { 0x111180, 0x0 }, + { 0x211180, 0x0 }, + { 0x12080, 0x0 }, + { 0x112080, 0x0 }, + { 0x212080, 0x0 }, + { 0x12180, 0x0 }, + { 0x112180, 0x0 }, + { 0x212180, 0x0 }, + { 0x13080, 0x0 }, + { 0x113080, 0x0 }, + { 0x213080, 0x0 }, + { 0x13180, 0x0 }, + { 0x113180, 0x0 }, + { 0x213180, 0x0 }, + { 0x10081, 0x0 }, + { 0x110081, 0x0 }, + { 0x210081, 0x0 }, + { 0x10181, 0x0 }, + { 0x110181, 0x0 }, + { 0x210181, 0x0 }, + { 0x11081, 0x0 }, + { 0x111081, 0x0 }, + { 0x211081, 0x0 }, + { 0x11181, 0x0 }, + { 0x111181, 0x0 }, + { 0x211181, 0x0 }, + { 0x12081, 0x0 }, + { 0x112081, 0x0 }, + { 0x212081, 0x0 }, + { 0x12181, 0x0 }, + { 0x112181, 0x0 }, + { 0x212181, 0x0 }, + { 0x13081, 0x0 }, + { 0x113081, 0x0 }, + { 0x213081, 0x0 }, + { 0x13181, 0x0 }, + { 0x113181, 0x0 }, + { 0x213181, 0x0 }, + { 0x100d0, 0x0 }, + { 0x1100d0, 0x0 }, + { 0x2100d0, 0x0 }, + { 0x101d0, 0x0 }, + { 0x1101d0, 0x0 }, + { 0x2101d0, 0x0 }, + { 0x110d0, 0x0 }, + { 0x1110d0, 0x0 }, + { 0x2110d0, 0x0 }, + { 0x111d0, 0x0 }, + { 0x1111d0, 0x0 }, + { 0x2111d0, 0x0 }, + { 0x120d0, 0x0 }, + { 0x1120d0, 0x0 }, + { 0x2120d0, 0x0 }, + { 0x121d0, 0x0 }, + { 0x1121d0, 0x0 }, + { 0x2121d0, 0x0 }, + { 0x130d0, 0x0 }, + { 0x1130d0, 0x0 }, + { 0x2130d0, 0x0 }, + { 0x131d0, 0x0 }, + { 0x1131d0, 0x0 }, + { 0x2131d0, 0x0 }, + { 0x100d1, 0x0 }, + { 0x1100d1, 0x0 }, + { 0x2100d1, 0x0 }, + { 0x101d1, 0x0 }, + { 0x1101d1, 0x0 }, + { 0x2101d1, 0x0 }, + { 0x110d1, 0x0 }, + { 0x1110d1, 0x0 }, + { 0x2110d1, 0x0 }, + { 0x111d1, 0x0 }, + { 0x1111d1, 0x0 }, + { 0x2111d1, 0x0 }, + { 0x120d1, 0x0 }, + { 0x1120d1, 0x0 }, + { 0x2120d1, 0x0 }, + { 0x121d1, 0x0 }, + { 0x1121d1, 0x0 }, + { 0x2121d1, 0x0 }, + { 0x130d1, 0x0 }, + { 0x1130d1, 0x0 }, + { 0x2130d1, 0x0 }, + { 0x131d1, 0x0 }, + { 0x1131d1, 0x0 }, + { 0x2131d1, 0x0 }, + { 0x10068, 0x0 }, + { 0x10168, 0x0 }, + { 0x10268, 0x0 }, + { 0x10368, 0x0 }, + { 0x10468, 0x0 }, + { 0x10568, 0x0 }, + { 0x10668, 0x0 }, + { 0x10768, 0x0 }, + { 0x10868, 0x0 }, + { 0x11068, 0x0 }, + { 0x11168, 0x0 }, + { 0x11268, 0x0 }, + { 0x11368, 0x0 }, + { 0x11468, 0x0 }, + { 0x11568, 0x0 }, + { 0x11668, 0x0 }, + { 0x11768, 0x0 }, + { 0x11868, 0x0 }, + { 0x12068, 0x0 }, + { 0x12168, 0x0 }, + { 0x12268, 0x0 }, + { 0x12368, 0x0 }, + { 0x12468, 0x0 }, + { 0x12568, 0x0 }, + { 0x12668, 0x0 }, + { 0x12768, 0x0 }, + { 0x12868, 0x0 }, + { 0x13068, 0x0 }, + { 0x13168, 0x0 }, + { 0x13268, 0x0 }, + { 0x13368, 0x0 }, + { 0x13468, 0x0 }, + { 0x13568, 0x0 }, + { 0x13668, 0x0 }, + { 0x13768, 0x0 }, + { 0x13868, 0x0 }, + { 0x10069, 0x0 }, + { 0x10169, 0x0 }, + { 0x10269, 0x0 }, + { 0x10369, 0x0 }, + { 0x10469, 0x0 }, + { 0x10569, 0x0 }, + { 0x10669, 0x0 }, + { 0x10769, 0x0 }, + { 0x10869, 0x0 }, + { 0x11069, 0x0 }, + { 0x11169, 0x0 }, + { 0x11269, 0x0 }, + { 0x11369, 0x0 }, + { 0x11469, 0x0 }, + { 0x11569, 0x0 }, + { 0x11669, 0x0 }, + { 0x11769, 0x0 }, + { 0x11869, 0x0 }, + { 0x12069, 0x0 }, + { 0x12169, 0x0 }, + { 0x12269, 0x0 }, + { 0x12369, 0x0 }, + { 0x12469, 0x0 }, + { 0x12569, 0x0 }, + { 0x12669, 0x0 }, + { 0x12769, 0x0 }, + { 0x12869, 0x0 }, + { 0x13069, 0x0 }, + { 0x13169, 0x0 }, + { 0x13269, 0x0 }, + { 0x13369, 0x0 }, + { 0x13469, 0x0 }, + { 0x13569, 0x0 }, + { 0x13669, 0x0 }, + { 0x13769, 0x0 }, + { 0x13869, 0x0 }, + { 0x1008c, 0x0 }, + { 0x11008c, 0x0 }, + { 0x21008c, 0x0 }, + { 0x1018c, 0x0 }, + { 0x11018c, 0x0 }, + { 0x21018c, 0x0 }, + { 0x1108c, 0x0 }, + { 0x11108c, 0x0 }, + { 0x21108c, 0x0 }, + { 0x1118c, 0x0 }, + { 0x11118c, 0x0 }, + { 0x21118c, 0x0 }, + { 0x1208c, 0x0 }, + { 0x11208c, 0x0 }, + { 0x21208c, 0x0 }, + { 0x1218c, 0x0 }, + { 0x11218c, 0x0 }, + { 0x21218c, 0x0 }, + { 0x1308c, 0x0 }, + { 0x11308c, 0x0 }, + { 0x21308c, 0x0 }, + { 0x1318c, 0x0 }, + { 0x11318c, 0x0 }, + { 0x21318c, 0x0 }, + { 0x1008d, 0x0 }, + { 0x11008d, 0x0 }, + { 0x21008d, 0x0 }, + { 0x1018d, 0x0 }, + { 0x11018d, 0x0 }, + { 0x21018d, 0x0 }, + { 0x1108d, 0x0 }, + { 0x11108d, 0x0 }, + { 0x21108d, 0x0 }, + { 0x1118d, 0x0 }, + { 0x11118d, 0x0 }, + { 0x21118d, 0x0 }, + { 0x1208d, 0x0 }, + { 0x11208d, 0x0 }, + { 0x21208d, 0x0 }, + { 0x1218d, 0x0 }, + { 0x11218d, 0x0 }, + { 0x21218d, 0x0 }, + { 0x1308d, 0x0 }, + { 0x11308d, 0x0 }, + { 0x21308d, 0x0 }, + { 0x1318d, 0x0 }, + { 0x11318d, 0x0 }, + { 0x21318d, 0x0 }, + { 0x100c0, 0x0 }, + { 0x1100c0, 0x0 }, + { 0x2100c0, 0x0 }, + { 0x101c0, 0x0 }, + { 0x1101c0, 0x0 }, + { 0x2101c0, 0x0 }, + { 0x102c0, 0x0 }, + { 0x1102c0, 0x0 }, + { 0x2102c0, 0x0 }, + { 0x103c0, 0x0 }, + { 0x1103c0, 0x0 }, + { 0x2103c0, 0x0 }, + { 0x104c0, 0x0 }, + { 0x1104c0, 0x0 }, + { 0x2104c0, 0x0 }, + { 0x105c0, 0x0 }, + { 0x1105c0, 0x0 }, + { 0x2105c0, 0x0 }, + { 0x106c0, 0x0 }, + { 0x1106c0, 0x0 }, + { 0x2106c0, 0x0 }, + { 0x107c0, 0x0 }, + { 0x1107c0, 0x0 }, + { 0x2107c0, 0x0 }, + { 0x108c0, 0x0 }, + { 0x1108c0, 0x0 }, + { 0x2108c0, 0x0 }, + { 0x110c0, 0x0 }, + { 0x1110c0, 0x0 }, + { 0x2110c0, 0x0 }, + { 0x111c0, 0x0 }, + { 0x1111c0, 0x0 }, + { 0x2111c0, 0x0 }, + { 0x112c0, 0x0 }, + { 0x1112c0, 0x0 }, + { 0x2112c0, 0x0 }, + { 0x113c0, 0x0 }, + { 0x1113c0, 0x0 }, + { 0x2113c0, 0x0 }, + { 0x114c0, 0x0 }, + { 0x1114c0, 0x0 }, + { 0x2114c0, 0x0 }, + { 0x115c0, 0x0 }, + { 0x1115c0, 0x0 }, + { 0x2115c0, 0x0 }, + { 0x116c0, 0x0 }, + { 0x1116c0, 0x0 }, + { 0x2116c0, 0x0 }, + { 0x117c0, 0x0 }, + { 0x1117c0, 0x0 }, + { 0x2117c0, 0x0 }, + { 0x118c0, 0x0 }, + { 0x1118c0, 0x0 }, + { 0x2118c0, 0x0 }, + { 0x120c0, 0x0 }, + { 0x1120c0, 0x0 }, + { 0x2120c0, 0x0 }, + { 0x121c0, 0x0 }, + { 0x1121c0, 0x0 }, + { 0x2121c0, 0x0 }, + { 0x122c0, 0x0 }, + { 0x1122c0, 0x0 }, + { 0x2122c0, 0x0 }, + { 0x123c0, 0x0 }, + { 0x1123c0, 0x0 }, + { 0x2123c0, 0x0 }, + { 0x124c0, 0x0 }, + { 0x1124c0, 0x0 }, + { 0x2124c0, 0x0 }, + { 0x125c0, 0x0 }, + { 0x1125c0, 0x0 }, + { 0x2125c0, 0x0 }, + { 0x126c0, 0x0 }, + { 0x1126c0, 0x0 }, + { 0x2126c0, 0x0 }, + { 0x127c0, 0x0 }, + { 0x1127c0, 0x0 }, + { 0x2127c0, 0x0 }, + { 0x128c0, 0x0 }, + { 0x1128c0, 0x0 }, + { 0x2128c0, 0x0 }, + { 0x130c0, 0x0 }, + { 0x1130c0, 0x0 }, + { 0x2130c0, 0x0 }, + { 0x131c0, 0x0 }, + { 0x1131c0, 0x0 }, + { 0x2131c0, 0x0 }, + { 0x132c0, 0x0 }, + { 0x1132c0, 0x0 }, + { 0x2132c0, 0x0 }, + { 0x133c0, 0x0 }, + { 0x1133c0, 0x0 }, + { 0x2133c0, 0x0 }, + { 0x134c0, 0x0 }, + { 0x1134c0, 0x0 }, + { 0x2134c0, 0x0 }, + { 0x135c0, 0x0 }, + { 0x1135c0, 0x0 }, + { 0x2135c0, 0x0 }, + { 0x136c0, 0x0 }, + { 0x1136c0, 0x0 }, + { 0x2136c0, 0x0 }, + { 0x137c0, 0x0 }, + { 0x1137c0, 0x0 }, + { 0x2137c0, 0x0 }, + { 0x138c0, 0x0 }, + { 0x1138c0, 0x0 }, + { 0x2138c0, 0x0 }, + { 0x100c1, 0x0 }, + { 0x1100c1, 0x0 }, + { 0x2100c1, 0x0 }, + { 0x101c1, 0x0 }, + { 0x1101c1, 0x0 }, + { 0x2101c1, 0x0 }, + { 0x102c1, 0x0 }, + { 0x1102c1, 0x0 }, + { 0x2102c1, 0x0 }, + { 0x103c1, 0x0 }, + { 0x1103c1, 0x0 }, + { 0x2103c1, 0x0 }, + { 0x104c1, 0x0 }, + { 0x1104c1, 0x0 }, + { 0x2104c1, 0x0 }, + { 0x105c1, 0x0 }, + { 0x1105c1, 0x0 }, + { 0x2105c1, 0x0 }, + { 0x106c1, 0x0 }, + { 0x1106c1, 0x0 }, + { 0x2106c1, 0x0 }, + { 0x107c1, 0x0 }, + { 0x1107c1, 0x0 }, + { 0x2107c1, 0x0 }, + { 0x108c1, 0x0 }, + { 0x1108c1, 0x0 }, + { 0x2108c1, 0x0 }, + { 0x110c1, 0x0 }, + { 0x1110c1, 0x0 }, + { 0x2110c1, 0x0 }, + { 0x111c1, 0x0 }, + { 0x1111c1, 0x0 }, + { 0x2111c1, 0x0 }, + { 0x112c1, 0x0 }, + { 0x1112c1, 0x0 }, + { 0x2112c1, 0x0 }, + { 0x113c1, 0x0 }, + { 0x1113c1, 0x0 }, + { 0x2113c1, 0x0 }, + { 0x114c1, 0x0 }, + { 0x1114c1, 0x0 }, + { 0x2114c1, 0x0 }, + { 0x115c1, 0x0 }, + { 0x1115c1, 0x0 }, + { 0x2115c1, 0x0 }, + { 0x116c1, 0x0 }, + { 0x1116c1, 0x0 }, + { 0x2116c1, 0x0 }, + { 0x117c1, 0x0 }, + { 0x1117c1, 0x0 }, + { 0x2117c1, 0x0 }, + { 0x118c1, 0x0 }, + { 0x1118c1, 0x0 }, + { 0x2118c1, 0x0 }, + { 0x120c1, 0x0 }, + { 0x1120c1, 0x0 }, + { 0x2120c1, 0x0 }, + { 0x121c1, 0x0 }, + { 0x1121c1, 0x0 }, + { 0x2121c1, 0x0 }, + { 0x122c1, 0x0 }, + { 0x1122c1, 0x0 }, + { 0x2122c1, 0x0 }, + { 0x123c1, 0x0 }, + { 0x1123c1, 0x0 }, + { 0x2123c1, 0x0 }, + { 0x124c1, 0x0 }, + { 0x1124c1, 0x0 }, + { 0x2124c1, 0x0 }, + { 0x125c1, 0x0 }, + { 0x1125c1, 0x0 }, + { 0x2125c1, 0x0 }, + { 0x126c1, 0x0 }, + { 0x1126c1, 0x0 }, + { 0x2126c1, 0x0 }, + { 0x127c1, 0x0 }, + { 0x1127c1, 0x0 }, + { 0x2127c1, 0x0 }, + { 0x128c1, 0x0 }, + { 0x1128c1, 0x0 }, + { 0x2128c1, 0x0 }, + { 0x130c1, 0x0 }, + { 0x1130c1, 0x0 }, + { 0x2130c1, 0x0 }, + { 0x131c1, 0x0 }, + { 0x1131c1, 0x0 }, + { 0x2131c1, 0x0 }, + { 0x132c1, 0x0 }, + { 0x1132c1, 0x0 }, + { 0x2132c1, 0x0 }, + { 0x133c1, 0x0 }, + { 0x1133c1, 0x0 }, + { 0x2133c1, 0x0 }, + { 0x134c1, 0x0 }, + { 0x1134c1, 0x0 }, + { 0x2134c1, 0x0 }, + { 0x135c1, 0x0 }, + { 0x1135c1, 0x0 }, + { 0x2135c1, 0x0 }, + { 0x136c1, 0x0 }, + { 0x1136c1, 0x0 }, + { 0x2136c1, 0x0 }, + { 0x137c1, 0x0 }, + { 0x1137c1, 0x0 }, + { 0x2137c1, 0x0 }, + { 0x138c1, 0x0 }, + { 0x1138c1, 0x0 }, + { 0x2138c1, 0x0 }, + { 0x10020, 0x0 }, + { 0x110020, 0x0 }, + { 0x210020, 0x0 }, + { 0x11020, 0x0 }, + { 0x111020, 0x0 }, + { 0x211020, 0x0 }, + { 0x12020, 0x0 }, + { 0x112020, 0x0 }, + { 0x212020, 0x0 }, + { 0x13020, 0x0 }, + { 0x113020, 0x0 }, + { 0x213020, 0x0 }, + { 0x20072, 0x0 }, + { 0x20073, 0x0 }, + { 0x20074, 0x0 }, + { 0x100aa, 0x0 }, + { 0x110aa, 0x0 }, + { 0x120aa, 0x0 }, + { 0x130aa, 0x0 }, + { 0x20010, 0x0 }, + { 0x120010, 0x0 }, + { 0x220010, 0x0 }, + { 0x20011, 0x0 }, + { 0x120011, 0x0 }, + { 0x220011, 0x0 }, + { 0x100ae, 0x0 }, + { 0x1100ae, 0x0 }, + { 0x2100ae, 0x0 }, + { 0x100af, 0x0 }, + { 0x1100af, 0x0 }, + { 0x2100af, 0x0 }, + { 0x110ae, 0x0 }, + { 0x1110ae, 0x0 }, + { 0x2110ae, 0x0 }, + { 0x110af, 0x0 }, + { 0x1110af, 0x0 }, + { 0x2110af, 0x0 }, + { 0x120ae, 0x0 }, + { 0x1120ae, 0x0 }, + { 0x2120ae, 0x0 }, + { 0x120af, 0x0 }, + { 0x1120af, 0x0 }, + { 0x2120af, 0x0 }, + { 0x130ae, 0x0 }, + { 0x1130ae, 0x0 }, + { 0x2130ae, 0x0 }, + { 0x130af, 0x0 }, + { 0x1130af, 0x0 }, + { 0x2130af, 0x0 }, + { 0x20020, 0x0 }, + { 0x120020, 0x0 }, + { 0x220020, 0x0 }, + { 0x100a0, 0x0 }, + { 0x100a1, 0x0 }, + { 0x100a2, 0x0 }, + { 0x100a3, 0x0 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x0 }, + { 0x100a6, 0x0 }, + { 0x100a7, 0x0 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x0 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x0 }, + { 0x110a4, 0x0 }, + { 0x110a5, 0x0 }, + { 0x110a6, 0x0 }, + { 0x110a7, 0x0 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x0 }, + { 0x120a2, 0x0 }, + { 0x120a3, 0x0 }, + { 0x120a4, 0x0 }, + { 0x120a5, 0x0 }, + { 0x120a6, 0x0 }, + { 0x120a7, 0x0 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x0 }, + { 0x130a2, 0x0 }, + { 0x130a3, 0x0 }, + { 0x130a4, 0x0 }, + { 0x130a5, 0x0 }, + { 0x130a6, 0x0 }, + { 0x130a7, 0x0 }, + { 0x2007c, 0x0 }, + { 0x12007c, 0x0 }, + { 0x22007c, 0x0 }, + { 0x2007d, 0x0 }, + { 0x12007d, 0x0 }, + { 0x22007d, 0x0 }, + { 0x400fd, 0x0 }, + { 0x400c0, 0x0 }, + { 0x90201, 0x0 }, + { 0x190201, 0x0 }, + { 0x290201, 0x0 }, + { 0x90202, 0x0 }, + { 0x190202, 0x0 }, + { 0x290202, 0x0 }, + { 0x90203, 0x0 }, + { 0x190203, 0x0 }, + { 0x290203, 0x0 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x90205, 0x0 }, + { 0x190205, 0x0 }, + { 0x290205, 0x0 }, + { 0x90206, 0x0 }, + { 0x190206, 0x0 }, + { 0x290206, 0x0 }, + { 0x90207, 0x0 }, + { 0x190207, 0x0 }, + { 0x290207, 0x0 }, + { 0x90208, 0x0 }, + { 0x190208, 0x0 }, + { 0x290208, 0x0 }, + { 0x10062, 0x0 }, + { 0x10162, 0x0 }, + { 0x10262, 0x0 }, + { 0x10362, 0x0 }, + { 0x10462, 0x0 }, + { 0x10562, 0x0 }, + { 0x10662, 0x0 }, + { 0x10762, 0x0 }, + { 0x10862, 0x0 }, + { 0x11062, 0x0 }, + { 0x11162, 0x0 }, + { 0x11262, 0x0 }, + { 0x11362, 0x0 }, + { 0x11462, 0x0 }, + { 0x11562, 0x0 }, + { 0x11662, 0x0 }, + { 0x11762, 0x0 }, + { 0x11862, 0x0 }, + { 0x12062, 0x0 }, + { 0x12162, 0x0 }, + { 0x12262, 0x0 }, + { 0x12362, 0x0 }, + { 0x12462, 0x0 }, + { 0x12562, 0x0 }, + { 0x12662, 0x0 }, + { 0x12762, 0x0 }, + { 0x12862, 0x0 }, + { 0x13062, 0x0 }, + { 0x13162, 0x0 }, + { 0x13262, 0x0 }, + { 0x13362, 0x0 }, + { 0x13462, 0x0 }, + { 0x13562, 0x0 }, + { 0x13662, 0x0 }, + { 0x13762, 0x0 }, + { 0x13862, 0x0 }, + { 0x20077, 0x0 }, + { 0x10001, 0x0 }, + { 0x11001, 0x0 }, + { 0x12001, 0x0 }, + { 0x13001, 0x0 }, + { 0x10040, 0x0 }, + { 0x10140, 0x0 }, + { 0x10240, 0x0 }, + { 0x10340, 0x0 }, + { 0x10440, 0x0 }, + { 0x10540, 0x0 }, + { 0x10640, 0x0 }, + { 0x10740, 0x0 }, + { 0x10840, 0x0 }, + { 0x10030, 0x0 }, + { 0x10130, 0x0 }, + { 0x10230, 0x0 }, + { 0x10330, 0x0 }, + { 0x10430, 0x0 }, + { 0x10530, 0x0 }, + { 0x10630, 0x0 }, + { 0x10730, 0x0 }, + { 0x10830, 0x0 }, + { 0x11040, 0x0 }, + { 0x11140, 0x0 }, + { 0x11240, 0x0 }, + { 0x11340, 0x0 }, + { 0x11440, 0x0 }, + { 0x11540, 0x0 }, + { 0x11640, 0x0 }, + { 0x11740, 0x0 }, + { 0x11840, 0x0 }, + { 0x11030, 0x0 }, + { 0x11130, 0x0 }, + { 0x11230, 0x0 }, + { 0x11330, 0x0 }, + { 0x11430, 0x0 }, + { 0x11530, 0x0 }, + { 0x11630, 0x0 }, + { 0x11730, 0x0 }, + { 0x11830, 0x0 }, + { 0x12040, 0x0 }, + { 0x12140, 0x0 }, + { 0x12240, 0x0 }, + { 0x12340, 0x0 }, + { 0x12440, 0x0 }, + { 0x12540, 0x0 }, + { 0x12640, 0x0 }, + { 0x12740, 0x0 }, + { 0x12840, 0x0 }, + { 0x12030, 0x0 }, + { 0x12130, 0x0 }, + { 0x12230, 0x0 }, + { 0x12330, 0x0 }, + { 0x12430, 0x0 }, + { 0x12530, 0x0 }, + { 0x12630, 0x0 }, + { 0x12730, 0x0 }, + { 0x12830, 0x0 }, + { 0x13040, 0x0 }, + { 0x13140, 0x0 }, + { 0x13240, 0x0 }, + { 0x13340, 0x0 }, + { 0x13440, 0x0 }, + { 0x13540, 0x0 }, + { 0x13640, 0x0 }, + { 0x13740, 0x0 }, + { 0x13840, 0x0 }, + { 0x13030, 0x0 }, + { 0x13130, 0x0 }, + { 0x13230, 0x0 }, + { 0x13330, 0x0 }, + { 0x13430, 0x0 }, + { 0x13530, 0x0 }, + { 0x13630, 0x0 }, + { 0x13730, 0x0 }, + { 0x13830, 0x0 }, +}; + +/* P0 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xbb8 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x11 }, + { 0x54008, 0x131f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x54012, 0x110 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d00 }, + { 0x5401e, 0x6 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d00 }, + { 0x54024, 0x6 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0xd400 }, + { 0x54033, 0x312d }, + { 0x54034, 0x6600 }, + { 0x54035, 0x4d }, + { 0x54036, 0x4d }, + { 0x54037, 0x600 }, + { 0x54038, 0xd400 }, + { 0x54039, 0x312d }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x4d }, + { 0x5403c, 0x4d }, + { 0x5403d, 0x600 }, + { 0xd0000, 0x1 }, +}; + +/* P1 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x101 }, + { 0x54003, 0x190 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x11 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x54012, 0x110 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d00 }, + { 0x5401e, 0x6 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d00 }, + { 0x54024, 0x6 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3100 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x4d }, + { 0x54036, 0x4d }, + { 0x54037, 0x600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3100 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x4d }, + { 0x5403c, 0x4d }, + { 0x5403d, 0x600 }, + { 0xd0000, 0x1 }, +}; + +/* P2 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp2_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x102 }, + { 0x54003, 0x64 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x11 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x54012, 0x110 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d00 }, + { 0x5401e, 0x6 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d00 }, + { 0x54024, 0x6 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3100 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x4d }, + { 0x54036, 0x4d }, + { 0x54037, 0x600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3100 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x4d }, + { 0x5403c, 0x4d }, + { 0x5403d, 0x600 }, + { 0xd0000, 0x1 }, +}; + +/* P0 2D message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xbb8 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x11 }, + { 0x54008, 0x61 }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54010, 0x1f7f }, + { 0x54012, 0x110 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d00 }, + { 0x5401e, 0x6 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d00 }, + { 0x54024, 0x6 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0xd400 }, + { 0x54033, 0x312d }, + { 0x54034, 0x6600 }, + { 0x54035, 0x4d }, + { 0x54036, 0x4d }, + { 0x54037, 0x600 }, + { 0x54038, 0xd400 }, + { 0x54039, 0x312d }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x4d }, + { 0x5403c, 0x4d }, + { 0x5403d, 0x600 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x0 }, + { 0x90033, 0xe8 }, + { 0x90034, 0x109 }, + { 0x90035, 0x2 }, + { 0x90036, 0x10 }, + { 0x90037, 0x139 }, + { 0x90038, 0xf }, + { 0x90039, 0x7c0 }, + { 0x9003a, 0x139 }, + { 0x9003b, 0x44 }, + { 0x9003c, 0x630 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x14f }, + { 0x9003f, 0x630 }, + { 0x90040, 0x159 }, + { 0x90041, 0x47 }, + { 0x90042, 0x630 }, + { 0x90043, 0x149 }, + { 0x90044, 0x4f }, + { 0x90045, 0x630 }, + { 0x90046, 0x179 }, + { 0x90047, 0x8 }, + { 0x90048, 0xe0 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x7c8 }, + { 0x9004c, 0x109 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x1 }, + { 0x9004f, 0x8 }, + { 0x90050, 0x0 }, + { 0x90051, 0x45a }, + { 0x90052, 0x9 }, + { 0x90053, 0x0 }, + { 0x90054, 0x448 }, + { 0x90055, 0x109 }, + { 0x90056, 0x40 }, + { 0x90057, 0x630 }, + { 0x90058, 0x179 }, + { 0x90059, 0x1 }, + { 0x9005a, 0x618 }, + { 0x9005b, 0x109 }, + { 0x9005c, 0x40c0 }, + { 0x9005d, 0x630 }, + { 0x9005e, 0x149 }, + { 0x9005f, 0x8 }, + { 0x90060, 0x4 }, + { 0x90061, 0x48 }, + { 0x90062, 0x4040 }, + { 0x90063, 0x630 }, + { 0x90064, 0x149 }, + { 0x90065, 0x0 }, + { 0x90066, 0x4 }, + { 0x90067, 0x48 }, + { 0x90068, 0x40 }, + { 0x90069, 0x630 }, + { 0x9006a, 0x149 }, + { 0x9006b, 0x10 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x18 }, + { 0x9006e, 0x0 }, + { 0x9006f, 0x4 }, + { 0x90070, 0x78 }, + { 0x90071, 0x549 }, + { 0x90072, 0x630 }, + { 0x90073, 0x159 }, + { 0x90074, 0xd49 }, + { 0x90075, 0x630 }, + { 0x90076, 0x159 }, + { 0x90077, 0x94a }, + { 0x90078, 0x630 }, + { 0x90079, 0x159 }, + { 0x9007a, 0x441 }, + { 0x9007b, 0x630 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x42 }, + { 0x9007e, 0x630 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x1 }, + { 0x90081, 0x630 }, + { 0x90082, 0x149 }, + { 0x90083, 0x0 }, + { 0x90084, 0xe0 }, + { 0x90085, 0x109 }, + { 0x90086, 0xa }, + { 0x90087, 0x10 }, + { 0x90088, 0x109 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x149 }, + { 0x9008c, 0x9 }, + { 0x9008d, 0x3c0 }, + { 0x9008e, 0x159 }, + { 0x9008f, 0x18 }, + { 0x90090, 0x10 }, + { 0x90091, 0x109 }, + { 0x90092, 0x0 }, + { 0x90093, 0x3c0 }, + { 0x90094, 0x109 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x48 }, + { 0x90098, 0x18 }, + { 0x90099, 0x4 }, + { 0x9009a, 0x58 }, + { 0x9009b, 0xa }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x2 }, + { 0x9009f, 0x10 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x5 }, + { 0x900a2, 0x7c0 }, + { 0x900a3, 0x109 }, + { 0x900a4, 0x10 }, + { 0x900a5, 0x10 }, + { 0x900a6, 0x109 }, + { 0x40000, 0x811 }, + { 0x40020, 0x880 }, + { 0x40040, 0x0 }, + { 0x40060, 0x0 }, + { 0x40001, 0x4008 }, + { 0x40021, 0x83 }, + { 0x40041, 0x4f }, + { 0x40061, 0x0 }, + { 0x40002, 0x4040 }, + { 0x40022, 0x83 }, + { 0x40042, 0x51 }, + { 0x40062, 0x0 }, + { 0x40003, 0x811 }, + { 0x40023, 0x880 }, + { 0x40043, 0x0 }, + { 0x40063, 0x0 }, + { 0x40004, 0x720 }, + { 0x40024, 0xf }, + { 0x40044, 0x1740 }, + { 0x40064, 0x0 }, + { 0x40005, 0x16 }, + { 0x40025, 0x83 }, + { 0x40045, 0x4b }, + { 0x40065, 0x0 }, + { 0x40006, 0x716 }, + { 0x40026, 0xf }, + { 0x40046, 0x2001 }, + { 0x40066, 0x0 }, + { 0x40007, 0x716 }, + { 0x40027, 0xf }, + { 0x40047, 0x2800 }, + { 0x40067, 0x0 }, + { 0x40008, 0x716 }, + { 0x40028, 0xf }, + { 0x40048, 0xf00 }, + { 0x40068, 0x0 }, + { 0x40009, 0x720 }, + { 0x40029, 0xf }, + { 0x40049, 0x1400 }, + { 0x40069, 0x0 }, + { 0x4000a, 0xe08 }, + { 0x4002a, 0xc15 }, + { 0x4004a, 0x0 }, + { 0x4006a, 0x0 }, + { 0x4000b, 0x623 }, + { 0x4002b, 0x15 }, + { 0x4004b, 0x0 }, + { 0x4006b, 0x0 }, + { 0x4000c, 0x4028 }, + { 0x4002c, 0x80 }, + { 0x4004c, 0x0 }, + { 0x4006c, 0x0 }, + { 0x4000d, 0xe08 }, + { 0x4002d, 0xc1a }, + { 0x4004d, 0x0 }, + { 0x4006d, 0x0 }, + { 0x4000e, 0x623 }, + { 0x4002e, 0x1a }, + { 0x4004e, 0x0 }, + { 0x4006e, 0x0 }, + { 0x4000f, 0x4040 }, + { 0x4002f, 0x80 }, + { 0x4004f, 0x0 }, + { 0x4006f, 0x0 }, + { 0x40010, 0x2604 }, + { 0x40030, 0x15 }, + { 0x40050, 0x0 }, + { 0x40070, 0x0 }, + { 0x40011, 0x708 }, + { 0x40031, 0x5 }, + { 0x40051, 0x0 }, + { 0x40071, 0x2002 }, + { 0x40012, 0x8 }, + { 0x40032, 0x80 }, + { 0x40052, 0x0 }, + { 0x40072, 0x0 }, + { 0x40013, 0x2604 }, + { 0x40033, 0x1a }, + { 0x40053, 0x0 }, + { 0x40073, 0x0 }, + { 0x40014, 0x708 }, + { 0x40034, 0xa }, + { 0x40054, 0x0 }, + { 0x40074, 0x2002 }, + { 0x40015, 0x4040 }, + { 0x40035, 0x80 }, + { 0x40055, 0x0 }, + { 0x40075, 0x0 }, + { 0x40016, 0x60a }, + { 0x40036, 0x15 }, + { 0x40056, 0x1200 }, + { 0x40076, 0x0 }, + { 0x40017, 0x61a }, + { 0x40037, 0x15 }, + { 0x40057, 0x1300 }, + { 0x40077, 0x0 }, + { 0x40018, 0x60a }, + { 0x40038, 0x1a }, + { 0x40058, 0x1200 }, + { 0x40078, 0x0 }, + { 0x40019, 0x642 }, + { 0x40039, 0x1a }, + { 0x40059, 0x1300 }, + { 0x40079, 0x0 }, + { 0x4001a, 0x4808 }, + { 0x4003a, 0x880 }, + { 0x4005a, 0x0 }, + { 0x4007a, 0x0 }, + { 0x900a7, 0x0 }, + { 0x900a8, 0x790 }, + { 0x900a9, 0x11a }, + { 0x900aa, 0x8 }, + { 0x900ab, 0x7aa }, + { 0x900ac, 0x2a }, + { 0x900ad, 0x10 }, + { 0x900ae, 0x7b2 }, + { 0x900af, 0x2a }, + { 0x900b0, 0x0 }, + { 0x900b1, 0x7c8 }, + { 0x900b2, 0x109 }, + { 0x900b3, 0x10 }, + { 0x900b4, 0x2a8 }, + { 0x900b5, 0x129 }, + { 0x900b6, 0x8 }, + { 0x900b7, 0x370 }, + { 0x900b8, 0x129 }, + { 0x900b9, 0xa }, + { 0x900ba, 0x3c8 }, + { 0x900bb, 0x1a9 }, + { 0x900bc, 0xc }, + { 0x900bd, 0x408 }, + { 0x900be, 0x199 }, + { 0x900bf, 0x14 }, + { 0x900c0, 0x790 }, + { 0x900c1, 0x11a }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x4 }, + { 0x900c4, 0x18 }, + { 0x900c5, 0xe }, + { 0x900c6, 0x408 }, + { 0x900c7, 0x199 }, + { 0x900c8, 0x8 }, + { 0x900c9, 0x8568 }, + { 0x900ca, 0x108 }, + { 0x900cb, 0x18 }, + { 0x900cc, 0x790 }, + { 0x900cd, 0x16a }, + { 0x900ce, 0x8 }, + { 0x900cf, 0x1d8 }, + { 0x900d0, 0x169 }, + { 0x900d1, 0x10 }, + { 0x900d2, 0x8558 }, + { 0x900d3, 0x168 }, + { 0x900d4, 0x70 }, + { 0x900d5, 0x788 }, + { 0x900d6, 0x16a }, + { 0x900d7, 0x1ff8 }, + { 0x900d8, 0x85a8 }, + { 0x900d9, 0x1e8 }, + { 0x900da, 0x50 }, + { 0x900db, 0x798 }, + { 0x900dc, 0x16a }, + { 0x900dd, 0x60 }, + { 0x900de, 0x7a0 }, + { 0x900df, 0x16a }, + { 0x900e0, 0x8 }, + { 0x900e1, 0x8310 }, + { 0x900e2, 0x168 }, + { 0x900e3, 0x8 }, + { 0x900e4, 0xa310 }, + { 0x900e5, 0x168 }, + { 0x900e6, 0xa }, + { 0x900e7, 0x408 }, + { 0x900e8, 0x169 }, + { 0x900e9, 0x6e }, + { 0x900ea, 0x0 }, + { 0x900eb, 0x68 }, + { 0x900ec, 0x0 }, + { 0x900ed, 0x408 }, + { 0x900ee, 0x169 }, + { 0x900ef, 0x0 }, + { 0x900f0, 0x8310 }, + { 0x900f1, 0x168 }, + { 0x900f2, 0x0 }, + { 0x900f3, 0xa310 }, + { 0x900f4, 0x168 }, + { 0x900f5, 0x1ff8 }, + { 0x900f6, 0x85a8 }, + { 0x900f7, 0x1e8 }, + { 0x900f8, 0x68 }, + { 0x900f9, 0x798 }, + { 0x900fa, 0x16a }, + { 0x900fb, 0x78 }, + { 0x900fc, 0x7a0 }, + { 0x900fd, 0x16a }, + { 0x900fe, 0x68 }, + { 0x900ff, 0x790 }, + { 0x90100, 0x16a }, + { 0x90101, 0x8 }, + { 0x90102, 0x8b10 }, + { 0x90103, 0x168 }, + { 0x90104, 0x8 }, + { 0x90105, 0xab10 }, + { 0x90106, 0x168 }, + { 0x90107, 0xa }, + { 0x90108, 0x408 }, + { 0x90109, 0x169 }, + { 0x9010a, 0x58 }, + { 0x9010b, 0x0 }, + { 0x9010c, 0x68 }, + { 0x9010d, 0x0 }, + { 0x9010e, 0x408 }, + { 0x9010f, 0x169 }, + { 0x90110, 0x0 }, + { 0x90111, 0x8b10 }, + { 0x90112, 0x168 }, + { 0x90113, 0x0 }, + { 0x90114, 0xab10 }, + { 0x90115, 0x168 }, + { 0x90116, 0x0 }, + { 0x90117, 0x1d8 }, + { 0x90118, 0x169 }, + { 0x90119, 0x80 }, + { 0x9011a, 0x790 }, + { 0x9011b, 0x16a }, + { 0x9011c, 0x18 }, + { 0x9011d, 0x7aa }, + { 0x9011e, 0x6a }, + { 0x9011f, 0xa }, + { 0x90120, 0x0 }, + { 0x90121, 0x1e9 }, + { 0x90122, 0x8 }, + { 0x90123, 0x8080 }, + { 0x90124, 0x108 }, + { 0x90125, 0xf }, + { 0x90126, 0x408 }, + { 0x90127, 0x169 }, + { 0x90128, 0xc }, + { 0x90129, 0x0 }, + { 0x9012a, 0x68 }, + { 0x9012b, 0x9 }, + { 0x9012c, 0x0 }, + { 0x9012d, 0x1a9 }, + { 0x9012e, 0x0 }, + { 0x9012f, 0x408 }, + { 0x90130, 0x169 }, + { 0x90131, 0x0 }, + { 0x90132, 0x8080 }, + { 0x90133, 0x108 }, + { 0x90134, 0x8 }, + { 0x90135, 0x7aa }, + { 0x90136, 0x6a }, + { 0x90137, 0x0 }, + { 0x90138, 0x8568 }, + { 0x90139, 0x108 }, + { 0x9013a, 0xb7 }, + { 0x9013b, 0x790 }, + { 0x9013c, 0x16a }, + { 0x9013d, 0x1f }, + { 0x9013e, 0x0 }, + { 0x9013f, 0x68 }, + { 0x90140, 0x8 }, + { 0x90141, 0x8558 }, + { 0x90142, 0x168 }, + { 0x90143, 0xf }, + { 0x90144, 0x408 }, + { 0x90145, 0x169 }, + { 0x90146, 0xc }, + { 0x90147, 0x0 }, + { 0x90148, 0x68 }, + { 0x90149, 0x0 }, + { 0x9014a, 0x408 }, + { 0x9014b, 0x169 }, + { 0x9014c, 0x0 }, + { 0x9014d, 0x8558 }, + { 0x9014e, 0x168 }, + { 0x9014f, 0x8 }, + { 0x90150, 0x3c8 }, + { 0x90151, 0x1a9 }, + { 0x90152, 0x3 }, + { 0x90153, 0x370 }, + { 0x90154, 0x129 }, + { 0x90155, 0x20 }, + { 0x90156, 0x2aa }, + { 0x90157, 0x9 }, + { 0x90158, 0x0 }, + { 0x90159, 0x400 }, + { 0x9015a, 0x10e }, + { 0x9015b, 0x8 }, + { 0x9015c, 0xe8 }, + { 0x9015d, 0x109 }, + { 0x9015e, 0x0 }, + { 0x9015f, 0x8140 }, + { 0x90160, 0x10c }, + { 0x90161, 0x10 }, + { 0x90162, 0x8138 }, + { 0x90163, 0x10c }, + { 0x90164, 0x8 }, + { 0x90165, 0x7c8 }, + { 0x90166, 0x101 }, + { 0x90167, 0x8 }, + { 0x90168, 0x0 }, + { 0x90169, 0x8 }, + { 0x9016a, 0x8 }, + { 0x9016b, 0x448 }, + { 0x9016c, 0x109 }, + { 0x9016d, 0xf }, + { 0x9016e, 0x7c0 }, + { 0x9016f, 0x109 }, + { 0x90170, 0x0 }, + { 0x90171, 0xe8 }, + { 0x90172, 0x109 }, + { 0x90173, 0x47 }, + { 0x90174, 0x630 }, + { 0x90175, 0x109 }, + { 0x90176, 0x8 }, + { 0x90177, 0x618 }, + { 0x90178, 0x109 }, + { 0x90179, 0x8 }, + { 0x9017a, 0xe0 }, + { 0x9017b, 0x109 }, + { 0x9017c, 0x0 }, + { 0x9017d, 0x7c8 }, + { 0x9017e, 0x109 }, + { 0x9017f, 0x8 }, + { 0x90180, 0x8140 }, + { 0x90181, 0x10c }, + { 0x90182, 0x0 }, + { 0x90183, 0x1 }, + { 0x90184, 0x8 }, + { 0x90185, 0x8 }, + { 0x90186, 0x4 }, + { 0x90187, 0x8 }, + { 0x90188, 0x8 }, + { 0x90189, 0x7c8 }, + { 0x9018a, 0x101 }, + { 0x90006, 0x0 }, + { 0x90007, 0x0 }, + { 0x90008, 0x8 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x0 }, + { 0x9000b, 0x0 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x9001f, 0x2a }, + { 0x90026, 0x6a }, + { 0x400d0, 0x0 }, + { 0x400d1, 0x101 }, + { 0x400d2, 0x105 }, + { 0x400d3, 0x107 }, + { 0x400d4, 0x10f }, + { 0x400d5, 0x202 }, + { 0x400d6, 0x20a }, + { 0x400d7, 0x20b }, + { 0x2003a, 0x2 }, + { 0x2000b, 0x5d }, + { 0x2000c, 0xbb }, + { 0x2000d, 0x753 }, + { 0x2000e, 0x2c }, + { 0x12000b, 0xc }, + { 0x12000c, 0x19 }, + { 0x12000d, 0xfa }, + { 0x12000e, 0x10 }, + { 0x22000b, 0x3 }, + { 0x22000c, 0x6 }, + { 0x22000d, 0x3e }, + { 0x22000e, 0x10 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0x60 }, + { 0x90013, 0x6152 }, + { 0x20010, 0x5a }, + { 0x20011, 0x3 }, + { 0x120010, 0x5a }, + { 0x120011, 0x3 }, + { 0x220010, 0x5a }, + { 0x220011, 0x3 }, + { 0x40080, 0xe0 }, + { 0x40081, 0x12 }, + { 0x40082, 0xe0 }, + { 0x40083, 0x12 }, + { 0x40084, 0xe0 }, + { 0x40085, 0x12 }, + { 0x140080, 0xe0 }, + { 0x140081, 0x12 }, + { 0x140082, 0xe0 }, + { 0x140083, 0x12 }, + { 0x140084, 0xe0 }, + { 0x140085, 0x12 }, + { 0x240080, 0xe0 }, + { 0x240081, 0x12 }, + { 0x240082, 0xe0 }, + { 0x240083, 0x12 }, + { 0x240084, 0xe0 }, + { 0x240085, 0x12 }, + { 0x400fd, 0xf }, + { 0x10011, 0x1 }, + { 0x10012, 0x1 }, + { 0x10013, 0x180 }, + { 0x10018, 0x1 }, + { 0x10002, 0x6209 }, + { 0x100b2, 0x1 }, + { 0x101b4, 0x1 }, + { 0x102b4, 0x1 }, + { 0x103b4, 0x1 }, + { 0x104b4, 0x1 }, + { 0x105b4, 0x1 }, + { 0x106b4, 0x1 }, + { 0x107b4, 0x1 }, + { 0x108b4, 0x1 }, + { 0x11011, 0x1 }, + { 0x11012, 0x1 }, + { 0x11013, 0x180 }, + { 0x11018, 0x1 }, + { 0x11002, 0x6209 }, + { 0x110b2, 0x1 }, + { 0x111b4, 0x1 }, + { 0x112b4, 0x1 }, + { 0x113b4, 0x1 }, + { 0x114b4, 0x1 }, + { 0x115b4, 0x1 }, + { 0x116b4, 0x1 }, + { 0x117b4, 0x1 }, + { 0x118b4, 0x1 }, + { 0x12011, 0x1 }, + { 0x12012, 0x1 }, + { 0x12013, 0x180 }, + { 0x12018, 0x1 }, + { 0x12002, 0x6209 }, + { 0x120b2, 0x1 }, + { 0x121b4, 0x1 }, + { 0x122b4, 0x1 }, + { 0x123b4, 0x1 }, + { 0x124b4, 0x1 }, + { 0x125b4, 0x1 }, + { 0x126b4, 0x1 }, + { 0x127b4, 0x1 }, + { 0x128b4, 0x1 }, + { 0x13011, 0x1 }, + { 0x13012, 0x1 }, + { 0x13013, 0x180 }, + { 0x13018, 0x1 }, + { 0x13002, 0x6209 }, + { 0x130b2, 0x1 }, + { 0x131b4, 0x1 }, + { 0x132b4, 0x1 }, + { 0x133b4, 0x1 }, + { 0x134b4, 0x1 }, + { 0x135b4, 0x1 }, + { 0x136b4, 0x1 }, + { 0x137b4, 0x1 }, + { 0x138b4, 0x1 }, + { 0x2003a, 0x2 }, + { 0xc0080, 0x2 }, + { 0xd0000, 0x1 } +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 3000mts 1D */ + .drate = 3000, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 3000mts 2D */ + .drate = 3000, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3000, 400, 100, }, +}; diff --git a/board/cloos/imx8mm_phg/spl.c b/board/cloos/imx8mm_phg/spl.c new file mode 100644 index 00000000000..e63904eade8 --- /dev/null +++ b/board/cloos/imx8mm_phg/spl.c @@ -0,0 +1,147 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int spl_board_boot_device(enum boot_device boot_dev_spl) +{ + switch (boot_dev_spl) { + case USB_BOOT: + return BOOT_DEVICE_BOARD; + case SD2_BOOT: + case MMC2_BOOT: + return BOOT_DEVICE_MMC1; + case SD3_BOOT: + case MMC3_BOOT: + return BOOT_DEVICE_MMC2; + default: + return BOOT_DEVICE_NONE; + } +} + +static void spl_dram_init(void) +{ + ddr_init(&dram_timing); +} + +void spl_board_init(void) +{ + if (is_usb_boot()) + puts("USB Boot\n"); + else + puts("Normal Boot\n"); +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif + +static int power_init_board(void) +{ + struct udevice *dev; + int ret; + + ret = pmic_get("pmic@25", &dev); + if (ret == -ENODEV) { + puts("No pmic\n"); + return 0; + } + if (ret != 0) + return ret; + + /* BUCKxOUT_DVS0/1 control BUCK123 output */ + pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); + + /* Buck 1 DVS control through PMIC_STBY_REQ */ + pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); + + /* Set DVS1 to 0.8V for suspend */ + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x10); + + /* increase VDD_DRAM to 0.95V for 3GHz DDR */ + pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x1C); + + /* VDD_DRAM needs off in suspend, set B1_ENMODE=10 (ON by PMIC_ON_REQ = H && PMIC_STBY_REQ = L) */ + pmic_reg_write(dev, PCA9450_BUCK3CTRL, 0x4a); + + /* set VDD_SNVS_0V8 from default 0.85V */ + pmic_reg_write(dev, PCA9450_LDO2CTRL, 0xC0); + + /* set WDOG_B_CFG to cold reset */ + pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1); + + return 0; +} + +void board_init_f(ulong dummy) +{ + struct udevice *dev; + int ret; + + arch_cpu_init(); + + init_uart_clk(1); + + timer_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + ret = spl_early_init(); + if (ret) { + debug("spl_early_init() failed: %d\n", ret); + hang(); + } + + ret = uclass_get_device_by_name(UCLASS_CLK, + "clock-controller@30380000", + &dev); + if (ret < 0) { + printf("Failed to find clock node. Check device tree\n"); + hang(); + } + + preloader_console_init(); + + enable_tzc380(); + + power_init_board(); + + /* DDR initialization */ + spl_dram_init(); + + board_init_r(NULL, 0); +} diff --git a/configs/imx8mm_phg_defconfig b/configs/imx8mm_phg_defconfig new file mode 100644 index 00000000000..2821b8837a9 --- /dev/null +++ b/configs/imx8mm_phg_defconfig @@ -0,0 +1,120 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_TEXT_BASE=0x40200000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x200000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx8mm-phg" +CONFIG_SPL_TEXT_BASE=0x7E1000 +CONFIG_TARGET_IMX8MM_PHG=y +CONFIG_SYS_PROMPT="u-boot=> " +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL=y +CONFIG_ENV_OFFSET_REDUND=0x204000 +CONFIG_SYS_LOAD_ADDR=0x40480000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_MONITOR_LEN=524288 +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +# CONFIG_USE_SPL_FIT_GENERATOR is not set +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x910000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x920000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 +CONFIG_SPL_I2C=y +CONFIG_SPL_POWER=y +CONFIG_SPL_USB_HOST=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2074 +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_MD5SUM=y +CONFIG_MD5SUM_VERIFY=y +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB_SDP=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK_COMPOSITE_CCF=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_IMX8MM=y +CONFIG_CLK_IMX8MM=y +CONFIG_MXC_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_PHYLIB=y +CONFIG_PHY_MARVELL=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_SPL_PHY=y +CONFIG_SPL_NOP_PHY=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8M_POWER_DOMAIN=y +CONFIG_DM_PMIC=y +CONFIG_SPL_DM_PMIC_PCA9450=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_SYSRESET_WATCHDOG=y +CONFIG_DM_THERMAL=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +# CONFIG_USB_STORAGE is not set +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_SDP_LOADADDR=0x40400000 +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_IMX_WATCHDOG=y diff --git a/doc/board/cloos/imx8mm_phg.rst b/doc/board/cloos/imx8mm_phg.rst new file mode 100644 index 00000000000..173f02d4aed --- /dev/null +++ b/doc/board/cloos/imx8mm_phg.rst @@ -0,0 +1,55 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Cloos i.MX8MM PHG board +======================= + +U-Boot for the Cloos i.MX8MM PHG board + +Quick Start +----------- + +- Get and Build the ARM Trusted firmware +- Get the DDR firmware +- Build U-Boot +- Flash U-Boot into the eMMC + +Get and Build the ARM Trusted firmware +-------------------------------------- + +Note: builddir is U-Boot build directory (source directory for in-tree builds) +Get ATF from: https://github.com/nxp-imx/imx-atf +branch: lf_v2.6 + +.. code-block:: bash + + $ make PLAT=imx8mm bl31 + $ cp build/imx8mm/release/bl31.bin $(builddir) + +Get the DDR firmware +-------------------- + +.. code-block:: bash + + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.9.bin + $ chmod +x firmware-imx-8.9.bin + $ ./firmware-imx-8.9 + $ cp firmware-imx-8.9/firmware/ddr/synopsys/lpddr4*.bin $(builddir) + +Build U-Boot +------------ + +.. code-block:: bash + + $ export CROSS_COMPILE=aarch64-poky-linux- + $ make imx8mm_phg_defconfig + $ make + +Flash U-Boot into the eMMC +-------------------------- + +Program flash.bin to the eMMC at offset 33KB: + +.. code-block:: bash + + $ ums 0 mmc 0 + $ sudo dd if=flash.bin of=/dev/sd[x] bs=1K seek=33; sync diff --git a/doc/board/cloos/index.rst b/doc/board/cloos/index.rst new file mode 100644 index 00000000000..02c84152db6 --- /dev/null +++ b/doc/board/cloos/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Cloos +===== + +.. toctree:: + :maxdepth: 2 + + imx8mm_phg diff --git a/doc/board/index.rst b/doc/board/index.rst index 53edd5301f2..1e628e99e63 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -16,6 +16,7 @@ Board-specific doc atmel/index broadcom/index bsh/index + cloos/index congatec/index coreboot/index emulation/index diff --git a/include/configs/imx8mm_phg.h b/include/configs/imx8mm_phg.h new file mode 100644 index 00000000000..d2d7ffa0f5b --- /dev/null +++ b/include/configs/imx8mm_phg.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + */ + +#ifndef __IMX8MM_PHG_H +#define __IMX8MM_PHG_H + +#include +#include +#include +#include + +#define CFG_SYS_UBOOT_BASE \ + (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) + +#ifdef CONFIG_SPL_BUILD +/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ +#define CFG_MALLOC_F_ADDR 0x930000 +#endif + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 2) \ + func(DHCP, dhcp, na) + +#include + +/* Initial environment variables */ +#define CFG_EXTRA_ENV_SETTINGS BOOTENV + +/* Link Definitions */ + +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x200000 + +#define CFG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM 0x40000000 +#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ + +#endif From 068027b1a0c1f445d9f4da88ab74b165f902b206 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 11 Jan 2023 09:22:58 -0300 Subject: [PATCH 39/87] pico-imx7d: Add support for the 2GB variant Add the board detection mechanism to be able to support the 2GB variant. Based on the code from TechNexion U-Boot downstream tree. Signed-off-by: Fabio Estevam --- board/technexion/pico-imx7d/spl.c | 30 +++++++++++++++++++++++++++--- 1 file changed, 27 insertions(+), 3 deletions(-) diff --git a/board/technexion/pico-imx7d/spl.c b/board/technexion/pico-imx7d/spl.c index df5f058577f..f86fee9c88e 100644 --- a/board/technexion/pico-imx7d/spl.c +++ b/board/technexion/pico-imx7d/spl.c @@ -61,6 +61,8 @@ static struct ddrc ddrc_regs_val = { .dramtmg0 = 0x09081109, .addrmap0 = 0x0000001f, .addrmap1 = 0x00080808, + .addrmap2 = 0x00000000, + .addrmap3 = 0x00000000, .addrmap4 = 0x00000f0f, .addrmap5 = 0x07070707, .addrmap6 = 0x0f0f0707, @@ -100,16 +102,38 @@ static void gpr_init(void) writel(0x4F400005, &gpr_regs->gpr[1]); } -static bool is_1g(void) +/* + * Revision Detection + * + * GPIO1_12 GPIO1_13 + * 0 0 1GB DDR3 + * 0 1 2GB DDR3 + * 1 0 512MB DDR3 + */ + +static int imx7d_pico_detect_board(void) { gpio_direction_input(IMX_GPIO_NR(1, 12)); - return !gpio_get_value(IMX_GPIO_NR(1, 12)); + gpio_direction_input(IMX_GPIO_NR(1, 13)); + + return gpio_get_value(IMX_GPIO_NR(1, 12)) << 1 | + gpio_get_value(IMX_GPIO_NR(1, 13)); } static void ddr_init(void) { - if (is_1g()) + switch (imx7d_pico_detect_board()) { + case 0: ddrc_regs_val.addrmap6 = 0x0f070707; + break; + case 1: + ddrc_regs_val.addrmap0 = 0x0000001f; + ddrc_regs_val.addrmap1 = 0x00181818; + ddrc_regs_val.addrmap4 = 0x00000f0f; + ddrc_regs_val.addrmap5 = 0x04040404; + ddrc_regs_val.addrmap6 = 0x04040404; + break; + } mx7_dram_cfg(&ddrc_regs_val, &ddrc_mp_val, &ddr_phy_regs_val, &calib_param); From 7150f56a85fd8d3b8ad162621026b0ba7bb6a367 Mon Sep 17 00:00:00 2001 From: Loic Poulain Date: Thu, 12 Jan 2023 18:19:50 +0100 Subject: [PATCH 40/87] serial: mxc: Wait for TX completion before reset MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The u-boot console may show some corrupted characters when printing in board_init() due to reset or baudrate change of the UART (probe) before the TX FIFO has been completely drained. To fix this issue, and in case UART is still running, we now try to flush the FIFO before proceeding to UART reinitialization. For this we're waiting for Transmitter Complete bit, indicating that the FIFO and the shift register are empty. flushing has a 4ms timeout guard, which is normally more than enough to consume the FIFO @ low baudrate (9600bps). Signed-off-by: Loic Poulain Tested-by: Lothar Waßmann Acked-by: Pali Rohár Reviewed-by: Fabio Estevam --- drivers/serial/serial_mxc.c | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c index 8bcbbf2bbfc..e4ffa9c3f6b 100644 --- a/drivers/serial/serial_mxc.c +++ b/drivers/serial/serial_mxc.c @@ -13,6 +13,7 @@ #include #include #include +#include /* UART Control Register Bit Fields.*/ #define URXD_CHARRDY (1<<15) @@ -144,8 +145,22 @@ struct mxc_uart { u32 ts; }; +static void _mxc_serial_flush(struct mxc_uart *base) +{ + unsigned int timeout = 4000; + + if (!(readl(&base->cr1) & UCR1_UARTEN) || + !(readl(&base->cr2) & UCR2_TXEN)) + return; + + while (!(readl(&base->sr2) & USR2_TXDC) && --timeout) + udelay(1); +} + static void _mxc_serial_init(struct mxc_uart *base, int use_dte) { + _mxc_serial_flush(base); + writel(0, &base->cr1); writel(0, &base->cr2); @@ -169,6 +184,8 @@ static void _mxc_serial_setbrg(struct mxc_uart *base, unsigned long clk, { u32 tmp; + _mxc_serial_flush(base); + tmp = RFDIV << UFCR_RFDIV_SHF; if (use_dte) tmp |= UFCR_DCEDTE; @@ -252,10 +269,17 @@ static int mxc_serial_init(void) return 0; } +static int mxc_serial_stop(void) +{ + _mxc_serial_flush(mxc_base); + + return 0; +} + static struct serial_device mxc_serial_drv = { .name = "mxc_serial", .start = mxc_serial_init, - .stop = NULL, + .stop = mxc_serial_stop, .setbrg = mxc_serial_setbrg, .putc = mxc_serial_putc, .puts = default_serial_puts, From ad725073d1666d94a96fbf9cba03777c3d58de24 Mon Sep 17 00:00:00 2001 From: Loic Poulain Date: Thu, 12 Jan 2023 18:19:51 +0100 Subject: [PATCH 41/87] serial: mxc: Speed-up character transmission MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Instead of waiting for empty FIFO condition before writing a character, wait for non-full FIFO condition. This helps in saving several tens of milliseconds during boot (depending verbosity). Signed-off-by: Loic Poulain Tested-by: Lothar Waßmann Acked-by: Pali Rohár Reviewed-by: Fabio Estevam Tested-by: Fabio Estevam --- drivers/serial/serial_mxc.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c index e4ffa9c3f6b..cc85a502726 100644 --- a/drivers/serial/serial_mxc.c +++ b/drivers/serial/serial_mxc.c @@ -240,11 +240,11 @@ static void mxc_serial_putc(const char c) if (c == '\n') serial_putc('\r'); - writel(c, &mxc_base->txd); - /* wait for transmitter to be ready */ - while (!(readl(&mxc_base->ts) & UTS_TXEMPTY)) + while (readl(&mxc_base->ts) & UTS_TXFULL) schedule(); + + writel(c, &mxc_base->txd); } /* Test whether a character is in the RX buffer */ @@ -335,7 +335,7 @@ static int mxc_serial_putc(struct udevice *dev, const char ch) struct mxc_serial_plat *plat = dev_get_plat(dev); struct mxc_uart *const uart = plat->reg; - if (!(readl(&uart->ts) & UTS_TXEMPTY)) + if (readl(&uart->ts) & UTS_TXFULL) return -EAGAIN; writel(ch, &uart->txd); From 5d4db6cf6bbbe9d5f17d715f888cb97597bc7d49 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 16 Jan 2023 09:32:11 -0300 Subject: [PATCH 42/87] mx53loco: Select CONFIG_CMD_EXT4 Select the CONFIG_CMD_EXT4 option so that files can be loaded from an ext4 partition. Signed-off-by: Fabio Estevam --- configs/mx53loco_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/mx53loco_defconfig b/configs/mx53loco_defconfig index 08bcd35f073..d5f2b7092db 100644 --- a/configs/mx53loco_defconfig +++ b/configs/mx53loco_defconfig @@ -34,6 +34,7 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y From 8b7036e6aa870fef1c72cd13a8fbc9a4737483ff Mon Sep 17 00:00:00 2001 From: "Ying-Chun Liu (PaulLiu)" Date: Wed, 18 Jan 2023 03:14:59 +0800 Subject: [PATCH 43/87] dts: imx8mp: assign binman_configuration label to config-SEQ assign a label for config-SEQ so that the board dts can modify the configuration more easily. Signed-off-by: Ying-Chun Liu (PaulLiu) Cc: Stefano Babic Cc: Fabio Estevam Cc: NXP i.MX U-Boot Team Reviewed-by: Fabio Estevam --- arch/arm/dts/imx8mp-u-boot.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/imx8mp-u-boot.dtsi b/arch/arm/dts/imx8mp-u-boot.dtsi index f9883aa1336..cb9b5b649a0 100644 --- a/arch/arm/dts/imx8mp-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-u-boot.dtsi @@ -148,7 +148,7 @@ configurations { default = "@config-DEFAULT-SEQ"; - @config-SEQ { + binman_configuration: @config-SEQ { description = "NAME"; fdt = "fdt-SEQ"; firmware = "uboot"; From 624c9dea9210e844faf15ef9b39667a902d1ff30 Mon Sep 17 00:00:00 2001 From: "Ying-Chun Liu (PaulLiu)" Date: Wed, 18 Jan 2023 03:15:00 +0800 Subject: [PATCH 44/87] dts: imx8mp-rsb3720: modify configrations to load fip into memory The changes of commit 6a21c695213b ("arm: dts: imx8mp: add of-list support to common imx8mp-u-boot.dtsi") breaks the loading of the fip. This commit fixes the break by modify the configuration properly. Signed-off-by: Ying-Chun Liu (PaulLiu) Cc: Stefano Babic Cc: Fabio Estevam Cc: NXP i.MX U-Boot Team Reviewed-by: Fabio Estevam --- arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi b/arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi index 4419967ee42..32d9fbc8863 100644 --- a/arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi @@ -158,12 +158,10 @@ }; }; }; - - configurations { - conf { - loadables = "atf", "fip"; - }; - }; }; }; }; + +&binman_configuration { + loadables = "atf", "fip"; +}; From 0e2862277915d67d775f190378c8a79dd3326d71 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Wed, 18 Jan 2023 17:31:15 +0800 Subject: [PATCH 45/87] ARM: dts: imx8ulp-evk: Fix iomuxc issue The property fsl,mux_mask is deleted by commit ed7bda5 (imx8ulp: synchronise device tree with linux). This causes the pinctrl driver not work on 8ULP, so fail to print any log. Signed-off-by: Ye Li Reviewed-by: Marcel Ziswiler --- arch/arm/dts/imx8ulp-evk-u-boot.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/dts/imx8ulp-evk-u-boot.dtsi b/arch/arm/dts/imx8ulp-evk-u-boot.dtsi index ad264f271ec..7acdb4a98a5 100644 --- a/arch/arm/dts/imx8ulp-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8ulp-evk-u-boot.dtsi @@ -26,6 +26,7 @@ &iomuxc1 { u-boot,dm-spl; + fsl,mux_mask = <0xf00>; }; &pinctrl_lpuart5 { From 0a0e3db0d20d5b4c70d24f1c6a384464abcc5807 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 19 Jan 2023 22:46:10 +0100 Subject: [PATCH 46/87] arm64: imx8mp: Disable Atheros PHY driver on i.MX8MP DHCOM These SoMs never ship with Atheros PHYs, disable the Atheros PHY driver. Signed-off-by: Marek Vasut --- configs/imx8mp_dhcom_pdk2_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/imx8mp_dhcom_pdk2_defconfig b/configs/imx8mp_dhcom_pdk2_defconfig index ecc28c89ef7..fc72df90f45 100644 --- a/configs/imx8mp_dhcom_pdk2_defconfig +++ b/configs/imx8mp_dhcom_pdk2_defconfig @@ -196,7 +196,6 @@ CONFIG_SPI_FLASH_SFDP_SUPPORT=y # CONFIG_SPI_FLASH_UNLOCK_ALL is not set CONFIG_SPI_FLASH_WINBOND=y CONFIG_SPI_FLASH_MTD=y -CONFIG_PHY_ATHEROS=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_MDIO=y From 5aa348d2bbf895c561af05bc758a98bf9c9a0354 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 19 Jan 2023 22:46:11 +0100 Subject: [PATCH 47/87] arm64: imx8mp: Enable SMSC LAN87xx PHY driver on i.MX8MP DHCOM These SoMs may ship with SMSC LAN8740Ai PHYs, enable the SMSC PHY driver. Signed-off-by: Marek Vasut --- configs/imx8mp_dhcom_pdk2_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/imx8mp_dhcom_pdk2_defconfig b/configs/imx8mp_dhcom_pdk2_defconfig index fc72df90f45..34796560fac 100644 --- a/configs/imx8mp_dhcom_pdk2_defconfig +++ b/configs/imx8mp_dhcom_pdk2_defconfig @@ -198,6 +198,7 @@ CONFIG_SPI_FLASH_WINBOND=y CONFIG_SPI_FLASH_MTD=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_PHY_SMSC=y CONFIG_DM_MDIO=y CONFIG_DM_ETH_PHY=y CONFIG_DWC_ETH_QOS=y From a7db74a4defe528050c396b53e0fad92bb910141 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 3 Jan 2023 10:19:38 -0300 Subject: [PATCH 48/87] pico-imx7d: Convert to CONFIG_DM_SERIAL The conversion to CONFIG_DM_SERIAL is mandatory, so select this option. Signed-off-by: Fabio Estevam --- configs/pico-dwarf-imx7d_defconfig | 1 + configs/pico-hobbit-imx7d_defconfig | 1 + configs/pico-imx7d_bl33_defconfig | 1 + configs/pico-imx7d_defconfig | 1 + configs/pico-nymph-imx7d_defconfig | 1 + configs/pico-pi-imx7d_defconfig | 1 + 6 files changed, 6 insertions(+) diff --git a/configs/pico-dwarf-imx7d_defconfig b/configs/pico-dwarf-imx7d_defconfig index 46777e04fdb..2d84e0bbec5 100644 --- a/configs/pico-dwarf-imx7d_defconfig +++ b/configs/pico-dwarf-imx7d_defconfig @@ -83,6 +83,7 @@ CONFIG_PINCTRL_IMX7=y CONFIG_POWER_LEGACY=y CONFIG_POWER_PFUZE3000=y CONFIG_POWER_I2C=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y CONFIG_USB=y diff --git a/configs/pico-hobbit-imx7d_defconfig b/configs/pico-hobbit-imx7d_defconfig index fb354d1cdee..143e7d0f845 100644 --- a/configs/pico-hobbit-imx7d_defconfig +++ b/configs/pico-hobbit-imx7d_defconfig @@ -83,6 +83,7 @@ CONFIG_PINCTRL_IMX7=y CONFIG_POWER_LEGACY=y CONFIG_POWER_PFUZE3000=y CONFIG_POWER_I2C=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y CONFIG_USB=y diff --git a/configs/pico-imx7d_bl33_defconfig b/configs/pico-imx7d_bl33_defconfig index 35e6f1d5493..2dcbb4352f3 100644 --- a/configs/pico-imx7d_bl33_defconfig +++ b/configs/pico-imx7d_bl33_defconfig @@ -80,6 +80,7 @@ CONFIG_POWER_LEGACY=y CONFIG_POWER_PFUZE3000=y CONFIG_POWER_I2C=y CONFIG_CONS_INDEX=4 +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y CONFIG_USB=y diff --git a/configs/pico-imx7d_defconfig b/configs/pico-imx7d_defconfig index 13cc97bb73c..1a818efe233 100644 --- a/configs/pico-imx7d_defconfig +++ b/configs/pico-imx7d_defconfig @@ -83,6 +83,7 @@ CONFIG_PINCTRL_IMX7=y CONFIG_POWER_LEGACY=y CONFIG_POWER_PFUZE3000=y CONFIG_POWER_I2C=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y CONFIG_USB=y diff --git a/configs/pico-nymph-imx7d_defconfig b/configs/pico-nymph-imx7d_defconfig index 46777e04fdb..2d84e0bbec5 100644 --- a/configs/pico-nymph-imx7d_defconfig +++ b/configs/pico-nymph-imx7d_defconfig @@ -83,6 +83,7 @@ CONFIG_PINCTRL_IMX7=y CONFIG_POWER_LEGACY=y CONFIG_POWER_PFUZE3000=y CONFIG_POWER_I2C=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y CONFIG_USB=y diff --git a/configs/pico-pi-imx7d_defconfig b/configs/pico-pi-imx7d_defconfig index 6e92366beff..5709fcfe646 100644 --- a/configs/pico-pi-imx7d_defconfig +++ b/configs/pico-pi-imx7d_defconfig @@ -83,6 +83,7 @@ CONFIG_PINCTRL_IMX7=y CONFIG_POWER_LEGACY=y CONFIG_POWER_PFUZE3000=y CONFIG_POWER_I2C=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y CONFIG_USB=y From ab79811c9f0118314c13fefb8d8739ff8e4c7669 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 3 Jan 2023 10:19:40 -0300 Subject: [PATCH 49/87] pico-imx7d: Convert to DM_I2C and DM_PMIC The conversion to DM_I2C is mandatory, so convert to it and also to DM_PMIC. Signed-off-by: Fabio Estevam --- board/technexion/pico-imx7d/pico-imx7d.c | 70 ++++++------------------ configs/pico-dwarf-imx7d_defconfig | 12 +--- configs/pico-hobbit-imx7d_defconfig | 12 +--- configs/pico-imx7d_bl33_defconfig | 12 +--- configs/pico-imx7d_defconfig | 12 +--- configs/pico-nymph-imx7d_defconfig | 12 +--- configs/pico-pi-imx7d_defconfig | 12 +--- include/configs/pico-imx7d.h | 3 - 8 files changed, 36 insertions(+), 109 deletions(-) diff --git a/board/technexion/pico-imx7d/pico-imx7d.c b/board/technexion/pico-imx7d/pico-imx7d.c index 7db34abcb1e..6e98b85b287 100644 --- a/board/technexion/pico-imx7d/pico-imx7d.c +++ b/board/technexion/pico-imx7d/pico-imx7d.c @@ -13,10 +13,8 @@ #include #include #include -#include #include #include -#include #include #include #include @@ -27,27 +25,6 @@ DECLARE_GLOBAL_DATA_PTR; #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \ PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS) -#define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ - PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM) - -#ifdef CONFIG_SYS_I2C_MXC -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) - -/* I2C4 for PMIC */ -static struct i2c_pads_info i2c_pad_info4 = { - .scl = { - .i2c_mode = MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL | PC, - .gpio_mode = MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 | PC, - .gp = IMX_GPIO_NR(6, 16), - }, - .sda = { - .i2c_mode = MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA | PC, - .gpio_mode = MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 | PC, - .gp = IMX_GPIO_NR(6, 17), - }, -}; -#endif - int dram_init(void) { gd->ram_size = imx_ddr_size(); @@ -60,50 +37,43 @@ int dram_init(void) return 0; } -#if CONFIG_IS_ENABLED(POWER_LEGACY) -#define I2C_PMIC 3 +#if CONFIG_IS_ENABLED(DM_PMIC) int power_init_board(void) { - struct pmic *p; + struct udevice *dev; + int reg, rev_id; int ret; - unsigned int reg, rev_id; - ret = power_pfuze3000_init(I2C_PMIC); - if (ret) + ret = pmic_get("pfuze3000@8", &dev); + if (ret == -ENODEV) + return 0; + if (ret != 0) return ret; - p = pmic_get("PFUZE3000"); - ret = pmic_probe(p); - if (ret) { - printf("Warning: Cannot find PMIC PFUZE3000\n"); - printf("\tPower consumption is not optimized.\n"); - return 0; - } - - pmic_reg_read(p, PFUZE3000_DEVICEID, ®); - pmic_reg_read(p, PFUZE3000_REVID, &rev_id); - printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id); + reg = pmic_reg_read(dev, PFUZE3000_DEVICEID); + rev_id = pmic_reg_read(dev, PFUZE3000_REVID); + printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id); /* disable Low Power Mode during standby mode */ - pmic_reg_read(p, PFUZE3000_LDOGCTL, ®); + reg = pmic_reg_read(dev, PFUZE3000_LDOGCTL); reg |= 0x1; - pmic_reg_write(p, PFUZE3000_LDOGCTL, reg); + pmic_reg_write(dev, PFUZE3000_LDOGCTL, reg); /* SW1A/1B mode set to APS/APS */ reg = 0x8; - pmic_reg_write(p, PFUZE3000_SW1AMODE, reg); - pmic_reg_write(p, PFUZE3000_SW1BMODE, reg); + pmic_reg_write(dev, PFUZE3000_SW1AMODE, reg); + pmic_reg_write(dev, PFUZE3000_SW1BMODE, reg); /* SW1A/1B standby voltage set to 1.025V */ reg = 0xd; - pmic_reg_write(p, PFUZE3000_SW1ASTBY, reg); - pmic_reg_write(p, PFUZE3000_SW1BSTBY, reg); + pmic_reg_write(dev, PFUZE3000_SW1ASTBY, reg); + pmic_reg_write(dev, PFUZE3000_SW1BSTBY, reg); /* decrease SW1B normal voltage to 0.975V */ - pmic_reg_read(p, PFUZE3000_SW1BVOLT, ®); + reg = pmic_reg_read(dev, PFUZE3000_SW1BVOLT); reg &= ~0x1f; reg |= PFUZE3000_SW1AB_SETP(975); - pmic_reg_write(p, PFUZE3000_SW1BVOLT, reg); + pmic_reg_write(dev, PFUZE3000_SW1BVOLT, reg); return 0; } @@ -168,10 +138,6 @@ int board_early_init_f(void) { setup_iomux_uart(); -#ifdef CONFIG_SYS_I2C_MXC - setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info4); -#endif - return 0; } diff --git a/configs/pico-dwarf-imx7d_defconfig b/configs/pico-dwarf-imx7d_defconfig index 2d84e0bbec5..13e8d0c27fe 100644 --- a/configs/pico-dwarf-imx7d_defconfig +++ b/configs/pico-dwarf-imx7d_defconfig @@ -7,10 +7,6 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 -CONFIG_SYS_I2C_MXC_I2C1=y -CONFIG_SYS_I2C_MXC_I2C2=y -CONFIG_SYS_I2C_MXC_I2C3=y -CONFIG_SYS_I2C_MXC_I2C4=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx7d-pico-pi" CONFIG_TARGET_PICO_IMX7D=y @@ -30,7 +26,6 @@ CONFIG_SPL_MAX_SIZE=0xe000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_MAX_SIZE=0x100000 CONFIG_SYS_SPL_MALLOC=y -CONFIG_SPL_I2C=y CONFIG_SPL_USB_HOST=y CONFIG_SPL_USB_GADGET=y CONFIG_SPL_USB_SDP_SUPPORT=y @@ -66,8 +61,7 @@ CONFIG_FASTBOOT_BUF_SIZE=0x10000000 CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=0 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y -CONFIG_SYS_I2C_LEGACY=y -CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y @@ -80,9 +74,9 @@ CONFIG_RGMII=y CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7=y -CONFIG_POWER_LEGACY=y CONFIG_POWER_PFUZE3000=y -CONFIG_POWER_I2C=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y diff --git a/configs/pico-hobbit-imx7d_defconfig b/configs/pico-hobbit-imx7d_defconfig index 143e7d0f845..63c168eeab8 100644 --- a/configs/pico-hobbit-imx7d_defconfig +++ b/configs/pico-hobbit-imx7d_defconfig @@ -7,10 +7,6 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 -CONFIG_SYS_I2C_MXC_I2C1=y -CONFIG_SYS_I2C_MXC_I2C2=y -CONFIG_SYS_I2C_MXC_I2C3=y -CONFIG_SYS_I2C_MXC_I2C4=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx7d-pico-pi" CONFIG_TARGET_PICO_IMX7D=y @@ -30,7 +26,6 @@ CONFIG_SPL_MAX_SIZE=0xe000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_MAX_SIZE=0x100000 CONFIG_SYS_SPL_MALLOC=y -CONFIG_SPL_I2C=y CONFIG_SPL_USB_HOST=y CONFIG_SPL_USB_GADGET=y CONFIG_SPL_USB_SDP_SUPPORT=y @@ -66,8 +61,7 @@ CONFIG_FASTBOOT_BUF_SIZE=0x10000000 CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=0 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y -CONFIG_SYS_I2C_LEGACY=y -CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y @@ -79,8 +73,8 @@ CONFIG_FEC_MXC=y CONFIG_RGMII=y CONFIG_MII=y CONFIG_PINCTRL=y -CONFIG_PINCTRL_IMX7=y -CONFIG_POWER_LEGACY=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y CONFIG_POWER_PFUZE3000=y CONFIG_POWER_I2C=y CONFIG_DM_SERIAL=y diff --git a/configs/pico-imx7d_bl33_defconfig b/configs/pico-imx7d_bl33_defconfig index 2dcbb4352f3..bfe0149befc 100644 --- a/configs/pico-imx7d_bl33_defconfig +++ b/configs/pico-imx7d_bl33_defconfig @@ -6,10 +6,6 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 -CONFIG_SYS_I2C_MXC_I2C1=y -CONFIG_SYS_I2C_MXC_I2C2=y -CONFIG_SYS_I2C_MXC_I2C3=y -CONFIG_SYS_I2C_MXC_I2C4=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx7d-pico-pi" CONFIG_TARGET_PICO_IMX7D=y @@ -31,7 +27,6 @@ CONFIG_SPL_MAX_SIZE=0xe000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_MAX_SIZE=0x100000 CONFIG_SYS_SPL_MALLOC=y -CONFIG_SPL_I2C=y CONFIG_SPL_USB_HOST=y CONFIG_SPL_USB_GADGET=y CONFIG_SPL_USB_SDP_SUPPORT=y @@ -63,8 +58,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_BOUNCE_BUFFER=y CONFIG_DFU_MMC=y -CONFIG_SYS_I2C_LEGACY=y -CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y CONFIG_MTD=y @@ -75,8 +69,8 @@ CONFIG_FEC_MXC=y CONFIG_RGMII=y CONFIG_MII=y CONFIG_PINCTRL=y -CONFIG_PINCTRL_IMX7=y -CONFIG_POWER_LEGACY=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y CONFIG_POWER_PFUZE3000=y CONFIG_POWER_I2C=y CONFIG_CONS_INDEX=4 diff --git a/configs/pico-imx7d_defconfig b/configs/pico-imx7d_defconfig index 1a818efe233..a4367db461a 100644 --- a/configs/pico-imx7d_defconfig +++ b/configs/pico-imx7d_defconfig @@ -7,10 +7,6 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 -CONFIG_SYS_I2C_MXC_I2C1=y -CONFIG_SYS_I2C_MXC_I2C2=y -CONFIG_SYS_I2C_MXC_I2C3=y -CONFIG_SYS_I2C_MXC_I2C4=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx7d-pico-pi" CONFIG_TARGET_PICO_IMX7D=y @@ -30,7 +26,6 @@ CONFIG_SPL_MAX_SIZE=0xe000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_MAX_SIZE=0x100000 CONFIG_SYS_SPL_MALLOC=y -CONFIG_SPL_I2C=y CONFIG_SPL_USB_HOST=y CONFIG_SPL_USB_GADGET=y CONFIG_SPL_USB_SDP_SUPPORT=y @@ -66,8 +61,7 @@ CONFIG_FASTBOOT_BUF_SIZE=0x10000000 CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=0 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y -CONFIG_SYS_I2C_LEGACY=y -CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y @@ -80,9 +74,9 @@ CONFIG_RGMII=y CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7=y -CONFIG_POWER_LEGACY=y CONFIG_POWER_PFUZE3000=y -CONFIG_POWER_I2C=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y diff --git a/configs/pico-nymph-imx7d_defconfig b/configs/pico-nymph-imx7d_defconfig index 2d84e0bbec5..13e8d0c27fe 100644 --- a/configs/pico-nymph-imx7d_defconfig +++ b/configs/pico-nymph-imx7d_defconfig @@ -7,10 +7,6 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 -CONFIG_SYS_I2C_MXC_I2C1=y -CONFIG_SYS_I2C_MXC_I2C2=y -CONFIG_SYS_I2C_MXC_I2C3=y -CONFIG_SYS_I2C_MXC_I2C4=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx7d-pico-pi" CONFIG_TARGET_PICO_IMX7D=y @@ -30,7 +26,6 @@ CONFIG_SPL_MAX_SIZE=0xe000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_MAX_SIZE=0x100000 CONFIG_SYS_SPL_MALLOC=y -CONFIG_SPL_I2C=y CONFIG_SPL_USB_HOST=y CONFIG_SPL_USB_GADGET=y CONFIG_SPL_USB_SDP_SUPPORT=y @@ -66,8 +61,7 @@ CONFIG_FASTBOOT_BUF_SIZE=0x10000000 CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=0 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y -CONFIG_SYS_I2C_LEGACY=y -CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y @@ -80,9 +74,9 @@ CONFIG_RGMII=y CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7=y -CONFIG_POWER_LEGACY=y CONFIG_POWER_PFUZE3000=y -CONFIG_POWER_I2C=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y diff --git a/configs/pico-pi-imx7d_defconfig b/configs/pico-pi-imx7d_defconfig index 5709fcfe646..4f07e53b808 100644 --- a/configs/pico-pi-imx7d_defconfig +++ b/configs/pico-pi-imx7d_defconfig @@ -7,10 +7,6 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 -CONFIG_SYS_I2C_MXC_I2C1=y -CONFIG_SYS_I2C_MXC_I2C2=y -CONFIG_SYS_I2C_MXC_I2C3=y -CONFIG_SYS_I2C_MXC_I2C4=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx7d-pico-pi" CONFIG_TARGET_PICO_IMX7D=y @@ -30,7 +26,6 @@ CONFIG_SPL_MAX_SIZE=0xe000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_MAX_SIZE=0x100000 CONFIG_SYS_SPL_MALLOC=y -CONFIG_SPL_I2C=y CONFIG_SPL_USB_HOST=y CONFIG_SPL_USB_GADGET=y CONFIG_SPL_USB_SDP_SUPPORT=y @@ -66,8 +61,7 @@ CONFIG_FASTBOOT_BUF_SIZE=0x10000000 CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=0 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y -CONFIG_SYS_I2C_LEGACY=y -CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y @@ -80,9 +74,9 @@ CONFIG_RGMII=y CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7=y -CONFIG_POWER_LEGACY=y CONFIG_POWER_PFUZE3000=y -CONFIG_POWER_I2C=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index 5774184300c..096e5bbe663 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -97,9 +97,6 @@ #define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE -/* PMIC */ -#define CFG_POWER_PFUZE3000_I2C_ADDR 0x08 - /* FLASH and environment organization */ /* Environment starts at 768k = 768 * 1024 = 786432 */ From ac68737ebdfe0d4b855d2b9de3969cd193707d95 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 7 Nov 2022 16:00:07 +0800 Subject: [PATCH 50/87] imx: mx6ull_14x14_evk: select DM_SERIAL Select DM_SERIAL Signed-off-by: Peng Fan --- configs/mx6ull_14x14_evk_defconfig | 1 + configs/mx6ull_14x14_evk_plugin_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/mx6ull_14x14_evk_defconfig b/configs/mx6ull_14x14_evk_defconfig index 881bc27a698..f1cc3d242fa 100644 --- a/configs/mx6ull_14x14_evk_defconfig +++ b/configs/mx6ull_14x14_evk_defconfig @@ -59,6 +59,7 @@ CONFIG_PINCTRL_IMX6=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/mx6ull_14x14_evk_plugin_defconfig b/configs/mx6ull_14x14_evk_plugin_defconfig index 5e6766282e4..d3a9edae51a 100644 --- a/configs/mx6ull_14x14_evk_plugin_defconfig +++ b/configs/mx6ull_14x14_evk_plugin_defconfig @@ -58,6 +58,7 @@ CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_DM_REGULATOR=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y From ad58df729558cfa9067d7e1e79d68183ed642324 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 7 Nov 2022 16:00:08 +0800 Subject: [PATCH 51/87] imx: mx6ulz: select DM_SERIAL Select DM_SERIAL Signed-off-by: Peng Fan --- configs/mx6ulz_14x14_evk_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/mx6ulz_14x14_evk_defconfig b/configs/mx6ulz_14x14_evk_defconfig index 0c1b442b682..2df2ccd2681 100644 --- a/configs/mx6ulz_14x14_evk_defconfig +++ b/configs/mx6ulz_14x14_evk_defconfig @@ -48,6 +48,7 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_DM_REGULATOR=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y From 3a6d7ef3898252ab42e13f506f18acc67a30163d Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 7 Nov 2022 16:00:09 +0800 Subject: [PATCH 52/87] imx: mx6ull/z_14x14_evk: clean up UART iomux After DM_SERIAL, and set pinctrl_uart1 as pre-reloc, no need initialize iomux at board file. Signed-off-by: Peng Fan --- arch/arm/dts/imx6ull-14x14-evk-u-boot.dtsi | 8 ++++++++ arch/arm/dts/imx6ulz-14x14-evk-u-boot.dtsi | 8 ++++++++ board/freescale/mx6ullevk/mx6ullevk.c | 16 ---------------- 3 files changed, 16 insertions(+), 16 deletions(-) create mode 100644 arch/arm/dts/imx6ull-14x14-evk-u-boot.dtsi create mode 100644 arch/arm/dts/imx6ulz-14x14-evk-u-boot.dtsi diff --git a/arch/arm/dts/imx6ull-14x14-evk-u-boot.dtsi b/arch/arm/dts/imx6ull-14x14-evk-u-boot.dtsi new file mode 100644 index 00000000000..d283e815e6a --- /dev/null +++ b/arch/arm/dts/imx6ull-14x14-evk-u-boot.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + */ + +&pinctrl_uart1 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/imx6ulz-14x14-evk-u-boot.dtsi b/arch/arm/dts/imx6ulz-14x14-evk-u-boot.dtsi new file mode 100644 index 00000000000..d283e815e6a --- /dev/null +++ b/arch/arm/dts/imx6ulz-14x14-evk-u-boot.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + */ + +&pinctrl_uart1 { + u-boot,dm-pre-reloc; +}; diff --git a/board/freescale/mx6ullevk/mx6ullevk.c b/board/freescale/mx6ullevk/mx6ullevk.c index e2473806475..de45f8b1d24 100644 --- a/board/freescale/mx6ullevk/mx6ullevk.c +++ b/board/freescale/mx6ullevk/mx6ullevk.c @@ -24,10 +24,6 @@ DECLARE_GLOBAL_DATA_PTR; -#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) - int dram_init(void) { gd->ram_size = imx_ddr_size(); @@ -35,16 +31,6 @@ int dram_init(void) return 0; } -static iomux_v3_cfg_t const uart1_pads[] = { - MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -static void setup_iomux_uart(void) -{ - imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); -} - int board_mmc_get_env_dev(int devno) { return devno; @@ -57,8 +43,6 @@ int mmc_map_to_kernel_blk(int devno) int board_early_init_f(void) { - setup_iomux_uart(); - return 0; } From 59bae6f58d3c8ac78d4675cddccc1a8cd7b1749a Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 7 Nov 2022 16:00:10 +0800 Subject: [PATCH 53/87] imx: mx6sllevk: correct pmic name The prefix 0 has been dropped in dts, so correct in board file Signed-off-by: Peng Fan --- board/freescale/mx6sllevk/mx6sllevk.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/freescale/mx6sllevk/mx6sllevk.c b/board/freescale/mx6sllevk/mx6sllevk.c index b4fddafe640..d9574623300 100644 --- a/board/freescale/mx6sllevk/mx6sllevk.c +++ b/board/freescale/mx6sllevk/mx6sllevk.c @@ -58,7 +58,7 @@ int power_init_board(void) u32 switch_num = 6; u32 offset = PFUZE100_SW1CMODE; - ret = pmic_get("pfuze100@08", &dev); + ret = pmic_get("pfuze100@8", &dev); if (ret == -ENODEV) return 0; From 2108db6c9267970b64c38687c94c53a78b82b4a9 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 7 Nov 2022 16:00:11 +0800 Subject: [PATCH 54/87] imx: mx6sllevk: select DM_SERIAL Select DM_SERIAL Signed-off-by: Peng Fan --- arch/arm/dts/imx6sll-evk-u-boot.dtsi | 8 ++++++++ board/freescale/mx6sllevk/mx6sllevk.c | 16 ---------------- configs/mx6sllevk_defconfig | 1 + configs/mx6sllevk_plugin_defconfig | 1 + 4 files changed, 10 insertions(+), 16 deletions(-) create mode 100644 arch/arm/dts/imx6sll-evk-u-boot.dtsi diff --git a/arch/arm/dts/imx6sll-evk-u-boot.dtsi b/arch/arm/dts/imx6sll-evk-u-boot.dtsi new file mode 100644 index 00000000000..14d0b58949a --- /dev/null +++ b/arch/arm/dts/imx6sll-evk-u-boot.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019, 2021 NXP + */ + +&pinctrl_uart1 { + u-boot,dm-pre-reloc; +}; diff --git a/board/freescale/mx6sllevk/mx6sllevk.c b/board/freescale/mx6sllevk/mx6sllevk.c index d9574623300..10a00095aff 100644 --- a/board/freescale/mx6sllevk/mx6sllevk.c +++ b/board/freescale/mx6sllevk/mx6sllevk.c @@ -24,10 +24,6 @@ DECLARE_GLOBAL_DATA_PTR; -#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) - int dram_init(void) { gd->ram_size = imx_ddr_size(); @@ -35,20 +31,10 @@ int dram_init(void) return 0; } -static iomux_v3_cfg_t const uart1_pads[] = { - MX6_PAD_UART1_TXD__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_UART1_RXD__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - static iomux_v3_cfg_t const wdog_pads[] = { MX6_PAD_WDOG_B__WDOG1_B | MUX_PAD_CTRL(NO_PAD_CTRL), }; -static void setup_iomux_uart(void) -{ - imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); -} - #ifdef CONFIG_DM_PMIC_PFUZE100 int power_init_board(void) { @@ -94,8 +80,6 @@ int power_init_board(void) int board_early_init_f(void) { - setup_iomux_uart(); - return 0; } diff --git a/configs/mx6sllevk_defconfig b/configs/mx6sllevk_defconfig index 39a15ae830e..ea46071626a 100644 --- a/configs/mx6sllevk_defconfig +++ b/configs/mx6sllevk_defconfig @@ -51,6 +51,7 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_PFUZE100=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y CONFIG_USB=y diff --git a/configs/mx6sllevk_plugin_defconfig b/configs/mx6sllevk_plugin_defconfig index 47d82540aca..885dda716c1 100644 --- a/configs/mx6sllevk_plugin_defconfig +++ b/configs/mx6sllevk_plugin_defconfig @@ -52,6 +52,7 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_PFUZE100=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y CONFIG_USB=y From 02fe5cda960106fa800d35e1968f7f1ad669665a Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 7 Nov 2022 16:00:12 +0800 Subject: [PATCH 55/87] imx: mx6slevk: select DM_SERIAL Select DM_SERIAL Signed-off-by: Peng Fan --- configs/mx6slevk_defconfig | 1 + configs/mx6slevk_spinor_defconfig | 1 + configs/mx6slevk_spl_defconfig | 1 + 3 files changed, 3 insertions(+) diff --git a/configs/mx6slevk_defconfig b/configs/mx6slevk_defconfig index 018df1bbfaf..3dba1b357e1 100644 --- a/configs/mx6slevk_defconfig +++ b/configs/mx6slevk_defconfig @@ -59,6 +59,7 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_PFUZE100=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/mx6slevk_spinor_defconfig b/configs/mx6slevk_spinor_defconfig index 5351d03510d..c970271dae8 100644 --- a/configs/mx6slevk_spinor_defconfig +++ b/configs/mx6slevk_spinor_defconfig @@ -59,6 +59,7 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_PFUZE100=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/mx6slevk_spl_defconfig b/configs/mx6slevk_spl_defconfig index 02ad43b1483..0d6bc24445b 100644 --- a/configs/mx6slevk_spl_defconfig +++ b/configs/mx6slevk_spl_defconfig @@ -75,6 +75,7 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_PFUZE100=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y From 388ccbe1fee999a0f1db17e2e47292081ac3093a Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 7 Nov 2022 16:00:13 +0800 Subject: [PATCH 56/87] imx: mx6ul_evk: select DM_SERIAL Select DM_SERIAL Signed-off-by: Peng Fan --- configs/mx6ul_14x14_evk_defconfig | 1 + configs/mx6ul_9x9_evk_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig index 598d72c61e4..043662204c2 100644 --- a/configs/mx6ul_14x14_evk_defconfig +++ b/configs/mx6ul_14x14_evk_defconfig @@ -86,6 +86,7 @@ CONFIG_PINCTRL_IMX6=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/mx6ul_9x9_evk_defconfig b/configs/mx6ul_9x9_evk_defconfig index a9979f6b4ec..99475ea26c6 100644 --- a/configs/mx6ul_9x9_evk_defconfig +++ b/configs/mx6ul_9x9_evk_defconfig @@ -81,6 +81,7 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_PFUZE100=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y From 1224dd8b157f039192dccdbe9bea0adb4de82eec Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 7 Nov 2022 16:00:14 +0800 Subject: [PATCH 57/87] imx: mx6sxsabreauto: select DM_SERIAL Select DM_SERIAL Signed-off-by: Peng Fan --- arch/arm/dts/imx6sx-sabreauto-u-boot.dtsi | 4 ++++ board/freescale/mx6sxsabreauto/mx6sxsabreauto.c | 16 ---------------- configs/mx6sxsabreauto_defconfig | 1 + 3 files changed, 5 insertions(+), 16 deletions(-) diff --git a/arch/arm/dts/imx6sx-sabreauto-u-boot.dtsi b/arch/arm/dts/imx6sx-sabreauto-u-boot.dtsi index 549461df71e..7812aa34ee1 100644 --- a/arch/arm/dts/imx6sx-sabreauto-u-boot.dtsi +++ b/arch/arm/dts/imx6sx-sabreauto-u-boot.dtsi @@ -14,3 +14,7 @@ compatible = "jedec,spi-nor"; }; }; + +&pinctrl_uart1 { + u-boot,dm-pre-reloc; +}; diff --git a/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c index 9205d5ef6dd..84cc51e9cac 100644 --- a/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c +++ b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c @@ -33,10 +33,6 @@ DECLARE_GLOBAL_DATA_PTR; -#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) - #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ PAD_CTL_SPEED_HIGH | \ PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) @@ -59,11 +55,6 @@ int dram_init(void) return 0; } -static iomux_v3_cfg_t const uart1_pads[] = { - MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - static iomux_v3_cfg_t const fec2_pads[] = { MX6_PAD_ENET1_MDC__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET1_MDIO__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), @@ -81,11 +72,6 @@ static iomux_v3_cfg_t const fec2_pads[] = { MX6_PAD_RGMII2_TXC__ENET2_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), }; -static void setup_iomux_uart(void) -{ - imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); -} - static int setup_fec(void) { struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; @@ -216,8 +202,6 @@ int board_ehci_hcd_init(int port) int board_early_init_f(void) { - setup_iomux_uart(); - return 0; } diff --git a/configs/mx6sxsabreauto_defconfig b/configs/mx6sxsabreauto_defconfig index 78780a8c706..3e8ba780929 100644 --- a/configs/mx6sxsabreauto_defconfig +++ b/configs/mx6sxsabreauto_defconfig @@ -64,6 +64,7 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_PFUZE100=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y From beb403f9e53b8dddf330228bd5f79a62aad5fcdc Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 7 Nov 2022 16:00:16 +0800 Subject: [PATCH 58/87] imx: mx6sabresd: select DM_SERIAL Select DM_SERIAL Signed-off-by: Peng Fan --- configs/mx6sabresd_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig index 9472e032c81..cae23b93ec2 100644 --- a/configs/mx6sabresd_defconfig +++ b/configs/mx6sabresd_defconfig @@ -106,6 +106,7 @@ CONFIG_POWER_PFUZE100=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_POWER_I2C=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y From 0c49f68915b3c909ff1a87844684ad8063327c6c Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 7 Nov 2022 16:00:15 +0800 Subject: [PATCH 59/87] imx: mx6sabreauto_defconfig: select DM_SERIAL Select DM_SERIAL Signed-off-by: Peng Fan --- configs/mx6sabreauto_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/mx6sabreauto_defconfig b/configs/mx6sabreauto_defconfig index 8e94a84409d..639f552b6da 100644 --- a/configs/mx6sabreauto_defconfig +++ b/configs/mx6sabreauto_defconfig @@ -98,6 +98,7 @@ CONFIG_POWER_LEGACY=y CONFIG_POWER_PFUZE100=y CONFIG_DM_REGULATOR=y CONFIG_POWER_I2C=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y From 747c2e613b9efd8034d35f568e206b7e95bad65b Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Mon, 14 Nov 2022 13:01:38 +0100 Subject: [PATCH 60/87] imx: imx6ul: kontron-sl-mx6ul: Disable CONFIG_FSL_QSPI_AHB_FULL_MAP to fix SPI NAND read access The introduction of CONFIG_FSL_QSPI_AHB_FULL_MAP as default in: def88bce094e ("spi: fsl_qspi: Support to use full AHB space on i.MX") broke the SPI NAND read access on the Kontron SL i.MX6UL/ULL boards. Reading data from the flash returns garbage instead of the actual content. Fix this for now by disabling the introduced option. In the long run this should be fixed globally. Fixes: def88bce094e ("spi: fsl_qspi: Support to use full AHB space on i.MX") Signed-off-by: Frieder Schrempf Reviewed-by: Fabio Estevam --- configs/kontron-sl-mx6ul_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/kontron-sl-mx6ul_defconfig b/configs/kontron-sl-mx6ul_defconfig index 02b963e7c33..72a433dbf84 100644 --- a/configs/kontron-sl-mx6ul_defconfig +++ b/configs/kontron-sl-mx6ul_defconfig @@ -97,6 +97,7 @@ CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y +# CONFIG_FSL_QSPI_AHB_FULL_MAP is not set CONFIG_MXC_SPI=y CONFIG_IMX_THERMAL=y CONFIG_USB=y From 0b32bc4831694c0b750811589543f540a2385b40 Mon Sep 17 00:00:00 2001 From: Detlev Casanova Date: Thu, 8 Dec 2022 13:15:52 -0500 Subject: [PATCH 61/87] imx6q-sabrelite: Re-add mmc aliases In commit d0399a46e7cda63c07e3eb8558bef84cfb068028, the device tree was synchronized from linux and the aliases were dropped. They need to be kept so that the mmc cards are in the right order. Without the aliases, u-boot reports: MMC: FSL_SDHC: 2, FSL_SDHC: 3 With the aliases, u-boot reports: MMC: FSL_SDHC: 0, FSL_SDHC: 1 The upstream linux device tree does not contain the same aliases than u-boot (It keeps the devices order with /dev/mmcblk2 and /dev/mmcblk3). Because this board has been using different aliases in u-boot and linux, a imx6q-sabrelite-u-boot.dtsi file is added to be automatically included in imx6q-sabrelite.dts. This way, linux and u-boot each keep their own aliases and there is no breakage on current installations. This should never be done for new boards as we want to keep linux and u-boot with the same aliases as much as possible. This patch is only necessary to avoid breaking existing setups. Signed-off-by: Detlev Casanova Reviewed-by: Fabio Estevam --- arch/arm/dts/imx6q-sabrelite-u-boot.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 arch/arm/dts/imx6q-sabrelite-u-boot.dtsi diff --git a/arch/arm/dts/imx6q-sabrelite-u-boot.dtsi b/arch/arm/dts/imx6q-sabrelite-u-boot.dtsi new file mode 100644 index 00000000000..9eb1c34b20a --- /dev/null +++ b/arch/arm/dts/imx6q-sabrelite-u-boot.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 Collabora + */ + +#include "imx6qdl-u-boot.dtsi" + +/ { + aliases { + mmc0 = &usdhc3; + mmc1 = &usdhc4; + }; +}; From 46dcb31065f873241c3b6076c1b500f8f90b4901 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 22 Dec 2022 01:46:34 +0100 Subject: [PATCH 62/87] arm: psci: Add PSCI v1.1 macro Add macro representing the PSCI v1.1 . Signed-off-by: Marek Vasut --- arch/arm/include/asm/psci.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h index 67e9234066b..8b3fb872255 100644 --- a/arch/arm/include/asm/psci.h +++ b/arch/arm/include/asm/psci.h @@ -22,6 +22,7 @@ #include #endif +#define ARM_PSCI_VER_1_1 (0x00010001) #define ARM_PSCI_VER_1_0 (0x00010000) #define ARM_PSCI_VER_0_2 (0x00000002) From 11a1a3b73d2e3ad08cd60936da7f4ebcd2ae8e0d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 22 Dec 2022 01:46:35 +0100 Subject: [PATCH 63/87] arm: psci: Fix RESET2 hook The RESET2 hook is a PSCI v1.1 functionality, rename the macro accordinly. Add missing handler for the RESET2 hook, so it can be implemented by U-Boot. Signed-off-by: Marek Vasut --- arch/arm/cpu/armv8/fwcall.c | 2 +- arch/arm/cpu/armv8/psci.S | 2 ++ arch/arm/include/asm/psci.h | 4 +++- 3 files changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv8/fwcall.c b/arch/arm/cpu/armv8/fwcall.c index 16914dc1eed..87de09979b1 100644 --- a/arch/arm/cpu/armv8/fwcall.c +++ b/arch/arm/cpu/armv8/fwcall.c @@ -103,7 +103,7 @@ void __noreturn psci_system_reset2(u32 reset_level, u32 cookie) { struct pt_regs regs; - regs.regs[0] = ARM_PSCI_0_2_FN64_SYSTEM_RESET2; + regs.regs[0] = ARM_PSCI_1_1_FN64_SYSTEM_RESET2; regs.regs[1] = PSCI_RESET2_TYPE_VENDOR | reset_level; regs.regs[2] = cookie; if (use_smc_for_psci) diff --git a/arch/arm/cpu/armv8/psci.S b/arch/arm/cpu/armv8/psci.S index 6aece119871..ab8b3df3416 100644 --- a/arch/arm/cpu/armv8/psci.S +++ b/arch/arm/cpu/armv8/psci.S @@ -81,6 +81,7 @@ PSCI_DEFAULT(psci_node_hw_state_64) PSCI_DEFAULT(psci_system_suspend_64) PSCI_DEFAULT(psci_stat_residency_64) PSCI_DEFAULT(psci_stat_count_64) +PSCI_DEFAULT(psci_system_reset2_64) .align 3 _psci_64_table: @@ -94,6 +95,7 @@ PSCI_TABLE(ARM_PSCI_1_0_FN64_NODE_HW_STATE, psci_node_hw_state_64) PSCI_TABLE(ARM_PSCI_1_0_FN64_SYSTEM_SUSPEND, psci_system_suspend_64) PSCI_TABLE(ARM_PSCI_1_0_FN64_STAT_RESIDENCY, psci_stat_residency_64) PSCI_TABLE(ARM_PSCI_1_0_FN64_STAT_COUNT, psci_stat_count_64) +PSCI_TABLE(ARM_PSCI_1_1_FN64_SYSTEM_RESET2, psci_system_reset2_64) PSCI_TABLE(0, 0) .macro psci_enter diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h index 8b3fb872255..7343b941ef0 100644 --- a/arch/arm/include/asm/psci.h +++ b/arch/arm/include/asm/psci.h @@ -69,7 +69,6 @@ #define ARM_PSCI_0_2_FN64_AFFINITY_INFO ARM_PSCI_0_2_FN64(4) #define ARM_PSCI_0_2_FN64_MIGRATE ARM_PSCI_0_2_FN64(5) #define ARM_PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU ARM_PSCI_0_2_FN64(7) -#define ARM_PSCI_0_2_FN64_SYSTEM_RESET2 ARM_PSCI_0_2_FN64(18) /* PSCI 1.0 interface */ #define ARM_PSCI_1_0_FN_PSCI_FEATURES ARM_PSCI_0_2_FN(10) @@ -87,6 +86,9 @@ #define ARM_PSCI_1_0_FN64_STAT_RESIDENCY ARM_PSCI_0_2_FN64(16) #define ARM_PSCI_1_0_FN64_STAT_COUNT ARM_PSCI_0_2_FN64(17) +/* PSCI 1.1 interface */ +#define ARM_PSCI_1_1_FN64_SYSTEM_RESET2 ARM_PSCI_0_2_FN64(18) + /* 1KB stack per core */ #define ARM_PSCI_STACK_SHIFT 10 #define ARM_PSCI_STACK_SIZE (1 << ARM_PSCI_STACK_SHIFT) From ae237b1e62d9f97125990c09d3320d853bb70412 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 22 Dec 2022 01:46:36 +0100 Subject: [PATCH 64/87] arm: imx: Drop custom lowlevel_init The custom lowlevel_init implementation is no longer necessary, since it is responsible for routing and trapping SErrors in U-Boot in EL2, which is implemented in common code since commit: 6c7691edd55 ("armv8: Always unmask SErrors") Signed-off-by: Marek Vasut --- arch/arm/mach-imx/Makefile | 2 -- arch/arm/mach-imx/lowlevel.S | 22 ---------------------- 2 files changed, 24 deletions(-) delete mode 100644 arch/arm/mach-imx/lowlevel.S diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 61b4f4f8cd3..4dfc60eedc4 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -235,8 +235,6 @@ endif targets += $(addprefix ../../../,SPL spl/u-boot-spl.cfgout u-boot-dtb.cfgout u-boot.cfgout u-boot.uim spl/u-boot-nand-spl.imx) -obj-$(CONFIG_ARM64) += lowlevel.o - obj-$(CONFIG_MX5) += mx5/ obj-$(CONFIG_MX6) += mx6/ obj-$(CONFIG_MX7) += mx7/ diff --git a/arch/arm/mach-imx/lowlevel.S b/arch/arm/mach-imx/lowlevel.S deleted file mode 100644 index 158fdb7d87b..00000000000 --- a/arch/arm/mach-imx/lowlevel.S +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2019 NXP - */ - -#include - -ENTRY(lowlevel_init) - mrs x0, CurrentEL - cmp x0, #8 - b.eq 1f - ret -1: - msr daifclr, #4 - - /* set HCR_EL2.AMO to catch SERROR */ - mrs x0, hcr_el2 - orr x0, x0, #0x20 - msr hcr_el2, x0 - isb - ret -ENDPROC(lowlevel_init) From 9694c0532a065e8f60182995dab181396cbd8c4d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 22 Dec 2022 01:46:37 +0100 Subject: [PATCH 65/87] arm: dts: imx8m: Require ATF BL31 blob only if not PSCI provider In case U-Boot itself if the PSCI provider on i.MX8M, do not require the ATF BL31 blob, as at that point the blob is useless and would interfere with U-Boot operation. Signed-off-by: Marek Vasut --- arch/arm/dts/imx8mm-u-boot.dtsi | 4 ++++ arch/arm/dts/imx8mn-u-boot.dtsi | 4 ++++ arch/arm/dts/imx8mp-u-boot.dtsi | 4 ++++ arch/arm/dts/imx8mq-u-boot.dtsi | 4 ++++ 4 files changed, 16 insertions(+) diff --git a/arch/arm/dts/imx8mm-u-boot.dtsi b/arch/arm/dts/imx8mm-u-boot.dtsi index 60d49bc3d7b..25dc8e12dde 100644 --- a/arch/arm/dts/imx8mm-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-u-boot.dtsi @@ -99,6 +99,7 @@ }; }; +#ifndef CONFIG_ARMV8_PSCI atf { arch = "arm64"; compression = "none"; @@ -112,6 +113,7 @@ type = "atf-bl31"; }; }; +#endif binman_fip: fip { arch = "arm64"; @@ -140,7 +142,9 @@ description = "NAME"; fdt = "fdt-SEQ"; firmware = "uboot"; +#ifndef CONFIG_ARMV8_PSCI loadables = "atf"; +#endif }; }; }; diff --git a/arch/arm/dts/imx8mn-u-boot.dtsi b/arch/arm/dts/imx8mn-u-boot.dtsi index ec53390afb3..d55dddbdb6e 100644 --- a/arch/arm/dts/imx8mn-u-boot.dtsi +++ b/arch/arm/dts/imx8mn-u-boot.dtsi @@ -163,6 +163,7 @@ }; }; +#ifndef CONFIG_ARMV8_PSCI atf { arch = "arm64"; compression = "none"; @@ -176,6 +177,7 @@ type = "atf-bl31"; }; }; +#endif binman_fip: fip { arch = "arm64"; @@ -204,7 +206,9 @@ description = "NAME"; fdt = "fdt-SEQ"; firmware = "uboot"; +#ifndef CONFIG_ARMV8_PSCI loadables = "atf"; +#endif }; }; }; diff --git a/arch/arm/dts/imx8mp-u-boot.dtsi b/arch/arm/dts/imx8mp-u-boot.dtsi index cb9b5b649a0..07538da6214 100644 --- a/arch/arm/dts/imx8mp-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-u-boot.dtsi @@ -120,6 +120,7 @@ }; }; +#ifndef CONFIG_ARMV8_PSCI atf { description = "ARM Trusted Firmware"; type = "firmware"; @@ -133,6 +134,7 @@ type = "atf-bl31"; }; }; +#endif @fdt-SEQ { description = "NAME"; @@ -152,7 +154,9 @@ description = "NAME"; fdt = "fdt-SEQ"; firmware = "uboot"; +#ifndef CONFIG_ARMV8_PSCI loadables = "atf"; +#endif }; }; }; diff --git a/arch/arm/dts/imx8mq-u-boot.dtsi b/arch/arm/dts/imx8mq-u-boot.dtsi index 8d385e8da4f..2bc9f413da0 100644 --- a/arch/arm/dts/imx8mq-u-boot.dtsi +++ b/arch/arm/dts/imx8mq-u-boot.dtsi @@ -114,6 +114,7 @@ }; }; +#ifndef CONFIG_ARMV8_PSCI atf { arch = "arm64"; compression = "none"; @@ -127,6 +128,7 @@ type = "blob-ext"; }; }; +#endif fdt { compression = "none"; @@ -147,7 +149,9 @@ description = "NAME"; fdt = "fdt"; firmware = "uboot"; +#ifndef CONFIG_ARMV8_PSCI loadables = "atf"; +#endif }; }; }; From 45dd377e3666a38b43143041c76b840c8c16db60 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 22 Dec 2022 01:46:38 +0100 Subject: [PATCH 66/87] arm: imx: imx8m: Only use ROM pointers if not PSCI provider The ROM pointers are in fact populated by the ATF BL31 blob, in case U-Boot itself if the PSCI provider, there is no ATF BL31 blob, hence ignore the ROM pointers. Signed-off-by: Marek Vasut --- arch/arm/mach-imx/imx8m/soc.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 90a59bd4398..93e10bf06f9 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -238,7 +238,7 @@ int dram_init(void) return ret; /* rom_pointer[1] contains the size of TEE occupies */ - if (rom_pointer[1]) + if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && rom_pointer[1]) gd->ram_size = sdram_size - rom_pointer[1]; else gd->ram_size = sdram_size; @@ -267,7 +267,7 @@ int dram_init_banksize(void) } gd->bd->bi_dram[bank].start = PHYS_SDRAM; - if (rom_pointer[1]) { + if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && rom_pointer[1]) { phys_addr_t optee_start = (phys_addr_t)rom_pointer[0]; phys_size_t optee_size = (size_t)rom_pointer[1]; @@ -312,7 +312,7 @@ phys_size_t get_effective_memsize(void) sdram_b1_size = sdram_size; } - if (rom_pointer[1]) { + if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && rom_pointer[1]) { /* We will relocate u-boot to Top of dram1. Tee position has two cases: * 1. At the top of dram1, Then return the size removed optee size. * 2. In the middle of dram1, return the size of dram1. @@ -344,7 +344,8 @@ phys_size_t board_get_usable_ram_top(phys_size_t total_size) * rom_pointer[1] stores the size TEE uses. * We need to reserve the memory region for TEE. */ - if (rom_pointer[0] && rom_pointer[1] && top_addr > rom_pointer[0]) + if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && rom_pointer[0] && + rom_pointer[1] && top_addr > rom_pointer[0]) top_addr = rom_pointer[0]; return top_addr; From 68c0ce8a5cbf3bc0742520c1abfc181968ec0402 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 22 Dec 2022 01:46:39 +0100 Subject: [PATCH 67/87] arm: imx: imx8m: Enable GICv3 support if PSCI provider In case U-Boot is a PSCI provider, enable GICv3 support as this is necessary to bring up secondary cores. Signed-off-by: Marek Vasut --- arch/arm/include/asm/arch-imx8m/imx-regs.h | 3 +++ arch/arm/mach-imx/imx8m/Kconfig | 1 + 2 files changed, 4 insertions(+) diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h index 20f4699a12b..cfd5479cd73 100644 --- a/arch/arm/include/asm/arch-imx8m/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h @@ -81,6 +81,9 @@ #define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000) #define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000) +#define GICD_BASE 0x38800000 +#define GICR_BASE 0x38880000 + #define DDRC_DDR_SS_GPR0 0x3d000000 #define DDRC_IPS_BASE_ADDR(X) (0x3d400000 + ((X) * 0x2000000)) #define DDR_CSD1_BASE_ADDR 0x40000000 diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 64e6b49f46b..6d35cda0bee 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -2,6 +2,7 @@ if ARCH_IMX8M config IMX8M bool + select GICV3 if ARMV8_PSCI select HAS_CAAM select ROM_UNIFIED_SECTIONS select ARMV8_CRYPTO From 1434f93ee016e55473031e47b84f9fe6f2e26b56 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 22 Dec 2022 01:46:40 +0100 Subject: [PATCH 68/87] arm: imx: imx8m: Map RAM as NS if PSCI provider In case U-Boot is a PSCI provider, map RAM explicitly as NS, otherwise secondary cores crash with SError when attempting to access RAM mapped as secure in EL2. Signed-off-by: Marek Vasut --- arch/arm/mach-imx/imx8m/soc.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 93e10bf06f9..cad9200dd1e 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -100,6 +100,12 @@ void set_wdog_reset(struct wdog_regs *wdog) setbits_le16(&wdog->wcr, WDOG_WDT_MASK | WDOG_WDZST_MASK); } +#ifdef CONFIG_ARMV8_PSCI +#define PTE_MAP_NS PTE_BLOCK_NS +#else +#define PTE_MAP_NS 0 +#endif + static struct mm_region imx8m_mem_map[] = { { /* ROM */ @@ -122,7 +128,7 @@ static struct mm_region imx8m_mem_map[] = { .phys = 0x180000UL, .size = 0x8000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_OUTER_SHARE + PTE_BLOCK_OUTER_SHARE | PTE_MAP_NS }, { /* TCM */ .virt = 0x7C0000UL, @@ -130,14 +136,14 @@ static struct mm_region imx8m_mem_map[] = { .size = 0x80000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN + PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_MAP_NS }, { /* OCRAM */ .virt = 0x900000UL, .phys = 0x900000UL, .size = 0x200000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_OUTER_SHARE + PTE_BLOCK_OUTER_SHARE | PTE_MAP_NS }, { /* AIPS */ .virt = 0xB00000UL, @@ -152,7 +158,7 @@ static struct mm_region imx8m_mem_map[] = { .phys = 0x40000000UL, .size = PHYS_SDRAM_SIZE, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_OUTER_SHARE + PTE_BLOCK_OUTER_SHARE | PTE_MAP_NS #ifdef PHYS_SDRAM_2_SIZE }, { /* DRAM2 */ @@ -160,7 +166,7 @@ static struct mm_region imx8m_mem_map[] = { .phys = 0x100000000UL, .size = PHYS_SDRAM_2_SIZE, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_OUTER_SHARE + PTE_BLOCK_OUTER_SHARE | PTE_MAP_NS #endif }, { /* empty entrie to split table entry 5 if needed when TEEs are used */ From 191937134b939718015de57dfda7355f4dfe4248 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 22 Dec 2022 01:46:41 +0100 Subject: [PATCH 69/87] arm: imx: imx8m: Define trampoline location if PSCI provider The common code used to bring up secondary cores requires a final jump location to be stored in some sort of memory location, define this memory location to be the start of OCRAM, since it is available. Signed-off-by: Marek Vasut --- arch/arm/include/asm/arch-imx8m/imx-regs.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h index cfd5479cd73..3034d280cc3 100644 --- a/arch/arm/include/asm/arch-imx8m/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h @@ -91,6 +91,10 @@ #define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK 0x70000 #define FEC_QUIRK_ENET_MAC +#ifdef CONFIG_ARMV8_PSCI /* Final jump location */ +#define CPU_RELEASE_ADDR 0x900000 +#endif + #define CAAM_ARB_BASE_ADDR (0x00100000) #define CAAM_ARB_END_ADDR (0x00107FFF) #define CAAM_IPS_BASE_ADDR (0x30900000) From 58552ab81b365bf5de8d40e2ea1978f6446e62c8 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 22 Dec 2022 01:46:42 +0100 Subject: [PATCH 70/87] arm: imx: imx8m: Program CSU and TZASC if PSCI provider In case U-Boot is the PSCI provider, it is necessary to correctly program CSU and TZASC registers. Those are poorly documented, so push in the correct values. Signed-off-by: Marek Vasut --- arch/arm/include/asm/arch-imx8m/imx-regs.h | 1 + arch/arm/mach-imx/imx8m/soc.c | 25 ++++++++++++++++++++++ 2 files changed, 26 insertions(+) diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h index 3034d280cc3..1559bf6d218 100644 --- a/arch/arm/include/asm/arch-imx8m/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h @@ -31,6 +31,7 @@ #define CCM_BASE_ADDR 0x30380000 #define SRC_BASE_ADDR 0x30390000 #define GPC_BASE_ADDR 0x303A0000 +#define CSU_BASE_ADDR 0x303E0000 #define SYSCNT_RD_BASE_ADDR 0x306A0000 #define SYSCNT_CMP_BASE_ADDR 0x306B0000 diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index cad9200dd1e..df865e997d3 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -561,6 +561,29 @@ static void imx8m_setup_snvs(void) writel(0xffffffff, SNVS_BASE_ADDR + SNVS_LPSR); } +static void imx8m_setup_csu_tzasc(void) +{ + const uintptr_t tzasc_base[4] = { + 0x301f0000, 0x301f0000, 0x301f0000, 0x301f0000 + }; + int i, j; + + if (!IS_ENABLED(CONFIG_ARMV8_PSCI)) + return; + + /* CSU */ + for (i = 0; i < 64; i++) + writel(0x00ff00ff, (void *)CSU_BASE_ADDR + (4 * i)); + + /* TZASC */ + for (j = 0; j < 4; j++) { + writel(0x77777777, (void *)(tzasc_base[j])); + writel(0x77777777, (void *)(tzasc_base[j]) + 0x4); + for (i = 0; i <= 0x10; i += 4) + writel(0, (void *)(tzasc_base[j]) + 0x40 + i); + } +} + int arch_cpu_init(void) { struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; @@ -613,6 +636,8 @@ int arch_cpu_init(void) imx8m_setup_snvs(); + imx8m_setup_csu_tzasc(); + return 0; } From ed50f82ceb678309eb350eff061fffcacf9c878c Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 22 Dec 2022 01:46:43 +0100 Subject: [PATCH 71/87] arm: imx: imx8m: Add basic PSCI provider implementation Implement basic PSCI provider to let OS turn CPU cores off and on, power off and restart the system and determine PSCI version. This is sufficient to remove the need for the ATF BL31 blob altogether. To make use of this functionality, active the following Kconfig options: # CONFIG_PSCI_RESET is not set CONFIG_ARMV8_MULTIENTRY=y CONFIG_ARMV8_SET_SMPEN=y CONFIG_ARMV8_SPL_EXCEPTION_VECTORS=y CONFIG_ARMV8_EA_EL3_FIRST=y CONFIG_ARMV8_PSCI=y CONFIG_ARMV8_PSCI_CPUS_PER_CLUSTER=4 CONFIG_ARMV8_SECURE_BASE=0x970000 CONFIG_ARM_SMCCC=y CONFIG_SYS_HAS_ARMV8_SECURE_BASE=y Signed-off-by: Marek Vasut --- arch/arm/mach-imx/imx8m/Kconfig | 8 + arch/arm/mach-imx/imx8m/Makefile | 1 + arch/arm/mach-imx/imx8m/psci.c | 288 +++++++++++++++++++++++++++++++ 3 files changed, 297 insertions(+) create mode 100644 arch/arm/mach-imx/imx8m/psci.c diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 6d35cda0bee..c332f849945 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -27,6 +27,14 @@ config IMX8MP config SYS_SOC default "imx8m" +config SYS_HAS_ARMV8_SECURE_BASE + bool "Enable secure address for PSCI image" + depends on ARMV8_PSCI + help + PSCI image can be re-located to secure RAM. + If enabled, please also define the value for ARMV8_SECURE_BASE, + for i.MX8M, it could be some address in OCRAM. + choice prompt "NXP i.MX8M board select" optional diff --git a/arch/arm/mach-imx/imx8m/Makefile b/arch/arm/mach-imx/imx8m/Makefile index d9dee894aae..abd5ddc1774 100644 --- a/arch/arm/mach-imx/imx8m/Makefile +++ b/arch/arm/mach-imx/imx8m/Makefile @@ -4,5 +4,6 @@ obj-y += lowlevel_init.o obj-y += clock_slice.o soc.o +obj-$(CONFIG_ARMV8_PSCI) += psci.o obj-$(CONFIG_IMX8MQ) += clock_imx8mq.o obj-$(CONFIG_IMX8MM)$(CONFIG_IMX8MN)$(CONFIG_IMX8MP) += clock_imx8mm.o diff --git a/arch/arm/mach-imx/imx8m/psci.c b/arch/arm/mach-imx/imx8m/psci.c new file mode 100644 index 00000000000..62f0b768cfa --- /dev/null +++ b/arch/arm/mach-imx/imx8m/psci.c @@ -0,0 +1,288 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * This file implements basic PSCI support for i.MX8M + * + * Copyright (C) 2022 Marek Vasut + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SNVS_LPCR 0x38 +#define SNVS_LPCR_TOP BIT(6) +#define SNVS_LPCR_DP_EN BIT(5) +#define SNVS_LPCR_SRTC_ENV BIT(0) + +#define MPIDR_AFF0 GENMASK(7, 0) + +#define GPC_LPCR_A53_AD 0x4 +#define EN_Cn_WFI_PDN(cpu) BIT(((((cpu) & 1) * 2) + (((cpu) & 2) * 8))) +#define GPC_PGC_nCTRL(cpu) (0x800 + ((cpu) * 0x40)) +#define PGC_PCR BIT(0) +#define GPC_CPU_PGC_SW_PUP_REQ (IS_ENABLED(CONFIG_IMX8MP) ? 0xd0 : 0xf0) +#define COREn_A53_SW_PUP_REQ(cpu) BIT(cpu) + +#define SRC_A53RCR1 0x8 +#define A53_COREn_ENABLE(n) BIT(n) +#define SRC_GPR(n) (0x74 + ((n) * 4)) + +/* + * Helper code + */ +static u8 psci_state[CONFIG_ARMV8_PSCI_NR_CPUS] __secure_data = { + PSCI_AFFINITY_LEVEL_ON, + PSCI_AFFINITY_LEVEL_OFF, + PSCI_AFFINITY_LEVEL_OFF, + PSCI_AFFINITY_LEVEL_OFF +}; + +int psci_update_dt(void *fdt) +{ + return 0; +} + +__secure static void psci_set_state(int cpu, u8 state) +{ + psci_state[cpu] = state; + dsb(); + isb(); +} + +__secure static s32 psci_cpu_on_validate_mpidr(u64 mpidr, u32 *cpu) +{ + *cpu = mpidr & MPIDR_AFF0; + + if (mpidr & ~MPIDR_AFF0) + return ARM_PSCI_RET_INVAL; + + if (*cpu >= CONFIG_ARMV8_PSCI_NR_CPUS) + return ARM_PSCI_RET_INVAL; + + if (psci_state[*cpu] == PSCI_AFFINITY_LEVEL_ON) + return ARM_PSCI_RET_ALREADY_ON; + + if (psci_state[*cpu] == PSCI_AFFINITY_LEVEL_ON_PENDING) + return ARM_PSCI_RET_ON_PENDING; + + return ARM_PSCI_RET_SUCCESS; +} + +__secure static void psci_cpu_on_write_entry_point(const u32 cpu, u64 entry_point) +{ + const u64 ep = CONFIG_SPL_TEXT_BASE; + + /* Trampoline target */ + writeq(entry_point, CPU_RELEASE_ADDR); + /* RVBAR address HI */ + writel((u32)(ep >> 24) & 0xffff, + (void *)SRC_BASE_ADDR + SRC_GPR(cpu * 2)); + /* RVBAR address LO */ + writel((u32)(ep >> 2) & 0x3fffff, + (void *)SRC_BASE_ADDR + SRC_GPR(cpu * 2 + 1)); +} + +__secure static void psci_cpu_on_power_on(const u32 cpu) +{ + int i; + + clrbits_le32((void *)GPC_BASE_ADDR + GPC_LPCR_A53_AD, EN_Cn_WFI_PDN(cpu)); + clrbits_le32((void *)SRC_BASE_ADDR + SRC_A53RCR1, A53_COREn_ENABLE(cpu)); + setbits_le32((void *)GPC_BASE_ADDR + GPC_PGC_nCTRL(cpu), PGC_PCR); + setbits_le32((void *)GPC_BASE_ADDR + GPC_CPU_PGC_SW_PUP_REQ, COREn_A53_SW_PUP_REQ(cpu)); + + /* If we fail here, the core gets power cycled, hang is OK */ + while (readl(GPC_BASE_ADDR + GPC_CPU_PGC_SW_PUP_REQ) & COREn_A53_SW_PUP_REQ(cpu)) + ; + + clrbits_le32((void *)GPC_BASE_ADDR + GPC_PGC_nCTRL(cpu), PGC_PCR); + setbits_le32((void *)SRC_BASE_ADDR + SRC_A53RCR1, A53_COREn_ENABLE(cpu)); + + /* Give the core a bit of time to boot and start executing code */ + for (i = 0; i < 100000; i++) + asm volatile("nop"); +} + +__secure static void psci_cpu_on_power_off(const u32 cpu) +{ + setbits_le32((void *)GPC_BASE_ADDR + GPC_LPCR_A53_AD, EN_Cn_WFI_PDN(cpu)); + setbits_le32((void *)GPC_BASE_ADDR + GPC_PGC_nCTRL(cpu), PGC_PCR); +} + +/* + * Common PSCI code + */ +/* Return supported PSCI version */ +__secure u32 psci_version(void) +{ + return ARM_PSCI_VER_1_0; +} + +/* + * 64bit PSCI code + */ +__secure s32 psci_cpu_on_64(u32 __always_unused function_id, u64 mpidr, + u64 entry_point_address, u64 context_id) +{ + u32 cpu = 0; + int ret; + + ret = psci_cpu_on_validate_mpidr(mpidr, &cpu); + if (ret != ARM_PSCI_RET_SUCCESS) + return ret; + + psci_cpu_on_write_entry_point(cpu, entry_point_address); + + psci_set_state(cpu, PSCI_AFFINITY_LEVEL_ON); + + psci_cpu_on_power_on(cpu); + + smp_kick_all_cpus(); + + return ARM_PSCI_RET_SUCCESS; +} + +__secure s32 psci_affinity_info_64(u32 __always_unused function_id, + u64 target_affinity, u32 lowest_affinity_level) +{ + u32 cpu = target_affinity & MPIDR_AFF0; + + if (lowest_affinity_level > 0) + return ARM_PSCI_RET_INVAL; + + if (target_affinity & ~MPIDR_AFF0) + return ARM_PSCI_RET_INVAL; + + if (cpu >= CONFIG_ARMV8_PSCI_NR_CPUS) + return ARM_PSCI_RET_INVAL; + + return psci_state[cpu]; +} + +__secure s32 psci_system_reset2_64(u32 __always_unused function_id, + u32 reset_type, u64 cookie) +{ + psci_system_reset(); + return 0; /* Not reached */ +} + +/* + * 32bit PSCI code + */ +__secure s32 psci_affinity_info(u32 __always_unused function_id, + u32 target_affinity, u32 lowest_affinity_level) +{ + return psci_affinity_info_64(function_id, target_affinity, lowest_affinity_level); +} + +__secure s32 psci_cpu_on(u32 __always_unused function_id, u32 mpidr, + u32 entry_point_address, u32 context_id) +{ + return psci_cpu_on_64(function_id, mpidr, entry_point_address, context_id); +} + +__secure s32 psci_cpu_off(void) +{ + u32 cpu = psci_get_cpu_id(); + + psci_cpu_on_power_off(cpu); + psci_set_state(cpu, PSCI_AFFINITY_LEVEL_OFF); + + while (1) + wfi(); +} + +__secure u32 psci_migrate_info_type(void) +{ + /* Trusted OS is either not present or does not require migration */ + return 2; +} + +__secure void psci_system_reset(void) +{ + struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; + bool ext_reset = true; + + u16 wcr = WCR_WDE; + + if (ext_reset) + wcr |= WCR_SRS; /* do not assert internal reset */ + else + wcr |= WCR_WDA; /* do not assert external reset */ + + /* Write 3 times to ensure it works, due to IMX6Q errata ERR004346 */ + writew(wcr, &wdog->wcr); + writew(wcr, &wdog->wcr); + writew(wcr, &wdog->wcr); + + while (1) + wfi(); +} + +__secure void psci_system_off(void) +{ + writel(SNVS_LPCR_TOP | SNVS_LPCR_DP_EN | SNVS_LPCR_SRTC_ENV, + SNVS_BASE_ADDR + SNVS_LPCR); + + while (1) + wfi(); +} + +/* + * PSCI jump table + */ +__secure s32 psci_features(u32 __always_unused function_id, u32 psci_fid) +{ + switch (psci_fid) { + case ARM_PSCI_0_2_FN_PSCI_VERSION: + case ARM_PSCI_0_2_FN_CPU_OFF: + case ARM_PSCI_0_2_FN_CPU_ON: + case ARM_PSCI_0_2_FN_AFFINITY_INFO: + case ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE: + case ARM_PSCI_0_2_FN_SYSTEM_OFF: + case ARM_PSCI_0_2_FN_SYSTEM_RESET: + case ARM_PSCI_0_2_FN64_CPU_ON: + case ARM_PSCI_0_2_FN64_AFFINITY_INFO: + + /* PSCI 1.0 interface */ + case ARM_PSCI_1_0_FN_PSCI_FEATURES: + + /* PSCI 1.1 interface */ + case ARM_PSCI_1_1_FN64_SYSTEM_RESET2: + return 0x0; + + /* + * Not implemented: + * ARM_PSCI_0_2_FN_CPU_SUSPEND + * ARM_PSCI_1_0_FN_CPU_FREEZE + * ARM_PSCI_1_0_FN_CPU_DEFAULT_SUSPEND + * ARM_PSCI_1_0_FN_NODE_HW_STATE + * ARM_PSCI_1_0_FN_SYSTEM_SUSPEND + * ARM_PSCI_1_0_FN_SET_SUSPEND_MODE + * ARM_PSCI_1_0_FN_STAT_RESIDENCY + * ARM_PSCI_1_0_FN_STAT_COUNT + * ARM_PSCI_0_2_FN64_CPU_SUSPEND + * ARM_PSCI_1_0_FN64_CPU_DEFAULT_SUSPEND + * ARM_PSCI_1_0_FN64_NODE_HW_STATE + * ARM_PSCI_1_0_FN64_SYSTEM_SUSPEND + * ARM_PSCI_1_0_FN64_STAT_RESIDENCY + * ARM_PSCI_1_0_FN64_STAT_COUNT + */ + + /* Not required, ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE returns 2 */ + case ARM_PSCI_0_2_FN_MIGRATE: + case ARM_PSCI_0_2_FN64_MIGRATE: + /* Not required */ + case ARM_PSCI_0_2_FN_MIGRATE_INFO_UP_CPU: + case ARM_PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU: + default: + return ARM_PSCI_RET_NI; + } +} From 0cf91115edff03df55c04dfdc3a0d7f505a22edf Mon Sep 17 00:00:00 2001 From: Andrejs Cainikovs Date: Tue, 17 Jan 2023 15:29:11 +0100 Subject: [PATCH 72/87] board: apalis-imx8: add 2nd ethernet address All Apalis iMX8 variants have 2nd RGMII on SoC, so add the address for 2nd ethernet. Signed-off-by: Andrejs Cainikovs Signed-off-by: Francesco Dolcini --- board/toradex/apalis-imx8/Kconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/board/toradex/apalis-imx8/Kconfig b/board/toradex/apalis-imx8/Kconfig index b43d6281b68..f16f9d27022 100644 --- a/board/toradex/apalis-imx8/Kconfig +++ b/board/toradex/apalis-imx8/Kconfig @@ -12,6 +12,9 @@ config SYS_CONFIG_NAME config TDX_CFG_BLOCK default y +config TDX_CFG_BLOCK_2ND_ETHADDR + default y + config TDX_HAVE_MMC default y From d3655bbb1398644e0b336a3ebde25be8c42424ff Mon Sep 17 00:00:00 2001 From: Max Krummenacher Date: Mon, 30 Jan 2023 13:39:06 +0100 Subject: [PATCH 73/87] ARM: arm: colibri-imx6ull-emmc: fix emmc access Synchronizing the device tree with linux introduced a regression. The U-Boot specific dtsi mustn't override the alias settings for the eMMC/SD interfaces. Without this U-Boot cannot access the eMMC and boot the kernel. Fixes: c21b61bff15 ("colibri-imx6ull/-emmc: synchronise device tree with linux") Signed-off-by: Max Krummenacher --- arch/arm/dts/imx6ull-colibri-eval-v3-u-boot.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/dts/imx6ull-colibri-eval-v3-u-boot.dtsi b/arch/arm/dts/imx6ull-colibri-eval-v3-u-boot.dtsi index 65dfeab5bb2..0a732269bab 100644 --- a/arch/arm/dts/imx6ull-colibri-eval-v3-u-boot.dtsi +++ b/arch/arm/dts/imx6ull-colibri-eval-v3-u-boot.dtsi @@ -6,7 +6,6 @@ / { aliases { u-boot,dm-pre-reloc; - mmc0 = &usdhc1; usb0 = &usbotg1; /* required for ums */ display0 = &lcdif; }; From e64bfd7b71b5d100bc7e682748caea8a24bf4f72 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Mon, 14 Nov 2022 22:07:54 +0000 Subject: [PATCH 74/87] include/configs: mx6/mx7: drop dangling comments Cleanup some dangling comments left by automated migration processes that are no longer value. Signed-off-by: Peter Robinson Acked-by: Peng Fan --- include/configs/mx6_common.h | 4 ---- include/configs/mx7_common.h | 12 ------------ 2 files changed, 16 deletions(-) diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index 0b8233de8c4..3db8e09b42a 100644 --- a/include/configs/mx6_common.h +++ b/include/configs/mx6_common.h @@ -21,8 +21,4 @@ #include #include -/* Miscellaneous configurable options */ - -/* MMC */ - #endif diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h index a542839ce1d..d0718bfa03e 100644 --- a/include/configs/mx7_common.h +++ b/include/configs/mx7_common.h @@ -16,16 +16,4 @@ /* Timer settings */ #define CFG_SC_TIMER_CLK 8000000 /* 8Mhz */ -/* Miscellaneous configurable options */ - -/* UART */ - -/* MMC */ - -/* - * If we have defined the OPTEE ram size and not OPTEE it means that we were - * launched by OPTEE, because of that we shall skip all the low level - * initialization since it was already done by ATF or OPTEE - */ - #endif From f0f461287eff2a797fefd845aa746df17f5b0624 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 12 Jan 2023 21:52:23 -0300 Subject: [PATCH 75/87] imx: Suggest the NXP ATF github repo As explained in the text at the bottom of the page https://source.codeaurora.org/external/imx/imx-atf: "QUIC repositories on this site will not receive any updates after March 31, 2022, and will be deleted on March 31, 2023." Point to the NXP ATF github repo instead. Signed-off-by: Fabio Estevam Reviewed-by: Oliver Graute Reviewed-by: Marcel Ziswiler Reviewed-by: Frieder Schrempf --- board/beacon/imx8mm/README | 2 +- board/beacon/imx8mn/README | 2 +- board/freescale/imx8qm_mek/README | 2 +- board/gateworks/venice/README | 2 +- board/google/imx8mq_phanbell/README | 2 +- board/ronetix/imx8mq-cm/README | 2 +- doc/board/advantech/imx8qm-rom7720-a1.rst | 2 +- doc/board/congatec/cgtqmx8.rst | 2 +- doc/board/kontron/sl-mx8mm.rst | 2 +- doc/board/nxp/imx8mm_evk.rst | 2 +- doc/board/nxp/imx8mn_evk.rst | 2 +- doc/board/nxp/imx8mp_evk.rst | 2 +- doc/board/nxp/imx8mq_evk.rst | 2 +- doc/board/nxp/imx8qxp_mek.rst | 2 +- doc/board/toradex/apalis-imx8.rst | 2 +- 15 files changed, 15 insertions(+), 15 deletions(-) diff --git a/board/beacon/imx8mm/README b/board/beacon/imx8mm/README index c65acef22d8..32b24bc03eb 100644 --- a/board/beacon/imx8mm/README +++ b/board/beacon/imx8mm/README @@ -11,7 +11,7 @@ Get and Build the ARM Trusted firmware ====================================== Note: $(srctree) is U-Boot source directory -$ git clone https://source.codeaurora.org/external/imx/imx-atf +$ git clone https://github.com/nxp-imx/imx-atf $ git lf-5.10.72-2.2.0 $ make PLAT=imx8mm bl31 CROSS_COMPILE=aarch64-linux-gnu- $ cp build/imx8mm/release/bl31.bin $(srctree) diff --git a/board/beacon/imx8mn/README b/board/beacon/imx8mn/README index 788ab1093b4..49da03c8d83 100644 --- a/board/beacon/imx8mn/README +++ b/board/beacon/imx8mn/README @@ -11,7 +11,7 @@ Get and Build the ARM Trusted firmware ====================================== Note: $(srctree) is U-Boot source directory -$ git clone https://source.codeaurora.org/external/imx/imx-atf +$ git clone https://github.com/nxp-imx/imx-atf $ git lf-5.10.72-2.2.0 $ make PLAT=imx8mn bl31 CROSS_COMPILE=aarch64-linux-gnu- $ cp build/imx8mn/release/bl31.bin $(srctree) diff --git a/board/freescale/imx8qm_mek/README b/board/freescale/imx8qm_mek/README index b1a4c6cc822..47fae3d2843 100644 --- a/board/freescale/imx8qm_mek/README +++ b/board/freescale/imx8qm_mek/README @@ -12,7 +12,7 @@ Quick Start Get and Build the ARM Trusted firmware ====================================== -$ git clone https://source.codeaurora.org/external/imx/imx-atf +$ git clone https://github.com/nxp-imx/imx-atf $ cd imx-atf/ $ git checkout origin/imx_4.14.78_1.0.0_ga -b imx_4.14.78_1.0.0_ga $ make PLAT=imx8qm bl31 diff --git a/board/gateworks/venice/README b/board/gateworks/venice/README index 9f3a250bb66..ea9b8348a7d 100644 --- a/board/gateworks/venice/README +++ b/board/gateworks/venice/README @@ -10,7 +10,7 @@ Quick Start Get and Build the ARM Trusted firmware ====================================== -$ git clone https://source.codeaurora.org/external/imx/imx-atf +$ git clone https://github.com/nxp-imx/imx-atf $ git checkout imx_5.4.47_2.2.0 $ make PLAT=imx8mm CROSS_COMPILE=aarch64-linux-gnu- bl31 $ cp build/imx8mm/release/bl31.bin . diff --git a/board/google/imx8mq_phanbell/README b/board/google/imx8mq_phanbell/README index 88a136b32c8..7c63fc52a73 100644 --- a/board/google/imx8mq_phanbell/README +++ b/board/google/imx8mq_phanbell/README @@ -10,7 +10,7 @@ Quick Start Get and Build the ARM Trusted firmware ====================================== Note: srctree is U-Boot source directory -Get ATF from: https://source.codeaurora.org/external/imx/imx-atf +Get ATF from: https://github.com/nxp-imx/imx-atf branch: imx_4.19.35_1.0.0 $ make PLAT=imx8mq bl31 $ cp build/imx8mq/release/bl31.bin $(builddir) diff --git a/board/ronetix/imx8mq-cm/README b/board/ronetix/imx8mq-cm/README index 1d43fa5f4f8..c57ff2477ea 100644 --- a/board/ronetix/imx8mq-cm/README +++ b/board/ronetix/imx8mq-cm/README @@ -9,7 +9,7 @@ Quick Start Get and Build the ARM Trusted firmware ====================================== -$ git clone https://source.codeaurora.org/external/imx/imx-atf +$ git clone https://github.com/nxp-imx/imx-atf $ cd imx-atf $ git checkout imx_4.19.35_1.0.0 $ make PLAT=imx8mq bl31 diff --git a/doc/board/advantech/imx8qm-rom7720-a1.rst b/doc/board/advantech/imx8qm-rom7720-a1.rst index 953cf01fde4..13ea2eb19e4 100644 --- a/doc/board/advantech/imx8qm-rom7720-a1.rst +++ b/doc/board/advantech/imx8qm-rom7720-a1.rst @@ -19,7 +19,7 @@ Get and Build the ARM Trusted firmware .. code-block:: bash - $ git clone https://source.codeaurora.org/external/imx/imx-atf + $ git clone https://github.com/nxp-imx/imx-atf $ cd imx-atf/ $ git checkout origin/imx_4.14.78_1.0.0_ga -b imx_4.14.78_1.0.0_ga $ make PLAT=imx8qm bl31 diff --git a/doc/board/congatec/cgtqmx8.rst b/doc/board/congatec/cgtqmx8.rst index 16711a844d5..a970cb82a12 100644 --- a/doc/board/congatec/cgtqmx8.rst +++ b/doc/board/congatec/cgtqmx8.rst @@ -19,7 +19,7 @@ Get and Build the ARM Trusted firmware .. code-block:: bash - $ git clone https://source.codeaurora.org/external/imx/imx-atf + $ git clone https://github.com/nxp-imx/imx-atf $ cd imx-atf/ $ git checkout origin/imx_4.14.78_1.0.0_ga -b imx_4.14.78_1.0.0_ga $ make PLAT=imx8qm bl31 diff --git a/doc/board/kontron/sl-mx8mm.rst b/doc/board/kontron/sl-mx8mm.rst index 702db60fe38..09c50aa8b16 100644 --- a/doc/board/kontron/sl-mx8mm.rst +++ b/doc/board/kontron/sl-mx8mm.rst @@ -40,7 +40,7 @@ There are two sources for the TF-A. Mainline and NXP. Get the one you prefer **NXP's imx-atf** -1. Get TF-A from: https://github.com/nxp-imx/imx-atf, branch: lf_v2.6 +1. Get TF-A from: https://github.com/nxp-imx/imx-atf, branch: imx_5.4.70_2.3.0 2. Build .. code-block:: bash diff --git a/doc/board/nxp/imx8mm_evk.rst b/doc/board/nxp/imx8mm_evk.rst index 5b178d703e9..327ce6e49cc 100644 --- a/doc/board/nxp/imx8mm_evk.rst +++ b/doc/board/nxp/imx8mm_evk.rst @@ -17,7 +17,7 @@ Get and Build the ARM Trusted firmware -------------------------------------- Note: builddir is U-Boot build directory (source directory for in-tree builds) -Get ATF from: https://source.codeaurora.org/external/imx/imx-atf +Get ATF from: https://github.com/nxp-imx/imx-atf branch: imx_5.4.47_2.2.0 .. code-block:: bash diff --git a/doc/board/nxp/imx8mn_evk.rst b/doc/board/nxp/imx8mn_evk.rst index c45bb7bac7a..4f225ea6601 100644 --- a/doc/board/nxp/imx8mn_evk.rst +++ b/doc/board/nxp/imx8mn_evk.rst @@ -17,7 +17,7 @@ Get and Build the ARM Trusted firmware -------------------------------------- Note: srctree is U-Boot source directory -Get ATF from: https://source.codeaurora.org/external/imx/imx-atf +Get ATF from: https://github.com/nxp-imx/imx-atf branch: imx_5.4.47_2.2.0 .. code-block:: bash diff --git a/doc/board/nxp/imx8mp_evk.rst b/doc/board/nxp/imx8mp_evk.rst index b996ae055e6..e7cc7b396b5 100644 --- a/doc/board/nxp/imx8mp_evk.rst +++ b/doc/board/nxp/imx8mp_evk.rst @@ -16,7 +16,7 @@ Quick Start Get and Build the ARM Trusted firmware -------------------------------------- -Get ATF from: https://source.codeaurora.org/external/imx/imx-atf +Get ATF from: https://github.com/nxp-imx/imx-atf branch: imx_5.4.70_2.3.0 .. code-block:: bash diff --git a/doc/board/nxp/imx8mq_evk.rst b/doc/board/nxp/imx8mq_evk.rst index aa1ecfb47ad..4b0624e7e86 100644 --- a/doc/board/nxp/imx8mq_evk.rst +++ b/doc/board/nxp/imx8mq_evk.rst @@ -17,7 +17,7 @@ Get and Build the ARM Trusted firmware -------------------------------------- Note: srctree is U-Boot source directory -Get ATF from: https://source.codeaurora.org/external/imx/imx-atf +Get ATF from: https://github.com/nxp-imx/imx-atf branch: imx_5.4.47_2.2.0 .. code-block:: bash diff --git a/doc/board/nxp/imx8qxp_mek.rst b/doc/board/nxp/imx8qxp_mek.rst index 708db1952e9..bdd38368f1a 100644 --- a/doc/board/nxp/imx8qxp_mek.rst +++ b/doc/board/nxp/imx8qxp_mek.rst @@ -19,7 +19,7 @@ Get and Build the ARM Trusted firmware .. code-block:: bash - $ git clone https://source.codeaurora.org/external/imx/imx-atf + $ git clone https://github.com/nxp-imx/imx-atf $ cd imx-atf/ $ git checkout origin/imx_4.19.35_1.1.0 -b imx_4.19.35_1.1.0 $ make PLAT=imx8qx bl31 diff --git a/doc/board/toradex/apalis-imx8.rst b/doc/board/toradex/apalis-imx8.rst index 29593faf1a0..849b1172bd4 100644 --- a/doc/board/toradex/apalis-imx8.rst +++ b/doc/board/toradex/apalis-imx8.rst @@ -18,7 +18,7 @@ Get and Build the ARM Trusted Firmware .. code-block:: bash - $ git clone -b imx_4.14.78_1.0.0_ga https://source.codeaurora.org/external/imx/imx-atf + $ git clone -b imx_4.14.78_1.0.0_ga https://github.com/nxp-imx/imx-atf $ cd imx-atf/ $ make PLAT=imx8qm bl31 From ea993cc26a8c1ffb355ae678acb01cfeabb8c963 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 7 Nov 2022 16:13:37 +0800 Subject: [PATCH 76/87] imx: mx6sabreauto: convert to DM_I2C Convert to DM_I2C Signed-off-by: Peng Fan --- configs/mx6sabreauto_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/mx6sabreauto_defconfig b/configs/mx6sabreauto_defconfig index 639f552b6da..50f63c23b17 100644 --- a/configs/mx6sabreauto_defconfig +++ b/configs/mx6sabreauto_defconfig @@ -76,7 +76,7 @@ CONFIG_ARP_TIMEOUT=200 CONFIG_BOUNCE_BUFFER=y CONFIG_DFU_MMC=y CONFIG_DFU_SF=y -CONFIG_SYS_I2C_LEGACY=y +CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y From 57d48522c9ad23ccc2736fbf6f4895bb496987c4 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 7 Nov 2022 16:13:38 +0800 Subject: [PATCH 77/87] imx: mx6sabresd: convert to DM_I2C Convert to DM_I2C Signed-off-by: Peng Fan --- configs/mx6sabresd_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig index cae23b93ec2..69058500839 100644 --- a/configs/mx6sabresd_defconfig +++ b/configs/mx6sabresd_defconfig @@ -82,7 +82,7 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12000000 CONFIG_FASTBOOT_BUF_SIZE=0x10000000 CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=2 -CONFIG_SYS_I2C_LEGACY=y +CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MXC=y CONFIG_SUPPORT_EMMC_BOOT=y From 4e2e2f898414c25f23349e19d2d0e9183ec6cab4 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Fri, 11 Nov 2022 07:55:46 -0800 Subject: [PATCH 78/87] arm64: dts: imx8m{m, n}-venice-gw7902: add gpio pins for new board revision Add gpio pins present on new board revision: * LTE modem support (imx8mm-gw7902 only) - lte_pwr# - lte_rst - lte_int * M2 power enable - m2_pwr_en * off-board 4.0V supply - vdd_4p0_en Signed-off-by: Tim Harvey --- arch/arm/dts/imx8mm-venice-gw7902-u-boot.dtsi | 14 ++++++++++++++ arch/arm/dts/imx8mm-venice-gw7902.dts | 12 ++++++++---- arch/arm/dts/imx8mn-venice-gw7902-u-boot.dtsi | 14 ++++++++++++++ arch/arm/dts/imx8mn-venice-gw7902.dts | 8 ++++---- 4 files changed, 40 insertions(+), 8 deletions(-) diff --git a/arch/arm/dts/imx8mm-venice-gw7902-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-gw7902-u-boot.dtsi index f21e46b12dd..d58a7d14b63 100644 --- a/arch/arm/dts/imx8mm-venice-gw7902-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-venice-gw7902-u-boot.dtsi @@ -6,6 +6,13 @@ #include "imx8mm-venice-u-boot.dtsi" &gpio1 { + m2pwren { + gpio-hog; + output-low; + gpios = <8 GPIO_ACTIVE_HIGH>; + line-name = "m2_pwren"; + }; + m2rst { gpio-hog; output-low; @@ -96,6 +103,13 @@ line-name = "app_gpio1"; }; + vdd4p0en { + gpio-hog; + output-low; + gpios = <22 GPIO_ACTIVE_HIGH>; + line-name = "vdd_4p0_en"; + }; + uart1rs485 { gpio-hog; output-low; diff --git a/arch/arm/dts/imx8mm-venice-gw7902.dts b/arch/arm/dts/imx8mm-venice-gw7902.dts index 31f4c735fe4..921bffae0cc 100644 --- a/arch/arm/dts/imx8mm-venice-gw7902.dts +++ b/arch/arm/dts/imx8mm-venice-gw7902.dts @@ -261,7 +261,7 @@ &gpio1 { gpio-line-names = "", "", "", "", "", "", "", "", - "", "", "", "", "", "m2_reset", "", "m2_wdis#", + "m2_pwr_en", "", "", "", "", "m2_reset", "", "m2_wdis#", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; @@ -283,7 +283,8 @@ &gpio4 { gpio-line-names = "", "", "", "", "", "", "", "", "", "", "", "amp_gpio3", "amp_gpio2", "", "amp_gpio1", "", - "", "", "", "", "amp_gpio4", "app_gpio1", "", "uart1_rs485", + "lte_pwr#", "lte_rst", "lte_int", "", + "amp_gpio4", "app_gpio1", "vdd_4p0_en", "uart1_rs485", "", "uart1_term", "uart1_half", "app_gpio2", "mipi_gpio1", "", "", ""; }; @@ -738,14 +739,19 @@ pinctrl_hog: hoggrp { fsl,pins = < MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */ + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x40000041 /* M2_PWR_EN */ MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RESET */ MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */ MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */ + MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x40000041 /* LTE_INT */ + MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x40000041 /* LTE_RST# */ + MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x40000041 /* LTE_PWR */ MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x40000041 /* AMP GPIO1 */ MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x40000041 /* AMP GPIO2 */ MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x40000041 /* AMP GPIO3 */ MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x40000041 /* AMP_GPIO4 */ MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 /* APP GPIO1 */ + MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x40000041 /* VDD_4P0_EN */ MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* APP GPIO2 */ MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* UART2_EN# */ MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x40000041 /* MIPI_GPIO1 */ @@ -779,8 +785,6 @@ MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* RST# */ MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* IRQ# */ - MX8MM_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x141 - MX8MM_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x141 >; }; diff --git a/arch/arm/dts/imx8mn-venice-gw7902-u-boot.dtsi b/arch/arm/dts/imx8mn-venice-gw7902-u-boot.dtsi index 17e6828c79f..10656ce903a 100644 --- a/arch/arm/dts/imx8mn-venice-gw7902-u-boot.dtsi +++ b/arch/arm/dts/imx8mn-venice-gw7902-u-boot.dtsi @@ -6,6 +6,13 @@ #include "imx8mn-venice-u-boot.dtsi" &gpio1 { + m2pwren { + gpio-hog; + output-low; + gpios = <8 GPIO_ACTIVE_HIGH>; + line-name = "m2_pwren"; + }; + m2rst { gpio-hog; output-low; @@ -54,6 +61,13 @@ line-name = "app_gpio1"; }; + vdd4p0en { + gpio-hog; + output-low; + gpios = <22 GPIO_ACTIVE_HIGH>; + line-name = "vdd_4p0_en"; + }; + uart1rs485 { gpio-hog; output-low; diff --git a/arch/arm/dts/imx8mn-venice-gw7902.dts b/arch/arm/dts/imx8mn-venice-gw7902.dts index dd4302ac1de..029ccdbee7d 100644 --- a/arch/arm/dts/imx8mn-venice-gw7902.dts +++ b/arch/arm/dts/imx8mn-venice-gw7902.dts @@ -256,7 +256,7 @@ &gpio1 { gpio-line-names = "", "", "", "", "", "", "", "", - "", "", "", "", "", "m2_reset", "", "m2_wdis#", + "m2_pwr_en", "", "", "", "", "m2_reset", "", "m2_wdis#", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; @@ -278,7 +278,7 @@ &gpio4 { gpio-line-names = "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", - "", "", "", "", "", "app_gpio1", "", "uart1_rs485", + "", "", "", "", "", "app_gpio1", "vdd_4p0_en", "uart1_rs485", "", "uart1_term", "uart1_half", "app_gpio2", "mipi_gpio1", "", "", ""; }; @@ -689,10 +689,12 @@ pinctrl_hog: hoggrp { fsl,pins = < MX8MN_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */ + MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x40000041 /* M2_PWR_EN */ MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RESET */ MX8MN_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */ MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */ MX8MN_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 /* APP GPIO1 */ + MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x40000041 /* VDD_4P0_EN */ MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* APP GPIO2 */ MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* UART2_EN# */ MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x40000041 /* MIPI_GPIO1 */ @@ -726,8 +728,6 @@ MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* RST# */ MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* IRQ# */ - MX8MN_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x141 - MX8MN_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x141 >; }; From a4dc847b6017cfedd246623ed29e6f85ae0b67c6 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Fri, 11 Nov 2022 08:03:06 -0800 Subject: [PATCH 79/87] arm: dts: imx8m*-venice-*: add I2C GPIO bus recovery support Add I2C GPIO bus recovery support by adding scl-gpios and sda-gpios for the various I2C busses on Gateworks Venice boards. Signed-off-by: Tim Harvey Reviewed-by: Fabio Estevam --- arch/arm/dts/imx8mm-venice-gw700x.dtsi | 24 +++++++++++-- arch/arm/dts/imx8mm-venice-gw7901.dts | 48 +++++++++++++++++++++++--- arch/arm/dts/imx8mm-venice-gw7902.dts | 48 +++++++++++++++++++++++--- arch/arm/dts/imx8mm-venice-gw7903.dts | 36 +++++++++++++++++-- arch/arm/dts/imx8mm-venice-gw7904.dts | 48 +++++++++++++++++++++++--- arch/arm/dts/imx8mn-venice-gw7902.dts | 48 +++++++++++++++++++++++--- arch/arm/dts/imx8mp-venice-gw74xx.dts | 48 +++++++++++++++++++++++--- 7 files changed, 275 insertions(+), 25 deletions(-) diff --git a/arch/arm/dts/imx8mm-venice-gw700x.dtsi b/arch/arm/dts/imx8mm-venice-gw700x.dtsi index 66a0d103c90..c305e325d00 100644 --- a/arch/arm/dts/imx8mm-venice-gw700x.dtsi +++ b/arch/arm/dts/imx8mm-venice-gw700x.dtsi @@ -119,8 +119,11 @@ &i2c1 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; gsc: gsc@20 { @@ -365,8 +368,11 @@ &i2c2 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; eeprom@52 { @@ -435,6 +441,13 @@ >; }; + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3 + >; + }; + pinctrl_i2c2: i2c2grp { fsl,pins = < MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 @@ -442,6 +455,13 @@ >; }; + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3 + MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3 + >; + }; + pinctrl_uart2: uart2grp { fsl,pins = < MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 diff --git a/arch/arm/dts/imx8mm-venice-gw7901.dts b/arch/arm/dts/imx8mm-venice-gw7901.dts index d3ee6fc4baa..826627bd450 100644 --- a/arch/arm/dts/imx8mm-venice-gw7901.dts +++ b/arch/arm/dts/imx8mm-venice-gw7901.dts @@ -326,8 +326,11 @@ &i2c1 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; gsc: gsc@20 { @@ -477,8 +480,11 @@ &i2c2 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; pmic@4b { @@ -600,8 +606,11 @@ &i2c3 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; leds_gpio: gpio@20 { @@ -673,8 +682,11 @@ &i2c4 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; }; @@ -852,6 +864,13 @@ >; }; + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3 + >; + }; + pinctrl_i2c2: i2c2grp { fsl,pins = < MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 @@ -859,6 +878,13 @@ >; }; + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3 + MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3 + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 @@ -866,6 +892,13 @@ >; }; + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3 + >; + }; + pinctrl_i2c4: i2c4grp { fsl,pins = < MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 @@ -873,6 +906,13 @@ >; }; + pinctrl_i2c4_gpio: i2c4gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c3 + MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c3 + >; + }; + pinctrl_ksz: kszgrp { fsl,pins = < MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x41 diff --git a/arch/arm/dts/imx8mm-venice-gw7902.dts b/arch/arm/dts/imx8mm-venice-gw7902.dts index 921bffae0cc..11481e09c75 100644 --- a/arch/arm/dts/imx8mm-venice-gw7902.dts +++ b/arch/arm/dts/imx8mm-venice-gw7902.dts @@ -299,8 +299,11 @@ &i2c1 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; gsc: gsc@20 { @@ -567,8 +570,11 @@ &i2c2 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; accelerometer@19 { @@ -586,16 +592,22 @@ /* off-board header */ &i2c3 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; }; /* off-board header */ &i2c4 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; }; @@ -801,6 +813,13 @@ >; }; + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3 + >; + }; + pinctrl_i2c2: i2c2grp { fsl,pins = < MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 @@ -808,6 +827,13 @@ >; }; + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3 + MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3 + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 @@ -815,6 +841,13 @@ >; }; + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3 + >; + }; + pinctrl_i2c4: i2c4grp { fsl,pins = < MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 @@ -822,6 +855,13 @@ >; }; + pinctrl_i2c4_gpio: i2c4gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c3 + MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c3 + >; + }; + pinctrl_gpio_leds: gpioledgrp { fsl,pins = < MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19 diff --git a/arch/arm/dts/imx8mm-venice-gw7903.dts b/arch/arm/dts/imx8mm-venice-gw7903.dts index 19f6d2943d2..1ec91c5c6a4 100644 --- a/arch/arm/dts/imx8mm-venice-gw7903.dts +++ b/arch/arm/dts/imx8mm-venice-gw7903.dts @@ -265,8 +265,11 @@ &i2c1 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; gsc: gsc@20 { @@ -397,8 +400,11 @@ &i2c2 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; pmic@4b { @@ -520,8 +526,11 @@ &i2c3 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; accelerometer@19 { @@ -681,6 +690,13 @@ >; }; + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3 + >; + }; + pinctrl_i2c2: i2c2grp { fsl,pins = < MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 @@ -688,6 +704,13 @@ >; }; + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3 + MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3 + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 @@ -695,6 +718,13 @@ >; }; + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3 + >; + }; + pinctrl_gpio_leds: gpioledgrp { fsl,pins = < MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19 diff --git a/arch/arm/dts/imx8mm-venice-gw7904.dts b/arch/arm/dts/imx8mm-venice-gw7904.dts index a67771d0214..93c9651c315 100644 --- a/arch/arm/dts/imx8mm-venice-gw7904.dts +++ b/arch/arm/dts/imx8mm-venice-gw7904.dts @@ -315,8 +315,11 @@ &i2c1 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; gsc: gsc@20 { @@ -441,8 +444,11 @@ &i2c2 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; pmic@4b { @@ -564,8 +570,11 @@ &i2c3 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; accelerometer@19 { @@ -582,8 +591,11 @@ &i2c4 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; gpioled: gpio@27 { @@ -738,6 +750,13 @@ >; }; + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3 + >; + }; + pinctrl_i2c2: i2c2grp { fsl,pins = < MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 @@ -745,6 +764,13 @@ >; }; + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3 + MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3 + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 @@ -752,6 +778,13 @@ >; }; + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3 + >; + }; + pinctrl_i2c4: i2c4grp { fsl,pins = < MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 @@ -759,6 +792,13 @@ >; }; + pinctrl_i2c4_gpio: i2c4gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c3 + MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c3 + >; + }; + pinctrl_pcie0: pciegrp { fsl,pins = < MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x41 diff --git a/arch/arm/dts/imx8mn-venice-gw7902.dts b/arch/arm/dts/imx8mn-venice-gw7902.dts index 029ccdbee7d..97582db71ca 100644 --- a/arch/arm/dts/imx8mn-venice-gw7902.dts +++ b/arch/arm/dts/imx8mn-venice-gw7902.dts @@ -297,8 +297,11 @@ &i2c1 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; gsc: gsc@20 { @@ -565,8 +568,11 @@ &i2c2 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; accelerometer@19 { @@ -584,16 +590,22 @@ /* off-board header */ &i2c3 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; }; /* off-board header */ &i2c4 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; }; @@ -744,6 +756,13 @@ >; }; + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3 + MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3 + >; + }; + pinctrl_i2c2: i2c2grp { fsl,pins = < MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 @@ -751,6 +770,13 @@ >; }; + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3 + MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3 + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 @@ -758,6 +784,13 @@ >; }; + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3 + MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3 + >; + }; + pinctrl_i2c4: i2c4grp { fsl,pins = < MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 @@ -765,6 +798,13 @@ >; }; + pinctrl_i2c4_gpio: i2c4gpiogrp { + fsl,pins = < + MX8MN_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c3 + MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c3 + >; + }; + pinctrl_gpio_leds: gpioledgrp { fsl,pins = < MX8MN_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19 diff --git a/arch/arm/dts/imx8mp-venice-gw74xx.dts b/arch/arm/dts/imx8mp-venice-gw74xx.dts index 06b4c93c587..ceeca4966fc 100644 --- a/arch/arm/dts/imx8mp-venice-gw74xx.dts +++ b/arch/arm/dts/imx8mp-venice-gw74xx.dts @@ -253,8 +253,11 @@ &i2c1 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; gsc: gsc@20 { @@ -477,8 +480,11 @@ &i2c2 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; accelerometer@19 { @@ -556,16 +562,22 @@ /* off-board header */ &i2c3 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; }; /* off-board header */ &i2c4 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; }; @@ -800,6 +812,13 @@ >; }; + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c2 + MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c2 + >; + }; + pinctrl_i2c2: i2c2grp { fsl,pins = < MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 @@ -807,6 +826,13 @@ >; }; + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c3 + MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c3 + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 @@ -814,6 +840,13 @@ >; }; + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c3 + MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c3 + >; + }; + pinctrl_i2c4: i2c4grp { fsl,pins = < MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c2 @@ -821,6 +854,13 @@ >; }; + pinctrl_i2c4_gpio: i2c4gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x400001c3 + MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001c3 + >; + }; + pinctrl_ksz: kszgrp { fsl,pins = < MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x150 /* IRQ# */ From 3041e094e45dba1853431e88d79a990d86fa80d7 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Fri, 11 Nov 2022 08:03:07 -0800 Subject: [PATCH 80/87] board: gateworks: venice: poll I2C lines to wait for GSC firmware In some situations the GSC firmware where the EEPROM containing the model and DRAM configuration may not be ready by the time the SoC is ready to talk to it over I2C. Instead of a hard delay, poll the I2C lines to wait until they are released to avoid the I2C drivers 'Arbitation lost' error message. Signed-off-by: Tim Harvey Reviewed-by: Fabio Estevam --- arch/arm/dts/imx8mm-venice-u-boot.dtsi | 4 +++ arch/arm/dts/imx8mm-venice.dts | 12 +++++++- arch/arm/dts/imx8mn-venice-u-boot.dtsi | 4 +++ arch/arm/dts/imx8mn-venice.dts | 12 +++++++- arch/arm/dts/imx8mp-venice-u-boot.dtsi | 4 +++ arch/arm/dts/imx8mp-venice.dts | 12 +++++++- board/gateworks/venice/spl.c | 39 +++++++++++++++++--------- 7 files changed, 70 insertions(+), 17 deletions(-) diff --git a/arch/arm/dts/imx8mm-venice-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-u-boot.dtsi index 68978a0413e..6f786b9467c 100644 --- a/arch/arm/dts/imx8mm-venice-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-venice-u-boot.dtsi @@ -57,6 +57,10 @@ u-boot,dm-spl; }; +&pinctrl_i2c1_gpio { + u-boot,dm-spl; +}; + &gsc { u-boot,dm-spl; }; diff --git a/arch/arm/dts/imx8mm-venice.dts b/arch/arm/dts/imx8mm-venice.dts index 39b030691e5..d0929908ce8 100644 --- a/arch/arm/dts/imx8mm-venice.dts +++ b/arch/arm/dts/imx8mm-venice.dts @@ -23,8 +23,11 @@ &i2c1 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; status = "okay"; gsc: gsc@20 { @@ -89,6 +92,13 @@ >; }; + pinctrl_i2c1_gpio: i2c1grp-gpio-grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3 + >; + }; + pinctrl_i2c2: i2c2grp { fsl,pins = < MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 diff --git a/arch/arm/dts/imx8mn-venice-u-boot.dtsi b/arch/arm/dts/imx8mn-venice-u-boot.dtsi index aea48f2d795..4af6b8b4ed8 100644 --- a/arch/arm/dts/imx8mn-venice-u-boot.dtsi +++ b/arch/arm/dts/imx8mn-venice-u-boot.dtsi @@ -49,6 +49,10 @@ u-boot,dm-spl; }; +&pinctrl_i2c1_gpio { + u-boot,dm-spl; +}; + &gsc { u-boot,dm-spl; }; diff --git a/arch/arm/dts/imx8mn-venice.dts b/arch/arm/dts/imx8mn-venice.dts index eeae225632d..9e31b37f249 100644 --- a/arch/arm/dts/imx8mn-venice.dts +++ b/arch/arm/dts/imx8mn-venice.dts @@ -23,8 +23,11 @@ &i2c1 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; status = "okay"; gsc: gsc@20 { @@ -89,6 +92,13 @@ >; }; + pinctrl_i2c1_gpio: i2c1grp-gpio-grp { + fsl,pins = < + MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3 + MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3 + >; + }; + pinctrl_i2c2: i2c2grp { fsl,pins = < MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 diff --git a/arch/arm/dts/imx8mp-venice-u-boot.dtsi b/arch/arm/dts/imx8mp-venice-u-boot.dtsi index 96b9fa89cf4..f9068ebfbee 100644 --- a/arch/arm/dts/imx8mp-venice-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-venice-u-boot.dtsi @@ -57,6 +57,10 @@ u-boot,dm-spl; }; +&pinctrl_i2c1_gpio { + u-boot,dm-spl; +}; + &gsc { u-boot,dm-spl; }; diff --git a/arch/arm/dts/imx8mp-venice.dts b/arch/arm/dts/imx8mp-venice.dts index 6b1a7f1a89d..77e5ac423db 100644 --- a/arch/arm/dts/imx8mp-venice.dts +++ b/arch/arm/dts/imx8mp-venice.dts @@ -23,8 +23,11 @@ &i2c1 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; status = "okay"; gsc: gsc@20 { @@ -89,6 +92,13 @@ >; }; + pinctrl_i2c1_gpio: i2c1grp-gpio-grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c3 + MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c3 + >; + }; + pinctrl_i2c2: i2c2grp { fsl,pins = < MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3 diff --git a/board/gateworks/venice/spl.c b/board/gateworks/venice/spl.c index 60830766ca9..4eb7bdfcee6 100644 --- a/board/gateworks/venice/spl.c +++ b/board/gateworks/venice/spl.c @@ -16,10 +16,12 @@ #include #include #include +#include #include #include #include #include +#include #include #include #include @@ -215,8 +217,8 @@ static int power_init_board(void) void board_init_f(ulong dummy) { - struct udevice *dev; - int ret; + struct udevice *bus, *dev; + int i, ret; int dram_sz; arch_cpu_init(); @@ -247,19 +249,28 @@ void board_init_f(ulong dummy) * * On a board with a missing/depleted backup battery for GSC, the * board may be ready to probe the GSC before its firmware is - * running. We will wait here indefinately for the GSC EEPROM. + * running. Wait here for 50ms for the GSC firmware to let go of + * the SCL/SDA lines to avoid the i2c driver spamming + * 'Arbitration lost' I2C errors */ -#ifdef CONFIG_IMX8MN - /* - * IMX8MN boots quicker than IMX8MM and exposes issue - * where because GSC I2C state machine isn't running and its - * SCL/SDA are driven low the I2C driver spams 'Arbitration lost' - * I2C errors. - * - * TODO: Put a loop here that somehow waits for I2C CLK/DAT to be high - */ - mdelay(50); -#endif + if (!uclass_get_device_by_seq(UCLASS_I2C, 0, &bus)) { + if (!pinctrl_select_state(bus, "gpio")) { + struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus); + struct gpio_desc *scl_gpio = &i2c_bus->scl_gpio; + struct gpio_desc *sda_gpio = &i2c_bus->sda_gpio; + + dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN); + dm_gpio_set_dir_flags(sda_gpio, GPIOD_IS_IN); + for (i = 0; i < 5; i++) { + if (dm_gpio_get_value(scl_gpio) && + dm_gpio_get_value(sda_gpio)) + break; + mdelay(10); + } + pinctrl_select_state(bus, "default"); + } + } + /* Wait indefiniately until the GSC probes */ while (1) { if (!uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(gsc), &dev)) break; From b1d4037e65a8d90d5823f0cac389f3156f669a29 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sat, 19 Nov 2022 09:11:03 -0600 Subject: [PATCH 81/87] configs: imx8m: Prepare imx8m-beacon boards for HAB support In order to enable HAB, FSL_CAAM, ARCH_MISC_INIT and SPL_CRYPTO should be enabled in Kconfig like other i.MX8M boards. Signed-off-by: Adam Ford --- arch/arm/mach-imx/imx8m/Kconfig | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index c332f849945..5e4836b02fe 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -249,6 +249,9 @@ config TARGET_IMX8MM_BEACON select IMX8MM select SUPPORT_SPL select IMX8M_LPDDR4 + select FSL_CAAM + select ARCH_MISC_INIT + select SPL_CRYPTO if SPL config TARGET_IMX8MN_BEACON bool "imx8mn Beacon Embedded devkit" @@ -256,6 +259,9 @@ config TARGET_IMX8MN_BEACON select IMX8MN select SUPPORT_SPL select IMX8M_LPDDR4 + select FSL_CAAM + select ARCH_MISC_INIT + select SPL_CRYPTO if SPL config TARGET_PHYCORE_IMX8MM bool "PHYTEC PHYCORE i.MX8MM" From 4aae15d383a2684fa77f6c12e308f150215b7066 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sat, 19 Nov 2022 13:30:08 -0600 Subject: [PATCH 82/87] configs: imx8mn_beacon_fspi: Add config for booting from QSPI The imx8mn-beacon SOM has a QSPI part on it connected to the FlexSPI controller. Add a defconfig option which supports booting from the QSPI NOR flash instead of sd/mmc. Signed-off-by: Adam Ford --- configs/imx8mn_beacon_fspi_defconfig | 156 +++++++++++++++++++++++++++ 1 file changed, 156 insertions(+) create mode 100644 configs/imx8mn_beacon_fspi_defconfig diff --git a/configs/imx8mn_beacon_fspi_defconfig b/configs/imx8mn_beacon_fspi_defconfig new file mode 100644 index 00000000000..27b60824f3e --- /dev/null +++ b/configs/imx8mn_beacon_fspi_defconfig @@ -0,0 +1,156 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_TEXT_BASE=0x40200000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xFFFFDE00 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx8mn-beacon-kit" +CONFIG_SPL_TEXT_BASE=0x912000 +CONFIG_TARGET_IMX8MN_BEACON=y +CONFIG_SYS_PROMPT="u-boot=> " +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 +CONFIG_SYS_LOAD_ADDR=0x42000000 +CONFIG_SYS_MEMTEST_START=0x40000000 +CONFIG_SYS_MEMTEST_END=0x44000000 +CONFIG_LTO=y +CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=524288 +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +# CONFIG_USE_SPL_FIT_GENERATOR is not set +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi" +CONFIG_DEFAULT_FDT_FILE="imx8mn-beacon-kit.dtb" +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_MAX_SIZE=0x25000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x950000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x980000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 +CONFIG_SPL_I2C=y +CONFIG_SPL_POWER=y +CONFIG_SPL_WATCHDOG=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2074 +# CONFIG_BOOTM_NETBSD is not set +CONFIG_SYS_BOOTM_LEN=0x800000 +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_ERASEENV=y +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_SPI=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_USE_ETHPRIME=y +CONFIG_ETHPRIME="FEC" +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_CLK_IMX8MN=y +CONFIG_CLK_IMX8MN=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_PMIC=y +# CONFIG_SPL_PMIC_CHILDREN is not set +CONFIG_DM_PMIC_BD71837=y +CONFIG_SPL_DM_PMIC_BD71837=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_BD71837=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RESET=y +CONFIG_DM_SERIAL=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_SYSRESET_WATCHDOG=y +CONFIG_DM_THERMAL=y +CONFIG_USB=y +# CONFIG_SPL_DM_USB is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_SDP_LOADADDR=0x0 +CONFIG_IMX_WATCHDOG=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_FSPI_CONF_HEADER=y +CONFIG_FSPI_CONF_FILE="fspi_header.bin" From 6dac63adca4bfef791426ff9208078ab3e7105eb Mon Sep 17 00:00:00 2001 From: Michael Trimarchi Date: Fri, 9 Dec 2022 15:05:49 +0530 Subject: [PATCH 83/87] engicam: imx6: migrate to DM_SERIAL Add the needed DT overrides and configs to enable UART in SPL. Cc: Fabio Estevam Signed-off-by: Michael Trimarchi Tested-by: Suniel Mahesh Reviewed-by: Fabio Estevam --- arch/arm/dts/imx6qdl-icore-u-boot.dtsi | 16 ++++++++++++++++ arch/arm/dts/imx6ul-isiot-u-boot.dtsi | 16 ++++++++++++++++ board/engicam/common/spl.c | 20 +++----------------- configs/imx6dl_icore_nand_defconfig | 1 + configs/imx6q_icore_nand_defconfig | 1 + configs/imx6qdl_icore_mipi_defconfig | 1 + configs/imx6qdl_icore_mmc_defconfig | 1 + configs/imx6qdl_icore_nand_defconfig | 1 + configs/imx6qdl_icore_rqs_defconfig | 1 + 9 files changed, 41 insertions(+), 17 deletions(-) diff --git a/arch/arm/dts/imx6qdl-icore-u-boot.dtsi b/arch/arm/dts/imx6qdl-icore-u-boot.dtsi index f95d49d00d6..12e46e38f6a 100644 --- a/arch/arm/dts/imx6qdl-icore-u-boot.dtsi +++ b/arch/arm/dts/imx6qdl-icore-u-boot.dtsi @@ -5,6 +5,22 @@ #include "imx6qdl-u-boot.dtsi" +&soc { + u-boot,dm-pre-reloc; +}; + +&aips1 { + u-boot,dm-pre-reloc; +}; + +&pinctrl_uart4 { + u-boot,dm-pre-reloc; +}; + +&uart4 { + u-boot,dm-pre-reloc; +}; + &usdhc1 { u-boot,dm-spl; }; diff --git a/arch/arm/dts/imx6ul-isiot-u-boot.dtsi b/arch/arm/dts/imx6ul-isiot-u-boot.dtsi index aa8e9804bfe..7213e719892 100644 --- a/arch/arm/dts/imx6ul-isiot-u-boot.dtsi +++ b/arch/arm/dts/imx6ul-isiot-u-boot.dtsi @@ -5,6 +5,22 @@ #include "imx6ul-u-boot.dtsi" +&soc { + u-boot,dm-pre-reloc; +}; + +&aips1 { + u-boot,dm-pre-reloc; +}; + +&pinctrl_uart1 { + u-boot,dm-pre-reloc; +}; + +&uart1 { + u-boot,dm-pre-reloc; +}; + &usdhc1 { u-boot,dm-spl; }; diff --git a/board/engicam/common/spl.c b/board/engicam/common/spl.c index 6a0612481a8..f1ccdc33436 100644 --- a/board/engicam/common/spl.c +++ b/board/engicam/common/spl.c @@ -26,20 +26,6 @@ #include #include -#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -static iomux_v3_cfg_t const uart_pads[] = { -#ifdef CONFIG_MX6QDL - IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), - IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), -#elif CONFIG_MX6UL - IOMUX_PADS(PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL)), - IOMUX_PADS(PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL)), -#endif -}; - #ifdef CONFIG_SPL_LOAD_FIT int board_fit_config_name_match(const char *name) { @@ -421,12 +407,12 @@ void board_init_f(ulong dummy) if (!(is_mx6ul())) gpr_init(); - /* iomux */ - SETUP_IOMUX_PADS(uart_pads); - /* setup GP timer */ timer_init(); + /* Enable device tree and early DM support*/ + spl_early_init(); + /* UART clocks enabled and gd valid - init serial console */ preloader_console_init(); diff --git a/configs/imx6dl_icore_nand_defconfig b/configs/imx6dl_icore_nand_defconfig index 759bbf9b34e..f4adda5b6d4 100644 --- a/configs/imx6dl_icore_nand_defconfig +++ b/configs/imx6dl_icore_nand_defconfig @@ -66,6 +66,7 @@ CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y CONFIG_VIDEO=y diff --git a/configs/imx6q_icore_nand_defconfig b/configs/imx6q_icore_nand_defconfig index c7d31d502ba..3b579bac460 100644 --- a/configs/imx6q_icore_nand_defconfig +++ b/configs/imx6q_icore_nand_defconfig @@ -67,6 +67,7 @@ CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y CONFIG_VIDEO=y diff --git a/configs/imx6qdl_icore_mipi_defconfig b/configs/imx6qdl_icore_mipi_defconfig index 90eb153c45f..8dd5e895112 100644 --- a/configs/imx6qdl_icore_mipi_defconfig +++ b/configs/imx6qdl_icore_mipi_defconfig @@ -74,5 +74,6 @@ CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y diff --git a/configs/imx6qdl_icore_mmc_defconfig b/configs/imx6qdl_icore_mmc_defconfig index f5a7e969786..05925d8b933 100644 --- a/configs/imx6qdl_icore_mmc_defconfig +++ b/configs/imx6qdl_icore_mmc_defconfig @@ -90,6 +90,7 @@ CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y CONFIG_VIDEO=y diff --git a/configs/imx6qdl_icore_nand_defconfig b/configs/imx6qdl_icore_nand_defconfig index c7d31d502ba..3b579bac460 100644 --- a/configs/imx6qdl_icore_nand_defconfig +++ b/configs/imx6qdl_icore_nand_defconfig @@ -67,6 +67,7 @@ CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y CONFIG_VIDEO=y diff --git a/configs/imx6qdl_icore_rqs_defconfig b/configs/imx6qdl_icore_rqs_defconfig index ee2c597bcb2..3bab6739d09 100644 --- a/configs/imx6qdl_icore_rqs_defconfig +++ b/configs/imx6qdl_icore_rqs_defconfig @@ -72,4 +72,5 @@ CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y From 7246ec19345a07befaabcde1cbf38ad78d0c1c8d Mon Sep 17 00:00:00 2001 From: Ye Li Date: Tue, 13 Dec 2022 05:08:02 +0100 Subject: [PATCH 84/87] imx8: scu_api: sync sc_rm_is_pad_owned api change SCFW has fixed a overflow issue in sc_rm_is_pad_owned API. This requires u-boot to update API implementation, since it will cause compatible issue. Otherwise all pad checking will have problem and cause pad setting not continue. Due to the compatible issue, the new u-boot only works with new SCFW (API version: 1.21 and later). old scfw + old u-boot: API overflow issue old scfw + new u-boot, or new scfw + old u-boot: API compatible issue new scfw + new u-boot: Working Signed-off-by: Ye Li Reviewed-by : Jason Liu Signed-off-by: Marcel Ziswiler --- arch/arm/include/asm/arch-imx8/sci/rpc.h | 2 +- drivers/misc/imx8/scu_api.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/arch-imx8/sci/rpc.h b/arch/arm/include/asm/arch-imx8/sci/rpc.h index 9f55904f442..39de7f0e3e0 100644 --- a/arch/arm/include/asm/arch-imx8/sci/rpc.h +++ b/arch/arm/include/asm/arch-imx8/sci/rpc.h @@ -11,7 +11,7 @@ /* Defines */ #define SCFW_API_VERSION_MAJOR 1U -#define SCFW_API_VERSION_MINOR 15U +#define SCFW_API_VERSION_MINOR 21U #define SC_RPC_VERSION 1U diff --git a/drivers/misc/imx8/scu_api.c b/drivers/misc/imx8/scu_api.c index 27ecce710fc..8f546e9b3fc 100644 --- a/drivers/misc/imx8/scu_api.c +++ b/drivers/misc/imx8/scu_api.c @@ -788,7 +788,7 @@ sc_bool_t sc_rm_is_pad_owned(sc_ipc_t ipc, sc_pad_t pad) RPC_VER(&msg) = SC_RPC_VERSION; RPC_SVC(&msg) = (u8)SC_RPC_SVC_RM; RPC_FUNC(&msg) = (u8)RM_FUNC_IS_PAD_OWNED; - RPC_U8(&msg, 0U) = (u8)pad; + RPC_U16(&msg, 0U) = (u16)pad; RPC_SIZE(&msg) = 2U; ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size); From a437d14fc8b2d935c9071082cd3e820d5d033251 Mon Sep 17 00:00:00 2001 From: Arnaud Ferraris Date: Thu, 15 Dec 2022 15:51:17 +0100 Subject: [PATCH 85/87] imx8mq_pins: fix configuration for UART4 on ECSPI2 pads When routing UART4 using the ECSPI2 pads, register IOMUXC_UART4_RXD_SELECT_INPUT (offset 0x050C) should be changed only when dealing with RX, as its name suggests. Signed-off-by: Arnaud Ferraris Reviewed-by: Fabio Estevam --- arch/arm/include/asm/arch-imx8m/imx8mq_pins.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-imx8m/imx8mq_pins.h b/arch/arm/include/asm/arch-imx8m/imx8mq_pins.h index c71913f2094..16d418c687e 100644 --- a/arch/arm/include/asm/arch-imx8m/imx8mq_pins.h +++ b/arch/arm/include/asm/arch-imx8m/imx8mq_pins.h @@ -538,7 +538,7 @@ enum { IMX8MQ_PAD_ECSPI2_SCLK__GPIO5_IO10 = IOMUX_PAD(0x046C, 0x0204, 5, 0x0000, 0, 0), IMX8MQ_PAD_ECSPI2_MOSI__ECSPI2_MOSI = IOMUX_PAD(0x0470, 0x0208, 0, 0x0000, 0, 0), - IMX8MQ_PAD_ECSPI2_MOSI__UART4_TX = IOMUX_PAD(0x0470, 0x0208, 1, 0x050C, 1, 0), + IMX8MQ_PAD_ECSPI2_MOSI__UART4_TX = IOMUX_PAD(0x0470, 0x0208, 1, 0x0000, 0, 0), IMX8MQ_PAD_ECSPI2_MOSI__GPIO5_IO11 = IOMUX_PAD(0x0470, 0x0208, 5, 0x0000, 0, 0), IMX8MQ_PAD_ECSPI2_MISO__ECSPI2_MISO = IOMUX_PAD(0x0474, 0x020C, 0, 0x0000, 0, 0), From 945c118409a40bfa18fa65bf7fc0afa04634e6dd Mon Sep 17 00:00:00 2001 From: Manoj Sai Date: Mon, 28 Nov 2022 17:15:31 +0530 Subject: [PATCH 86/87] configs: imx8mp_evk: revert to old ram settings The 'commit 864ac2cf383e ("board: imx8mp: Add Engicam i.Core MX8M Plus EDIMM2.2 Starter Kit")' has changed the imx8mp evk ram settings from 6GB ram to 2GB. This changeset reverts the above change. Signed-off-by: Manoj Sai Reported-by : Peter Bergin Reviewed-by: Peng Fan Reviewed-by: Fabio Estevam --- include/configs/imx8mp_evk.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h index 1fea5b72deb..1759318fdd3 100644 --- a/include/configs/imx8mp_evk.h +++ b/include/configs/imx8mp_evk.h @@ -46,9 +46,11 @@ #define CFG_SYS_INIT_RAM_SIZE 0x80000 -/* Totally 2GB DDR */ +/* Totally 6GB DDR */ #define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 -#define PHYS_SDRAM_SIZE 0x80000000 +#define PHYS_SDRAM_SIZE 0xC0000000 /* 3 GB */ +#define PHYS_SDRAM_2 0x100000000 +#define PHYS_SDRAM_2_SIZE 0xC0000000 /* 3 GB */ #endif From f42c0726fd02e978a524ab35b060382d317ef438 Mon Sep 17 00:00:00 2001 From: Oleksandr Suvorov Date: Mon, 16 Jan 2023 17:21:27 +0200 Subject: [PATCH 87/87] arm: dts: imx8mn-u-boot: use versioned ddr4 firmware NXP tested imx8mn-ddr4 with firmware version 201810 only. Use this version for all imx8mn targets with DRAM DDR4. Fixes: 93c4c0e4dd1 ("arm: dts: imx8mn-u-boot: Create common imx8mn-u-boot.dtsi") Signed-off-by: Oleksandr Suvorov Reviewed-by: Fabio Estevam --- arch/arm/dts/imx8mn-u-boot.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/imx8mn-u-boot.dtsi b/arch/arm/dts/imx8mn-u-boot.dtsi index d55dddbdb6e..98659bb5285 100644 --- a/arch/arm/dts/imx8mn-u-boot.dtsi +++ b/arch/arm/dts/imx8mn-u-boot.dtsi @@ -85,7 +85,7 @@ #ifdef CONFIG_IMX8M_LPDDR4 filename = "lpddr4_pmu_train_1d_imem.bin"; #elif CONFIG_IMX8M_DDR4 - filename = "ddr4_imem_1d.bin"; + filename = "ddr4_imem_1d_201810.bin"; #else filename = "ddr3_imem_1d.bin"; #endif @@ -97,7 +97,7 @@ #ifdef CONFIG_IMX8M_LPDDR4 filename = "lpddr4_pmu_train_1d_dmem.bin"; #elif CONFIG_IMX8M_DDR4 - filename = "ddr4_dmem_1d.bin"; + filename = "ddr4_dmem_1d_201810.bin"; #else filename = "ddr3_dmem_1d.bin"; #endif @@ -110,7 +110,7 @@ #ifdef CONFIG_IMX8M_LPDDR4 filename = "lpddr4_pmu_train_2d_imem.bin"; #else - filename = "ddr4_imem_2d.bin"; + filename = "ddr4_imem_2d_201810.bin"; #endif type = "blob-ext"; align-end = <4>; @@ -120,7 +120,7 @@ #ifdef CONFIG_IMX8M_LPDDR4 filename = "lpddr4_pmu_train_2d_dmem.bin"; #else - filename = "ddr4_dmem_2d.bin"; + filename = "ddr4_dmem_2d_201810.bin"; #endif type = "blob-ext"; align-end = <4>;