mirrors/u-boot
1
0
Fork 0
mirror of https://source.denx.de/u-boot/u-boot.git synced 2026-05-05 04:36:13 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity

board: xilinx: zynqmp: Register alternate FPGA device for zu63dr_SE

Browse Source 
The zu63dr_SE and zu67dr_SE devices share the same silicon ID code
0x046D7093 and cannot be distinguished at runtime. The SOC driver
reports zu67dr_SE for this ID, which causes fpga loadb to reject
zu63dr_SE bitstreams.

Register zu63dr_SE as an alternate FPGA device when zu67dr_SE is
detected. This allows users to load either bitstream by selecting
the appropriate device number:
  - Device 0 (zu67dr_SE): fpga loadb 0 ${loadaddr} ${filesize}
  - Device 1 (zu63dr_SE): fpga loadb 1 ${loadaddr} ${filesize}

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/591134b1c66701fa14a21fecac4f7a772ddba876.1775558062.git.michal.simek@amd.com
This commit is contained in:
Michal Simek 2026-04-07 12:34:24 +02:00
parent 1938e7ee4e
commit 106a7f7d7f
1 changed files with 17 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
board/xilinx/zynqmp/zynqmp.c
View File

@ -183,6 +183,23 @@ int board_init(void)
zynqmppl.name = strdup(name);
fpga_init();
fpga_add(fpga_xilinx, &zynqmppl);
/*
* zu63dr_SE and zu67dr_SE share ID 0x046D7093.
* Register zu63dr_SE as alternate device.
*/
if (!strcmp(name, "zu67dr_SE")) {
xilinx_desc *alt;
alt = calloc(1, sizeof(*alt));
if (!alt) {
log_err("Failed to allocate alt FPGA descriptor\n");
} else {
*alt = zynqmppl;
alt->name = "zu63dr_SE";
fpga_add(fpga_xilinx, alt);
}
}
}
}
#endif