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Merge https://gitlab.denx.de/u-boot/custodians/u-boot-spi

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- rk spi transfer limit fix
- Gigadevice, gd25q128 support
- spi-nor-core warnings
This commit is contained in:
Tom Rini 2019-12-27 16:46:15 -05:00
commit 1058bc5ccc
3 changed files with 19 additions and 2 deletions
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6
drivers/mtd/spi/spi-nor-core.c
View File

@ -546,6 +546,9 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr, dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr,
(long long)instr->len); (long long)instr->len);
if (!instr->len)
return 0;
div_u64_rem(instr->len, mtd->erasesize, &rem); div_u64_rem(instr->len, mtd->erasesize, &rem);
if (rem) if (rem)
return -EINVAL; return -EINVAL;
@ -1226,6 +1229,9 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len); dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
if (!len)
return 0;
for (i = 0; i < len; ) { for (i = 0; i < len; ) {
ssize_t written; ssize_t written;
loff_t addr = to + i; loff_t addr = to + i;

5
drivers/mtd/spi/spi-nor-ids.c
View File

@ -107,6 +107,11 @@ const struct flash_info spi_nor_ids[] = {
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
}, },
{
INFO("gd25q128", 0xc84018, 0, 64 * 1024, 256,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
{ {
INFO("gd25lq128", 0xc86018, 0, 64 * 1024, 256, INFO("gd25lq128", 0xc86018, 0, 64 * 1024, 256,
SECT_4K | SPI_NOR_DUAL_READ | SECT_4K | SPI_NOR_DUAL_READ |

10
drivers/spi/rk_spi.c
View File

@ -27,6 +27,12 @@
/* Change to 1 to output registers at the start of each transaction */ /* Change to 1 to output registers at the start of each transaction */
#define DEBUG_RK_SPI 0 #define DEBUG_RK_SPI 0
/*
* ctrlr1 is 16-bits, so we should support lengths of 0xffff + 1. However,
* the controller seems to hang when given 0x10000, so stick with this for now.
*/
#define ROCKCHIP_SPI_MAX_TRANLEN 0xffff
struct rockchip_spi_params { struct rockchip_spi_params {
/* RXFIFO overruns and TXFIFO underruns stop the master clock */ /* RXFIFO overruns and TXFIFO underruns stop the master clock */
bool master_manages_fifo; bool master_manages_fifo;
@ -367,7 +373,7 @@ static inline int rockchip_spi_16bit_reader(struct udevice *dev,
* represented in CTRLR1. * represented in CTRLR1.
*/ */
if (data && data->master_manages_fifo) if (data && data->master_manages_fifo)
max_chunk_size = 0x10000; max_chunk_size = ROCKCHIP_SPI_MAX_TRANLEN;
// rockchip_spi_configure(dev, mode, size) // rockchip_spi_configure(dev, mode, size)
rkspi_enable_chip(regs, false); rkspi_enable_chip(regs, false);
@ -451,7 +457,7 @@ static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen,
/* This is the original 8bit reader/writer code */ /* This is the original 8bit reader/writer code */
while (len > 0) { while (len > 0) {
int todo = min(len, 0x10000); int todo = min(len, ROCKCHIP_SPI_MAX_TRANLEN);
rkspi_enable_chip(regs, false); rkspi_enable_chip(regs, false);
writel(todo - 1, &regs->ctrlr1); writel(todo - 1, &regs->ctrlr1);