From 864d66431a05a1ab78ac2995c1e98bd460766b35 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Thu, 14 Nov 2019 00:01:22 +0000 Subject: [PATCH 1/3] mtd: spi-nor: ids: Add GigaDevice gd25q128 Add gd25q128 128Mbit chip to spi-nor id table. Tested on Pinebook Pro Signed-off-by: Peter Robinson Acked-by: Vignesh Raghavendra Tested-by: Jagan Teki # roc-rk3399-pc Reviewed-by: Jagan Teki --- drivers/mtd/spi/spi-nor-ids.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index d3b84574ac4..973b6f86c94 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -107,6 +107,11 @@ const struct flash_info spi_nor_ids[] = { SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, + { + INFO("gd25q128", 0xc84018, 0, 64 * 1024, 256, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) + }, { INFO("gd25lq128", 0xc86018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | From cb56caacf8113cef90a3b477f08912260fd6a02e Mon Sep 17 00:00:00 2001 From: Vignesh Raghavendra Date: Sat, 9 Nov 2019 12:04:13 +0530 Subject: [PATCH 2/3] mtd: spi-nor-core: Fix static checker warnings Static checker warns 'ret' variable may be used uninitialized in spi_nor_erase() and spi_nor_write() in case of zero length requests. Fix these warnings by checking for zero length requests and returning early. Reported-by: Dan Murphy Signed-off-by: Vignesh Raghavendra --- drivers/mtd/spi/spi-nor-core.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 5a8c0842556..eb49a6c11c4 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -546,6 +546,9 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr, (long long)instr->len); + if (!instr->len) + return 0; + div_u64_rem(instr->len, mtd->erasesize, &rem); if (rem) return -EINVAL; @@ -1226,6 +1229,9 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len, dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len); + if (!len) + return 0; + for (i = 0; i < len; ) { ssize_t written; loff_t addr = to + i; From dbbdc81c6064b4cb7ffc796b71713a19488a2c4c Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Sat, 21 Dec 2019 13:24:30 +0530 Subject: [PATCH 3/3] spi: rk: Limit transfers to (64K - 1) bytes The Rockchip SPI controller's length register only supports 16-bits, yielding a maximum length of 64KiB (the CTRLR1 register holds "length - 1"). Trying to transfer more than that (e.g., with a large SPI flash read) will cause the driver to hang. Now, it seems that while theoretically we should be able to program CTRLR1 with 0xffff, and get a 64KiB transfer, but that also seems to cause the core to choke, so stick with a maximum of 64K - 1 bytes -- i.e., 0xffff. Note, that the size is further divided into 'minus 1' while writing into CTRLR1. This change fixed two different read issues, 1. sf read failure when with > 0x10000 2. Boot from SPI flash failed during spi_flash_read call in common/spl/spl_spi.c Observed and Tested in - Rockpro64 with Gigadevice flash - ROC-RK3399-PC with Winbond flash Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- drivers/spi/rk_spi.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c index c04535ac445..95eeb8307ad 100644 --- a/drivers/spi/rk_spi.c +++ b/drivers/spi/rk_spi.c @@ -27,6 +27,12 @@ /* Change to 1 to output registers at the start of each transaction */ #define DEBUG_RK_SPI 0 +/* + * ctrlr1 is 16-bits, so we should support lengths of 0xffff + 1. However, + * the controller seems to hang when given 0x10000, so stick with this for now. + */ +#define ROCKCHIP_SPI_MAX_TRANLEN 0xffff + struct rockchip_spi_params { /* RXFIFO overruns and TXFIFO underruns stop the master clock */ bool master_manages_fifo; @@ -367,7 +373,7 @@ static inline int rockchip_spi_16bit_reader(struct udevice *dev, * represented in CTRLR1. */ if (data && data->master_manages_fifo) - max_chunk_size = 0x10000; + max_chunk_size = ROCKCHIP_SPI_MAX_TRANLEN; // rockchip_spi_configure(dev, mode, size) rkspi_enable_chip(regs, false); @@ -451,7 +457,7 @@ static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen, /* This is the original 8bit reader/writer code */ while (len > 0) { - int todo = min(len, 0x10000); + int todo = min(len, ROCKCHIP_SPI_MAX_TRANLEN); rkspi_enable_chip(regs, false); writel(todo - 1, ®s->ctrlr1);