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realtek: dsa: move fib_entries to config structure
The fib_entries attribute is a device specific constant. Therefore move it into the configuration structure. Add a comment why someone used 16K fib_entries for RTL931x instead of the possible 32K. Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de> Link: https://github.com/openwrt/openwrt/pull/22438 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
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@ -1610,7 +1610,6 @@ static int rtl83xx_sw_probe(struct platform_device *pdev)
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case RTL8380_FAMILY_ID:
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priv->ds->ops = &rtldsa_83xx_switch_ops;
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priv->ds->phylink_mac_ops = &rtldsa_83xx_phylink_mac_ops;
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priv->fib_entries = 8192;
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priv->ds->num_lag_ids = 8;
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priv->l2_bucket_size = 4;
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priv->n_mst = 64;
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@ -1618,7 +1617,6 @@ static int rtl83xx_sw_probe(struct platform_device *pdev)
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case RTL8390_FAMILY_ID:
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priv->ds->ops = &rtldsa_83xx_switch_ops;
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priv->ds->phylink_mac_ops = &rtldsa_83xx_phylink_mac_ops;
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priv->fib_entries = 16384;
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priv->ds->num_lag_ids = 16;
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priv->l2_bucket_size = 4;
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priv->n_mst = 256;
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@ -1626,7 +1624,6 @@ static int rtl83xx_sw_probe(struct platform_device *pdev)
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case RTL9300_FAMILY_ID:
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priv->ds->ops = &rtldsa_93xx_switch_ops;
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priv->ds->phylink_mac_ops = &rtldsa_93xx_phylink_mac_ops;
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priv->fib_entries = 16384;
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priv->ds->num_lag_ids = 16;
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sw_w32(0, RTL930X_ST_CTRL);
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priv->l2_bucket_size = 8;
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@ -1635,7 +1632,6 @@ static int rtl83xx_sw_probe(struct platform_device *pdev)
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case RTL9310_FAMILY_ID:
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priv->ds->ops = &rtldsa_93xx_switch_ops;
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priv->ds->phylink_mac_ops = &rtldsa_93xx_phylink_mac_ops;
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priv->fib_entries = 16384;
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priv->ds->num_lag_ids = 16;
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sw_w32(0, RTL931x_ST_CTRL);
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priv->l2_bucket_size = 8;
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@ -324,7 +324,7 @@ static int l2_table_show(struct seq_file *m, void *v)
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mutex_lock(&priv->reg_mutex);
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for (int i = 0; i < priv->fib_entries; i++) {
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for (int i = 0; i < priv->r->fib_entries; i++) {
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bucket = i >> 2;
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index = i & 0x3;
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priv->r->read_l2_entry_using_hash(bucket, index, &e);
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@ -2002,7 +2002,7 @@ static int rtldsa_port_fdb_dump(struct dsa_switch *ds, int port,
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mutex_lock(&priv->reg_mutex);
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for (int i = 0; i < priv->fib_entries; i++) {
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for (int i = 0; i < priv->r->fib_entries; i++) {
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priv->r->read_l2_entry_using_hash(i >> 2, i & 0x3, &e);
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if (!e.valid)
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@ -1808,6 +1808,7 @@ int rtldsa_83xx_lag_setup_algomask(struct rtl838x_switch_priv *priv, int group,
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const struct rtldsa_config rtldsa_838x_cfg = {
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.cpu_port = RTL838X_CPU_PORT,
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.fib_entries = 8192,
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.mask_port_reg_be = rtl838x_mask_port_reg,
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.set_port_reg_be = rtl838x_set_port_reg,
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.get_port_reg_be = rtl838x_get_port_reg,
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@ -1414,6 +1414,7 @@ struct rtldsa_config {
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int n_pie_blocks;
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u8 cpu_port;
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u8 port_ignore;
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u32 fib_entries;
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int trk_ctrl;
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int trk_hash_ctrl;
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void (*vlan_tables_read)(u32 vlan, struct rtl838x_vlan_info *info);
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@ -1517,7 +1518,6 @@ struct rtl838x_switch_priv {
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struct mii_bus *parent_bus;
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const struct rtldsa_config *r;
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u64 irq_mask;
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u32 fib_entries;
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int l2_bucket_size;
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u16 n_mst;
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struct dentry *dbgfs_dir;
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@ -1723,6 +1723,7 @@ int rtldsa_83xx_lag_setup_algomask(struct rtl838x_switch_priv *priv, int group,
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const struct rtldsa_config rtldsa_839x_cfg = {
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.cpu_port = RTL839X_CPU_PORT,
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.fib_entries = 16384,
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.mask_port_reg_be = rtl839x_mask_port_reg_be,
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.set_port_reg_be = rtl839x_set_port_reg_be,
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.get_port_reg_be = rtl839x_get_port_reg_be,
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@ -2794,6 +2794,7 @@ static void rtldsa_930x_qos_init(struct rtl838x_switch_priv *priv)
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const struct rtldsa_config rtldsa_930x_cfg = {
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.cpu_port = RTL930X_CPU_PORT,
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.fib_entries = 16384,
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.mask_port_reg_be = rtl838x_mask_port_reg,
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.set_port_reg_be = rtl838x_set_port_reg,
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.get_port_reg_be = rtl838x_get_port_reg,
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@ -1935,6 +1935,7 @@ static void rtldsa_931x_qos_init(struct rtl838x_switch_priv *priv)
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const struct rtldsa_config rtldsa_931x_cfg = {
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.cpu_port = RTL931X_CPU_PORT,
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.fib_entries = 16384, /* TODO: has 32K but code cannot handle that */
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.mask_port_reg_be = rtl839x_mask_port_reg_be,
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.set_port_reg_be = rtl839x_set_port_reg_be,
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.get_port_reg_be = rtl839x_get_port_reg_be,
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