mirrors/openwrt
1
0
Fork 0
mirror of https://git.openwrt.org/openwrt/openwrt.git synced 2026-05-05 09:56:12 +02:00
Code Issues Projects Releases Wiki Activity

realtek: dts: rtl93xx: use PHY_* macros for Zyxel XGS1X10/1250

Browse Source 
Replace the verbose ethernet-phy node definitions with the PHY_C45 and
PHY_C45_PAIR_ORDER macros to drop boilerplate.

Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/23118
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This commit is contained in:
Jonas Jelonek 2026-04-16 08:26:54 +00:00 committed by Hauke Mehrtens
parent 0136c48bd5
commit 322f8e6771
5 changed files with 34 additions and 98 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
target/linux/realtek/dts/rtl9302_zyxel_xgs1010-12-a1.dts
View File

@ -104,17 +104,9 @@
};
&mdio_bus1 {
phy24: ethernet-phy@8 {
reg = <8>;
compatible = "ethernet-phy-ieee802.3-c45";
enet-phy-pair-order = <1>;
};
PHY_C45_PAIR_ORDER(24, 8, 1)
};
&mdio_bus2 {
phy25: ethernet-phy@9 {
reg = <9>;
compatible = "ethernet-phy-ieee802.3-c45";
enet-phy-pair-order = <1>;
};
PHY_C45_PAIR_ORDER(25, 9, 1)
};

12
target/linux/realtek/dts/rtl9302_zyxel_xgs1210-12-a1.dts
View File

@ -9,17 +9,9 @@
};
&mdio_bus1 {
phy24: ethernet-phy@8 {
reg = <8>;
compatible = "ethernet-phy-ieee802.3-c45";
enet-phy-pair-order = <1>;
};
PHY_C45_PAIR_ORDER(24, 8, 1)
};
&mdio_bus2 {
phy25: ethernet-phy@9 {
reg = <9>;
compatible = "ethernet-phy-ieee802.3-c45";
enet-phy-pair-order = <1>;
};
PHY_C45_PAIR_ORDER(25, 9, 1)
};

10
target/linux/realtek/dts/rtl9302_zyxel_xgs1210-12-b1.dts
View File

@ -9,15 +9,9 @@
};
&mdio_bus1 {
phy24: ethernet-phy@1 {
reg = <1>;
compatible = "ethernet-phy-ieee802.3-c45";
};
PHY_C45(24, 1)
};
&mdio_bus2 {
phy25: ethernet-phy@2 {
reg = <2>;
compatible = "ethernet-phy-ieee802.3-c45";
};
PHY_C45(25, 2)
};

49
target/linux/realtek/dts/rtl9302_zyxel_xgs1250-12-common.dtsi
View File

@ -232,41 +232,20 @@
};
&mdio_bus0 {
/* External RTL8218D or RTL8218E PHY */
phy0: ethernet-phy@0 {
reg = <0>;
compatible = "ethernet-phy-ieee802.3-c22";
// Disabled because we do not know how to bring up again
// reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
};
phy1: ethernet-phy@1 {
reg = <1>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy2: ethernet-phy@2 {
reg = <2>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy3: ethernet-phy@3 {
reg = <3>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy4: ethernet-phy@4 {
reg = <4>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy5: ethernet-phy@5 {
reg = <5>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy6: ethernet-phy@6 {
reg = <6>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy7: ethernet-phy@7 {
reg = <7>;
compatible = "ethernet-phy-ieee802.3-c22";
};
/*
* External RTL8218D or RTL8218E PHY
*
* reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
* disabled because we do not know how to bring up again
*/
PHY_C22(0, 0)
PHY_C22(1, 1)
PHY_C22(2, 2)
PHY_C22(3, 3)
PHY_C22(4, 4)
PHY_C22(5, 5)
PHY_C22(6, 6)
PHY_C22(7, 7)
};
&switch0 {

49
target/linux/realtek/dts/rtl9302_zyxel_xgs1x10-12-common.dtsi
View File

@ -86,41 +86,20 @@
};
&mdio_bus0 {
/* External RTL8218D PHY */
phy0: ethernet-phy@0 {
reg = <0>;
compatible = "ethernet-phy-ieee802.3-c22";
// Disabled because we do not know how to bring up again
// reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
};
phy1: ethernet-phy@1 {
reg = <1>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy2: ethernet-phy@2 {
reg = <2>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy3: ethernet-phy@3 {
reg = <3>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy4: ethernet-phy@4 {
reg = <4>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy5: ethernet-phy@5 {
reg = <5>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy6: ethernet-phy@6 {
reg = <6>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy7: ethernet-phy@7 {
reg = <7>;
compatible = "ethernet-phy-ieee802.3-c22";
};
/*
* External RTL8218D PHY
*
* reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
* disabled because we do not know how to bring up again
*/
PHY_C22(0, 0)
PHY_C22(1, 1)
PHY_C22(2, 2)
PHY_C22(3, 3)
PHY_C22(4, 4)
PHY_C22(5, 5)
PHY_C22(6, 6)
PHY_C22(7, 7)
};
&switch0 {