From 322f8e6771031e53d426ffe942b14dd375cde7a6 Mon Sep 17 00:00:00 2001 From: Jonas Jelonek Date: Thu, 16 Apr 2026 08:26:54 +0000 Subject: [PATCH] realtek: dts: rtl93xx: use PHY_* macros for Zyxel XGS1X10/1250 Replace the verbose ethernet-phy node definitions with the PHY_C45 and PHY_C45_PAIR_ORDER macros to drop boilerplate. Signed-off-by: Jonas Jelonek Link: https://github.com/openwrt/openwrt/pull/23118 Signed-off-by: Hauke Mehrtens --- .../dts/rtl9302_zyxel_xgs1010-12-a1.dts | 12 +---- .../dts/rtl9302_zyxel_xgs1210-12-a1.dts | 12 +---- .../dts/rtl9302_zyxel_xgs1210-12-b1.dts | 10 +--- .../dts/rtl9302_zyxel_xgs1250-12-common.dtsi | 49 ++++++------------- .../dts/rtl9302_zyxel_xgs1x10-12-common.dtsi | 49 ++++++------------- 5 files changed, 34 insertions(+), 98 deletions(-) diff --git a/target/linux/realtek/dts/rtl9302_zyxel_xgs1010-12-a1.dts b/target/linux/realtek/dts/rtl9302_zyxel_xgs1010-12-a1.dts index acd2195e0b..7a5d2f4b3d 100644 --- a/target/linux/realtek/dts/rtl9302_zyxel_xgs1010-12-a1.dts +++ b/target/linux/realtek/dts/rtl9302_zyxel_xgs1010-12-a1.dts @@ -104,17 +104,9 @@ }; &mdio_bus1 { - phy24: ethernet-phy@8 { - reg = <8>; - compatible = "ethernet-phy-ieee802.3-c45"; - enet-phy-pair-order = <1>; - }; + PHY_C45_PAIR_ORDER(24, 8, 1) }; &mdio_bus2 { - phy25: ethernet-phy@9 { - reg = <9>; - compatible = "ethernet-phy-ieee802.3-c45"; - enet-phy-pair-order = <1>; - }; + PHY_C45_PAIR_ORDER(25, 9, 1) }; diff --git a/target/linux/realtek/dts/rtl9302_zyxel_xgs1210-12-a1.dts b/target/linux/realtek/dts/rtl9302_zyxel_xgs1210-12-a1.dts index e2b4c8d057..e0fd7b23f0 100644 --- a/target/linux/realtek/dts/rtl9302_zyxel_xgs1210-12-a1.dts +++ b/target/linux/realtek/dts/rtl9302_zyxel_xgs1210-12-a1.dts @@ -9,17 +9,9 @@ }; &mdio_bus1 { - phy24: ethernet-phy@8 { - reg = <8>; - compatible = "ethernet-phy-ieee802.3-c45"; - enet-phy-pair-order = <1>; - }; + PHY_C45_PAIR_ORDER(24, 8, 1) }; &mdio_bus2 { - phy25: ethernet-phy@9 { - reg = <9>; - compatible = "ethernet-phy-ieee802.3-c45"; - enet-phy-pair-order = <1>; - }; + PHY_C45_PAIR_ORDER(25, 9, 1) }; diff --git a/target/linux/realtek/dts/rtl9302_zyxel_xgs1210-12-b1.dts b/target/linux/realtek/dts/rtl9302_zyxel_xgs1210-12-b1.dts index ebbf4c8cd1..33e97fe44e 100644 --- a/target/linux/realtek/dts/rtl9302_zyxel_xgs1210-12-b1.dts +++ b/target/linux/realtek/dts/rtl9302_zyxel_xgs1210-12-b1.dts @@ -9,15 +9,9 @@ }; &mdio_bus1 { - phy24: ethernet-phy@1 { - reg = <1>; - compatible = "ethernet-phy-ieee802.3-c45"; - }; + PHY_C45(24, 1) }; &mdio_bus2 { - phy25: ethernet-phy@2 { - reg = <2>; - compatible = "ethernet-phy-ieee802.3-c45"; - }; + PHY_C45(25, 2) }; diff --git a/target/linux/realtek/dts/rtl9302_zyxel_xgs1250-12-common.dtsi b/target/linux/realtek/dts/rtl9302_zyxel_xgs1250-12-common.dtsi index e1feaff9f4..8a38ac345c 100644 --- a/target/linux/realtek/dts/rtl9302_zyxel_xgs1250-12-common.dtsi +++ b/target/linux/realtek/dts/rtl9302_zyxel_xgs1250-12-common.dtsi @@ -232,41 +232,20 @@ }; &mdio_bus0 { - /* External RTL8218D or RTL8218E PHY */ - phy0: ethernet-phy@0 { - reg = <0>; - compatible = "ethernet-phy-ieee802.3-c22"; - // Disabled because we do not know how to bring up again - // reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; - }; - phy1: ethernet-phy@1 { - reg = <1>; - compatible = "ethernet-phy-ieee802.3-c22"; - }; - phy2: ethernet-phy@2 { - reg = <2>; - compatible = "ethernet-phy-ieee802.3-c22"; - }; - phy3: ethernet-phy@3 { - reg = <3>; - compatible = "ethernet-phy-ieee802.3-c22"; - }; - phy4: ethernet-phy@4 { - reg = <4>; - compatible = "ethernet-phy-ieee802.3-c22"; - }; - phy5: ethernet-phy@5 { - reg = <5>; - compatible = "ethernet-phy-ieee802.3-c22"; - }; - phy6: ethernet-phy@6 { - reg = <6>; - compatible = "ethernet-phy-ieee802.3-c22"; - }; - phy7: ethernet-phy@7 { - reg = <7>; - compatible = "ethernet-phy-ieee802.3-c22"; - }; + /* + * External RTL8218D or RTL8218E PHY + * + * reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; + * disabled because we do not know how to bring up again + */ + PHY_C22(0, 0) + PHY_C22(1, 1) + PHY_C22(2, 2) + PHY_C22(3, 3) + PHY_C22(4, 4) + PHY_C22(5, 5) + PHY_C22(6, 6) + PHY_C22(7, 7) }; &switch0 { diff --git a/target/linux/realtek/dts/rtl9302_zyxel_xgs1x10-12-common.dtsi b/target/linux/realtek/dts/rtl9302_zyxel_xgs1x10-12-common.dtsi index efe600ad55..844f7c8313 100644 --- a/target/linux/realtek/dts/rtl9302_zyxel_xgs1x10-12-common.dtsi +++ b/target/linux/realtek/dts/rtl9302_zyxel_xgs1x10-12-common.dtsi @@ -86,41 +86,20 @@ }; &mdio_bus0 { - /* External RTL8218D PHY */ - phy0: ethernet-phy@0 { - reg = <0>; - compatible = "ethernet-phy-ieee802.3-c22"; - // Disabled because we do not know how to bring up again - // reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; - }; - phy1: ethernet-phy@1 { - reg = <1>; - compatible = "ethernet-phy-ieee802.3-c22"; - }; - phy2: ethernet-phy@2 { - reg = <2>; - compatible = "ethernet-phy-ieee802.3-c22"; - }; - phy3: ethernet-phy@3 { - reg = <3>; - compatible = "ethernet-phy-ieee802.3-c22"; - }; - phy4: ethernet-phy@4 { - reg = <4>; - compatible = "ethernet-phy-ieee802.3-c22"; - }; - phy5: ethernet-phy@5 { - reg = <5>; - compatible = "ethernet-phy-ieee802.3-c22"; - }; - phy6: ethernet-phy@6 { - reg = <6>; - compatible = "ethernet-phy-ieee802.3-c22"; - }; - phy7: ethernet-phy@7 { - reg = <7>; - compatible = "ethernet-phy-ieee802.3-c22"; - }; + /* + * External RTL8218D PHY + * + * reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; + * disabled because we do not know how to bring up again + */ + PHY_C22(0, 0) + PHY_C22(1, 1) + PHY_C22(2, 2) + PHY_C22(3, 3) + PHY_C22(4, 4) + PHY_C22(5, 5) + PHY_C22(6, 6) + PHY_C22(7, 7) }; &switch0 {