mirror of
https://github.com/armbian/build.git
synced 2025-08-16 16:16:57 +02:00
1297 lines
30 KiB
Diff
1297 lines
30 KiB
Diff
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
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index 01d178a2..bfba239c 100644
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--- a/arch/arm/boot/dts/Makefile
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+++ b/arch/arm/boot/dts/Makefile
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@@ -990,4 +990,7 @@ dtstree := $(srctree)/$(src)
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dtb-$(CONFIG_OF_ALL_DTBS) := $(patsubst $(dtstree)/%.dts,%.dtb, $(wildcard $(dtstree)/*.dts))
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always := $(dtb-y)
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+subdir-y := overlay
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clean-files := *.dtb
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+
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+dts-dirs += overlay
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diff --git a/arch/arm/boot/dts/overlay/Makefile b/arch/arm/boot/dts/overlay/Makefile
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new file mode 100644
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index 00000000..945091fd
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--- /dev/null
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+++ b/arch/arm/boot/dts/overlay/Makefile
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@@ -0,0 +1,33 @@
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+ifeq ($(CONFIG_OF_CONFIGFS),y)
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+
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+dtbo-$(CONFIG_MACH_SUN7I) += \
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+ sun7i-a20-analog-codec.dtbo \
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+ sun7i-a20-can.dtbo \
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+ sun7i-a20-i2c1.dtbo \
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+ sun7i-a20-i2c2.dtbo \
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+ sun7i-a20-i2c3.dtbo \
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+ sun7i-a20-i2c3-edt-ft5x06.dtbo \
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+ sun7i-a20-i2c4.dtbo \
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+ sun7i-a20-nand.dtbo \
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+ sun7i-a20-spdif-out.dtbo \
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+ sun7i-a20-spi-jedec-nor.dtbo \
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+ sun7i-a20-spi-mcp2515.dtbo \
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+ sun7i-a20-spi-spidev.dtbo \
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+ sun7i-a20-uart2.dtbo \
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+ sun7i-a20-uart3.dtbo \
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+ sun7i-a20-uart4.dtbo \
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+ sun7i-a20-uart5.dtbo \
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+ sun7i-a20-uart6.dtbo \
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+ sun7i-a20-uart7.dtbo \
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+ sun7i-a20-w1-gpio.dtbo
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+
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+scr-$(CONFIG_MACH_SUN7I) += sun7i-a20-fixup.scr
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+
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+dtbotxt-$(CONFIG_MACH_SUN7I) += README.sun7i-a20-overlays
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+
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+targets += $(dtbo-y) $(scr-y) $(dtbotxt-y)
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+
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+endif
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+
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+always := $(dtbo-y) $(scr-y) $(dtbotxt-y)
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+clean-files := *.dtbo *.scr
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diff --git a/arch/arm/boot/dts/overlay/README.sun7i-a20-overlays b/arch/arm/boot/dts/overlay/README.sun7i-a20-overlays
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new file mode 100644
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index 00000000..176345f1
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--- /dev/null
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+++ b/arch/arm/boot/dts/overlay/README.sun7i-a20-overlays
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@@ -0,0 +1,247 @@
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+This document describes overlays provided in the kernel packages
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+For generic Armbian overlays documentation please see
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+https://docs.armbian.com/Hardware_Allwinner_overlays/
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+
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+### Platform:
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+
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+sun7i-a20 (Allwinner A20)
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+
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+### Platform details:
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+
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+Supported pin banks: PB, PC, PD, PE, PG, PH, PI
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+
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+SPI controller 0 have 2 exposed hardware CS,
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+other SPI controllers have only one hardware CS
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+Reference: A20 Datasheet sections 6.3.5.1, 1.19.2
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+
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+I2C bus 0 is used for the AXP209 PMIC
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+
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+### Provided overlays:
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+
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+- analog-codec
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+- can
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+- i2c1
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+- i2c2
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+- i2c3
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+- i2c4
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+- nand
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+- spdif-out
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+- spi-jedec-nor
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+- spi-mcp2515
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+- spi-spidev
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+- uart1
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+- uart2
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+- uart3
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+- uart4
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+- uart5
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+- uart6
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+- uart7
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+- w1-gpio
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+
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+### Overlay details:
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+
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+### analog-codec
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+
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+Activates SoC analog codec driver that provides Line Out and Mic In
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+functionality
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+
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+## can
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+
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+Activates SoC CAN controller
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+
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+CAN pins (TX, RX): PH20, PH21
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+
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+### i2c1
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+
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+Activates TWI/I2C bus 1
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+
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+I2C1 pins (SCL, SDA): PB18, PB19
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+
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+### i2c2
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+
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+Activates TWI/I2C bus 2
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+
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+I2C2 pins (SCL, SDA): PB20, PB21
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+
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+### i2c3
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+
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+Activates TWI/I2C bus 3
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+
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+I2C3 pins (SCL, SDA): PI0, PI1
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+
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+### i2c4
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+
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+Activates TWI/I2C bus 4
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+
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+I2C4 pins (SCL, SDA): PI2, PI3
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+
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+### nand
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+
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+Activates NAND controller
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+
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+This overlay should not be used until mainline MLC NAND support
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+allows using NAND storage reliably
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+
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+### spdif-out
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+
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+Activates SPDIF/Toslink audio output
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+
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+SPDIF pin: PB13
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+
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+### spi-jedec-nor
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+
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+Activates MTD support for JEDEC compatible SPI NOR flash chips on SPI bus
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+supported by the kernel SPI NOR driver
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+
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+SPI 0 pins (MOSI, MISO, SCK, CS0, CS1): PI12, PI13, PI11, PI10, PI14
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+SPI 1 pins (MOSI, MISO, SCK, CS0): PI18, PI19, PI17, PI16
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+SPI 2 pins a (MOSI, MISO, SCK, CS0): PC21, PC22, PC20, PC19
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+SPI 2 pins b (MOSI, MISO, SCK, CS0): PB16, PB17, PB15, PB14
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+
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+Parameters:
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+
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+param_spinor_spi_bus (int)
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+ SPI bus to activate SPI NOR flash support on
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+ Required
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+ Supported values: 0, 1, 2
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+
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+param_spi2_bus_pins (char)
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+ SPI bus 2 pinmux variant
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+ Determines what pins SPI bus 2 is exposed on if SPI 2 is used by any overlay
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+ Default: a
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+ Supported values: a, b
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+
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+param_spinor_max_freq (int)
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+ Maximum SPI frequency
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+ Default: 1000000
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+ Range: 3000 - 100000000
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+
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+### spi-mcp2515
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+
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+Activates mcp2515 SPI CAN controller connected to SPI bus
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+
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+SPI 0 pins (MOSI, MISO, SCK, CS0, CS1): PI12, PI13, PI11, PI10, PI14
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+SPI 1 pins (MOSI, MISO, SCK, CS0): PI18, PI19, PI17, PI16
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+SPI 2 pins a (MOSI, MISO, SCK, CS0): PC21, PC22, PC20, PC19
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+SPI 2 pins b (MOSI, MISO, SCK, CS0): PB16, PB17, PB15, PB14
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+
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+Parameters:
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+
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+param_mcp2515_spi_bus (int)
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+ SPI bus to activate mcp2515 support on
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+ Required
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+ Supported values: 0, 1, 2
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+
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+param_spi2_bus_pins (char)
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+ SPI bus 2 pinmux variant
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+ Determines what pins SPI bus 2 is exposed on if SPI 2 is used by any overlay
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+ Default: a
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+ Supported values: a, b
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+
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+param_mcp2515_clk_freq (int)
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+ Onboard oscillator clock frequency
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+ Default: 8000000
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+ Typical values: 8000000, 16000000
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+
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+param_mcp2515_int_pin (pin)
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+ Interrupt pin
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+ Default: PH15
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+ Selected pin should support interrupts (EINT)
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+
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+### spi-spidev
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+
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+Activates SPIdev device node (/dev/spidev0.0) for userspace SPI access
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+
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+SPI 0 pins (MOSI, MISO, SCK, CS0, CS1): PI12, PI13, PI11, PI10, PI14
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+SPI 1 pins (MOSI, MISO, SCK, CS0): PI18, PI19, PI17, PI16
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+SPI 2 pins a (MOSI, MISO, SCK, CS0): PC21, PC22, PC20, PC19
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+SPI 2 pins b (MOSI, MISO, SCK, CS0): PB16, PB17, PB15, PB14
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+
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+Parameters:
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+
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+param_spi2_bus_pins (char)
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+ SPI bus 2 pinmux variant
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+ Determines what pins SPI bus 2 is exposed on if SPI 2 is used by any overlay
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+ Default: a
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+ Supported values: a, b
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+
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+param_spidev_max_freq (int)
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+ Maximum SPIdev frequency
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+ Default: 1000000
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+ Range: 3000 - 100000000
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+
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+### uart2
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+
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+Activates serial port 2 (/dev/ttyS2)
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+
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+UART 2 pins (TX, RX, RTS, CTS): PI18, PI19, PI16, PI17
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+
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+Parameters:
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+
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+param_uart2_rtscts (bool)
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+ Enable RTS and CTS pins
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+ Default: 0
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+ Set to 1 to enable CTS and RTS pins
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+
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+### uart3
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+
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+Activates serial port 3 (/dev/ttyS3)
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+
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+UART 3 pins (TX, RX, RTS, CTS): PG6, PG7, PG8, PG9
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+
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+Parameters:
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+
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+param_uart3_rtscts (bool)
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+ Enable RTS and CTS pins
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+ Default: 0
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+ Set to 1 to enable CTS and RTS pins
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+
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+### uart4
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+
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+Activates serial port 4 (/dev/ttyS4)
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+
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+UART 4 pins a (TX, RX): PG10, PG11
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+UART 4 pins b (TX, RX): PH4, PH5
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+
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+Parameters:
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+
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+param_uart4_pins (char)
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+ Determines what pins UART 4 is exposed on
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+ Default: a
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+ Supported values: a, b
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+
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+### uart 5
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+
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+Activates serial port 5 (/dev/ttyS5)
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+
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+UART 5 pins (TX, RX): PH6, PH7
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+
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+### uart 6
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+
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+Activates serial port 6 (/dev/ttyS6)
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+
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+UART 6 pins (TX, RX): PI12, PI13
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+
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+### uart 7
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+
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+Activates serial port 7 (/dev/ttyS7)
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+
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+UART 7 pins (TX, RX): PI20, PI21
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+
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+### w1-gpio
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+
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+Activates 1-Wire GPIO master
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+Requires external pull-up resistor on data pin
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+
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+Parameters:
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+
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+param_w1_pin (pin)
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+ Data pin for 1-Wire master
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+ Default: PI15
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+
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+param_w1_pin_int_pullup (bool)
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+ Enable internal pull-up for the data pin
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+ This option should not be used with multiple sensors or long wires -
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+ please use external pull-up resistor instead
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+ Default: 0
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+ Set to 1 to enable the pull-up
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diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-analog-codec.dts b/arch/arm/boot/dts/overlay/sun7i-a20-analog-codec.dts
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new file mode 100644
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index 00000000..74bb13d0
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--- /dev/null
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+++ b/arch/arm/boot/dts/overlay/sun7i-a20-analog-codec.dts
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@@ -0,0 +1,12 @@
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+/dts-v1/ /plugin/;
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+
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+/ {
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+ compatible = "allwinner,sun7i-a20";
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+
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+ fragment@0 {
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+ target = <&codec>;
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+ __overlay__ {
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+ status = "okay";
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+ };
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+ };
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+};
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diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-can.dts b/arch/arm/boot/dts/overlay/sun7i-a20-can.dts
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new file mode 100644
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index 00000000..17601ec1
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--- /dev/null
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+++ b/arch/arm/boot/dts/overlay/sun7i-a20-can.dts
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@@ -0,0 +1,32 @@
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+/dts-v1/ /plugin/;
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+
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+#include <dt-bindings/interrupt-controller/arm-gic.h>
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+
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+/ {
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+ compatible = "allwinner,sun7i-a20";
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+
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+ fragment@0 {
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+ target = <&pio>;
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+ __overlay__ {
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+ can_pins: can_pins {
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+ pins = "PH20", "PH21";
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+ function = "can";
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+ };
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+ };
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+ };
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+
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+ fragment@1 {
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+ target-path = "/soc@01c00000";
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+ __overlay__ {
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+ can0: can@01c2bc00 {
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+ compatible = "allwinner,sun4i-a10-can";
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+ reg = <0x01c2bc00 0x400>;
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+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&apb1_gates 4>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&can_pins>;
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+ status = "okay";
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+ };
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+ };
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+ };
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+};
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diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-fixup.scr-cmd b/arch/arm/boot/dts/overlay/sun7i-a20-fixup.scr-cmd
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new file mode 100644
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index 00000000..9ff225a4
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--- /dev/null
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+++ b/arch/arm/boot/dts/overlay/sun7i-a20-fixup.scr-cmd
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@@ -0,0 +1,154 @@
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+# overlays fixup script
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+# implements (or rather substitutes) overlay arguments functionality
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+# using u-boot scripting, environment variables and "fdt" command
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+
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+# setexpr test_var ${tmp_bank} - A
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+# works only for hex numbers (A-F)
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+
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+setenv decompose_pin 'setexpr tmp_bank sub "P(B|C|D|E|G|H|I)\\d+" "\\1";
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+setexpr tmp_pin sub "P\\S(\\d+)" "\\1";
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+test "${tmp_bank}" = "B" && setenv tmp_bank 1;
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+test "${tmp_bank}" = "C" && setenv tmp_bank 2;
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+test "${tmp_bank}" = "D" && setenv tmp_bank 3;
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+test "${tmp_bank}" = "E" && setenv tmp_bank 4;
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+test "${tmp_bank}" = "G" && setenv tmp_bank 6;
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+test "${tmp_bank}" = "H" && setenv tmp_bank 7;
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+test "${tmp_bank}" = "I" && setenv tmp_bank 8'
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+
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+if test "${param_spinor_spi_bus}" = "0"; then
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+ fdt set /soc@01c00000/spi@01c05000 status "okay"
|
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+ fdt set /soc@01c00000/spi@01c05000/spiflash status "okay"
|
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+fi
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+
|
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+if test "${param_spinor_spi_bus}" = "1"; then
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+ fdt set /soc@01c00000/spi@01c06000 status "okay"
|
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+ fdt set /soc@01c00000/spi@01c06000/spiflash status "okay"
|
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+fi
|
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+
|
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+if test "${param_spinor_spi_bus}" = "2"; then
|
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+ fdt set /soc@01c00000/spi@01c17000 status "okay"
|
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+ fdt set /soc@01c00000/spi@01c17000/spiflash status "okay"
|
|
+fi
|
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+
|
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+if test "${param_mcp2515_spi_bus}" = "0"; then
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+ fdt set /soc@01c00000/spi@01c05000 status "okay"
|
|
+ fdt set /soc@01c00000/spi@01c05000/mcp2515 status "okay"
|
|
+fi
|
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+
|
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+if test "${param_mcp2515_spi_bus}" = "1"; then
|
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+ fdt set /soc@01c00000/spi@01c06000 status "okay"
|
|
+ fdt set /soc@01c00000/spi@01c06000/mcp2515 status "okay"
|
|
+fi
|
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+
|
|
+if test "${param_mcp2515_spi_bus}" = "2"; then
|
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+ fdt set /soc@01c00000/spi@01c17000 status "okay"
|
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+ fdt set /soc@01c00000/spi@01c17000/mcp2515 status "okay"
|
|
+fi
|
|
+
|
|
+if test "${param_spidev_spi_bus}" = "0"; then
|
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+ fdt set /soc@01c00000/spi@01c05000 status "okay"
|
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+ fdt set /soc@01c00000/spi@01c05000/spidev status "okay"
|
|
+fi
|
|
+
|
|
+if test "${param_spidev_spi_bus}" = "1"; then
|
|
+ fdt set /soc@01c00000/spi@01c06000 status "okay"
|
|
+ fdt set /soc@01c00000/spi@01c06000/spidev status "okay"
|
|
+fi
|
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+
|
|
+if test "${param_spidev_spi_bus}" = "2"; then
|
|
+ fdt set /soc@01c00000/spi@01c17000 status "okay"
|
|
+ fdt set /soc@01c00000/spi@01c17000/spidev status "okay"
|
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+fi
|
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+
|
|
+if test -n "${param_mcp2515_clk_freq}"; then
|
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+ fdt set /clocks/can0_osc_fixed clock-frequency "<${param_mcp2515_clk_freq}>"
|
|
+fi
|
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+
|
|
+if test "${param_spi2_bus_pins}" = "b"; then
|
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+ fdt get value tmp_phandle1 /soc@01c00000/pinctrl@01c20800/spi2@1 phandle
|
|
+ fdt get value tmp_phandle2 /soc@01c00000/pinctrl@01c20800/spi2_cs0@1 phandle
|
|
+ fdt set /soc@01c00000/spi@01c17000 pinctrl-0 "<${tmp_phandle1}>"
|
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+ fdt set /soc@01c00000/spi@01c17000 pinctrl-1 "<${tmp_phandle2}>"
|
|
+ env delete tmp_phandle1 tmp_phandle2
|
|
+fi
|
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+
|
|
+if test -n "${param_mcp2515_int_pin}"; then
|
|
+ setenv tmp_bank "${param_mcp2515_int_pin}"
|
|
+ setenv tmp_pin "${param_mcp2515_int_pin}"
|
|
+ run decompose_pin
|
|
+ fdt set /soc@01c00000/pinctrl@01c20800/can0_pin_irq pins "${param_mcp2515_int_pin}"
|
|
+ if test "${param_mcp2515_spi_bus}" = "0"; then
|
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+ setenv tmp_spi_path "spi@01c05000"
|
|
+ fi
|
|
+ if test "${param_mcp2515_spi_bus}" = "1"; then
|
|
+ setenv tmp_spi_path "spi@01c06000"
|
|
+ fi
|
|
+ if test "${param_mcp2515_spi_bus}" = "2"; then
|
|
+ setenv tmp_spi_path "spi@01c17000"
|
|
+ fi
|
|
+ fdt set /soc@01c00000/${tmp_spi_path}/mcp2515 interrupts "<${tmp_bank} ${tmp_pin} 0x2>"
|
|
+ env delete tmp_pin tmp_bank tmp_spi_path
|
|
+fi
|
|
+
|
|
+if test -n "${param_spidev_max_freq}"; then
|
|
+ if test "${param_spidev_spi_bus}" = "0"; then
|
|
+ setenv tmp_spi_path "spi@01c05000"
|
|
+ fi
|
|
+ if test "${param_spidev_spi_bus}" = "1"; then
|
|
+ setenv tmp_spi_path "spi@01c06000"
|
|
+ fi
|
|
+ if test "${param_spidev_spi_bus}" = "2"; then
|
|
+ setenv tmp_spi_path "spi@01c17000"
|
|
+ fi
|
|
+ fdt set /soc@01c00000/${tmp_spi_path}/spidev spi-max-frequency "<${param_spidev_max_freq}>"
|
|
+ env delete tmp_spi_path
|
|
+fi
|
|
+
|
|
+if test -n "${param_spinor_max_freq}"; then
|
|
+ if test "${param_spinor_spi_bus}" = "0"; then
|
|
+ setenv tmp_spi_path "spi@01c05000"
|
|
+ fi
|
|
+ if test "${param_spinor_spi_bus}" = "1"; then
|
|
+ setenv tmp_spi_path "spi@01c06000"
|
|
+ fi
|
|
+ if test "${param_spinor_spi_bus}" = "2"; then
|
|
+ setenv tmp_spi_path "spi@01c17000"
|
|
+ fi
|
|
+ fdt set /soc@01c00000/${tmp_spi_path}/spiflash spi-max-frequency "<${param_spinor_max_freq}>"
|
|
+ env delete tmp_spi_path
|
|
+fi
|
|
+
|
|
+if test -n "${param_w1_pin}"; then
|
|
+ setenv tmp_bank "${param_w1_pin}"
|
|
+ setenv tmp_pin "${param_w1_pin}"
|
|
+ run decompose_pin
|
|
+ fdt set /soc@01c00000/pinctrl@01c20800/w1_pins pins "${param_w1_pin}"
|
|
+ fdt get value tmp_phandle /soc@01c00000/pinctrl@01c20800 phandle
|
|
+ fdt set /onewire@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>"
|
|
+ env delete tmp_pin tmp_bank tmp_phandle
|
|
+fi
|
|
+
|
|
+if test "${param_w1_pin_int_pullup}" = "1"; then
|
|
+ fdt set /soc@01c00000/pinctrl@01c20800/w1_pins bias-pull-up
|
|
+fi
|
|
+
|
|
+if test "${param_uart2_rtscts}" = "1"; then
|
|
+ fdt get value tmp_phandle /soc@01c00000/pinctrl@01c20800/uart2@0 phandle
|
|
+ fdt set /soc@01c00000/serial@01c28800 pinctrl-0 "<${tmp_phandle}>"
|
|
+ env delete tmp_phandle
|
|
+fi
|
|
+
|
|
+if test "${param_uart3_rtscts}" = "1"; then
|
|
+ fdt get value tmp_phandle1 /soc@01c00000/pinctrl@01c20800/uart3 phandle
|
|
+ fdt get value tmp_phandle2 /soc@01c00000/pinctrl@01c20800/uart3_rts_cts phandle
|
|
+ fdt set /soc@01c00000/serial@01c28c00 pinctrl-names "default" "default"
|
|
+ fdt set /soc@01c00000/serial@01c28c00 pinctrl-0 "<${tmp_phandle1}>"
|
|
+ fdt set /soc@01c00000/serial@01c28c00 pinctrl-1 "<${tmp_phandle2}>"
|
|
+ env delete tmp_phandle1 tmp_phandle2
|
|
+fi
|
|
+
|
|
+if test "${param_uart4_pins}" = "b"; then
|
|
+ fdt get value tmp_phandle /soc@01c00000/pinctrl@01c20800/uart4@1 phandle
|
|
+ fdt set /soc@01c00000/serial@01c29000 pinctrl-0 "<${tmp_phandle}>"
|
|
+ env delete tmp_phandle
|
|
+fi
|
|
diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-i2c1.dts b/arch/arm/boot/dts/overlay/sun7i-a20-i2c1.dts
|
|
new file mode 100644
|
|
index 00000000..4c551399
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun7i-a20-i2c1.dts
|
|
@@ -0,0 +1,21 @@
|
|
+/dts-v1/ /plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun7i-a20";
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ i2c1 = "/soc@01c00000/i2c@01c2b000";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&i2c1>;
|
|
+ __overlay__ {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&i2c1_pins_a>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-i2c2.dts b/arch/arm/boot/dts/overlay/sun7i-a20-i2c2.dts
|
|
new file mode 100644
|
|
index 00000000..db4478fb
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun7i-a20-i2c2.dts
|
|
@@ -0,0 +1,21 @@
|
|
+/dts-v1/ /plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun7i-a20";
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ i2c2 = "/soc@01c00000/i2c@01c2b400";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&i2c2>;
|
|
+ __overlay__ {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&i2c2_pins_a>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-i2c3-edt-ft5x06.dts b/arch/arm/boot/dts/overlay/sun7i-a20-i2c3-edt-ft5x06.dts
|
|
new file mode 100644
|
|
index 00000000..e3f13e7b
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun7i-a20-i2c3-edt-ft5x06.dts
|
|
@@ -0,0 +1,41 @@
|
|
+/dts-v1/ /plugin/;
|
|
+
|
|
+#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
+#include <dt-bindings/gpio/gpio.h>
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun7i-a20";
|
|
+
|
|
+ fragment@0 {
|
|
+ target = <&pio>;
|
|
+ __overlay__ {
|
|
+ edt_ft5x06_pins: edt_ft5x06_pins {
|
|
+ pins = "PH7", "PH9";
|
|
+ function = "gpio_out";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&i2c3>;
|
|
+ __overlay__ {
|
|
+ status = "okay";
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&i2c3_pins_a>;
|
|
+ edt: edt-ft5x06@38 {
|
|
+ compatible = "edt,edt-ft5x06";
|
|
+ reg = <0x38>;
|
|
+ interrupt-parent = <&pio>;
|
|
+ interrupts = <7 9 IRQ_TYPE_EDGE_FALLING>;
|
|
+ wake-gpios = <7 7 GPIO_ACTIVE_LOW>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&edt_ft5x06_pins>;
|
|
+ touchscreen-size-x = <1024>;
|
|
+ touchscreen-size-y = <600>;
|
|
+ touchscreen-inverted-x;
|
|
+ touchscreen-swapped-x-y;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-i2c3.dts b/arch/arm/boot/dts/overlay/sun7i-a20-i2c3.dts
|
|
new file mode 100644
|
|
index 00000000..a04e0264
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun7i-a20-i2c3.dts
|
|
@@ -0,0 +1,21 @@
|
|
+/dts-v1/ /plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun7i-a20";
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ i2c3 = "/soc@01c00000/i2c@01c2b800";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&i2c3>;
|
|
+ __overlay__ {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&i2c3_pins_a>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-i2c4.dts b/arch/arm/boot/dts/overlay/sun7i-a20-i2c4.dts
|
|
new file mode 100644
|
|
index 00000000..5f8c313a
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun7i-a20-i2c4.dts
|
|
@@ -0,0 +1,31 @@
|
|
+/dts-v1/ /plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun7i-a20";
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ i2c4 = "/soc@01c00000/i2c@01c2c000";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&pio>;
|
|
+ __overlay__ {
|
|
+ i2c4_pins_a: i2c4@0 {
|
|
+ pins = "PI2", "PI3";
|
|
+ function = "i2c4";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@2 {
|
|
+ target = <&i2c4>;
|
|
+ __overlay__ {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&i2c4_pins_a>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-nand.dts b/arch/arm/boot/dts/overlay/sun7i-a20-nand.dts
|
|
new file mode 100644
|
|
index 00000000..dec3a70c
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun7i-a20-nand.dts
|
|
@@ -0,0 +1,102 @@
|
|
+/dts-v1/ /plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun7i-a20";
|
|
+
|
|
+ fragment@0 {
|
|
+ target = <&pio>;
|
|
+ __overlay__ {
|
|
+ nand_pins_a: nand_pins@0 {
|
|
+ pins = "PC0", "PC1", "PC2",
|
|
+ "PC5", "PC8", "PC9", "PC10",
|
|
+ "PC11", "PC12", "PC13", "PC14",
|
|
+ "PC15", "PC16";
|
|
+ function = "nand0";
|
|
+ };
|
|
+
|
|
+ nand_cs0_pins_a: nand_cs@0 {
|
|
+ pins = "PC4";
|
|
+ function = "nand0";
|
|
+ };
|
|
+
|
|
+ nand_cs1_pins_a: nand_cs@1 {
|
|
+ pins = "PC3";
|
|
+ function = "nand0";
|
|
+ };
|
|
+
|
|
+ nand_cs2_pins_a: nand_cs@2 {
|
|
+ pins = "PC17";
|
|
+ function = "nand0";
|
|
+ };
|
|
+
|
|
+ nand_cs3_pins_a: nand_cs@3 {
|
|
+ pins = "PC18";
|
|
+ function = "nand0";
|
|
+ };
|
|
+
|
|
+ nand_rb0_pins_a: nand_rb@0 {
|
|
+ pins = "PC6";
|
|
+ function = "nand0";
|
|
+ };
|
|
+
|
|
+ nand_rb1_pins_a: nand_rb@1 {
|
|
+ pins = "PC7";
|
|
+ function = "nand0";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&nfc>;
|
|
+ __overlay__ {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&nand_pins_a>, <&nand_cs0_pins_a>, <&nand_rb0_pins_a>;
|
|
+ status = "okay";
|
|
+
|
|
+ nand@0 {
|
|
+ reg = <0>;
|
|
+ allwinner,rb = <0>;
|
|
+ nand-ecc-mode = "hw";
|
|
+ nand-on-flash-bbt;
|
|
+
|
|
+ partitions {
|
|
+ compatible = "fixed-partitions";
|
|
+ #address-cells = <2>;
|
|
+ #size-cells = <2>;
|
|
+
|
|
+ partition@0 {
|
|
+ label = "SPL";
|
|
+ reg = <0x0 0x0 0x0 0x400000>;
|
|
+ };
|
|
+
|
|
+ partition@400000 {
|
|
+ label = "SPL.backup";
|
|
+ reg = <0x0 0x400000 0x0 0x400000>;
|
|
+ };
|
|
+
|
|
+ partition@800000 {
|
|
+ label = "U-Boot";
|
|
+ reg = <0x0 0x800000 0x0 0x400000>;
|
|
+ };
|
|
+
|
|
+ partition@c00000 {
|
|
+ label = "U-Boot.backup";
|
|
+ reg = <0x0 0xc00000 0x0 0x400000>;
|
|
+ };
|
|
+
|
|
+ partition@1000000 {
|
|
+ label = "env";
|
|
+ reg = <0x0 0x1000000 0x0 0x400000>;
|
|
+ };
|
|
+
|
|
+ partition@1400000 {
|
|
+ label = "rootfs";
|
|
+ reg = <0x0 0xa00000 0x01 0xff000000>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-spdif-out.dts b/arch/arm/boot/dts/overlay/sun7i-a20-spdif-out.dts
|
|
new file mode 100644
|
|
index 00000000..0463f43c
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun7i-a20-spdif-out.dts
|
|
@@ -0,0 +1,37 @@
|
|
+/dts-v1/ /plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun7i-a20";
|
|
+
|
|
+ fragment@0 {
|
|
+ target = <&spdif>;
|
|
+ __overlay__ {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&spdif_tx_pins_a>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target-path = "/";
|
|
+ __overlay__ {
|
|
+ sound {
|
|
+ compatible = "simple-audio-card";
|
|
+ simple-audio-card,name = "On-board SPDIF";
|
|
+
|
|
+ simple-audio-card,cpu {
|
|
+ sound-dai = <&spdif>;
|
|
+ };
|
|
+
|
|
+ simple-audio-card,codec {
|
|
+ sound-dai = <&spdif_out>;
|
|
+ };
|
|
+
|
|
+ spdif_out: spdif-out {
|
|
+ #sound-dai-cells = <0>;
|
|
+ compatible = "linux,spdif-dit";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-spi-jedec-nor.dts b/arch/arm/boot/dts/overlay/sun7i-a20-spi-jedec-nor.dts
|
|
new file mode 100644
|
|
index 00000000..e8d2e17d
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun7i-a20-spi-jedec-nor.dts
|
|
@@ -0,0 +1,67 @@
|
|
+/dts-v1/ /plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun7i-a20";
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ spi0 = "/soc/spi@01c05000";
|
|
+ spi1 = "/soc/spi@01c06000";
|
|
+ spi2 = "/soc/spi@01c17000";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&spi0>;
|
|
+ __overlay__ {
|
|
+ status = "okay";
|
|
+ pinctrl-names = "default", "default";
|
|
+ pinctrl-0 = <&spi0_pins_a>;
|
|
+ pinctrl-1 = <&spi0_cs0_pins_a>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ spiflash {
|
|
+ compatible = "jedec,spi-nor";
|
|
+ reg = <0>;
|
|
+ spi-max-frequency = <1000000>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@2 {
|
|
+ target = <&spi1>;
|
|
+ __overlay__ {
|
|
+ status = "disabled";
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&spi1_pins_a>, <&spi1_cs0_pins_a>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ spiflash {
|
|
+ compatible = "jedec,spi-nor";
|
|
+ status = "disabled";
|
|
+ reg = <0>;
|
|
+ spi-max-frequency = <1000000>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@3 {
|
|
+ target = <&spi2>;
|
|
+ __overlay__ {
|
|
+ status = "disabled";
|
|
+ pinctrl-names = "default", "default";
|
|
+ pinctrl-0 = <&spi2_pins_a>;
|
|
+ pinctrl-1 = <&spi2_cs0_pins_a>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ spiflash {
|
|
+ compatible = "jedec,spi-nor";
|
|
+ status = "disabled";
|
|
+ reg = <0>;
|
|
+ spi-max-frequency = <1000000>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-spi-mcp2515.dts b/arch/arm/boot/dts/overlay/sun7i-a20-spi-mcp2515.dts
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new file mode 100644
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index 00000000..5ebcf66d
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--- /dev/null
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+++ b/arch/arm/boot/dts/overlay/sun7i-a20-spi-mcp2515.dts
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@@ -0,0 +1,105 @@
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+/dts-v1/ /plugin/;
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+
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+#include <dt-bindings/interrupt-controller/irq.h>
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+
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+/ {
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+ compatible = "allwinner,sun7i-a20";
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+
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+ fragment@0 {
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+ target-path = "/aliases";
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+ __overlay__ {
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+ spi1 = "/soc/spi@01c06000";
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+ spi2 = "/soc/spi@01c17000";
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+ spi3 = "/soc/spi@01c1f000";
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+ };
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+ };
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+
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+ fragment@1 {
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+ target-path = "/clocks";
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+ __overlay__ {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ can0_osc_fixed: can0_osc_fixed {
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+ compatible = "fixed-clock";
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+ #clock-cells = <0>;
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+ clock-frequency = <8000000>;
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+ };
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+ };
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+ };
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+
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+ fragment@2 {
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+ target = <&pio>;
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+ __overlay__ {
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+ can0_pin_irq: can0_pin_irq {
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+ pins = "PH15";
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+ function = "irq";
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+ bias-pull-up;
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+ };
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+ };
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+ };
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+
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+ fragment@3 {
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+ target = <&spi0>;
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+ __overlay__ {
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+ pinctrl-names = "default", "default";
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+ pinctrl-0 = <&spi0_pins_a>;
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+ pinctrl-1 = <&spi0_cs0_pins_a>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ mcp2515 {
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+ reg = <0>;
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+ compatible = "microchip,mcp2515";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&can0_pin_irq>;
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+ spi-max-frequency = <10000000>;
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+ interrupt-parent = <&pio>;
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+ interrupts = <7 15 IRQ_TYPE_EDGE_FALLING>; /* PH15 */
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+ clocks = <&can0_osc_fixed>;
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+ status = "disabled";
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+ };
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+ };
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+ };
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+
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+ fragment@4 {
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+ target = <&spi1>;
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+ __overlay__ {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&spi1_pins_a>, <&spi1_cs0_pins_a>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ mcp2515 {
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+ reg = <0>;
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+ compatible = "microchip,mcp2515";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&can0_pin_irq>;
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+ spi-max-frequency = <10000000>;
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+ interrupt-parent = <&pio>;
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+ interrupts = <7 15 IRQ_TYPE_EDGE_FALLING>; /* PH15 */
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+ clocks = <&can0_osc_fixed>;
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+ status = "disabled";
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+ };
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+ };
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+ };
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+
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+ fragment@5 {
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+ target = <&spi2>;
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+ __overlay__ {
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+ pinctrl-names = "default", "default";
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+ pinctrl-0 = <&spi2_pins_a>;
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+ pinctrl-1 = <&spi2_cs0_pins_a>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ mcp2515 {
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+ reg = <0>;
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+ compatible = "microchip,mcp2515";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&can0_pin_irq>;
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+ spi-max-frequency = <10000000>;
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+ interrupt-parent = <&pio>;
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+ interrupts = <7 15 IRQ_TYPE_EDGE_FALLING>; /* PH15 */
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+ clocks = <&can0_osc_fixed>;
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+ status = "disabled";
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+ };
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+ };
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+ };
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+};
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diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-spi-spidev.dts b/arch/arm/boot/dts/overlay/sun7i-a20-spi-spidev.dts
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new file mode 100644
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index 00000000..4d448661
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--- /dev/null
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+++ b/arch/arm/boot/dts/overlay/sun7i-a20-spi-spidev.dts
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@@ -0,0 +1,64 @@
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+/dts-v1/ /plugin/;
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+
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+/ {
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+ compatible = "allwinner,sun7i-a20";
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+
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+ fragment@0 {
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+ target-path = "/aliases";
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+ __overlay__ {
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+ spi0 = "/soc/spi@01c05000";
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+ spi1 = "/soc/spi@01c06000";
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+ spi2 = "/soc/spi@01c17000";
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+ };
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+ };
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+
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+ fragment@1 {
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+ target = <&spi0>;
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+ __overlay__ {
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+ pinctrl-names = "default", "default";
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+ pinctrl-0 = <&spi0_pins_a>;
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+ pinctrl-1 = <&spi0_cs0_pins_a>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ spidev {
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+ compatible = "spidev";
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+ status = "disabled";
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+ reg = <0>;
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+ spi-max-frequency = <1000000>;
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+ };
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+ };
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+ };
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+
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+ fragment@2 {
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+ target = <&spi1>;
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+ __overlay__ {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&spi1_pins_a>, <&spi1_cs0_pins_a>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ spidev {
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+ compatible = "spidev";
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+ status = "disabled";
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+ reg = <0>;
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+ spi-max-frequency = <1000000>;
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+ };
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+ };
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+ };
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+
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+ fragment@3 {
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+ target = <&spi2>;
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+ __overlay__ {
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+ pinctrl-names = "default", "default";
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+ pinctrl-0 = <&spi2_pins_a>;
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+ pinctrl-1 = <&spi2_cs0_pins_a>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ spidev {
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+ compatible = "spidev";
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+ status = "disabled";
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+ reg = <0>;
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+ spi-max-frequency = <1000000>;
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+ };
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+ };
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+ };
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+};
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diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-uart2.dts b/arch/arm/boot/dts/overlay/sun7i-a20-uart2.dts
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new file mode 100644
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index 00000000..e4992768
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--- /dev/null
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+++ b/arch/arm/boot/dts/overlay/sun7i-a20-uart2.dts
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@@ -0,0 +1,21 @@
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+/dts-v1/ /plugin/;
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+
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+/ {
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+ compatible = "allwinner,sun7i-a20";
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+
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+ fragment@0 {
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+ target-path = "/aliases";
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+ __overlay__ {
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+ uart2 = "/soc@01c00000/serial@01c28800";
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+ };
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+ };
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+
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+ fragment@1 {
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+ target = <&uart2>;
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+ __overlay__ {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&uart2_pins>;
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+ status = "okay";
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+ };
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+ };
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+};
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diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-uart3.dts b/arch/arm/boot/dts/overlay/sun7i-a20-uart3.dts
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new file mode 100644
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index 00000000..4f932c54
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--- /dev/null
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+++ b/arch/arm/boot/dts/overlay/sun7i-a20-uart3.dts
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@@ -0,0 +1,31 @@
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+/dts-v1/ /plugin/;
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+
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+/ {
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+ compatible = "allwinner,sun7i-a20";
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+
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+ fragment@0 {
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+ target-path = "/aliases";
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+ __overlay__ {
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+ uart3 = "/soc@01c00000/serial@01c28c00";
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+ };
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+ };
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+
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+ fragment@1 {
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+ target = <&pio>;
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+ __overlay__ {
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+ uart3_pins_a_2: uart3@2 {
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+ pins = "PG6", "PG7";
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+ function = "uart3";
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+ };
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+ };
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+ };
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+
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+ fragment@2 {
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+ target = <&uart3>;
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+ __overlay__ {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&uart3_pins_a_2>;
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+ status = "okay";
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+ };
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+ };
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+};
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diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-uart4.dts b/arch/arm/boot/dts/overlay/sun7i-a20-uart4.dts
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new file mode 100644
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index 00000000..e6fd8a3b
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--- /dev/null
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+++ b/arch/arm/boot/dts/overlay/sun7i-a20-uart4.dts
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@@ -0,0 +1,21 @@
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+/dts-v1/ /plugin/;
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+
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+/ {
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+ compatible = "allwinner,sun7i-a20";
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+
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+ fragment@0 {
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+ target-path = "/aliases";
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+ __overlay__ {
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+ serial4 = "/soc@01c00000/serial@01c29000";
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+ };
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+ };
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+
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+ fragment@1 {
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+ target = <&uart4>;
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+ __overlay__ {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&uart4_pins_a>;
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+ status = "okay";
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+ };
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+ };
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+};
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diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-uart5.dts b/arch/arm/boot/dts/overlay/sun7i-a20-uart5.dts
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new file mode 100644
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index 00000000..65675241
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--- /dev/null
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+++ b/arch/arm/boot/dts/overlay/sun7i-a20-uart5.dts
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@@ -0,0 +1,21 @@
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+/dts-v1/ /plugin/;
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+
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+/ {
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+ compatible = "allwinner,sun7i-a20";
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+
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+ fragment@0 {
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+ target-path = "/aliases";
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+ __overlay__ {
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+ serial5 = "/soc@01c00000/serial@01c29400";
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+ };
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+ };
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+
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+ fragment@1 {
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+ target = <&uart5>;
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+ __overlay__ {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&uart5_pins_a>;
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+ status = "okay";
|
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+ };
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+ };
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+};
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diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-uart6.dts b/arch/arm/boot/dts/overlay/sun7i-a20-uart6.dts
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new file mode 100644
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index 00000000..3642fd35
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--- /dev/null
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+++ b/arch/arm/boot/dts/overlay/sun7i-a20-uart6.dts
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@@ -0,0 +1,21 @@
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+/dts-v1/ /plugin/;
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+
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+/ {
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+ compatible = "allwinner,sun7i-a20";
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+
|
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+ fragment@0 {
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+ target-path = "/aliases";
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+ __overlay__ {
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+ serial6 = "/soc@01c00000/serial@01c29800";
|
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+ };
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+ };
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+
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+ fragment@1 {
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+ target = <&uart6>;
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+ __overlay__ {
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+ pinctrl-names = "default";
|
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+ pinctrl-0 = <&uart6_pins_a>;
|
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+ status = "okay";
|
|
+ };
|
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+ };
|
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+};
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diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-uart7.dts b/arch/arm/boot/dts/overlay/sun7i-a20-uart7.dts
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new file mode 100644
|
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index 00000000..bd0d1b48
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--- /dev/null
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+++ b/arch/arm/boot/dts/overlay/sun7i-a20-uart7.dts
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@@ -0,0 +1,21 @@
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+/dts-v1/ /plugin/;
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+
|
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+/ {
|
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+ compatible = "allwinner,sun7i-a20";
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ serial7 = "/soc@01c00000/serial@01c29c00";
|
|
+ };
|
|
+ };
|
|
+
|
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+ fragment@1 {
|
|
+ target = <&uart7>;
|
|
+ __overlay__ {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&uart7_pins_a>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
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|
diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-w1-gpio.dts b/arch/arm/boot/dts/overlay/sun7i-a20-w1-gpio.dts
|
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new file mode 100644
|
|
index 00000000..771af0de
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun7i-a20-w1-gpio.dts
|
|
@@ -0,0 +1,28 @@
|
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+/dts-v1/ /plugin/;
|
|
+
|
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+/ {
|
|
+ compatible = "allwinner,sun7i-a20";
|
|
+
|
|
+ fragment@0 {
|
|
+ target = <&pio>;
|
|
+ __overlay__ {
|
|
+ w1_pins: w1_pins {
|
|
+ pins = "PI15";
|
|
+ function = "gpio_in";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target-path = "/";
|
|
+ __overlay__ {
|
|
+ w1: onewire@0 {
|
|
+ compatible = "w1-gpio";
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&w1_pins>;
|
|
+ gpios = <&pio 8 15 0>; /* PI15 */
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+};
|