diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 01d178a2..bfba239c 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -990,4 +990,7 @@ dtstree		:= $(srctree)/$(src)
 dtb-$(CONFIG_OF_ALL_DTBS) := $(patsubst $(dtstree)/%.dts,%.dtb, $(wildcard $(dtstree)/*.dts))
 
 always		:= $(dtb-y)
+subdir-y	:= overlay
 clean-files	:= *.dtb
+
+dts-dirs += overlay
diff --git a/arch/arm/boot/dts/overlay/Makefile b/arch/arm/boot/dts/overlay/Makefile
new file mode 100644
index 00000000..945091fd
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/Makefile
@@ -0,0 +1,33 @@
+ifeq ($(CONFIG_OF_CONFIGFS),y)
+
+dtbo-$(CONFIG_MACH_SUN7I) += \
+	sun7i-a20-analog-codec.dtbo \
+	sun7i-a20-can.dtbo \
+	sun7i-a20-i2c1.dtbo \
+	sun7i-a20-i2c2.dtbo \
+	sun7i-a20-i2c3.dtbo \
+	sun7i-a20-i2c3-edt-ft5x06.dtbo \
+	sun7i-a20-i2c4.dtbo \
+	sun7i-a20-nand.dtbo \
+	sun7i-a20-spdif-out.dtbo \
+	sun7i-a20-spi-jedec-nor.dtbo \
+	sun7i-a20-spi-mcp2515.dtbo \
+	sun7i-a20-spi-spidev.dtbo \
+	sun7i-a20-uart2.dtbo \
+	sun7i-a20-uart3.dtbo \
+	sun7i-a20-uart4.dtbo \
+	sun7i-a20-uart5.dtbo \
+	sun7i-a20-uart6.dtbo \
+	sun7i-a20-uart7.dtbo \
+	sun7i-a20-w1-gpio.dtbo
+
+scr-$(CONFIG_MACH_SUN7I) += sun7i-a20-fixup.scr
+
+dtbotxt-$(CONFIG_MACH_SUN7I) += README.sun7i-a20-overlays
+
+targets += $(dtbo-y) $(scr-y) $(dtbotxt-y)
+
+endif
+
+always		:= $(dtbo-y) $(scr-y) $(dtbotxt-y)
+clean-files	:= *.dtbo *.scr
diff --git a/arch/arm/boot/dts/overlay/README.sun7i-a20-overlays b/arch/arm/boot/dts/overlay/README.sun7i-a20-overlays
new file mode 100644
index 00000000..176345f1
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/README.sun7i-a20-overlays
@@ -0,0 +1,247 @@
+This document describes overlays provided in the kernel packages
+For generic Armbian overlays documentation please see
+https://docs.armbian.com/Hardware_Allwinner_overlays/
+
+### Platform:
+
+sun7i-a20 (Allwinner A20)
+
+### Platform details:
+
+Supported pin banks: PB, PC, PD, PE, PG, PH, PI
+
+SPI controller 0 have 2 exposed hardware CS,
+other SPI controllers have only one hardware CS
+Reference: A20 Datasheet sections 6.3.5.1, 1.19.2
+
+I2C bus 0 is used for the AXP209 PMIC
+
+### Provided overlays:
+
+- analog-codec
+- can
+- i2c1
+- i2c2
+- i2c3
+- i2c4
+- nand
+- spdif-out
+- spi-jedec-nor
+- spi-mcp2515
+- spi-spidev
+- uart1
+- uart2
+- uart3
+- uart4
+- uart5
+- uart6
+- uart7
+- w1-gpio
+
+### Overlay details:
+
+### analog-codec
+
+Activates SoC analog codec driver that provides Line Out and Mic In
+functionality
+
+## can
+
+Activates SoC CAN controller
+
+CAN pins (TX, RX): PH20, PH21
+
+### i2c1
+
+Activates TWI/I2C bus 1
+
+I2C1 pins (SCL, SDA): PB18, PB19
+
+### i2c2
+
+Activates TWI/I2C bus 2
+
+I2C2 pins (SCL, SDA): PB20, PB21
+
+### i2c3
+
+Activates TWI/I2C bus 3
+
+I2C3 pins (SCL, SDA): PI0, PI1
+
+### i2c4
+
+Activates TWI/I2C bus 4
+
+I2C4 pins (SCL, SDA): PI2, PI3
+
+### nand
+
+Activates NAND controller
+
+This overlay should not be used until mainline MLC NAND support
+allows using NAND storage reliably
+
+### spdif-out
+
+Activates SPDIF/Toslink audio output
+
+SPDIF pin: PB13
+
+### spi-jedec-nor
+
+Activates MTD support for JEDEC compatible SPI NOR flash chips on SPI bus
+supported by the kernel SPI NOR driver
+
+SPI 0 pins (MOSI, MISO, SCK, CS0, CS1): PI12, PI13, PI11, PI10, PI14
+SPI 1 pins (MOSI, MISO, SCK, CS0): PI18, PI19, PI17, PI16
+SPI 2 pins a (MOSI, MISO, SCK, CS0): PC21, PC22, PC20, PC19
+SPI 2 pins b (MOSI, MISO, SCK, CS0): PB16, PB17, PB15, PB14
+
+Parameters:
+
+param_spinor_spi_bus (int)
+	SPI bus to activate SPI NOR flash support on
+	Required
+	Supported values: 0, 1, 2
+
+param_spi2_bus_pins (char)
+	SPI bus 2 pinmux variant
+	Determines what pins SPI bus 2 is exposed on if SPI 2 is used by any overlay
+	Default: a
+	Supported values: a, b
+
+param_spinor_max_freq (int)
+	Maximum SPI frequency
+	Default: 1000000
+	Range: 3000 - 100000000
+
+### spi-mcp2515
+
+Activates mcp2515 SPI CAN controller connected to SPI bus
+
+SPI 0 pins (MOSI, MISO, SCK, CS0, CS1): PI12, PI13, PI11, PI10, PI14
+SPI 1 pins (MOSI, MISO, SCK, CS0): PI18, PI19, PI17, PI16
+SPI 2 pins a (MOSI, MISO, SCK, CS0): PC21, PC22, PC20, PC19
+SPI 2 pins b (MOSI, MISO, SCK, CS0): PB16, PB17, PB15, PB14
+
+Parameters:
+
+param_mcp2515_spi_bus (int)
+	SPI bus to activate mcp2515 support on
+	Required
+	Supported values: 0, 1, 2
+
+param_spi2_bus_pins (char)
+	SPI bus 2 pinmux variant
+	Determines what pins SPI bus 2 is exposed on if SPI 2 is used by any overlay
+	Default: a
+	Supported values: a, b
+
+param_mcp2515_clk_freq (int)
+	Onboard oscillator clock frequency
+	Default: 8000000
+	Typical values: 8000000, 16000000
+
+param_mcp2515_int_pin (pin)
+	Interrupt pin
+	Default: PH15
+	Selected pin should support interrupts (EINT)
+
+### spi-spidev
+
+Activates SPIdev device node (/dev/spidev0.0) for userspace SPI access
+
+SPI 0 pins (MOSI, MISO, SCK, CS0, CS1): PI12, PI13, PI11, PI10, PI14
+SPI 1 pins (MOSI, MISO, SCK, CS0): PI18, PI19, PI17, PI16
+SPI 2 pins a (MOSI, MISO, SCK, CS0): PC21, PC22, PC20, PC19
+SPI 2 pins b (MOSI, MISO, SCK, CS0): PB16, PB17, PB15, PB14
+
+Parameters:
+
+param_spi2_bus_pins (char)
+	SPI bus 2 pinmux variant
+	Determines what pins SPI bus 2 is exposed on if SPI 2 is used by any overlay
+	Default: a
+	Supported values: a, b
+
+param_spidev_max_freq (int)
+	Maximum SPIdev frequency
+	Default: 1000000
+	Range: 3000 - 100000000
+
+### uart2
+
+Activates serial port 2 (/dev/ttyS2)
+
+UART 2 pins (TX, RX, RTS, CTS): PI18, PI19, PI16, PI17
+
+Parameters:
+
+param_uart2_rtscts (bool)
+	Enable RTS and CTS pins
+	Default: 0
+	Set to 1 to enable CTS and RTS pins
+
+### uart3
+
+Activates serial port 3 (/dev/ttyS3)
+
+UART 3 pins (TX, RX, RTS, CTS): PG6, PG7, PG8, PG9
+
+Parameters:
+
+param_uart3_rtscts (bool)
+	Enable RTS and CTS pins
+	Default: 0
+	Set to 1 to enable CTS and RTS pins
+
+### uart4
+
+Activates serial port 4 (/dev/ttyS4)
+
+UART 4 pins a (TX, RX): PG10, PG11
+UART 4 pins b (TX, RX): PH4, PH5
+
+Parameters:
+
+param_uart4_pins (char)
+	Determines what pins UART 4 is exposed on
+	Default: a
+	Supported values: a, b
+
+### uart 5
+
+Activates serial port 5 (/dev/ttyS5)
+
+UART 5 pins (TX, RX): PH6, PH7
+
+### uart 6
+
+Activates serial port 6 (/dev/ttyS6)
+
+UART 6 pins (TX, RX): PI12, PI13
+
+### uart 7
+
+Activates serial port 7 (/dev/ttyS7)
+
+UART 7 pins (TX, RX): PI20, PI21
+
+### w1-gpio
+
+Activates 1-Wire GPIO master
+Requires external pull-up resistor on data pin
+
+Parameters:
+
+param_w1_pin (pin)
+	Data pin for 1-Wire master
+	Default: PI15
+
+param_w1_pin_int_pullup (bool)
+	Enable internal pull-up for the data pin
+	This option should not be used with multiple sensors or long wires -
+		please use external pull-up resistor instead
+	Default: 0
+	Set to 1 to enable the pull-up
diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-analog-codec.dts b/arch/arm/boot/dts/overlay/sun7i-a20-analog-codec.dts
new file mode 100644
index 00000000..74bb13d0
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/sun7i-a20-analog-codec.dts
@@ -0,0 +1,12 @@
+/dts-v1/ /plugin/;
+
+/ {
+	compatible = "allwinner,sun7i-a20";
+
+	fragment@0 {
+		target = <&codec>;
+		__overlay__ {
+			status = "okay";
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-can.dts b/arch/arm/boot/dts/overlay/sun7i-a20-can.dts
new file mode 100644
index 00000000..17601ec1
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/sun7i-a20-can.dts
@@ -0,0 +1,32 @@
+/dts-v1/ /plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	compatible = "allwinner,sun7i-a20";
+
+	fragment@0 {
+		target = <&pio>;
+		__overlay__ {
+			can_pins: can_pins {
+				pins = "PH20", "PH21";
+				function = "can";
+			};
+		};
+	};
+
+	fragment@1 {
+		target-path = "/soc@01c00000";
+		__overlay__ {
+			can0: can@01c2bc00 {
+				compatible = "allwinner,sun4i-a10-can";
+				reg = <0x01c2bc00 0x400>;
+				interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&apb1_gates 4>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&can_pins>;
+				status = "okay";
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-fixup.scr-cmd b/arch/arm/boot/dts/overlay/sun7i-a20-fixup.scr-cmd
new file mode 100644
index 00000000..9ff225a4
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/sun7i-a20-fixup.scr-cmd
@@ -0,0 +1,154 @@
+# overlays fixup script
+# implements (or rather substitutes) overlay arguments functionality
+# using u-boot scripting, environment variables and "fdt" command
+
+# setexpr test_var ${tmp_bank} - A
+# works only for hex numbers (A-F)
+
+setenv decompose_pin 'setexpr tmp_bank sub "P(B|C|D|E|G|H|I)\\d+" "\\1";
+setexpr tmp_pin sub "P\\S(\\d+)" "\\1";
+test "${tmp_bank}" = "B" && setenv tmp_bank 1;
+test "${tmp_bank}" = "C" && setenv tmp_bank 2;
+test "${tmp_bank}" = "D" && setenv tmp_bank 3;
+test "${tmp_bank}" = "E" && setenv tmp_bank 4;
+test "${tmp_bank}" = "G" && setenv tmp_bank 6;
+test "${tmp_bank}" = "H" && setenv tmp_bank 7;
+test "${tmp_bank}" = "I" && setenv tmp_bank 8'
+
+if test "${param_spinor_spi_bus}" = "0"; then
+	fdt set /soc@01c00000/spi@01c05000 status "okay"
+	fdt set /soc@01c00000/spi@01c05000/spiflash status "okay"
+fi
+
+if test "${param_spinor_spi_bus}" = "1"; then
+	fdt set /soc@01c00000/spi@01c06000 status "okay"
+	fdt set /soc@01c00000/spi@01c06000/spiflash status "okay"
+fi
+
+if test "${param_spinor_spi_bus}" = "2"; then
+	fdt set /soc@01c00000/spi@01c17000 status "okay"
+	fdt set /soc@01c00000/spi@01c17000/spiflash status "okay"
+fi
+
+if test "${param_mcp2515_spi_bus}" = "0"; then
+	fdt set /soc@01c00000/spi@01c05000 status "okay"
+	fdt set /soc@01c00000/spi@01c05000/mcp2515 status "okay"
+fi
+
+if test "${param_mcp2515_spi_bus}" = "1"; then
+	fdt set /soc@01c00000/spi@01c06000 status "okay"
+	fdt set /soc@01c00000/spi@01c06000/mcp2515 status "okay"
+fi
+
+if test "${param_mcp2515_spi_bus}" = "2"; then
+	fdt set /soc@01c00000/spi@01c17000 status "okay"
+	fdt set /soc@01c00000/spi@01c17000/mcp2515 status "okay"
+fi
+
+if test "${param_spidev_spi_bus}" = "0"; then
+	fdt set /soc@01c00000/spi@01c05000 status "okay"
+	fdt set /soc@01c00000/spi@01c05000/spidev status "okay"
+fi
+
+if test "${param_spidev_spi_bus}" = "1"; then
+	fdt set /soc@01c00000/spi@01c06000 status "okay"
+	fdt set /soc@01c00000/spi@01c06000/spidev status "okay"
+fi
+
+if test "${param_spidev_spi_bus}" = "2"; then
+	fdt set /soc@01c00000/spi@01c17000 status "okay"
+	fdt set /soc@01c00000/spi@01c17000/spidev status "okay"
+fi
+
+if test -n "${param_mcp2515_clk_freq}"; then
+	fdt set /clocks/can0_osc_fixed clock-frequency "<${param_mcp2515_clk_freq}>"
+fi
+
+if test "${param_spi2_bus_pins}" = "b"; then
+	fdt get value tmp_phandle1 /soc@01c00000/pinctrl@01c20800/spi2@1 phandle
+	fdt get value tmp_phandle2 /soc@01c00000/pinctrl@01c20800/spi2_cs0@1 phandle
+	fdt set /soc@01c00000/spi@01c17000 pinctrl-0 "<${tmp_phandle1}>"
+	fdt set /soc@01c00000/spi@01c17000 pinctrl-1 "<${tmp_phandle2}>"
+	env delete tmp_phandle1 tmp_phandle2
+fi
+
+if test -n "${param_mcp2515_int_pin}"; then
+	setenv tmp_bank "${param_mcp2515_int_pin}"
+	setenv tmp_pin "${param_mcp2515_int_pin}"
+	run decompose_pin
+	fdt set /soc@01c00000/pinctrl@01c20800/can0_pin_irq pins "${param_mcp2515_int_pin}"
+	if test "${param_mcp2515_spi_bus}" = "0"; then
+		setenv tmp_spi_path "spi@01c05000"
+	fi
+	if test "${param_mcp2515_spi_bus}" = "1"; then
+		setenv tmp_spi_path "spi@01c06000"
+	fi
+	if test "${param_mcp2515_spi_bus}" = "2"; then
+		setenv tmp_spi_path "spi@01c17000"
+	fi
+	fdt set /soc@01c00000/${tmp_spi_path}/mcp2515 interrupts "<${tmp_bank} ${tmp_pin} 0x2>"
+	env delete tmp_pin tmp_bank tmp_spi_path
+fi
+
+if test -n "${param_spidev_max_freq}"; then
+	if test "${param_spidev_spi_bus}" = "0"; then
+		setenv tmp_spi_path "spi@01c05000"
+	fi
+	if test "${param_spidev_spi_bus}" = "1"; then
+		setenv tmp_spi_path "spi@01c06000"
+	fi
+	if test "${param_spidev_spi_bus}" = "2"; then
+		setenv tmp_spi_path "spi@01c17000"
+	fi
+	fdt set /soc@01c00000/${tmp_spi_path}/spidev spi-max-frequency "<${param_spidev_max_freq}>"
+	env delete tmp_spi_path
+fi
+
+if test -n "${param_spinor_max_freq}"; then
+	if test "${param_spinor_spi_bus}" = "0"; then
+		setenv tmp_spi_path "spi@01c05000"
+	fi
+	if test "${param_spinor_spi_bus}" = "1"; then
+		setenv tmp_spi_path "spi@01c06000"
+	fi
+	if test "${param_spinor_spi_bus}" = "2"; then
+		setenv tmp_spi_path "spi@01c17000"
+	fi
+	fdt set /soc@01c00000/${tmp_spi_path}/spiflash spi-max-frequency "<${param_spinor_max_freq}>"
+	env delete tmp_spi_path
+fi
+
+if test -n "${param_w1_pin}"; then
+	setenv tmp_bank "${param_w1_pin}"
+	setenv tmp_pin "${param_w1_pin}"
+	run decompose_pin
+	fdt set /soc@01c00000/pinctrl@01c20800/w1_pins pins "${param_w1_pin}"
+	fdt get value tmp_phandle /soc@01c00000/pinctrl@01c20800 phandle
+	fdt set /onewire@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>"
+	env delete tmp_pin tmp_bank tmp_phandle
+fi
+
+if test "${param_w1_pin_int_pullup}" = "1"; then
+	fdt set /soc@01c00000/pinctrl@01c20800/w1_pins bias-pull-up
+fi
+
+if test "${param_uart2_rtscts}" = "1"; then
+	fdt get value tmp_phandle /soc@01c00000/pinctrl@01c20800/uart2@0 phandle
+	fdt set /soc@01c00000/serial@01c28800 pinctrl-0 "<${tmp_phandle}>"
+	env delete tmp_phandle
+fi
+
+if test "${param_uart3_rtscts}" = "1"; then
+	fdt get value tmp_phandle1 /soc@01c00000/pinctrl@01c20800/uart3 phandle
+	fdt get value tmp_phandle2 /soc@01c00000/pinctrl@01c20800/uart3_rts_cts phandle
+	fdt set /soc@01c00000/serial@01c28c00 pinctrl-names "default" "default"
+	fdt set /soc@01c00000/serial@01c28c00 pinctrl-0 "<${tmp_phandle1}>"
+	fdt set /soc@01c00000/serial@01c28c00 pinctrl-1 "<${tmp_phandle2}>"
+	env delete tmp_phandle1 tmp_phandle2
+fi
+
+if test "${param_uart4_pins}" = "b"; then
+	fdt get value tmp_phandle /soc@01c00000/pinctrl@01c20800/uart4@1 phandle
+	fdt set /soc@01c00000/serial@01c29000 pinctrl-0 "<${tmp_phandle}>"
+	env delete tmp_phandle
+fi
diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-i2c1.dts b/arch/arm/boot/dts/overlay/sun7i-a20-i2c1.dts
new file mode 100644
index 00000000..4c551399
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/sun7i-a20-i2c1.dts
@@ -0,0 +1,21 @@
+/dts-v1/ /plugin/;
+
+/ {
+	compatible = "allwinner,sun7i-a20";
+
+	fragment@0 {
+		target-path = "/aliases";
+		__overlay__ {
+			i2c1 = "/soc@01c00000/i2c@01c2b000";
+		};
+	};
+
+	fragment@1 {
+		target = <&i2c1>;
+		__overlay__ {
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c1_pins_a>;
+			status = "okay";
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-i2c2.dts b/arch/arm/boot/dts/overlay/sun7i-a20-i2c2.dts
new file mode 100644
index 00000000..db4478fb
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/sun7i-a20-i2c2.dts
@@ -0,0 +1,21 @@
+/dts-v1/ /plugin/;
+
+/ {
+	compatible = "allwinner,sun7i-a20";
+
+	fragment@0 {
+		target-path = "/aliases";
+		__overlay__ {
+			i2c2 = "/soc@01c00000/i2c@01c2b400";
+		};
+	};
+
+	fragment@1 {
+		target = <&i2c2>;
+		__overlay__ {
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c2_pins_a>;
+			status = "okay";
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-i2c3-edt-ft5x06.dts b/arch/arm/boot/dts/overlay/sun7i-a20-i2c3-edt-ft5x06.dts
new file mode 100644
index 00000000..e3f13e7b
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/sun7i-a20-i2c3-edt-ft5x06.dts
@@ -0,0 +1,41 @@
+/dts-v1/ /plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	compatible = "allwinner,sun7i-a20";
+
+	fragment@0 {
+		target = <&pio>;
+		__overlay__ {
+			edt_ft5x06_pins: edt_ft5x06_pins {
+				pins = "PH7", "PH9";
+				function = "gpio_out";
+			};
+		};
+	};
+
+	fragment@1 {
+		target = <&i2c3>;
+		__overlay__ {
+			status = "okay";
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c3_pins_a>;
+			edt: edt-ft5x06@38 {
+				compatible = "edt,edt-ft5x06";
+				reg = <0x38>;
+				interrupt-parent = <&pio>;
+				interrupts = <7 9 IRQ_TYPE_EDGE_FALLING>;
+				wake-gpios = <7 7 GPIO_ACTIVE_LOW>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&edt_ft5x06_pins>;
+				touchscreen-size-x = <1024>;
+				touchscreen-size-y = <600>;
+				touchscreen-inverted-x;
+				touchscreen-swapped-x-y;
+			};
+		};
+
+	};
+};
diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-i2c3.dts b/arch/arm/boot/dts/overlay/sun7i-a20-i2c3.dts
new file mode 100644
index 00000000..a04e0264
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/sun7i-a20-i2c3.dts
@@ -0,0 +1,21 @@
+/dts-v1/ /plugin/;
+
+/ {
+	compatible = "allwinner,sun7i-a20";
+
+	fragment@0 {
+		target-path = "/aliases";
+		__overlay__ {
+			i2c3 = "/soc@01c00000/i2c@01c2b800";
+		};
+	};
+
+	fragment@1 {
+		target = <&i2c3>;
+		__overlay__ {
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c3_pins_a>;
+			status = "okay";
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-i2c4.dts b/arch/arm/boot/dts/overlay/sun7i-a20-i2c4.dts
new file mode 100644
index 00000000..5f8c313a
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/sun7i-a20-i2c4.dts
@@ -0,0 +1,31 @@
+/dts-v1/ /plugin/;
+
+/ {
+	compatible = "allwinner,sun7i-a20";
+
+	fragment@0 {
+		target-path = "/aliases";
+		__overlay__ {
+			i2c4 = "/soc@01c00000/i2c@01c2c000";
+		};
+	};
+
+	fragment@1 {
+		target = <&pio>;
+		__overlay__ {
+			i2c4_pins_a: i2c4@0 {
+				pins = "PI2", "PI3";
+				function = "i2c4";
+			};
+		};
+	};
+
+	fragment@2 {
+		target = <&i2c4>;
+		__overlay__ {
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c4_pins_a>;
+			status = "okay";
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-nand.dts b/arch/arm/boot/dts/overlay/sun7i-a20-nand.dts
new file mode 100644
index 00000000..dec3a70c
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/sun7i-a20-nand.dts
@@ -0,0 +1,102 @@
+/dts-v1/ /plugin/;
+
+/ {
+	compatible = "allwinner,sun7i-a20";
+
+	fragment@0 {
+		target = <&pio>;
+		__overlay__ {
+			nand_pins_a: nand_pins@0 {
+				pins = "PC0", "PC1", "PC2",
+						"PC5", "PC8", "PC9", "PC10",
+						"PC11", "PC12", "PC13", "PC14",
+						"PC15", "PC16";
+				function = "nand0";
+			};
+
+			nand_cs0_pins_a: nand_cs@0 {
+				pins = "PC4";
+				function = "nand0";
+			};
+
+			nand_cs1_pins_a: nand_cs@1 {
+				pins = "PC3";
+				function = "nand0";
+			};
+
+			nand_cs2_pins_a: nand_cs@2 {
+				pins = "PC17";
+				function = "nand0";
+			};
+
+			nand_cs3_pins_a: nand_cs@3 {
+				pins = "PC18";
+				function = "nand0";
+			};
+
+			nand_rb0_pins_a: nand_rb@0 {
+				pins = "PC6";
+				function = "nand0";
+			};
+
+			nand_rb1_pins_a: nand_rb@1 {
+				pins = "PC7";
+				function = "nand0";
+			};
+		};
+	};
+
+	fragment@1 {
+		target = <&nfc>;
+		__overlay__ {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&nand_pins_a>, <&nand_cs0_pins_a>, <&nand_rb0_pins_a>;
+			status = "okay";
+
+			nand@0 {
+				reg = <0>;
+				allwinner,rb = <0>;
+				nand-ecc-mode = "hw";
+				nand-on-flash-bbt;
+
+				partitions {
+					compatible = "fixed-partitions";
+					#address-cells = <2>;
+					#size-cells = <2>;
+
+					partition@0 {
+						label = "SPL";
+						reg = <0x0 0x0 0x0 0x400000>;
+					};
+
+					partition@400000 {
+						label = "SPL.backup";
+						reg = <0x0 0x400000 0x0 0x400000>;
+					};
+
+					partition@800000 {
+						label = "U-Boot";
+						reg = <0x0 0x800000 0x0 0x400000>;
+					};
+
+					partition@c00000 {
+						label = "U-Boot.backup";
+						reg = <0x0 0xc00000 0x0 0x400000>;
+					};
+
+					partition@1000000 {
+						label = "env";
+						reg = <0x0 0x1000000 0x0 0x400000>;
+					};
+
+					partition@1400000 {
+						label = "rootfs";
+						reg = <0x0 0xa00000 0x01 0xff000000>;
+					};
+				};
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-spdif-out.dts b/arch/arm/boot/dts/overlay/sun7i-a20-spdif-out.dts
new file mode 100644
index 00000000..0463f43c
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/sun7i-a20-spdif-out.dts
@@ -0,0 +1,37 @@
+/dts-v1/ /plugin/;
+
+/ {
+	compatible = "allwinner,sun7i-a20";
+
+	fragment@0 {
+		target = <&spdif>;
+		__overlay__ {
+			pinctrl-names = "default";
+			pinctrl-0 = <&spdif_tx_pins_a>;
+			status = "okay";
+		};
+	};
+
+	fragment@1 {
+		target-path = "/";
+		__overlay__ {
+			sound {
+				compatible = "simple-audio-card";
+				simple-audio-card,name = "On-board SPDIF";
+
+				simple-audio-card,cpu {
+					sound-dai = <&spdif>;
+				};
+
+				simple-audio-card,codec {
+					sound-dai = <&spdif_out>;
+				};
+
+				spdif_out: spdif-out {
+					#sound-dai-cells = <0>;
+					compatible = "linux,spdif-dit";
+				};
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-spi-jedec-nor.dts b/arch/arm/boot/dts/overlay/sun7i-a20-spi-jedec-nor.dts
new file mode 100644
index 00000000..e8d2e17d
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/sun7i-a20-spi-jedec-nor.dts
@@ -0,0 +1,67 @@
+/dts-v1/ /plugin/;
+
+/ {
+	compatible = "allwinner,sun7i-a20";
+
+	fragment@0 {
+		target-path = "/aliases";
+		__overlay__ {
+			spi0 = "/soc/spi@01c05000";
+			spi1 = "/soc/spi@01c06000";
+			spi2 = "/soc/spi@01c17000";
+		};
+	};
+
+	fragment@1 {
+		target = <&spi0>;
+		__overlay__ {
+			status = "okay";
+			pinctrl-names = "default", "default";
+			pinctrl-0 = <&spi0_pins_a>;
+			pinctrl-1 = <&spi0_cs0_pins_a>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			spiflash {
+				compatible = "jedec,spi-nor";
+				reg = <0>;
+				spi-max-frequency = <1000000>;
+				status = "okay";
+			};
+		};
+	};
+
+	fragment@2 {
+		target = <&spi1>;
+		__overlay__ {
+			status = "disabled";
+			pinctrl-names = "default";
+			pinctrl-0 = <&spi1_pins_a>, <&spi1_cs0_pins_a>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			spiflash {
+				compatible = "jedec,spi-nor";
+				status = "disabled";
+				reg = <0>;
+				spi-max-frequency = <1000000>;
+			};
+		};
+	};
+
+	fragment@3 {
+		target = <&spi2>;
+		__overlay__ {
+			status = "disabled";
+			pinctrl-names = "default", "default";
+			pinctrl-0 = <&spi2_pins_a>;
+			pinctrl-1 = <&spi2_cs0_pins_a>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			spiflash {
+				compatible = "jedec,spi-nor";
+				status = "disabled";
+				reg = <0>;
+				spi-max-frequency = <1000000>;
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-spi-mcp2515.dts b/arch/arm/boot/dts/overlay/sun7i-a20-spi-mcp2515.dts
new file mode 100644
index 00000000..5ebcf66d
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/sun7i-a20-spi-mcp2515.dts
@@ -0,0 +1,105 @@
+/dts-v1/ /plugin/;
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+	compatible = "allwinner,sun7i-a20";
+
+	fragment@0 {
+		target-path = "/aliases";
+		__overlay__ {
+			spi1 = "/soc/spi@01c06000";
+			spi2 = "/soc/spi@01c17000";
+			spi3 = "/soc/spi@01c1f000";
+		};
+	};
+
+	fragment@1 {
+		target-path = "/clocks";
+		__overlay__ {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			can0_osc_fixed: can0_osc_fixed {
+				compatible = "fixed-clock";
+				#clock-cells = <0>;
+				clock-frequency  = <8000000>;
+			};
+		};
+	};
+
+	fragment@2 {
+		target = <&pio>;
+		__overlay__ {
+			can0_pin_irq: can0_pin_irq {
+				pins = "PH15";
+				function = "irq";
+				bias-pull-up;
+			};
+		};
+	};
+
+	fragment@3 {
+		target = <&spi0>;
+		__overlay__ {
+			pinctrl-names = "default", "default";
+			pinctrl-0 = <&spi0_pins_a>;
+			pinctrl-1 = <&spi0_cs0_pins_a>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			mcp2515 {
+				reg = <0>;
+				compatible = "microchip,mcp2515";
+				pinctrl-names = "default";
+				pinctrl-0 = <&can0_pin_irq>;
+				spi-max-frequency = <10000000>;
+				interrupt-parent = <&pio>;
+				interrupts = <7 15 IRQ_TYPE_EDGE_FALLING>; /* PH15 */
+				clocks = <&can0_osc_fixed>;
+				status = "disabled";
+			};
+		};
+	};
+
+	fragment@4 {
+		target = <&spi1>;
+		__overlay__ {
+			pinctrl-names = "default";
+			pinctrl-0 = <&spi1_pins_a>, <&spi1_cs0_pins_a>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			mcp2515 {
+				reg = <0>;
+				compatible = "microchip,mcp2515";
+				pinctrl-names = "default";
+				pinctrl-0 = <&can0_pin_irq>;
+				spi-max-frequency = <10000000>;
+				interrupt-parent = <&pio>;
+				interrupts = <7 15 IRQ_TYPE_EDGE_FALLING>; /* PH15 */
+				clocks = <&can0_osc_fixed>;
+				status = "disabled";
+			};
+		};
+	};
+
+	fragment@5 {
+		target = <&spi2>;
+		__overlay__ {
+			pinctrl-names = "default", "default";
+			pinctrl-0 = <&spi2_pins_a>;
+			pinctrl-1 = <&spi2_cs0_pins_a>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			mcp2515 {
+				reg = <0>;
+				compatible = "microchip,mcp2515";
+				pinctrl-names = "default";
+				pinctrl-0 = <&can0_pin_irq>;
+				spi-max-frequency = <10000000>;
+				interrupt-parent = <&pio>;
+				interrupts = <7 15 IRQ_TYPE_EDGE_FALLING>; /* PH15 */
+				clocks = <&can0_osc_fixed>;
+				status = "disabled";
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-spi-spidev.dts b/arch/arm/boot/dts/overlay/sun7i-a20-spi-spidev.dts
new file mode 100644
index 00000000..4d448661
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/sun7i-a20-spi-spidev.dts
@@ -0,0 +1,64 @@
+/dts-v1/ /plugin/;
+
+/ {
+	compatible = "allwinner,sun7i-a20";
+
+	fragment@0 {
+		target-path = "/aliases";
+		__overlay__ {
+			spi0 = "/soc/spi@01c05000";
+			spi1 = "/soc/spi@01c06000";
+			spi2 = "/soc/spi@01c17000";
+		};
+	};
+
+	fragment@1 {
+		target = <&spi0>;
+		__overlay__ {
+			pinctrl-names = "default", "default";
+			pinctrl-0 = <&spi0_pins_a>;
+			pinctrl-1 = <&spi0_cs0_pins_a>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			spidev {
+				compatible = "spidev";
+				status = "disabled";
+				reg = <0>;
+				spi-max-frequency = <1000000>;
+			};
+		};
+	};
+
+	fragment@2 {
+		target = <&spi1>;
+		__overlay__ {
+			pinctrl-names = "default";
+			pinctrl-0 = <&spi1_pins_a>, <&spi1_cs0_pins_a>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			spidev {
+				compatible = "spidev";
+				status = "disabled";
+				reg = <0>;
+				spi-max-frequency = <1000000>;
+			};
+		};
+	};
+
+	fragment@3 {
+		target = <&spi2>;
+		__overlay__ {
+			pinctrl-names = "default", "default";
+			pinctrl-0 = <&spi2_pins_a>;
+			pinctrl-1 = <&spi2_cs0_pins_a>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			spidev {
+				compatible = "spidev";
+				status = "disabled";
+				reg = <0>;
+				spi-max-frequency = <1000000>;
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-uart2.dts b/arch/arm/boot/dts/overlay/sun7i-a20-uart2.dts
new file mode 100644
index 00000000..e4992768
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/sun7i-a20-uart2.dts
@@ -0,0 +1,21 @@
+/dts-v1/ /plugin/;
+
+/ {
+	compatible = "allwinner,sun7i-a20";
+
+	fragment@0 {
+		target-path = "/aliases";
+		__overlay__ {
+			uart2 = "/soc@01c00000/serial@01c28800";
+		};
+	};
+
+	fragment@1 {
+		target = <&uart2>;
+		 __overlay__ {
+			pinctrl-names = "default";
+			pinctrl-0 = <&uart2_pins>;
+			status = "okay";
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-uart3.dts b/arch/arm/boot/dts/overlay/sun7i-a20-uart3.dts
new file mode 100644
index 00000000..4f932c54
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/sun7i-a20-uart3.dts
@@ -0,0 +1,31 @@
+/dts-v1/ /plugin/;
+
+/ {
+	compatible = "allwinner,sun7i-a20";
+
+	fragment@0 {
+		target-path = "/aliases";
+		__overlay__ {
+			uart3 = "/soc@01c00000/serial@01c28c00";
+		};
+	};
+
+	fragment@1 {
+		target = <&pio>;
+		__overlay__ {
+			uart3_pins_a_2: uart3@2 {
+				pins = "PG6", "PG7";
+				function = "uart3";
+			};
+		};
+	};
+
+	fragment@2 {
+		target = <&uart3>;
+		 __overlay__ {
+			pinctrl-names = "default";
+			pinctrl-0 = <&uart3_pins_a_2>;
+			status = "okay";
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-uart4.dts b/arch/arm/boot/dts/overlay/sun7i-a20-uart4.dts
new file mode 100644
index 00000000..e6fd8a3b
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/sun7i-a20-uart4.dts
@@ -0,0 +1,21 @@
+/dts-v1/ /plugin/;
+
+/ {
+	compatible = "allwinner,sun7i-a20";
+
+	fragment@0 {
+		target-path = "/aliases";
+		__overlay__ {
+			serial4 = "/soc@01c00000/serial@01c29000";
+		};
+	};
+
+	fragment@1 {
+		target = <&uart4>;
+		 __overlay__ {
+			pinctrl-names = "default";
+			pinctrl-0 = <&uart4_pins_a>;
+			status = "okay";
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-uart5.dts b/arch/arm/boot/dts/overlay/sun7i-a20-uart5.dts
new file mode 100644
index 00000000..65675241
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/sun7i-a20-uart5.dts
@@ -0,0 +1,21 @@
+/dts-v1/ /plugin/;
+
+/ {
+	compatible = "allwinner,sun7i-a20";
+
+	fragment@0 {
+		target-path = "/aliases";
+		__overlay__ {
+			serial5 = "/soc@01c00000/serial@01c29400";
+		};
+	};
+
+	fragment@1 {
+		target = <&uart5>;
+		 __overlay__ {
+			pinctrl-names = "default";
+			pinctrl-0 = <&uart5_pins_a>;
+			status = "okay";
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-uart6.dts b/arch/arm/boot/dts/overlay/sun7i-a20-uart6.dts
new file mode 100644
index 00000000..3642fd35
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/sun7i-a20-uart6.dts
@@ -0,0 +1,21 @@
+/dts-v1/ /plugin/;
+
+/ {
+	compatible = "allwinner,sun7i-a20";
+
+	fragment@0 {
+		target-path = "/aliases";
+		__overlay__ {
+			serial6 = "/soc@01c00000/serial@01c29800";
+		};
+	};
+
+	fragment@1 {
+		target = <&uart6>;
+		 __overlay__ {
+			pinctrl-names = "default";
+			pinctrl-0 = <&uart6_pins_a>;
+			status = "okay";
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-uart7.dts b/arch/arm/boot/dts/overlay/sun7i-a20-uart7.dts
new file mode 100644
index 00000000..bd0d1b48
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/sun7i-a20-uart7.dts
@@ -0,0 +1,21 @@
+/dts-v1/ /plugin/;
+
+/ {
+	compatible = "allwinner,sun7i-a20";
+
+	fragment@0 {
+		target-path = "/aliases";
+		__overlay__ {
+			serial7 = "/soc@01c00000/serial@01c29c00";
+		};
+	};
+
+	fragment@1 {
+		target = <&uart7>;
+		 __overlay__ {
+			pinctrl-names = "default";
+			pinctrl-0 = <&uart7_pins_a>;
+			status = "okay";
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-w1-gpio.dts b/arch/arm/boot/dts/overlay/sun7i-a20-w1-gpio.dts
new file mode 100644
index 00000000..771af0de
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/sun7i-a20-w1-gpio.dts
@@ -0,0 +1,28 @@
+/dts-v1/ /plugin/;
+
+/ {
+	compatible = "allwinner,sun7i-a20";
+
+	fragment@0 {
+		target = <&pio>;
+		__overlay__ {
+			w1_pins: w1_pins {
+				pins = "PI15";
+				function = "gpio_in";
+			};
+		};
+	};
+
+	fragment@1 {
+		target-path = "/";
+		__overlay__ {
+			w1: onewire@0 {
+				compatible = "w1-gpio";
+				pinctrl-names = "default";
+				pinctrl-0 = <&w1_pins>;
+				gpios = <&pio 8 15 0>; /* PI15 */
+				status = "okay";
+			};
+		};
+	};
+};