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* sunxi-6.0: initial state: add megous patches to series * sunxi-6.0: Switch to v6.0.1 * wifi: Limit the version 6.0 for Realtek 88x2cs chipsets * Adjust kernel configs * Remove not needed patches * Adjust broken patches Co-authored-by: Igor <igor@armbian.com>
138 lines
4.8 KiB
Diff
138 lines
4.8 KiB
Diff
From aefbc059c9d7f51065d65dbce0da6a60ae8c8a24 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
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Date: Wed, 3 Jun 2020 11:06:05 +0200
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Subject: [PATCH 198/486] drm debugging code
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---
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drivers/gpu/drm/sun4i/sun8i_ui_layer.c | 14 ++++++++++++++
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drivers/gpu/drm/sun4i/sun8i_vi_layer.c | 22 ++++++++++++++++++++++
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2 files changed, 36 insertions(+)
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diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
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index 98acc58b7..8a6fe09a0 100644
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--- a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
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+++ b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
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@@ -31,6 +31,7 @@ static void sun8i_ui_layer_enable(struct sun8i_mixer *mixer, int channel,
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{
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u32 val, bld_base, ch_base;
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unsigned int old_pipe_ch;
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+ unsigned tmp;
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bld_base = sun8i_blender_base(mixer);
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ch_base = sun8i_channel_base(mixer, channel);
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@@ -103,6 +104,10 @@ static void sun8i_ui_layer_enable(struct sun8i_mixer *mixer, int channel,
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DRM_DEBUG_DRIVER(" enable pipe %d <- ch %d\n", zpos, channel);
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}
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+
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+ regmap_read(mixer->engine.regs,
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+ SUN8I_MIXER_CHAN_UI_LAYER_ATTR(ch_base, overlay), &tmp);
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+ DRM_DEBUG_DRIVER(" post-en-dis %08x\n", tmp);
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}
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static void sun8i_ui_layer_update_alpha(struct sun8i_mixer *mixer, int channel,
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@@ -200,6 +205,7 @@ static int sun8i_ui_layer_update_formats(struct sun8i_mixer *mixer, int channel,
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struct drm_plane_state *state = plane->state;
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const struct drm_format_info *fmt;
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u32 val, ch_base, hw_fmt;
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+ unsigned tmp;
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int ret;
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ch_base = sun8i_channel_base(mixer, channel);
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@@ -211,11 +217,19 @@ static int sun8i_ui_layer_update_formats(struct sun8i_mixer *mixer, int channel,
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return -EINVAL;
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}
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+ regmap_read(mixer->engine.regs,
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+ SUN8I_MIXER_CHAN_UI_LAYER_ATTR(ch_base, overlay), &tmp);
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+ DRM_DEBUG_DRIVER(" pre-format %08x\n", tmp);
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+
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val = hw_fmt << SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_OFFSET;
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regmap_update_bits(mixer->engine.regs,
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SUN8I_MIXER_CHAN_UI_LAYER_ATTR(ch_base, overlay),
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SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_MASK, val);
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+ regmap_read(mixer->engine.regs,
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+ SUN8I_MIXER_CHAN_UI_LAYER_ATTR(ch_base, overlay), &tmp);
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+ DRM_DEBUG_DRIVER(" post-format %08x\n", tmp);
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+
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return 0;
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}
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diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
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index 8576f58f0..0f578511e 100644
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--- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
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+++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
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@@ -25,6 +25,7 @@ static void sun8i_vi_layer_enable(struct sun8i_mixer *mixer, int channel,
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{
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u32 val, bld_base, ch_base;
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unsigned int old_pipe_ch;
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+ unsigned tmp;
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bld_base = sun8i_blender_base(mixer);
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ch_base = sun8i_channel_base(mixer, channel);
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@@ -97,6 +98,10 @@ static void sun8i_vi_layer_enable(struct sun8i_mixer *mixer, int channel,
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DRM_DEBUG_DRIVER(" enable pipe %d <- ch %d\n", zpos, channel);
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}
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+
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+ regmap_read(mixer->engine.regs,
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+ SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base, overlay), &tmp);
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+ DRM_DEBUG_DRIVER(" post-en-dis %08x\n", tmp);
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}
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static void sun8i_vi_layer_update_alpha(struct sun8i_mixer *mixer, int channel,
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@@ -296,6 +301,7 @@ static int sun8i_vi_layer_update_formats(struct sun8i_mixer *mixer, int channel,
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struct drm_plane_state *state = plane->state;
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u32 val, ch_base, csc_mode, hw_fmt;
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const struct drm_format_info *fmt;
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+ unsigned tmp;
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int ret;
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ch_base = sun8i_channel_base(mixer, channel);
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@@ -307,11 +313,19 @@ static int sun8i_vi_layer_update_formats(struct sun8i_mixer *mixer, int channel,
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return ret;
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}
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+ regmap_read(mixer->engine.regs,
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+ SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base, overlay), &tmp);
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+ DRM_DEBUG_DRIVER(" pre-format %08x\n", tmp);
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+
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val = hw_fmt << SUN8I_MIXER_CHAN_VI_LAYER_ATTR_FBFMT_OFFSET;
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regmap_update_bits(mixer->engine.regs,
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SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base, overlay),
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SUN8I_MIXER_CHAN_VI_LAYER_ATTR_FBFMT_MASK, val);
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+ regmap_read(mixer->engine.regs,
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+ SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base, overlay), &tmp);
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+ DRM_DEBUG_DRIVER(" mid1-format %08x\n", tmp);
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+
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csc_mode = sun8i_vi_layer_get_csc_mode(fmt);
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if (csc_mode != SUN8I_CSC_MODE_OFF) {
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sun8i_csc_set_ccsc_coefficients(mixer, channel, csc_mode,
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@@ -322,6 +336,10 @@ static int sun8i_vi_layer_update_formats(struct sun8i_mixer *mixer, int channel,
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sun8i_csc_enable_ccsc(mixer, channel, false);
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}
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+ regmap_read(mixer->engine.regs,
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+ SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base, overlay), &tmp);
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+ DRM_DEBUG_DRIVER(" mid2-format %08x\n", tmp);
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+
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if (!fmt->is_yuv)
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val = SUN8I_MIXER_CHAN_VI_LAYER_ATTR_RGB_MODE;
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else
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@@ -331,6 +349,10 @@ static int sun8i_vi_layer_update_formats(struct sun8i_mixer *mixer, int channel,
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SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base, overlay),
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SUN8I_MIXER_CHAN_VI_LAYER_ATTR_RGB_MODE, val);
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+ regmap_read(mixer->engine.regs,
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+ SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base, overlay), &tmp);
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+ DRM_DEBUG_DRIVER(" post-format %08x\n", tmp);
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+
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return 0;
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}
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--
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2.35.3
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