From aefbc059c9d7f51065d65dbce0da6a60ae8c8a24 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Wed, 3 Jun 2020 11:06:05 +0200 Subject: [PATCH 198/486] drm debugging code --- drivers/gpu/drm/sun4i/sun8i_ui_layer.c | 14 ++++++++++++++ drivers/gpu/drm/sun4i/sun8i_vi_layer.c | 22 ++++++++++++++++++++++ 2 files changed, 36 insertions(+) diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c index 98acc58b7..8a6fe09a0 100644 --- a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c +++ b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c @@ -31,6 +31,7 @@ static void sun8i_ui_layer_enable(struct sun8i_mixer *mixer, int channel, { u32 val, bld_base, ch_base; unsigned int old_pipe_ch; + unsigned tmp; bld_base = sun8i_blender_base(mixer); ch_base = sun8i_channel_base(mixer, channel); @@ -103,6 +104,10 @@ static void sun8i_ui_layer_enable(struct sun8i_mixer *mixer, int channel, DRM_DEBUG_DRIVER(" enable pipe %d <- ch %d\n", zpos, channel); } + + regmap_read(mixer->engine.regs, + SUN8I_MIXER_CHAN_UI_LAYER_ATTR(ch_base, overlay), &tmp); + DRM_DEBUG_DRIVER(" post-en-dis %08x\n", tmp); } static void sun8i_ui_layer_update_alpha(struct sun8i_mixer *mixer, int channel, @@ -200,6 +205,7 @@ static int sun8i_ui_layer_update_formats(struct sun8i_mixer *mixer, int channel, struct drm_plane_state *state = plane->state; const struct drm_format_info *fmt; u32 val, ch_base, hw_fmt; + unsigned tmp; int ret; ch_base = sun8i_channel_base(mixer, channel); @@ -211,11 +217,19 @@ static int sun8i_ui_layer_update_formats(struct sun8i_mixer *mixer, int channel, return -EINVAL; } + regmap_read(mixer->engine.regs, + SUN8I_MIXER_CHAN_UI_LAYER_ATTR(ch_base, overlay), &tmp); + DRM_DEBUG_DRIVER(" pre-format %08x\n", tmp); + val = hw_fmt << SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_OFFSET; regmap_update_bits(mixer->engine.regs, SUN8I_MIXER_CHAN_UI_LAYER_ATTR(ch_base, overlay), SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_MASK, val); + regmap_read(mixer->engine.regs, + SUN8I_MIXER_CHAN_UI_LAYER_ATTR(ch_base, overlay), &tmp); + DRM_DEBUG_DRIVER(" post-format %08x\n", tmp); + return 0; } diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c index 8576f58f0..0f578511e 100644 --- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c +++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c @@ -25,6 +25,7 @@ static void sun8i_vi_layer_enable(struct sun8i_mixer *mixer, int channel, { u32 val, bld_base, ch_base; unsigned int old_pipe_ch; + unsigned tmp; bld_base = sun8i_blender_base(mixer); ch_base = sun8i_channel_base(mixer, channel); @@ -97,6 +98,10 @@ static void sun8i_vi_layer_enable(struct sun8i_mixer *mixer, int channel, DRM_DEBUG_DRIVER(" enable pipe %d <- ch %d\n", zpos, channel); } + + regmap_read(mixer->engine.regs, + SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base, overlay), &tmp); + DRM_DEBUG_DRIVER(" post-en-dis %08x\n", tmp); } static void sun8i_vi_layer_update_alpha(struct sun8i_mixer *mixer, int channel, @@ -296,6 +301,7 @@ static int sun8i_vi_layer_update_formats(struct sun8i_mixer *mixer, int channel, struct drm_plane_state *state = plane->state; u32 val, ch_base, csc_mode, hw_fmt; const struct drm_format_info *fmt; + unsigned tmp; int ret; ch_base = sun8i_channel_base(mixer, channel); @@ -307,11 +313,19 @@ static int sun8i_vi_layer_update_formats(struct sun8i_mixer *mixer, int channel, return ret; } + regmap_read(mixer->engine.regs, + SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base, overlay), &tmp); + DRM_DEBUG_DRIVER(" pre-format %08x\n", tmp); + val = hw_fmt << SUN8I_MIXER_CHAN_VI_LAYER_ATTR_FBFMT_OFFSET; regmap_update_bits(mixer->engine.regs, SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base, overlay), SUN8I_MIXER_CHAN_VI_LAYER_ATTR_FBFMT_MASK, val); + regmap_read(mixer->engine.regs, + SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base, overlay), &tmp); + DRM_DEBUG_DRIVER(" mid1-format %08x\n", tmp); + csc_mode = sun8i_vi_layer_get_csc_mode(fmt); if (csc_mode != SUN8I_CSC_MODE_OFF) { sun8i_csc_set_ccsc_coefficients(mixer, channel, csc_mode, @@ -322,6 +336,10 @@ static int sun8i_vi_layer_update_formats(struct sun8i_mixer *mixer, int channel, sun8i_csc_enable_ccsc(mixer, channel, false); } + regmap_read(mixer->engine.regs, + SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base, overlay), &tmp); + DRM_DEBUG_DRIVER(" mid2-format %08x\n", tmp); + if (!fmt->is_yuv) val = SUN8I_MIXER_CHAN_VI_LAYER_ATTR_RGB_MODE; else @@ -331,6 +349,10 @@ static int sun8i_vi_layer_update_formats(struct sun8i_mixer *mixer, int channel, SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base, overlay), SUN8I_MIXER_CHAN_VI_LAYER_ATTR_RGB_MODE, val); + regmap_read(mixer->engine.regs, + SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base, overlay), &tmp); + DRM_DEBUG_DRIVER(" post-format %08x\n", tmp); + return 0; } -- 2.35.3