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95ea87ffc2
DCM means dynamic clock management, and it can dynamically slow down or gate clocks during CPU or bus idle. 1. Add MCUSYS related DCM drivers. 2. Enable MCUSYS related DCM by default. TEST=build pass BUG=b:202871018 Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.corp-partner.google.com> Change-Id: Idc669364c89cde0974d2940bd12987ee833d1965
59 lines
2.2 KiB
C
59 lines
2.2 KiB
C
/*
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* Copyright (c) 2021, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef MTK_DCM_UTILS_H
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#define MTK_DCM_UTILS_H
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#include <stdbool.h>
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#include <mtk_dcm.h>
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#include <platform_def.h>
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/* Base */
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#define MP_CPUSYS_TOP_BASE 0xc538000
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#define CPCCFG_REG_BASE 0xc53a800
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/* Register Definition */
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#define CPCCFG_REG_EMI_WFIFO (CPCCFG_REG_BASE + 0x100)
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#define MP_CPUSYS_TOP_BUS_PLLDIV_CFG (MP_CPUSYS_TOP_BASE + 0x22e0)
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#define MP_CPUSYS_TOP_CPU_PLLDIV_CFG0 (MP_CPUSYS_TOP_BASE + 0x22a0)
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#define MP_CPUSYS_TOP_CPU_PLLDIV_CFG1 (MP_CPUSYS_TOP_BASE + 0x22a4)
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#define MP_CPUSYS_TOP_MCSIC_DCM0 (MP_CPUSYS_TOP_BASE + 0x2440)
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#define MP_CPUSYS_TOP_MCSI_CFG2 (MP_CPUSYS_TOP_BASE + 0x2418)
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#define MP_CPUSYS_TOP_MCUSYS_DCM_CFG0 (MP_CPUSYS_TOP_BASE + 0x25c0)
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#define MP_CPUSYS_TOP_MP0_DCM_CFG0 (MP_CPUSYS_TOP_BASE + 0x4880)
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#define MP_CPUSYS_TOP_MP0_DCM_CFG7 (MP_CPUSYS_TOP_BASE + 0x489c)
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#define MP_CPUSYS_TOP_MP_ADB_DCM_CFG4 (MP_CPUSYS_TOP_BASE + 0x2510)
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#define MP_CPUSYS_TOP_MP_MISC_DCM_CFG0 (MP_CPUSYS_TOP_BASE + 0x2518)
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bool dcm_mp_cpusys_top_adb_dcm_is_on(void);
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void dcm_mp_cpusys_top_adb_dcm(bool on);
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bool dcm_mp_cpusys_top_apb_dcm_is_on(void);
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void dcm_mp_cpusys_top_apb_dcm(bool on);
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bool dcm_mp_cpusys_top_bus_pll_div_dcm_is_on(void);
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void dcm_mp_cpusys_top_bus_pll_div_dcm(bool on);
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bool dcm_mp_cpusys_top_core_stall_dcm_is_on(void);
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void dcm_mp_cpusys_top_core_stall_dcm(bool on);
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bool dcm_mp_cpusys_top_cpubiu_dbg_cg_is_on(void);
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void dcm_mp_cpusys_top_cpubiu_dbg_cg(bool on);
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bool dcm_mp_cpusys_top_cpubiu_dcm_is_on(void);
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void dcm_mp_cpusys_top_cpubiu_dcm(bool on);
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bool dcm_mp_cpusys_top_cpu_pll_div_0_dcm_is_on(void);
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void dcm_mp_cpusys_top_cpu_pll_div_0_dcm(bool on);
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bool dcm_mp_cpusys_top_cpu_pll_div_1_dcm_is_on(void);
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void dcm_mp_cpusys_top_cpu_pll_div_1_dcm(bool on);
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bool dcm_mp_cpusys_top_fcm_stall_dcm_is_on(void);
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void dcm_mp_cpusys_top_fcm_stall_dcm(bool on);
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bool dcm_mp_cpusys_top_last_cor_idle_dcm_is_on(void);
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void dcm_mp_cpusys_top_last_cor_idle_dcm(bool on);
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bool dcm_mp_cpusys_top_misc_dcm_is_on(void);
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void dcm_mp_cpusys_top_misc_dcm(bool on);
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bool dcm_mp_cpusys_top_mp0_qdcm_is_on(void);
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void dcm_mp_cpusys_top_mp0_qdcm(bool on);
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bool dcm_cpccfg_reg_emi_wfifo_is_on(void);
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void dcm_cpccfg_reg_emi_wfifo(bool on);
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#endif
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