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95ea87ffc2
DCM means dynamic clock management, and it can dynamically slow down or gate clocks during CPU or bus idle. 1. Add MCUSYS related DCM drivers. 2. Enable MCUSYS related DCM by default. TEST=build pass BUG=b:202871018 Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.corp-partner.google.com> Change-Id: Idc669364c89cde0974d2940bd12987ee833d1965
67 lines
1.6 KiB
C
67 lines
1.6 KiB
C
/*
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* Copyright (c) 2021, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common/debug.h>
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#include <mtk_dcm.h>
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#include <mtk_dcm_utils.h>
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static void dcm_armcore(bool mode)
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{
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dcm_mp_cpusys_top_bus_pll_div_dcm(mode);
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dcm_mp_cpusys_top_cpu_pll_div_0_dcm(mode);
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dcm_mp_cpusys_top_cpu_pll_div_1_dcm(mode);
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}
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static void dcm_mcusys(bool on)
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{
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dcm_mp_cpusys_top_adb_dcm(on);
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dcm_mp_cpusys_top_apb_dcm(on);
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dcm_mp_cpusys_top_cpubiu_dcm(on);
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dcm_mp_cpusys_top_cpubiu_dbg_cg(on);
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dcm_mp_cpusys_top_misc_dcm(on);
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dcm_mp_cpusys_top_mp0_qdcm(on);
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dcm_cpccfg_reg_emi_wfifo(on);
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dcm_mp_cpusys_top_last_cor_idle_dcm(on);
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}
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static void dcm_stall(bool on)
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{
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dcm_mp_cpusys_top_core_stall_dcm(on);
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dcm_mp_cpusys_top_fcm_stall_dcm(on);
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}
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static bool check_dcm_state(void)
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{
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bool ret = true;
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ret &= dcm_mp_cpusys_top_bus_pll_div_dcm_is_on();
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ret &= dcm_mp_cpusys_top_cpu_pll_div_0_dcm_is_on();
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ret &= dcm_mp_cpusys_top_cpu_pll_div_1_dcm_is_on();
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ret &= dcm_mp_cpusys_top_adb_dcm_is_on();
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ret &= dcm_mp_cpusys_top_apb_dcm_is_on();
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ret &= dcm_mp_cpusys_top_cpubiu_dcm_is_on();
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ret &= dcm_mp_cpusys_top_cpubiu_dbg_cg_is_on();
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ret &= dcm_mp_cpusys_top_misc_dcm_is_on();
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ret &= dcm_mp_cpusys_top_mp0_qdcm_is_on();
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ret &= dcm_cpccfg_reg_emi_wfifo_is_on();
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ret &= dcm_mp_cpusys_top_last_cor_idle_dcm_is_on();
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ret &= dcm_mp_cpusys_top_core_stall_dcm_is_on();
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ret &= dcm_mp_cpusys_top_fcm_stall_dcm_is_on();
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return ret;
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}
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void dcm_set_default(void)
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{
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dcm_armcore(true);
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dcm_mcusys(true);
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dcm_stall(true);
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INFO("%s: %d", __func__, check_dcm_state());
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}
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