12179 Commits

Author SHA1 Message Date
Nicolas Le Bayon
2742374414 feat(stm32mp1): add RNG initialization in BL2 for STM32MP13
Initialize RNG driver at platform level for STM32MP13.

Change-Id: I64832de43e5f6559a12e26680142db54c88f0b9e
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@foss.st.com>
2022-11-14 10:55:17 +01:00
Lionel Debieve
6b5fc19227 feat(st-crypto): remove BL32 HASH driver usage
Remove unused mode for HASH driver. The driver will only be
used in BL2 scope.

Change-Id: I1fce09cdaa9da0c11554ac5f73433b4bee776011
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
2022-11-14 10:55:17 +01:00
Lionel Debieve
ad3e46a35c feat(stm32mp1): add a stm32mp crypto library
Add the crypto library for STM32MP1 to use STM32 hardware
accelerators.

Change-Id: I0bbb941001242a6fdc47514ab3efe07b12249285
Signed-off-by: Nicolas Toromanoff <nicolas.toromanoff@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
2022-11-14 10:55:17 +01:00
Yann Gautier
af8dee20d5 feat(st-crypto): add STM32 RNG driver
This driver manages the STM32 Random Number Generator
peripheral.

Change-Id: I4403ebb2dbdaa8df993a4413f1ef48eeba00427c
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
2022-11-14 10:55:17 +01:00
Nicolas Toromanoff
4bb4e83649 feat(st-crypto): add AES decrypt/auth by SAES IP
Add code to be able to use STMicroelectronics SAES IP. This driver
can manage many AES algorithms (CBC, ECB, CCM, GCM). It will be used
by the authenticated decryption framework (AES-GCM only).

Change-Id: Ibd4030719fb12877dcecd5d2c395d13b4b15c260
Signed-off-by: Nicolas Toromanoff <nicolas.toromanoff@st.com>
2022-11-14 10:55:17 +01:00
Nicolas Toromanoff
b0fbc02aea feat(st-crypto): add ECDSA signature check with PKA
Add code to be able to use STMicroelectronics PKA peripheral
in the authentication framework.

Change-Id: Ifeafe84c68db483cd18674f2280576cc065f92ee
Signed-off-by: Nicolas Toromanoff <nicolas.toromanoff@st.com>
2022-11-14 10:55:17 +01:00
Nicolas Toromanoff
68039f2d14 feat(st-crypto): update HASH for new hardware version used in STM32MP13
Introduce new flag to manage hardware version.
STM32MP15 currently uses the HASH_V2 and STM32MP13 uses the HASH_V4.
For STM32_HASH_V4: remove MD5 algorithm (no more supported) and
add SHA384 and SHA512.

For STM32_HASH_V2: no change.

Change-Id: I3a9ae9e38249a2421c657232cb0877004d04dae1
Signed-off-by: Nicolas Toromanoff <nicolas.toromanoff@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
2022-11-14 10:55:17 +01:00
Liju-Clr Chen
32071c0263 fix(mt8188): add mmap entry for CPU idle SRAM
CPU PM driver accesses CPU idle SRAM during the system suspend
process. The region of CPU idle SRAM needs to be added as mmap entry.
Otherwise, the execption would occur.

BUG=b:244215539
TEST=Test of suspend resume passes.

Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com>
Change-Id: I5838964fd9cb1b833e4006e2123febb4a4601003
2022-11-14 15:54:09 +08:00
James Liao
210ebbb0a6 fix(mt8188): refine gic init flow after system resume
Call gicv3_distif_init() instead of mt_gic_init() in
armv8_2_mcusys_pwr_on_common(). This is to prevent
gicv3_rdistif_init() and gicv3_cpuif_enable() from being called twice
in the power-on flow. gicv3_rdistif_init() and gicv3_cpuif_enable()
are called in later armv8_2_cpu_pwr_on_common().

BUG=b:244215539
TEST=Suspend Resume Test pass

Change-Id: Id752c1ccbb9eab277ed6278c2dd90a051a894146
Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com>
2022-11-14 09:55:07 +08:00
Allen-KH Cheng
600f168172 fix(mt8186): fix the DRAM voltage after the system resumes
The DRAM power supply must sustain at 0.8V after the system resumes.
Otherwise, unexpected errors would occur. Therefore, we update the
DRAM voltage to 0.8v in PMIC voltage wrap table.

BUG=b:253537849
TEST=Suspend Resume Test

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.corp-partner.google.com>
Change-Id: Idd42d5a2d646468822e391e48d01d870c3b7f0d3
2022-11-14 09:55:07 +08:00
Trevor Wu
c70f567ad7 feat(mt8188): add audio support
For MT8188, MTK_AUDIO_SMC_OP_DOMAIN_SIDEBANDS is required for normal
mode switch.
  - Add audio common code and chip specific code.
  - Add new id (MTK_SIP_AUDIO_CONTROL) to mtk_sip_def.h.
  - Enable for MT8188.

Signed-off-by: Trevor Wu <trevor.wu@mediatek.com>
Change-Id: Iff4680cd0b520b2b519ecf30ecafe100f147cc62
2022-11-14 09:55:07 +08:00
Liju-Clr Chen
f278d84ded refactor(mt8195): use ptp3 common drivers
Some 8195 ptp3 drivers are the same in plat/mediatek/drivers/ptp3, so
add this patch to reuse them.

Change-Id: I2b1801a73b6a2979e20d49d314c57f663dc5bf04
Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com>
2022-11-14 09:55:07 +08:00
Riven Chen
44a10511c9 feat(mt8188): add support for PTP3
Add PTP3 driver to protect CPU from excessive voltage drop in CPU
heavy loading.

Signed-off-by: Riven Chen <riven.chen@mediatek.corp-partner.google.com>
Change-Id: I394096be43e1d1d615f99b22f38f0b3ae0bb40c1
2022-11-14 09:55:07 +08:00
Rex-BC Chen
0b1186a3e6 feat(mt8188): enable MTK_PUBEVENT_ENABLE
Enable MTK_PUBEVENT_ENABLE for subscribing CPUPM events. This
patch also corrects the header file naming.

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Iabd89a4ead21ccafa833390367484bfea5d351f6
2022-11-14 09:55:07 +08:00
Manish V Badarkhe
797d7446a0 Merge "refactor(security): add OpenSSL 1.x compatibility" into integration 2022-11-11 19:59:58 +01:00
Juan Pablo Conde
cf2dd17ddd refactor(security): add OpenSSL 1.x compatibility
When updated to work with OpenSSL 3.0, the host tools lost their
compatibility with previous versions (1.x) of OpenSSL. This is
mainly due to the fact that 1.x APIs became deprecated in 3.0 and
therefore their use cause compiling errors. In addition, updating
for a newer version of OpenSSL meant improving the stability
against security threats. However, although version 1.1.1 is
now deprecated, it still receives security updates, so it would
not imply major security issues to keep compatibility with it too.

This patch adds backwards compatibility with OpenSSL 1.x versions
by adding back 1.x API code. It defines a macro USING_OPENSSL3,
which will select the appropriate OpenSSL API version depending on
the OpenSSL library path chosen (which is determined by the
already-existing OPENSSL_DIR variable).

In addition, cleanup items were packed in functions and moved to
the proper modules in order to make the code more maintainable and
legible.

Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
Change-Id: I8deceb5e419edc73277792861882404790ccd33c
2022-11-11 13:33:42 -05:00
Manish Pandey
7e88791a13 Merge "fix(docs): add LTS maintainers" into integration 2022-11-11 18:40:39 +01:00
Bipin Ravi
20a43156f7 Merge "feat(cpus): make cache ops conditional" into integration 2022-11-11 17:49:20 +01:00
Bipin Ravi
ab0d4d9d44 fix(docs): add LTS maintainers
Adding the  maintainers for the TF-A LTS releases.

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I683885b8b52c0d004218fa52f71a245bd26b1229
2022-11-11 10:08:05 -06:00
Manish Pandey
2f54614630 Merge "fix(pmu): add sensible default for MDCR_EL2" into integration 2022-11-11 16:56:30 +01:00
Manish V Badarkhe
b416d1aaee Merge "build: deprecate Arm TC0 FVP platform" into integration 2022-11-11 14:06:03 +01:00
Boyan Karatotev
7f85619857 fix(pmu): add sensible default for MDCR_EL2
When TF-A is set to save and restore EL2 registers it initially zeroes
all of them so that it does not leak any information. However,
MDCR_EL2.HPMN of 0 is poorly defined when FEAT_HPMN0 is not implemented.
Set it to its hardware reset value so that lower ELs don't inherit a
wrong value.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I8055005ef9b6eaafefa13b62a0b41289079fdd23
2022-11-11 12:14:53 +00:00
Manish V Badarkhe
42c70c08a8 build: deprecate Arm TC0 FVP platform
Arm has decided to deprecate the TC0 platform. The development of
software and fast models for TC0 platform has been discontinued.
TC0 platform has been superseded by the TC1 and TC2 platforms,
which are already supported in TF-A and CI repositories.

Change-Id: I0269816a6ee733f732669027eae4e14cd60b6084
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2022-11-11 09:43:21 +00:00
Bipin Ravi
2b138c6b31 Merge "fix(cpus): workaround for Cortex-A77 erratum 2743100" into integration 2022-11-11 05:35:21 +01:00
Joanna Farley
79bf51c2ff Merge "fix(docs): update maintainers list" into integration 2022-11-11 01:02:44 +01:00
Manish Pandey
f23ce63905 fix(docs): update maintainers list
As part of release process revisit list of maintainers to keep
it updated.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I63b87265a6bff00ad05d8b3b7cad694cdf48e9ea
2022-11-10 19:40:29 +00:00
Manish V Badarkhe
a06c5cad54 Merge "chore(docs): fix broken url references to arm procedure call" into integration 2022-11-10 19:25:01 +01:00
Olivier Deprez
f41e23ea73 Merge changes from topic "mp/ras_refactoring" into integration
* changes:
  docs: document do_panic() and panic() helper functions
  fix(ras): restrict RAS support for NS world
2022-11-10 17:46:21 +01:00
Govindraj Raja
702b46cba3 chore(docs): fix broken url references to arm procedure call
Couple for urls under section: `5.6. Use of built-in C and libc
data types` from docs has broken urls since the new arm procedure
call doc is moved to be part of `ARM-software/abi-aa`.

Change-Id: Ied184ed56c8335d4cbc687e56962439091a18e42
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
2022-11-10 16:24:54 +00:00
Manish Pandey
680b7aa9c0 Merge changes from topic "mp/ras_refactoring" into integration
* changes:
  fix(debug): decouple "get_el_str()" from backtrace
  fix(bl31): harden check in delegate_async_ea
2022-11-10 17:22:39 +01:00
Boyan Karatotev
4fdeaffe86 fix(cpus): workaround for Cortex-A77 erratum 2743100
Cortex-A77 erratum 2743100 is a Cat B erratum that applies to revisions
r0p0, r1p0, r1p1, and is still open. The workaround is to insert a dsb
before the isb in the power down sequence.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1152370/latest

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I8e49a2dac8611f31ace249a17ae7a90cd60e742a
2022-11-10 15:51:16 +00:00
Joanna Farley
7eb6fa4a22 Merge changes from topic "ffa_el3_spmc_fixes" into integration
* changes:
  fix(el3-spmc): check descriptor size for overflow
  fix(el3-spmc): fix location of fragment length check
  fix(el3-spmc): fix detection of overlapping memory regions
  fix(el3-spmc): fix incomplete reclaim validation
2022-11-10 13:46:33 +01:00
Okash Khawaja
04c7303b9c feat(cpus): make cache ops conditional
When a core is in debug recovery mode its caches are not invalidated
upon reset, so the L1 and L2 cache contents from before reset are
observable after reset. Similarly, debug recovery mode of DynamIQ
cluster ensures that contents of the shared L3 cache are also not
invalidated upon transition to On mode.

Booting cores in debug recovery mode means booting with caches disabled
and preserving the caches until a point where software can dump the
caches and retrieve their contents. TF-A however unconditionally cleans
and invalidates caches at multiple points during boot. This can lead to
memory corruption as well as loss of cache contents to be used for
debugging.

This patch fixes this by calling a platform hook before performing CMOs
in helper routines in cache_helpers.S. The platform hook plat_can_cmo is
an assembly routine which must not clobber x2 and x3, and avoid using
stack. The whole checking is conditional upon `CONDITIONAL_CMO` which
can be set at compile time.

Signed-off-by: Okash Khawaja <okash@google.com>
Change-Id: I172e999e4acd0f872c24056e647cc947ee54b193
2022-11-10 12:14:05 +00:00
Manish Pandey
0d41e17400 Merge "chore(docs): move deprecated platforms information around" into integration 2022-11-10 12:59:17 +01:00
Sandrine Bailleux
49e6f94c13 Merge "build: warn about RSS driver experimental status" into integration 2022-11-10 07:46:25 +01:00
Madhukar Pappireddy
c87e1f6228 Merge changes from topic "errata" into integration
* changes:
  fix(cpus): workaround for Cortex-A76 erratum 2743102
  fix(cpus): workaround for Neoverse N1 erratum 2743102
2022-11-09 21:20:24 +01:00
Marc Bonnici
62cd8f3147 fix(el3-spmc): report execution state in partition info get
Ensure that the correct execution state of an SP is reported
as part of an FF-A v1.1 PARTITION_INFO_GET response.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: I714e53ae71c376463797a42cd5ab7a5e9c687fb7
2022-11-09 19:05:14 +00:00
Manish V Badarkhe
00bf236e32 Merge "refactor(trng): cleanup the existing TRNG support" into integration 2022-11-09 17:30:17 +01:00
Joanna Farley
0d231b9bdf Merge "fix(versal-net): add default values for silicon" into integration 2022-11-09 12:49:28 +01:00
Soby Mathew
00c322b30b Merge "docs(rme): add instruction to build rmm" into integration 2022-11-09 12:48:38 +01:00
Joanna Farley
51a96ceeec Merge "docs(security): rename Makalu and SB optimisation" into integration 2022-11-09 12:48:23 +01:00
Joanna Farley
0e5fd0658d Merge "docs(maintainers): update qti maintainer" into integration 2022-11-09 12:38:48 +01:00
Shruti Gupta
99d9ce8a68 docs(rme): add instruction to build rmm
Add documentation to build and run TF-A with RMM,
Linux kernel and TFTF Realm Payload.

Signed-off-by: Shruti Gupta <shruti.gupta@arm.com>
Change-Id: I951b41a144aabe0fec16eb933d7f005a65f06fb2
2022-11-09 09:55:41 +00:00
Manish V Badarkhe
2f3d647b99 Merge "docs: add link to DCO" into integration 2022-11-09 10:43:51 +01:00
Michal Simek
faa22d48d9 fix(versal-net): add default values for silicon
Add missing default value for silicon.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: Iac7d4db17a29a148298e9e3bd3eb3f74cafe7bc1
2022-11-09 15:11:30 +05:30
Sandrine Bailleux
a6a1dcbee6 chore(docs): move deprecated platforms information around
We used to have a dedicated page for deprecated platforms information.
This document contained 2 pieces of information:

 a) the process for deprecating a platform port;
 b) the list of deprecated platforms to this day.

I think it makes more sense to move b) to the platforms ports landing
page, such that it is more visible.

This also has the nice effect to move the 'Deprecated platforms' title
as the last entry of the 'Platform ports' table of contents, like so:

 - Platform ports
   - 1. Allwinner ARMv8 SoCs
   - 2. Arm Development Platforms
     ...
   - 39. Broadcom Stingray
   - Deprecated platforms

instead of it being lost in the middle of supported platform ports.

Regarding a), this gets moved under the "Processes & Policies" section.
More specifically, it gets clubbed with the existing platform
compatibility policy. The combined document gets renamed into a
"Platforms Ports Policy" document.

Change-Id: I6e9ce2abc68b8a8ac88e7bd5f21749c14c9a2af6
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2022-11-09 10:32:59 +01:00
Sandrine Bailleux
e28d403c76 Merge "chore(docs): refresh platform ports landing page" into integration 2022-11-09 10:28:07 +01:00
Manish V Badarkhe
5605c44282 Merge changes from topic "rdn2cfg2_spi_support" into integration
* changes:
  feat(rdn2): enable extended SPI support
  feat(rdn2): add SPI ID ranges for RD-N2 multichip platform
2022-11-09 10:21:56 +01:00
Olivier Deprez
78e7b2b4c1 Merge "feat: pass SMCCCv1.3 SVE hint bit to dispatchers" into integration 2022-11-09 09:04:07 +01:00
Bipin Ravi
b80cd43142 docs(security): rename Makalu and SB optimisation
Changing Makalu reference to the public name Cortex-A715. Also, added
a note on use of SB instruction for all CPUs supporting ENABLE_FEAT_SB.

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I98bd36c684fa7ae79bd4e8e641fd73404435c202
2022-11-08 13:02:49 -06:00