mirror of
https://gitlab.alpinelinux.org/alpine/aports.git
synced 2026-01-06 01:02:26 +01:00
102 lines
3.7 KiB
Diff
102 lines
3.7 KiB
Diff
grsec patch includes <linux/fs.h> which defines READ and WRITE.
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Remove the macro hackery, and use the proper #define names for
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macro invocations so there's no surprises.
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--- linux-4.4/drivers/mtd/spi-nor/fsl-quadspi.c.orig
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+++ linux-4.4/drivers/mtd/spi-nor/fsl-quadspi.c
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@@ -183,8 +183,8 @@
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/* Macros for constructing the LUT register. */
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#define LUT0(ins, pad, opr) \
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- (((opr) << OPRND0_SHIFT) | ((LUT_##pad) << PAD0_SHIFT) | \
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- ((LUT_##ins) << INSTR0_SHIFT))
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+ (((opr) << OPRND0_SHIFT) | ((pad) << PAD0_SHIFT) | \
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+ ((ins) << INSTR0_SHIFT))
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#define LUT1(ins, pad, opr) (LUT0(ins, pad, opr) << OPRND1_SHIFT)
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@@ -364,14 +364,14 @@
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dummy = 8;
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}
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- writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
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+ writel(LUT0(LUT_CMD, LUT_PAD1, cmd) | LUT1(LUT_ADDR, LUT_PAD1, addrlen),
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base + QUADSPI_LUT(lut_base));
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- writel(LUT0(DUMMY, PAD1, dummy) | LUT1(FSL_READ, PAD4, rxfifo),
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+ writel(LUT0(LUT_DUMMY, LUT_PAD1, dummy) | LUT1(LUT_FSL_READ, LUT_PAD4, rxfifo),
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base + QUADSPI_LUT(lut_base + 1));
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/* Write enable */
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lut_base = SEQID_WREN * 4;
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- writel(LUT0(CMD, PAD1, SPINOR_OP_WREN), base + QUADSPI_LUT(lut_base));
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+ writel(LUT0(LUT_CMD, LUT_PAD1, SPINOR_OP_WREN), base + QUADSPI_LUT(lut_base));
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/* Page Program */
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lut_base = SEQID_PP * 4;
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@@ -385,13 +385,13 @@
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addrlen = ADDR32BIT;
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}
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- writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
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+ writel(LUT0(LUT_CMD, LUT_PAD1, cmd) | LUT1(LUT_ADDR, LUT_PAD1, addrlen),
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base + QUADSPI_LUT(lut_base));
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- writel(LUT0(FSL_WRITE, PAD1, 0), base + QUADSPI_LUT(lut_base + 1));
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+ writel(LUT0(LUT_FSL_WRITE, LUT_PAD1, 0), base + QUADSPI_LUT(lut_base + 1));
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/* Read Status */
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lut_base = SEQID_RDSR * 4;
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- writel(LUT0(CMD, PAD1, SPINOR_OP_RDSR) | LUT1(FSL_READ, PAD1, 0x1),
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+ writel(LUT0(LUT_CMD, LUT_PAD1, SPINOR_OP_RDSR) | LUT1(LUT_FSL_READ, LUT_PAD1, 0x1),
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base + QUADSPI_LUT(lut_base));
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/* Erase a sector */
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@@ -400,40 +400,40 @@
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cmd = q->nor[0].erase_opcode;
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addrlen = q->nor_size <= SZ_16M ? ADDR24BIT : ADDR32BIT;
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- writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
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+ writel(LUT0(LUT_CMD, LUT_PAD1, cmd) | LUT1(LUT_ADDR, LUT_PAD1, addrlen),
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base + QUADSPI_LUT(lut_base));
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/* Erase the whole chip */
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lut_base = SEQID_CHIP_ERASE * 4;
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- writel(LUT0(CMD, PAD1, SPINOR_OP_CHIP_ERASE),
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+ writel(LUT0(LUT_CMD, LUT_PAD1, SPINOR_OP_CHIP_ERASE),
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base + QUADSPI_LUT(lut_base));
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/* READ ID */
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lut_base = SEQID_RDID * 4;
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- writel(LUT0(CMD, PAD1, SPINOR_OP_RDID) | LUT1(FSL_READ, PAD1, 0x8),
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+ writel(LUT0(LUT_CMD, LUT_PAD1, SPINOR_OP_RDID) | LUT1(LUT_FSL_READ, LUT_PAD1, 0x8),
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base + QUADSPI_LUT(lut_base));
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/* Write Register */
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lut_base = SEQID_WRSR * 4;
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- writel(LUT0(CMD, PAD1, SPINOR_OP_WRSR) | LUT1(FSL_WRITE, PAD1, 0x2),
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+ writel(LUT0(LUT_CMD, LUT_PAD1, SPINOR_OP_WRSR) | LUT1(LUT_FSL_WRITE, LUT_PAD1, 0x2),
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base + QUADSPI_LUT(lut_base));
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/* Read Configuration Register */
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lut_base = SEQID_RDCR * 4;
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- writel(LUT0(CMD, PAD1, SPINOR_OP_RDCR) | LUT1(FSL_READ, PAD1, 0x1),
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+ writel(LUT0(LUT_CMD, LUT_PAD1, SPINOR_OP_RDCR) | LUT1(LUT_FSL_READ, LUT_PAD1, 0x1),
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base + QUADSPI_LUT(lut_base));
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/* Write disable */
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lut_base = SEQID_WRDI * 4;
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- writel(LUT0(CMD, PAD1, SPINOR_OP_WRDI), base + QUADSPI_LUT(lut_base));
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+ writel(LUT0(LUT_CMD, LUT_PAD1, SPINOR_OP_WRDI), base + QUADSPI_LUT(lut_base));
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/* Enter 4 Byte Mode (Micron) */
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lut_base = SEQID_EN4B * 4;
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- writel(LUT0(CMD, PAD1, SPINOR_OP_EN4B), base + QUADSPI_LUT(lut_base));
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+ writel(LUT0(LUT_CMD, LUT_PAD1, SPINOR_OP_EN4B), base + QUADSPI_LUT(lut_base));
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/* Enter 4 Byte Mode (Spansion) */
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lut_base = SEQID_BRWR * 4;
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- writel(LUT0(CMD, PAD1, SPINOR_OP_BRWR), base + QUADSPI_LUT(lut_base));
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+ writel(LUT0(LUT_CMD, LUT_PAD1, SPINOR_OP_BRWR), base + QUADSPI_LUT(lut_base));
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fsl_qspi_lock_lut(q);
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}
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