mirror of
https://source.denx.de/u-boot/u-boot.git
synced 2025-08-21 06:31:22 +02:00
e12337915c
The header file is not necessary in either of those files, remove it as common.h is going away. Include missing asm/arch/rmobile.h in board/renesas/rcar-common/v3-common.c to prevent build failure of r8a77970_eagle r8a779a0_falcon r8a77980_v3hsk and r8a77970_v3msk . Include missing asm/u-boot.h in falcon.c and grpeach.c to fix build failure due to missing definition of struct bd_info . Include errno.h in grpeach.c to fix build error due to missing definition of EINVAL. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
42 lines
922 B
C
42 lines
922 B
C
// SPDX-License-Identifier: GPL-2.0+
|
|
/*
|
|
* Copyright (C) 2017-2023 Marek Vasut <marek.vasut+renesas@mailbox.org>
|
|
*/
|
|
|
|
#include <clock_legacy.h>
|
|
#include <asm/arch/rmobile.h>
|
|
#include <asm/io.h>
|
|
|
|
#define CPGWPR 0xE6150900
|
|
#define CPGWPCR 0xE6150904
|
|
|
|
/* PLL */
|
|
#define PLL0CR 0xE61500D8
|
|
#define PLL0_STC_MASK 0x7F000000
|
|
#define PLL0_STC_OFFSET 24
|
|
|
|
#define CLK2MHZ(clk) (clk / 1000 / 1000)
|
|
void s_init(void)
|
|
{
|
|
struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
|
|
struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
|
|
u32 stc;
|
|
|
|
/* Watchdog init */
|
|
writel(0xA5A5A500, &rwdt->rwtcsra);
|
|
writel(0xA5A5A500, &swdt->swtcsra);
|
|
|
|
/* CPU frequency setting. Set to 0.8GHz */
|
|
stc = ((800 / CLK2MHZ(get_board_sys_clk())) - 1) << PLL0_STC_OFFSET;
|
|
clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
|
|
}
|
|
|
|
int board_early_init_f(void)
|
|
{
|
|
/* Unlock CPG access */
|
|
writel(0xA5A5FFFF, CPGWPR);
|
|
writel(0x5A5A0000, CPGWPCR);
|
|
|
|
return 0;
|
|
}
|