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abb086efd5
To return a 64-bit Allwinner chip back to the 32-bit BootROM code, we have some embedded AArch32 code that restores the CPU state, before branching back to the BootROM. At the moment the pointer to the buffer with that state is located *after* the code, which makes the PC relative code fragile: adding or removing instructions will change the distance to that pointer variable. The "new" Allwinner A523 SoC requires more state to be restored (GICv3 system registers), but we must do that *only* on that SoC. Conditional compilation sounds like the easiest solution, but would mean that the distance to that pointer would change. Solve this rather easily by moving the pointer to the *front* of the code: we load that pointer in the first instruction, so the distance would always stay the same. Later in the code we won't need PC relative addressing anymore, so this code can grow or shrink easily, for instance due to conditional compilation. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> |
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| .. | ||
| bcmns3 | ||
| fsl-layerscape | ||
| hisilicon | ||
| xen | ||
| acpi_park_v8.S | ||
| cache_v8.c | ||
| cache.S | ||
| config.mk | ||
| cpu-dt.c | ||
| cpu.c | ||
| exception_level.c | ||
| exceptions.S | ||
| fel_utils.S | ||
| fwcall.c | ||
| generic_timer.c | ||
| Kconfig | ||
| linux-kernel-image-header-vars.h | ||
| Makefile | ||
| psci.S | ||
| sec_firmware_asm.S | ||
| sec_firmware.c | ||
| sha1_ce_core.S | ||
| sha1_ce_glue.c | ||
| sha256_ce_core.S | ||
| sha256_ce_glue.c | ||
| smccc-call.S | ||
| spin_table_v8.S | ||
| spin_table.c | ||
| spl_data.c | ||
| start.S | ||
| sysinfo.c | ||
| tlb.S | ||
| transition.S | ||
| u-boot-spl.lds | ||
| u-boot.lds | ||