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40 lines
966 B
C
40 lines
966 B
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
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*/
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#ifndef __ASM_ARC_CACHE_H
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#define __ASM_ARC_CACHE_H
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#include <config.h>
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/*
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* As of today we may handle any L1 cache line length right in software.
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* For that essentially cache line length is a variable not constant.
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* And to satisfy users of ARCH_DMA_MINALIGN we just use largest line length
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* that may exist in either L1 or L2 (AKA SLC) caches on ARC.
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*/
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#define ARCH_DMA_MINALIGN 128
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#ifndef __ASSEMBLY__
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void cache_init(void);
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void flush_n_invalidate_dcache_all(void);
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void sync_n_cleanup_cache_all(void);
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static const inline int is_ioc_enabled(void)
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{
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return IS_ENABLED(CONFIG_ARC_DBG_IOC_ENABLE);
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}
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/*
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* We export SLC control functions to use them in platform configuration code.
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* They maust not be used in any generic code!
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*/
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void slc_enable(void);
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void slc_disable(void);
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#endif /* __ASSEMBLY__ */
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#endif /* __ASM_ARC_CACHE_H */
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