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The SH7753 EVB board has SH7753, 512MB DDR3-SDRAM, SPI ROM, Gigabit Ethernet, and eMMC. This patch support the following functions: - 512MB DDR3-SDRAM, SCIF4, SPI ROM, Gigabit Ethernet, eMMC Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
80 lines
2.2 KiB
C
80 lines
2.2 KiB
C
/*
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* (C) Copyright 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_CPU_SH4_H_
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#define _ASM_CPU_SH4_H_
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/* cache control */
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#define CCR_CACHE_STOP 0x00000808
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#define CCR_CACHE_ENABLE 0x00000101
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#define CCR_CACHE_ICI 0x00000800
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#define CACHE_OC_ADDRESS_ARRAY 0xf4000000
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#if defined (CONFIG_CPU_SH7750) || \
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defined(CONFIG_CPU_SH7751)
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#define CACHE_OC_WAY_SHIFT 14
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#define CACHE_OC_NUM_ENTRIES 512
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#else
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#define CACHE_OC_WAY_SHIFT 13
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#define CACHE_OC_NUM_ENTRIES 256
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#endif
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#define CACHE_OC_ENTRY_SHIFT 5
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#if defined (CONFIG_CPU_SH7750) || \
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defined(CONFIG_CPU_SH7751)
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# include <asm/cpu_sh7750.h>
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#elif defined (CONFIG_CPU_SH7722)
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# include <asm/cpu_sh7722.h>
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#elif defined (CONFIG_CPU_SH7723)
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# include <asm/cpu_sh7723.h>
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#elif defined (CONFIG_CPU_SH7724)
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# include <asm/cpu_sh7724.h>
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#elif defined (CONFIG_CPU_SH7734)
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# include <asm/cpu_sh7734.h>
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#elif defined (CONFIG_CPU_SH7752)
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# include <asm/cpu_sh7752.h>
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#elif defined (CONFIG_CPU_SH7753)
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# include <asm/cpu_sh7753.h>
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#elif defined (CONFIG_CPU_SH7757)
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# include <asm/cpu_sh7757.h>
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#elif defined (CONFIG_CPU_SH7763)
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# include <asm/cpu_sh7763.h>
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#elif defined (CONFIG_CPU_SH7780)
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# include <asm/cpu_sh7780.h>
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#elif defined (CONFIG_CPU_SH7785)
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# include <asm/cpu_sh7785.h>
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#else
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# error "Unknown SH4 variant"
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#endif
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#if defined(CONFIG_SH_32BIT)
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#define PMB_ADDR_ARRAY 0xf6100000
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#define PMB_ADDR_ENTRY 8
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#define PMB_VPN 24
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#define PMB_DATA_ARRAY 0xf7100000
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#define PMB_DATA_ENTRY 8
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#define PMB_PPN 24
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#define PMB_UB 9 /* Buffered write */
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#define PMB_V 8 /* Valid */
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#define PMB_SZ1 7 /* Page size (upper bit) */
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#define PMB_SZ0 4 /* Page size (lower bit) */
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#define PMB_C 3 /* Cacheability */
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#define PMB_WT 0 /* Write-through */
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#define PMB_ADDR_BASE(entry) (PMB_ADDR_ARRAY + (entry << PMB_ADDR_ENTRY))
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#define PMB_DATA_BASE(entry) (PMB_DATA_ARRAY + (entry << PMB_DATA_ENTRY))
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#define mk_pmb_addr_val(vpn) ((vpn << PMB_VPN))
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#define mk_pmb_data_val(ppn, ub, v, sz1, sz0, c, wt) \
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((ppn << PMB_PPN) | (ub << PMB_UB) | \
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(v << PMB_V) | (sz1 << PMB_SZ1) | \
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(sz0 << PMB_SZ0) | (c << PMB_C) | \
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(wt << PMB_WT))
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#endif
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#endif /* _ASM_CPU_SH4_H_ */
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