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b45c48a7c3
454179: Stale prediction may inhibit target address misprediction on next predicted taken branch Impacts: Every Cortex-A8 processors with revision lower than r2p1 Work around: Set IBE and disable branch size mispredict to 1 Also provide a hook for SoC specific handling to take place if needed. Based on ARM errata Document revision 20.0 (13 Nov 2010) Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Matt Porter <mporter@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
30 lines
638 B
C
30 lines
638 B
C
/*
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* (C) Copyright 2015 Texas Insturments
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* CP15 specific code
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/system.h>
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#include <asm/cache.h>
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#include <asm/armv7.h>
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#include <linux/compiler.h>
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void __weak v7_arch_cp15_set_l2aux_ctrl(u32 l2actlr, u32 cpu_midr,
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u32 cpu_rev_comb, u32 cpu_variant,
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u32 cpu_rev)
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{
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asm volatile ("mcr p15, 1, %0, c15, c0, 0\n\t" : : "r"(l2actlr));
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}
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void __weak v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
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u32 cpu_variant, u32 cpu_rev)
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{
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asm volatile ("mcr p15, 0, %0, c1, c0, 1\n\t" : : "r"(acr));
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}
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