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52f69f818c
This change adds initial support for NXP LPC32x0 SoC series. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Acked-by: Marek Vasut <marek.vasut@gmail.com>
75 lines
2.6 KiB
C
75 lines
2.6 KiB
C
/*
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* Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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#ifndef _LPC32XX_TIMER_H
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#define _LPC32XX_TIMER_H
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#include <asm/types.h>
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/* Timer/Counter Registers */
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struct timer_regs {
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u32 ir; /* Interrupt Register */
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u32 tcr; /* Timer Control Register */
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u32 tc; /* Timer Counter */
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u32 pr; /* Prescale Register */
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u32 pc; /* Prescale Counter */
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u32 mcr; /* Match Control Register */
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u32 mr[4]; /* Match Registers */
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u32 ccr; /* Capture Control Register */
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u32 cr[4]; /* Capture Registers */
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u32 emr; /* External Match Register */
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u32 reserved[12];
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u32 ctcr; /* Count Control Register */
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};
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/* Timer/Counter Interrupt Register bits */
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#define TIMER_IR_CR(n) (1 << ((n) + 4))
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#define TIMER_IR_MR(n) (1 << (n))
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/* Timer/Counter Timer Control Register bits */
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#define TIMER_TCR_COUNTER_RESET (1 << 1)
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#define TIMER_TCR_COUNTER_ENABLE (1 << 0)
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#define TIMER_TCR_COUNTER_DISABLE (0 << 0)
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/* Timer/Counter Match Control Register bits */
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#define TIMER_MCR_STOP(n) (1 << (3 * (n) + 2))
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#define TIMER_MCR_RESET(n) (1 << (3 * (n) + 1))
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#define TIMER_MCR_INTERRUPT(n) (1 << (3 * (n)))
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/* Timer/Counter Capture Control Register bits */
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#define TIMER_CCR_INTERRUPT(n) (1 << (3 * (n) + 2))
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#define TIMER_CCR_FALLING_EDGE(n) (1 << (3 * (n) + 1))
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#define TIMER_CCR_RISING_EDGE(n) (1 << (3 * (n)))
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/* Timer/Counter External Match Register bits */
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#define TIMER_EMR_EMC_TOGGLE(n) (0x3 << (2 * (n) + 4))
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#define TIMER_EMR_EMC_SET(n) (0x2 << (2 * (n) + 4))
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#define TIMER_EMR_EMC_CLEAR(n) (0x1 << (2 * (n) + 4))
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#define TIMER_EMR_EMC_NOTHING(n) (0x0 << (2 * (n) + 4))
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#define TIMER_EMR_EM(n) (1 << (n))
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/* Timer/Counter Count Control Register bits */
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#define TIMER_CTCR_INPUT(n) ((n) << 2)
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#define TIMER_CTCR_MODE_COUNTER_BOTH (0x3 << 0)
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#define TIMER_CTCR_MODE_COUNTER_FALLING (0x2 << 0)
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#define TIMER_CTCR_MODE_COUNTER_RISING (0x1 << 0)
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#define TIMER_CTCR_MODE_TIMER (0x0 << 0)
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#endif /* _LPC32XX_TIMER_H */
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