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https://source.denx.de/u-boot/u-boot.git
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16b94903e2
Currently mach-mt7620 contains only support for mt7628. To avoid confusion, rename mach-mt7620 to mach-mtmips, which means MediaTek MIPS platforms. MT7620 and MT7628 should be distinguished by SOC_MT7620 and SOC_MT7628 because they do not share the same lowlevel codes. Dependencies of four drivers are changed to SOC_MT7628 as these drivers are only used by MT7628. Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
329 lines
6.0 KiB
ArmAsm
329 lines
6.0 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (c) 2018 Stefan Roese <sr@denx.de>
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*
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* This code is mostly based on the code extracted from this MediaTek
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* github repository:
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*
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* https://github.com/MediaTek-Labs/linkit-smart-uboot.git
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*
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* I was not able to find a specific license or other developers
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* copyrights here, so I can't add them here.
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*/
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#include <config.h>
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#include <asm/regdef.h>
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#include <asm/mipsregs.h>
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#include <asm/addrspace.h>
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#include <asm/asm.h>
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#include "mt76xx.h"
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#ifndef BIT
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#define BIT(nr) (1 << (nr))
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#endif
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#define DELAY_USEC(us) ((us) / 100)
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#define DDR_CFG1_CHIP_WIDTH_MASK (0x3 << 16)
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#define DDR_CFG1_BUS_WIDTH_MASK (0x3 << 12)
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#if defined(CONFIG_ONBOARD_DDR2_SIZE_256MBIT)
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#define DDR_CFG1_SIZE_VAL 0x222e2323
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#define DDR_CFG4_SIZE_VAL 7
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#endif
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#if defined(CONFIG_ONBOARD_DDR2_SIZE_512MBIT)
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#define DDR_CFG1_SIZE_VAL 0x22322323
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#define DDR_CFG4_SIZE_VAL 9
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#endif
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#if defined(CONFIG_ONBOARD_DDR2_SIZE_1024MBIT)
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#define DDR_CFG1_SIZE_VAL 0x22362323
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#define DDR_CFG4_SIZE_VAL 9
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#endif
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#if defined(CONFIG_ONBOARD_DDR2_SIZE_2048MBIT)
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#define DDR_CFG1_SIZE_VAL 0x223a2323
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#define DDR_CFG4_SIZE_VAL 9
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#endif
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#if defined(CONFIG_ONBOARD_DDR2_CHIP_WIDTH_8BIT)
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#define DDR_CFG1_CHIP_WIDTH_VAL (0x1 << 16)
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#endif
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#if defined(CONFIG_ONBOARD_DDR2_CHIP_WIDTH_16BIT)
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#define DDR_CFG1_CHIP_WIDTH_VAL (0x2 << 16)
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#endif
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#if defined(CONFIG_ONBOARD_DDR2_BUS_WIDTH_16BIT)
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#define DDR_CFG1_BUS_WIDTH_VAL (0x2 << 12)
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#endif
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#if defined(CONFIG_ONBOARD_DDR2_BUS_WIDTH_32BIT)
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#define DDR_CFG1_BUS_WIDTH_VAL (0x3 << 12)
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#endif
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.set noreorder
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LEAF(lowlevel_init)
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/* Load base addresses as physical addresses for later usage */
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li s0, CKSEG1ADDR(MT76XX_SYSCTL_BASE)
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li s1, CKSEG1ADDR(MT76XX_MEMCTRL_BASE)
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li s2, CKSEG1ADDR(MT76XX_RGCTRL_BASE)
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/* polling CPLL is ready */
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li t1, DELAY_USEC(1000000)
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la t5, MT76XX_ROM_STATUS_REG
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1:
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lw t2, 0(t5)
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andi t2, t2, 0x1
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bnez t2, CPLL_READY
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subu t1, t1, 1
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bgtz t1, 1b
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nop
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la t0, MT76XX_CLKCFG0_REG
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lw t3, 0(t0)
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ori t3, t3, 0x1
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sw t3, 0(t0)
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b CPLL_DONE
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nop
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CPLL_READY:
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la t0, MT76XX_CLKCFG0_REG
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lw t1, 0(t0)
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li t2, ~0x0c
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and t1, t1, t2
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ori t1, t1, 0xc
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sw t1, 0(t0)
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la t0, MT76XX_DYN_CFG0_REG
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lw t3, 0(t0)
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li t5, ~((0x0f << 8) | (0x0f << 0))
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and t3, t3, t5
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li t5, (10 << 8) | (1 << 0)
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or t3, t3, t5
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sw t3, 0(t0)
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la t0, MT76XX_CLKCFG0_REG
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lw t3, 0(t0)
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li t4, ~0x0F
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and t3, t3, t4
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ori t3, t3, 0xc
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sw t3, 0(t0)
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lw t3, 0(t0)
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ori t3, t3, 0x08
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sw t3, 0(t0)
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CPLL_DONE:
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/* Reset MC */
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lw t2, 0x34(s0)
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ori t2, BIT(10)
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sw t2, 0x34(s0)
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nop
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/*
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* SDR and DDR initialization: delay 200us
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*/
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li t0, DELAY_USEC(200 + 40)
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li t1, 0x1
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1:
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sub t0, t0, t1
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bnez t0, 1b
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nop
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/* set DRAM IO PAD for MT7628IC */
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/* DDR LDO Enable */
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lw t4, 0x100(s2)
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li t2, BIT(31)
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or t4, t4, t2
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sw t4, 0x100(s2)
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lw t4, 0x10c(s2)
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j LDO_1P8V
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nop
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LDO_1P8V:
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li t2, ~BIT(6)
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and t4, t4, t2
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sw t4, 0x10c(s2)
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j DDRLDO_SOFT_START
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LDO_2P5V:
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/* suppose external DDR1 LDO 2.5V */
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li t2, BIT(6)
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or t4, t4, t2
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sw t4, 0x10c(s2)
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DDRLDO_SOFT_START:
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lw t2, 0x10c(s2)
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li t3, BIT(16)
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or t2, t2, t3
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sw t2, 0x10c(s2)
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li t3, DELAY_USEC(250*50)
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LDO_DELAY:
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subu t3, t3, 1
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bnez t3, LDO_DELAY
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nop
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lw t2, 0x10c(s2)
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li t3, BIT(18)
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or t2, t2, t3
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sw t2, 0x10c(s2)
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SET_RG_BUCK_FPWM:
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lw t2, 0x104(s2)
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ori t2, t2, BIT(10)
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sw t2, 0x104(s2)
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DDR_PAD_CFG:
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/* clean CLK PAD */
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lw t2, 0x704(s2)
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li t8, 0xfffff0f0
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and t2, t2, t8
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/* clean CMD PAD */
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lw t3, 0x70c(s2)
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li t8, 0xfffff0f0
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and t3, t3, t8
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/* clean DQ IPAD */
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lw t4, 0x710(s2)
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li t8, 0xfffff8ff
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and t4, t4, t8
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/* clean DQ OPAD */
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lw t5, 0x714(s2)
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li t8, 0xfffff0f0
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and t5, t5, t8
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/* clean DQS IPAD */
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lw t6, 0x718(s2)
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li t8, 0xfffff8ff
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and t6, t6, t8
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/* clean DQS OPAD */
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lw t7, 0x71c(s2)
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li t8, 0xfffff0f0
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and t7, t7, t8
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lw t9, 0xc(s0)
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srl t9, t9, 16
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andi t9, t9, 0x1
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bnez t9, MT7628_AN_DDR1_PAD
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MT7628_KN_PAD:
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li t8, 0x00000303
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or t2, t2, t8
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or t3, t3, t8
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or t5, t5, t8
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or t7, t7, t8
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li t8, 0x00000000
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or t4, t4, t8
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or t6, t6, t8
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j SET_PAD_CFG
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MT7628_AN_DDR1_PAD:
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lw t1, 0x10(s0)
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andi t1, t1, 0x1
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beqz t1, MT7628_AN_DDR2_PAD
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li t8, 0x00000c0c
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or t2, t2, t8
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li t8, 0x00000202
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or t3, t3, t8
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li t8, 0x00000707
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or t5, t5, t8
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li t8, 0x00000c0c
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or t7, t7, t8
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li t8, 0x00000000
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or t4, t4, t8
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or t6, t6, t8
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j SET_PAD_CFG
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MT7628_AN_DDR2_PAD:
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li t8, 0x00000c0c
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or t2, t2, t8
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li t8, 0x00000202
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or t3, t3, t8
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li t8, 0x00000404
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or t5, t5, t8
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li t8, 0x00000c0c
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or t7, t7, t8
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li t8, 0x00000000 /* ODT off */
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or t4, t4, t8
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or t6, t6, t8
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SET_PAD_CFG:
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sw t2, 0x704(s2)
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sw t3, 0x70c(s2)
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sw t4, 0x710(s2)
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sw t5, 0x714(s2)
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sw t6, 0x718(s2)
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sw t7, 0x71c(s2)
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/*
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* DDR initialization: reset pin to 0
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*/
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lw t2, 0x34(s0)
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and t2, ~BIT(10)
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sw t2, 0x34(s0)
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nop
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/*
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* DDR initialization: wait til reg DDR_CFG1 bit 21 equal to 1 (ready)
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*/
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DDR_READY:
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li t1, DDR_CFG1_REG
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lw t0, 0(t1)
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nop
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and t2, t0, BIT(21)
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beqz t2, DDR_READY
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nop
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/*
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* DDR initialization
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*
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* Only DDR2 supported right now. DDR2 support can be added, once
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* boards using it will get added to mainline U-Boot.
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*/
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li t1, DDR_CFG2_REG
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lw t0, 0(t1)
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nop
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and t0, ~BIT(30)
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and t0, ~(7 << 4)
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or t0, (4 << 4)
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or t0, BIT(30)
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or t0, BIT(11)
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sw t0, 0(t1)
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nop
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li t1, DDR_CFG3_REG
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lw t2, 0(t1)
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/* Disable ODT; reference board ok, ev board fail */
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and t2, ~BIT(6)
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or t2, BIT(2)
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li t0, DDR_CFG4_REG
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lw t1, 0(t0)
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li t2, ~(0x01f | 0x0f0)
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and t1, t1, t2
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ori t1, t1, DDR_CFG4_SIZE_VAL
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sw t1, 0(t0)
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nop
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/*
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* DDR initialization: config size and width on reg DDR_CFG1
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*/
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li t6, DDR_CFG1_SIZE_VAL
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and t6, ~DDR_CFG1_CHIP_WIDTH_MASK
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or t6, DDR_CFG1_CHIP_WIDTH_VAL
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/* CONFIG DDR_CFG1[13:12] about TOTAL WIDTH */
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and t6, ~DDR_CFG1_BUS_WIDTH_MASK
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or t6, DDR_CFG1_BUS_WIDTH_VAL
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li t5, DDR_CFG1_REG
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sw t6, 0(t5)
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nop
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/*
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* DDR: enable self auto refresh for power saving
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* enable it by default for both RAM and ROM version (for CoC)
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*/
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lw t1, 0x14(s1)
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nop
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and t1, 0xff000000
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or t1, 0x01
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sw t1, 0x14(s1)
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nop
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lw t1, 0x10(s1)
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nop
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or t1, 0x10
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sw t1, 0x10(s1)
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nop
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jr ra
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nop
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END(lowlevel_init)
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