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46203baf66
Caches should be configured to mode CONF_CM_CACHABLE_NONCOHERENT (or CONF_CM_CACHABLE_COW when a CM is available). There is no need to make this configurable. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
430 lines
11 KiB
ArmAsm
430 lines
11 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Cache-handling routined for MIPS CPUs
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*
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* Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
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*/
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#include <asm-offsets.h>
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#include <config.h>
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#include <asm/asm.h>
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#include <asm/regdef.h>
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#include <asm/mipsregs.h>
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#include <asm/addrspace.h>
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#include <asm/cacheops.h>
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#include <asm/cm.h>
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.macro f_fill64 dst, offset, val
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LONG_S \val, (\offset + 0 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 1 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 2 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 3 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 4 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 5 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 6 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 7 * LONGSIZE)(\dst)
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#if LONGSIZE == 4
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LONG_S \val, (\offset + 8 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 9 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 10 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 11 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 12 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 13 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 14 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 15 * LONGSIZE)(\dst)
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#endif
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.endm
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.macro cache_loop curr, end, line_sz, op
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10: cache \op, 0(\curr)
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PTR_ADDU \curr, \curr, \line_sz
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bne \curr, \end, 10b
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.endm
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.macro l1_info sz, line_sz, off
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.set push
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.set noat
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mfc0 $1, CP0_CONFIG, 1
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/* detect line size */
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srl \line_sz, $1, \off + MIPS_CONF1_DL_SHF - MIPS_CONF1_DA_SHF
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andi \line_sz, \line_sz, (MIPS_CONF1_DL >> MIPS_CONF1_DL_SHF)
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move \sz, zero
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beqz \line_sz, 10f
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li \sz, 2
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sllv \line_sz, \sz, \line_sz
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/* detect associativity */
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srl \sz, $1, \off + MIPS_CONF1_DA_SHF - MIPS_CONF1_DA_SHF
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andi \sz, \sz, (MIPS_CONF1_DA >> MIPS_CONF1_DA_SHF)
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addiu \sz, \sz, 1
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/* sz *= line_sz */
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mul \sz, \sz, \line_sz
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/* detect log32(sets) */
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srl $1, $1, \off + MIPS_CONF1_DS_SHF - MIPS_CONF1_DA_SHF
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andi $1, $1, (MIPS_CONF1_DS >> MIPS_CONF1_DS_SHF)
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addiu $1, $1, 1
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andi $1, $1, 0x7
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/* sz <<= log32(sets) */
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sllv \sz, \sz, $1
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/* sz *= 32 */
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li $1, 32
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mul \sz, \sz, $1
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10:
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.set pop
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.endm
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/*
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* mips_cache_reset - low level initialisation of the primary caches
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*
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* This routine initialises the primary caches to ensure that they have good
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* parity. It must be called by the ROM before any cached locations are used
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* to prevent the possibility of data with bad parity being written to memory.
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*
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* To initialise the instruction cache it is essential that a source of data
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* with good parity is available. This routine will initialise an area of
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* memory starting at location zero to be used as a source of parity.
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*
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* Note that this function does not follow the standard calling convention &
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* may clobber typically callee-saved registers.
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*
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* RETURNS: N/A
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*
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*/
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#define R_RETURN s0
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#define R_IC_SIZE s1
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#define R_IC_LINE s2
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#define R_DC_SIZE s3
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#define R_DC_LINE s4
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#define R_L2_SIZE s5
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#define R_L2_LINE s6
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#define R_L2_BYPASSED s7
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#define R_L2_L2C t8
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LEAF(mips_cache_reset)
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move R_RETURN, ra
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#ifdef CONFIG_MIPS_L2_CACHE
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/*
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* For there to be an L2 present, Config2 must be present. If it isn't
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* then we proceed knowing there's no L2 cache.
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*/
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move R_L2_SIZE, zero
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move R_L2_LINE, zero
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move R_L2_BYPASSED, zero
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move R_L2_L2C, zero
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mfc0 t0, CP0_CONFIG, 1
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bgez t0, l2_probe_done
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/*
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* From MIPSr6 onwards the L2 cache configuration might not be reported
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* by Config2. The Config5.L2C bit indicates whether this is the case,
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* and if it is then we need knowledge of where else to look. For cores
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* from Imagination Technologies this is a CM GCR.
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*/
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# if __mips_isa_rev >= 6
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/* Check that Config5 exists */
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mfc0 t0, CP0_CONFIG, 2
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bgez t0, l2_probe_cop0
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mfc0 t0, CP0_CONFIG, 3
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bgez t0, l2_probe_cop0
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mfc0 t0, CP0_CONFIG, 4
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bgez t0, l2_probe_cop0
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/* Check Config5.L2C is set */
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mfc0 t0, CP0_CONFIG, 5
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and R_L2_L2C, t0, MIPS_CONF5_L2C
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beqz R_L2_L2C, l2_probe_cop0
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/* Config5.L2C is set */
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# ifdef CONFIG_MIPS_CM
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/* The CM will provide L2 configuration */
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PTR_LI t0, CKSEG1ADDR(CONFIG_MIPS_CM_BASE)
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lw t1, GCR_L2_CONFIG(t0)
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bgez t1, l2_probe_done
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ext R_L2_LINE, t1, \
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GCR_L2_CONFIG_LINESZ_SHIFT, GCR_L2_CONFIG_LINESZ_BITS
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beqz R_L2_LINE, l2_probe_done
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li t2, 2
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sllv R_L2_LINE, t2, R_L2_LINE
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ext t2, t1, GCR_L2_CONFIG_ASSOC_SHIFT, GCR_L2_CONFIG_ASSOC_BITS
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addiu t2, t2, 1
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mul R_L2_SIZE, R_L2_LINE, t2
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ext t2, t1, GCR_L2_CONFIG_SETSZ_SHIFT, GCR_L2_CONFIG_SETSZ_BITS
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sllv R_L2_SIZE, R_L2_SIZE, t2
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li t2, 64
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mul R_L2_SIZE, R_L2_SIZE, t2
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/* Bypass the L2 cache so that we can init the L1s early */
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or t1, t1, GCR_L2_CONFIG_BYPASS
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sw t1, GCR_L2_CONFIG(t0)
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sync
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li R_L2_BYPASSED, 1
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/* Zero the L2 tag registers */
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sw zero, GCR_L2_TAG_ADDR(t0)
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sw zero, GCR_L2_TAG_ADDR_UPPER(t0)
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sw zero, GCR_L2_TAG_STATE(t0)
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sw zero, GCR_L2_TAG_STATE_UPPER(t0)
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sw zero, GCR_L2_DATA(t0)
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sw zero, GCR_L2_DATA_UPPER(t0)
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sync
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# else
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/* We don't know how to retrieve L2 configuration on this system */
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# endif
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b l2_probe_done
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# endif
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/*
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* For pre-r6 systems, or r6 systems with Config5.L2C==0, probe the L2
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* cache configuration from the cop0 Config2 register.
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*/
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l2_probe_cop0:
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mfc0 t0, CP0_CONFIG, 2
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srl R_L2_LINE, t0, MIPS_CONF2_SL_SHF
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andi R_L2_LINE, R_L2_LINE, MIPS_CONF2_SL >> MIPS_CONF2_SL_SHF
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beqz R_L2_LINE, l2_probe_done
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li t1, 2
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sllv R_L2_LINE, t1, R_L2_LINE
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srl t1, t0, MIPS_CONF2_SA_SHF
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andi t1, t1, MIPS_CONF2_SA >> MIPS_CONF2_SA_SHF
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addiu t1, t1, 1
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mul R_L2_SIZE, R_L2_LINE, t1
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srl t1, t0, MIPS_CONF2_SS_SHF
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andi t1, t1, MIPS_CONF2_SS >> MIPS_CONF2_SS_SHF
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sllv R_L2_SIZE, R_L2_SIZE, t1
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li t1, 64
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mul R_L2_SIZE, R_L2_SIZE, t1
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/* Attempt to bypass the L2 so that we can init the L1s early */
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or t0, t0, MIPS_CONF2_L2B
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mtc0 t0, CP0_CONFIG, 2
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ehb
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mfc0 t0, CP0_CONFIG, 2
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and R_L2_BYPASSED, t0, MIPS_CONF2_L2B
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/* Zero the L2 tag registers */
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mtc0 zero, CP0_TAGLO, 4
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ehb
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l2_probe_done:
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#endif
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#ifndef CONFIG_SYS_CACHE_SIZE_AUTO
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li R_IC_SIZE, CONFIG_SYS_ICACHE_SIZE
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li R_IC_LINE, CONFIG_SYS_ICACHE_LINE_SIZE
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#else
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l1_info R_IC_SIZE, R_IC_LINE, MIPS_CONF1_IA_SHF
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#endif
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#ifndef CONFIG_SYS_CACHE_SIZE_AUTO
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li R_DC_SIZE, CONFIG_SYS_DCACHE_SIZE
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li R_DC_LINE, CONFIG_SYS_DCACHE_LINE_SIZE
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#else
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l1_info R_DC_SIZE, R_DC_LINE, MIPS_CONF1_DA_SHF
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#endif
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#ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
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/* Determine the largest L1 cache size */
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#ifndef CONFIG_SYS_CACHE_SIZE_AUTO
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#if CONFIG_SYS_ICACHE_SIZE > CONFIG_SYS_DCACHE_SIZE
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li v0, CONFIG_SYS_ICACHE_SIZE
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#else
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li v0, CONFIG_SYS_DCACHE_SIZE
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#endif
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#else
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move v0, R_IC_SIZE
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sltu t1, R_IC_SIZE, R_DC_SIZE
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movn v0, R_DC_SIZE, t1
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#endif
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/*
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* Now clear that much memory starting from zero.
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*/
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PTR_LI a0, CKSEG1ADDR(CONFIG_MIPS_CACHE_INDEX_BASE)
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PTR_ADDU a1, a0, v0
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2: PTR_ADDIU a0, 64
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f_fill64 a0, -64, zero
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bne a0, a1, 2b
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#endif /* CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD */
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#ifdef CONFIG_MIPS_L2_CACHE
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/*
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* If the L2 is bypassed, init the L1 first so that we can execute the
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* rest of the cache initialisation using the L1 instruction cache.
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*/
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bnez R_L2_BYPASSED, l1_init
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l2_init:
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PTR_LI t0, CKSEG0ADDR(CONFIG_MIPS_CACHE_INDEX_BASE)
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PTR_ADDU t1, t0, R_L2_SIZE
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1: cache INDEX_STORE_TAG_SD, 0(t0)
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PTR_ADDU t0, t0, R_L2_LINE
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bne t0, t1, 1b
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/*
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* If the L2 was bypassed then we already initialised the L1s before
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* the L2, so we are now done.
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*/
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bnez R_L2_BYPASSED, l2_unbypass
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#endif
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/*
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* The TagLo registers used depend upon the CPU implementation, but the
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* architecture requires that it is safe for software to write to both
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* TagLo selects 0 & 2 covering supported cases.
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*/
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l1_init:
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mtc0 zero, CP0_TAGLO
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mtc0 zero, CP0_TAGLO, 2
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ehb
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/*
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* The caches are probably in an indeterminate state, so we force good
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* parity into them by doing an invalidate for each line. If
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* CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD is set then we'll proceed to
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* perform a load/fill & a further invalidate for each line, assuming
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* that the bottom of RAM (having just been cleared) will generate good
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* parity for the cache.
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*/
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/*
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* Initialize the I-cache first,
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*/
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blez R_IC_SIZE, 1f
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PTR_LI t0, CKSEG0ADDR(CONFIG_MIPS_CACHE_INDEX_BASE)
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PTR_ADDU t1, t0, R_IC_SIZE
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/* clear tag to invalidate */
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cache_loop t0, t1, R_IC_LINE, INDEX_STORE_TAG_I
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#ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
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/* fill once, so data field parity is correct */
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PTR_LI t0, CKSEG0ADDR(CONFIG_MIPS_CACHE_INDEX_BASE)
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cache_loop t0, t1, R_IC_LINE, FILL
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/* invalidate again - prudent but not strictly neccessary */
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PTR_LI t0, CKSEG0ADDR(CONFIG_MIPS_CACHE_INDEX_BASE)
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cache_loop t0, t1, R_IC_LINE, INDEX_STORE_TAG_I
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#endif
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sync
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/*
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* Enable use of the I-cache by setting Config.K0. The code for this
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* must be executed from KSEG1. Jump from KSEG0 to KSEG1 to do this.
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* Jump back to KSEG0 after caches are enabled and insert an
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* instruction hazard barrier.
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*/
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PTR_LA t0, change_k0_cca
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li t1, CPHYSADDR(~0)
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and t0, t0, t1
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PTR_LI t1, CKSEG1
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or t0, t0, t1
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li a0, CONF_CM_CACHABLE_NONCOHERENT
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jalr.hb t0
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/*
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* then initialize D-cache.
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*/
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1: blez R_DC_SIZE, 3f
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PTR_LI t0, CKSEG0ADDR(CONFIG_MIPS_CACHE_INDEX_BASE)
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PTR_ADDU t1, t0, R_DC_SIZE
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/* clear all tags */
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cache_loop t0, t1, R_DC_LINE, INDEX_STORE_TAG_D
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#ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
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/* load from each line (in cached space) */
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PTR_LI t0, CKSEG0ADDR(CONFIG_MIPS_CACHE_INDEX_BASE)
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2: LONG_L zero, 0(t0)
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PTR_ADDU t0, R_DC_LINE
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bne t0, t1, 2b
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/* clear all tags */
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PTR_LI t0, CKSEG0ADDR(CONFIG_MIPS_CACHE_INDEX_BASE)
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cache_loop t0, t1, R_DC_LINE, INDEX_STORE_TAG_D
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#endif
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3:
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#ifdef CONFIG_MIPS_L2_CACHE
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/* If the L2 isn't bypassed then we're done */
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beqz R_L2_BYPASSED, return
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/* The L2 is bypassed - go initialise it */
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b l2_init
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l2_unbypass:
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# if __mips_isa_rev >= 6
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beqz R_L2_L2C, 1f
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li t0, CKSEG1ADDR(CONFIG_MIPS_CM_BASE)
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lw t1, GCR_L2_CONFIG(t0)
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xor t1, t1, GCR_L2_CONFIG_BYPASS
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sw t1, GCR_L2_CONFIG(t0)
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sync
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ehb
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b 2f
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# endif
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1: mfc0 t0, CP0_CONFIG, 2
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xor t0, t0, MIPS_CONF2_L2B
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mtc0 t0, CP0_CONFIG, 2
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ehb
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2:
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# ifdef CONFIG_MIPS_CM
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/* Config3 must exist for a CM to be present */
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mfc0 t0, CP0_CONFIG, 1
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bgez t0, 2f
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mfc0 t0, CP0_CONFIG, 2
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bgez t0, 2f
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/* Check Config3.CMGCR to determine CM presence */
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mfc0 t0, CP0_CONFIG, 3
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and t0, t0, MIPS_CONF3_CMGCR
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beqz t0, 2f
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/* Change Config.K0 to a coherent CCA */
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PTR_LA t0, change_k0_cca
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li a0, CONF_CM_CACHABLE_COW
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jalr t0
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/*
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* Join the coherent domain such that the caches of this core are kept
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* coherent with those of other cores.
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*/
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PTR_LI t0, CKSEG1ADDR(CONFIG_MIPS_CM_BASE)
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lw t1, GCR_REV(t0)
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li t2, GCR_REV_CM3
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li t3, GCR_Cx_COHERENCE_EN
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bge t1, t2, 1f
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li t3, GCR_Cx_COHERENCE_DOM_EN
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1: sw t3, GCR_Cx_COHERENCE(t0)
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ehb
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2:
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# endif
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#endif
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return:
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/* Ensure all cache operations complete before returning */
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sync
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jr R_RETURN
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END(mips_cache_reset)
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LEAF(change_k0_cca)
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mfc0 t0, CP0_CONFIG
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#if __mips_isa_rev >= 2
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ins t0, a0, 0, 3
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#else
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xor a0, a0, t0
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andi a0, a0, CONF_CM_CMASK
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xor a0, a0, t0
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#endif
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mtc0 a0, CP0_CONFIG
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jr.hb ra
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END(change_k0_cca)
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