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bbed056e55
Provides initial support for TI OMAP-L1x/DA8xx SoC devices. See http://www.ti.com The DA8xx devices are similar to DaVinci devices but have a differing memory map and updated peripheral versions. Signed-off-by: Nick Thompson <nick.thompson@gefanuc.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
447 lines
13 KiB
C
447 lines
13 KiB
C
/*
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* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
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*
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* Based on:
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*
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* -------------------------------------------------------------------------
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*
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* linux/include/asm-arm/arch-davinci/hardware.h
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*
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* Copyright (C) 2006 Texas Instruments.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*/
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#ifndef __ASM_ARCH_HARDWARE_H
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#define __ASM_ARCH_HARDWARE_H
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#include <config.h>
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#include <asm/sizes.h>
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#define REG(addr) (*(volatile unsigned int *)(addr))
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#define REG_P(addr) ((volatile unsigned int *)(addr))
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typedef volatile unsigned int dv_reg;
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typedef volatile unsigned int * dv_reg_p;
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/*
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* Base register addresses
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*
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* NOTE: some of these DM6446-specific addresses DO NOT WORK
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* on other DaVinci chips. Double check them before you try
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* using the addresses ... or PSC module identifiers, etc.
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*/
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#ifndef CONFIG_SOC_DA8XX
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#define DAVINCI_DMA_3PCC_BASE (0x01c00000)
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#define DAVINCI_DMA_3PTC0_BASE (0x01c10000)
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#define DAVINCI_DMA_3PTC1_BASE (0x01c10400)
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#define DAVINCI_UART0_BASE (0x01c20000)
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#define DAVINCI_UART1_BASE (0x01c20400)
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#define DAVINCI_I2C_BASE (0x01c21000)
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#define DAVINCI_TIMER0_BASE (0x01c21400)
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#define DAVINCI_TIMER1_BASE (0x01c21800)
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#define DAVINCI_WDOG_BASE (0x01c21c00)
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#define DAVINCI_PWM0_BASE (0x01c22000)
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#define DAVINCI_PWM1_BASE (0x01c22400)
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#define DAVINCI_PWM2_BASE (0x01c22800)
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#define DAVINCI_SYSTEM_MODULE_BASE (0x01c40000)
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#define DAVINCI_PLL_CNTRL0_BASE (0x01c40800)
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#define DAVINCI_PLL_CNTRL1_BASE (0x01c40c00)
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#define DAVINCI_PWR_SLEEP_CNTRL_BASE (0x01c41000)
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#define DAVINCI_ARM_INTC_BASE (0x01c48000)
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#define DAVINCI_USB_OTG_BASE (0x01c64000)
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#define DAVINCI_CFC_ATA_BASE (0x01c66000)
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#define DAVINCI_SPI_BASE (0x01c66800)
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#define DAVINCI_GPIO_BASE (0x01c67000)
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#define DAVINCI_VPSS_REGS_BASE (0x01c70000)
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#if !defined(CONFIG_SOC_DM646X)
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#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE (0x02000000)
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#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE (0x04000000)
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#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE (0x06000000)
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#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x08000000)
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#endif
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#define DAVINCI_DDR_BASE (0x80000000)
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#ifdef CONFIG_SOC_DM644X
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#define DAVINCI_UART2_BASE 0x01c20800
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#define DAVINCI_UHPI_BASE 0x01c67800
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#define DAVINCI_EMAC_CNTRL_REGS_BASE 0x01c80000
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#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE 0x01c81000
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#define DAVINCI_EMAC_WRAPPER_RAM_BASE 0x01c82000
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#define DAVINCI_MDIO_CNTRL_REGS_BASE 0x01c84000
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#define DAVINCI_IMCOP_BASE 0x01cc0000
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#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01e00000
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#define DAVINCI_VLYNQ_BASE 0x01e01000
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#define DAVINCI_ASP_BASE 0x01e02000
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#define DAVINCI_MMC_SD_BASE 0x01e10000
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#define DAVINCI_MS_BASE 0x01e20000
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#define DAVINCI_VLYNQ_REMOTE_BASE 0x0c000000
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#elif defined(CONFIG_SOC_DM355)
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#define DAVINCI_MMC_SD1_BASE 0x01e00000
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#define DAVINCI_ASP0_BASE 0x01e02000
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#define DAVINCI_ASP1_BASE 0x01e04000
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#define DAVINCI_UART2_BASE 0x01e06000
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#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01e10000
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#define DAVINCI_MMC_SD0_BASE 0x01e11000
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#elif defined(CONFIG_SOC_DM365)
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#define DAVINCI_MMC_SD1_BASE 0x01d00000
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#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01d10000
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#define DAVINCI_MMC_SD0_BASE 0x01d11000
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#elif defined(CONFIG_SOC_DM646X)
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#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x20008000
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#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x42000000
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#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE 0x44000000
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#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x46000000
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#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 0x48000000
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#endif
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#else /* CONFIG_SOC_DA8XX */
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#define DAVINCI_UART0_BASE 0x01c42000
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#define DAVINCI_UART1_BASE 0x01d0c000
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#define DAVINCI_UART2_BASE 0x01d0d000
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#define DAVINCI_I2C0_BASE 0x01c22000
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#define DAVINCI_I2C1_BASE 0x01e28000
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#define DAVINCI_TIMER0_BASE 0x01c20000
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#define DAVINCI_TIMER1_BASE 0x01c21000
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#define DAVINCI_WDOG_BASE 0x01c21000
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#define DAVINCI_PLL_CNTRL0_BASE 0x01c11000
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#define DAVINCI_PSC0_BASE 0x01c10000
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#define DAVINCI_PSC1_BASE 0x01e27000
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#define DAVINCI_SPI0_BASE 0x01c41000
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#define DAVINCI_USB_OTG_BASE 0x01e00000
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#define DAVINCI_SPI1_BASE 0x01e12000
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#define DAVINCI_GPIO_BASE 0x01e26000
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#define DAVINCI_EMAC_CNTRL_REGS_BASE 0x01e23000
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#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE 0x01e22000
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#define DAVINCI_EMAC_WRAPPER_RAM_BASE 0x01e20000
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#define DAVINCI_MDIO_CNTRL_REGS_BASE 0x01e24000
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#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x68000000
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#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x40000000
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#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x60000000
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#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 0x62000000
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#define DAVINCI_ASYNC_EMIF_DATA_CE4_BASE 0x64000000
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#define DAVINCI_ASYNC_EMIF_DATA_CE5_BASE 0x66000000
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#define DAVINCI_DDR_EMIF_CTRL_BASE 0xb0000000
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#define DAVINCI_DDR_EMIF_DATA_BASE 0xc0000000
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#define DAVINCI_INTC_BASE 0xfffee000
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#define DAVINCI_BOOTCFG_BASE 0x01c14000
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#endif /* CONFIG_SOC_DA8XX */
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/* Power and Sleep Controller (PSC) Domains */
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#define DAVINCI_GPSC_ARMDOMAIN 0
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#define DAVINCI_GPSC_DSPDOMAIN 1
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#ifndef CONFIG_SOC_DA8XX
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#define DAVINCI_LPSC_VPSSMSTR 0
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#define DAVINCI_LPSC_VPSSSLV 1
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#define DAVINCI_LPSC_TPCC 2
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#define DAVINCI_LPSC_TPTC0 3
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#define DAVINCI_LPSC_TPTC1 4
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#define DAVINCI_LPSC_EMAC 5
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#define DAVINCI_LPSC_EMAC_WRAPPER 6
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#define DAVINCI_LPSC_MDIO 7
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#define DAVINCI_LPSC_IEEE1394 8
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#define DAVINCI_LPSC_USB 9
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#define DAVINCI_LPSC_ATA 10
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#define DAVINCI_LPSC_VLYNQ 11
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#define DAVINCI_LPSC_UHPI 12
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#define DAVINCI_LPSC_DDR_EMIF 13
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#define DAVINCI_LPSC_AEMIF 14
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#define DAVINCI_LPSC_MMC_SD 15
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#define DAVINCI_LPSC_MEMSTICK 16
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#define DAVINCI_LPSC_McBSP 17
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#define DAVINCI_LPSC_I2C 18
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#define DAVINCI_LPSC_UART0 19
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#define DAVINCI_LPSC_UART1 20
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#define DAVINCI_LPSC_UART2 21
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#define DAVINCI_LPSC_SPI 22
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#define DAVINCI_LPSC_PWM0 23
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#define DAVINCI_LPSC_PWM1 24
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#define DAVINCI_LPSC_PWM2 25
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#define DAVINCI_LPSC_GPIO 26
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#define DAVINCI_LPSC_TIMER0 27
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#define DAVINCI_LPSC_TIMER1 28
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#define DAVINCI_LPSC_TIMER2 29
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#define DAVINCI_LPSC_SYSTEM_SUBSYS 30
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#define DAVINCI_LPSC_ARM 31
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#define DAVINCI_LPSC_SCR2 32
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#define DAVINCI_LPSC_SCR3 33
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#define DAVINCI_LPSC_SCR4 34
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#define DAVINCI_LPSC_CROSSBAR 35
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#define DAVINCI_LPSC_CFG27 36
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#define DAVINCI_LPSC_CFG3 37
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#define DAVINCI_LPSC_CFG5 38
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#define DAVINCI_LPSC_GEM 39
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#define DAVINCI_LPSC_IMCOP 40
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#define DAVINCI_DM646X_LPSC_EMAC 14
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#define DAVINCI_DM646X_LPSC_UART0 26
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#define DAVINCI_DM646X_LPSC_I2C 31
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#else /* CONFIG_SOC_DA8XX */
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enum davinci_lpsc_ids {
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DAVINCI_LPSC_TPCC = 0,
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DAVINCI_LPSC_TPTC0,
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DAVINCI_LPSC_TPTC1,
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DAVINCI_LPSC_AEMIF,
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DAVINCI_LPSC_SPI0,
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DAVINCI_LPSC_MMC_SD,
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DAVINCI_LPSC_AINTC,
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DAVINCI_LPSC_ARM_RAM_ROM,
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DAVINCI_LPSC_SECCTL_KEYMGR,
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DAVINCI_LPSC_UART0,
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DAVINCI_LPSC_SCR0,
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DAVINCI_LPSC_SCR1,
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DAVINCI_LPSC_SCR2,
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DAVINCI_LPSC_DMAX,
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DAVINCI_LPSC_ARM,
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DAVINCI_LPSC_GEM,
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/* for LPSCs in PSC1, offset from 32 for differentiation */
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DAVINCI_LPSC_PSC1_BASE = 32,
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DAVINCI_LPSC_USB11,
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DAVINCI_LPSC_USB20,
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DAVINCI_LPSC_GPIO,
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DAVINCI_LPSC_UHPI,
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DAVINCI_LPSC_EMAC,
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DAVINCI_LPSC_DDR_EMIF,
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DAVINCI_LPSC_McASP0,
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DAVINCI_LPSC_McASP1,
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DAVINCI_LPSC_McASP2,
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DAVINCI_LPSC_SPI1,
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DAVINCI_LPSC_I2C1,
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DAVINCI_LPSC_UART1,
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DAVINCI_LPSC_UART2,
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DAVINCI_LPSC_LCDC,
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DAVINCI_LPSC_ePWM,
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DAVINCI_LPSC_eCAP,
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DAVINCI_LPSC_eQEP,
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DAVINCI_LPSC_SCR_P0,
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DAVINCI_LPSC_SCR_P1,
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DAVINCI_LPSC_CR_P3,
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DAVINCI_LPSC_L3_CBA_RAM
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};
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#endif /* CONFIG_SOC_DA8XX */
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void lpsc_on(unsigned int id);
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void dsp_on(void);
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void davinci_enable_uart0(void);
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void davinci_enable_emac(void);
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void davinci_enable_i2c(void);
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void davinci_errata_workarounds(void);
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#ifndef CONFIG_SOC_DA8XX
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/* Some PSC defines */
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#define PSC_CHP_SHRTSW (0x01c40038)
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#define PSC_GBLCTL (0x01c41010)
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#define PSC_EPCPR (0x01c41070)
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#define PSC_EPCCR (0x01c41078)
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#define PSC_PTCMD (0x01c41120)
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#define PSC_PTSTAT (0x01c41128)
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#define PSC_PDSTAT (0x01c41200)
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#define PSC_PDSTAT1 (0x01c41204)
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#define PSC_PDCTL (0x01c41300)
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#define PSC_PDCTL1 (0x01c41304)
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#define PSC_MDCTL_BASE (0x01c41a00)
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#define PSC_MDSTAT_BASE (0x01c41800)
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#define VDD3P3V_PWDN (0x01c40048)
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#define UART0_PWREMU_MGMT (0x01c20030)
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#define PSC_SILVER_BULLET (0x01c41a20)
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#else /* CONFIG_SOC_DA8XX */
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#define PSC_PSC0_MODULE_ID_CNT 16
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#define PSC_PSC1_MODULE_ID_CNT 32
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struct davinci_psc_regs {
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dv_reg revid;
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dv_reg rsvd0[71];
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dv_reg ptcmd;
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dv_reg rsvd1;
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dv_reg ptstat;
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dv_reg rsvd2[437];
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union {
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struct {
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dv_reg mdstat[PSC_PSC0_MODULE_ID_CNT];
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dv_reg rsvd3[112];
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dv_reg mdctl[PSC_PSC0_MODULE_ID_CNT];
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} psc0;
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struct {
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dv_reg mdstat[PSC_PSC1_MODULE_ID_CNT];
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dv_reg rsvd3[96];
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dv_reg mdctl[PSC_PSC1_MODULE_ID_CNT];
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} psc1;
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};
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};
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#define davinci_psc0_regs ((struct davinci_psc_regs *)DAVINCI_PSC0_BASE)
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#define davinci_psc1_regs ((struct davinci_psc_regs *)DAVINCI_PSC1_BASE)
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#endif /* CONFIG_SOC_DA8XX */
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#ifndef CONFIG_SOC_DA8XX
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/* Miscellania... */
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#define VBPR (0x20000020)
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/* NOTE: system control modules are *highly* chip-specific, both
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* as to register content (e.g. for muxing) and which registers exist.
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*/
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#define PINMUX0 0x01c40000
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#define PINMUX1 0x01c40004
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#define PINMUX2 0x01c40008
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#define PINMUX3 0x01c4000c
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#define PINMUX4 0x01c40010
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#else /* CONFIG_SOC_DA8XX */
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struct davinci_pllc_regs {
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dv_reg revid;
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dv_reg rsvd1[56];
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dv_reg rstype;
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dv_reg rsvd2[6];
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dv_reg pllctl;
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dv_reg ocsel;
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dv_reg rsvd3[2];
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dv_reg pllm;
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dv_reg prediv;
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dv_reg plldiv1;
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dv_reg plldiv2;
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dv_reg plldiv3;
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dv_reg oscdiv;
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dv_reg postdiv;
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dv_reg rsvd4[3];
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dv_reg pllcmd;
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dv_reg pllstat;
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dv_reg alnctl;
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dv_reg dchange;
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dv_reg cken;
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dv_reg ckstat;
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dv_reg systat;
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dv_reg rsvd5[3];
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dv_reg plldiv4;
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dv_reg plldiv5;
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dv_reg plldiv6;
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dv_reg plldiv7;
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dv_reg rsvd6[32];
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dv_reg emucnt0;
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dv_reg emucnt1;
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};
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#define davinci_pllc_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL0_BASE)
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#define DAVINCI_PLLC_DIV_MASK 0x1f
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/* Clock IDs */
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enum davinci_clk_ids {
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DAVINCI_SPI0_CLKID = 2,
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DAVINCI_UART2_CLKID = 2,
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DAVINCI_MDIO_CLKID = 4,
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DAVINCI_ARM_CLKID = 6,
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DAVINCI_PLLM_CLKID = 0xff,
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DAVINCI_PLLC_CLKID = 0x100,
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DAVINCI_AUXCLK_CLKID = 0x101
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};
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int clk_get(enum davinci_clk_ids id);
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/* Boot config */
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struct davinci_syscfg_regs {
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dv_reg revid;
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dv_reg rsvd[71];
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dv_reg pinmux[20];
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dv_reg suspsrc;
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dv_reg chipsig;
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dv_reg chipsig_clr;
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dv_reg cfgchip0;
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dv_reg cfgchip1;
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dv_reg cfgchip2;
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dv_reg cfgchip3;
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dv_reg cfgchip4;
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};
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#define davinci_syscfg_regs \
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((struct davinci_syscfg_regs *)DAVINCI_BOOTCFG_BASE)
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/* Emulation suspend bits */
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#define DAVINCI_SYSCFG_SUSPSRC_EMAC (1 << 5)
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#define DAVINCI_SYSCFG_SUSPSRC_I2C (1 << 16)
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#define DAVINCI_SYSCFG_SUSPSRC_SPI0 (1 << 21)
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#define DAVINCI_SYSCFG_SUSPSRC_UART2 (1 << 20)
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#define DAVINCI_SYSCFG_SUSPSRC_TIMER0 (1 << 27)
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/* Interrupt controller */
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struct davinci_aintc_regs {
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dv_reg revid;
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dv_reg cr;
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dv_reg dummy0[2];
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dv_reg ger;
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dv_reg dummy1[219];
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dv_reg ecr1;
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dv_reg ecr2;
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dv_reg ecr3;
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dv_reg dummy2[1117];
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dv_reg hier;
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};
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#define davinci_aintc_regs ((struct davinci_aintc_regs *)DAVINCI_INTC_BASE)
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struct davinci_uart_ctrl_regs {
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dv_reg revid1;
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dv_reg revid2;
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dv_reg pwremu_mgmt;
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dv_reg mdr;
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};
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#define DAVINCI_UART_CTRL_BASE 0x28
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#define DAVINCI_UART0_CTRL_ADDR (DAVINCI_UART0_BASE + DAVINCI_UART_CTRL_BASE)
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#define DAVINCI_UART1_CTRL_ADDR (DAVINCI_UART1_BASE + DAVINCI_UART_CTRL_BASE)
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#define DAVINCI_UART2_CTRL_ADDR (DAVINCI_UART2_BASE + DAVINCI_UART_CTRL_BASE)
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#define davinci_uart0_ctrl_regs \
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((struct davinci_uart_ctrl_regs *)DAVINCI_UART0_CTRL_ADDR)
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#define davinci_uart1_ctrl_regs \
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((struct davinci_uart_ctrl_regs *)DAVINCI_UART1_CTRL_ADDR)
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#define davinci_uart2_ctrl_regs \
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((struct davinci_uart_ctrl_regs *)DAVINCI_UART2_CTRL_ADDR)
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/* UART PWREMU_MGMT definitions */
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#define DAVINCI_UART_PWREMU_MGMT_FREE (1 << 0)
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#define DAVINCI_UART_PWREMU_MGMT_URRST (1 << 13)
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#define DAVINCI_UART_PWREMU_MGMT_UTRST (1 << 14)
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#endif /* CONFIG_SOC_DA8XX */
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#endif /* __ASM_ARCH_HARDWARE_H */
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