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https://source.denx.de/u-boot/u-boot.git
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d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
157 lines
3.7 KiB
C
157 lines
3.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2012 Altera Corporation <www.altera.com>
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*/
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#include <common.h>
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#include <hang.h>
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#include <init.h>
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#include <log.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm/u-boot.h>
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#include <asm/utils.h>
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#include <image.h>
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#include <asm/arch/reset_manager.h>
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#include <spl.h>
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#include <asm/arch/system_manager.h>
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#include <asm/arch/freeze_controller.h>
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#include <asm/arch/clock_manager.h>
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#include <asm/arch/misc.h>
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#include <asm/arch/scan_manager.h>
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#include <asm/arch/sdram.h>
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#include <asm/sections.h>
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#include <debug_uart.h>
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#include <fdtdec.h>
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#include <watchdog.h>
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#include <dm/uclass.h>
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#include <linux/bitops.h>
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DECLARE_GLOBAL_DATA_PTR;
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u32 spl_boot_device(void)
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{
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const u32 bsel = readl(socfpga_get_sysmgr_addr() +
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SYSMGR_GEN5_BOOTINFO);
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switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
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case 0x1: /* FPGA (HPS2FPGA Bridge) */
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return BOOT_DEVICE_RAM;
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case 0x2: /* NAND Flash (1.8V) */
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case 0x3: /* NAND Flash (3.0V) */
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return BOOT_DEVICE_NAND;
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case 0x4: /* SD/MMC External Transceiver (1.8V) */
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case 0x5: /* SD/MMC Internal Transceiver (3.0V) */
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return BOOT_DEVICE_MMC1;
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case 0x6: /* QSPI Flash (1.8V) */
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case 0x7: /* QSPI Flash (3.0V) */
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return BOOT_DEVICE_SPI;
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default:
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printf("Invalid boot device (bsel=%08x)!\n", bsel);
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hang();
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}
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}
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#ifdef CONFIG_SPL_MMC
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u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
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{
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#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
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return MMCSD_MODE_FS;
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#else
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return MMCSD_MODE_RAW;
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#endif
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}
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#endif
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void board_init_f(ulong dummy)
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{
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const struct cm_config *cm_default_cfg = cm_get_default_config();
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unsigned long reg;
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int ret;
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struct udevice *dev;
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ret = spl_early_init();
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if (ret)
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hang();
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socfpga_get_managers_addr();
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/*
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* Clear fake OCRAM ECC first as SBE
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* and DBE might triggered during power on
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*/
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reg = readl(socfpga_get_sysmgr_addr() + SYSMGR_GEN5_ECCGRP_OCRAM);
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if (reg & SYSMGR_ECC_OCRAM_SERR)
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writel(SYSMGR_ECC_OCRAM_SERR | SYSMGR_ECC_OCRAM_EN,
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socfpga_get_sysmgr_addr() + SYSMGR_GEN5_ECCGRP_OCRAM);
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if (reg & SYSMGR_ECC_OCRAM_DERR)
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writel(SYSMGR_ECC_OCRAM_DERR | SYSMGR_ECC_OCRAM_EN,
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socfpga_get_sysmgr_addr() + SYSMGR_GEN5_ECCGRP_OCRAM);
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socfpga_sdram_remap_zero();
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socfpga_pl310_clear();
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debug("Freezing all I/O banks\n");
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/* freeze all IO banks */
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sys_mgr_frzctrl_freeze_req();
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/* Put everything into reset but L4WD0. */
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socfpga_per_reset_all();
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if (!socfpga_is_booting_from_fpga()) {
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/* Put FPGA bridges into reset too. */
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socfpga_bridges_reset(1);
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}
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socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
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timer_init();
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debug("Reconfigure Clock Manager\n");
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/* reconfigure the PLLs */
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if (cm_basic_init(cm_default_cfg))
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hang();
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/* Enable bootrom to configure IOs. */
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sysmgr_config_warmrstcfgio(1);
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/* configure the IOCSR / IO buffer settings */
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if (scan_mgr_configure_iocsr())
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hang();
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sysmgr_config_warmrstcfgio(0);
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/* configure the pin muxing through system manager */
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sysmgr_config_warmrstcfgio(1);
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sysmgr_pinmux_init();
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sysmgr_config_warmrstcfgio(0);
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/* Set bridges handoff value */
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socfpga_bridges_set_handoff_regs(true, true, true);
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debug("Unfreezing/Thaw all I/O banks\n");
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/* unfreeze / thaw all IO banks */
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sys_mgr_frzctrl_thaw_req();
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#ifdef CONFIG_DEBUG_UART
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socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
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debug_uart_init();
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#endif
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ret = uclass_get_device(UCLASS_RESET, 0, &dev);
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if (ret)
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debug("Reset init failed: %d\n", ret);
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#ifdef CONFIG_SPL_NAND_DENALI
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clrbits_le32(SOCFPGA_RSTMGR_ADDRESS + RSTMGR_GEN5_PERMODRST, BIT(4));
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#endif
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/* enable console uart printing */
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preloader_console_init();
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ret = uclass_get_device(UCLASS_RAM, 0, &dev);
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if (ret) {
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debug("DRAM init failed: %d\n", ret);
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hang();
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}
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}
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