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d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
63 lines
1.4 KiB
C
63 lines
1.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* This file configures the internal USB PHY in AM35X.
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*
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* Copyright (C) 2012 Ilya Yanok <ilya.yanok@gmail.com>
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*
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* Based on omap_phy_internal.c code from Linux by
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* Hema HK <hemahk@ti.com>
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*/
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#include <common.h>
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#include <log.h>
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#include <dm/device.h>
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#include <asm/io.h>
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#include <asm/arch/am35x_def.h>
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void am35x_musb_reset(struct udevice *dev)
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{
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/* Reset the musb interface */
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clrsetbits_le32(&am35x_scm_general_regs->ip_sw_reset,
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0, USBOTGSS_SW_RST);
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clrsetbits_le32(&am35x_scm_general_regs->ip_sw_reset,
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USBOTGSS_SW_RST, 0);
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}
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void am35x_musb_phy_power(struct udevice *dev, u8 on)
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{
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unsigned long start = get_timer(0);
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if (on) {
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/*
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* Start the on-chip PHY and its PLL.
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*/
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clrsetbits_le32(&am35x_scm_general_regs->devconf2,
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CONF2_RESET | CONF2_PHYPWRDN | CONF2_OTGPWRDN,
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CONF2_PHY_PLLON);
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debug("Waiting for PHY clock good...\n");
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while (!(readl(&am35x_scm_general_regs->devconf2)
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& CONF2_PHYCLKGD)) {
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if (get_timer(start) > CONFIG_SYS_HZ / 10) {
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printf("musb PHY clock good timed out\n");
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break;
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}
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}
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} else {
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/*
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* Power down the on-chip PHY.
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*/
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clrsetbits_le32(&am35x_scm_general_regs->devconf2,
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CONF2_PHY_PLLON,
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CONF2_PHYPWRDN | CONF2_OTGPWRDN);
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}
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}
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void am35x_musb_clear_irq(struct udevice *dev)
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{
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clrsetbits_le32(&am35x_scm_general_regs->lvl_intr_clr,
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0, USBOTGSS_INT_CLR);
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readl(&am35x_scm_general_regs->lvl_intr_clr);
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}
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