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d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
67 lines
1.4 KiB
C
67 lines
1.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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*
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* Common functions for OMAP4/5 based boards
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*
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* (C) Copyright 2010
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* Texas Instruments, <www.ti.com>
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*
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* Author :
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* Aneesh V <aneesh@ti.com>
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* Steve Sakoman <steve@sakoman.com>
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <log.h>
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#include <asm/cache.h>
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#include <asm/global_data.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Without LPAE short descriptors are used
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* Set C - Cache Bit3
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* Set B - Buffer Bit2
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* The last 2 bits set to 0b10
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* Do Not set XN bit4
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* So value is 0xe
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*
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* With LPAE cache configuration happens via MAIR0 register
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* AttrIndx value is 0x3 for picking byte3 for MAIR0 which has 0xFF.
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* 0xFF maps to Cache writeback with Read and Write Allocate set
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* The bits[1:0] should have the value 0b01 for the first level
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* descriptor.
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* So the value is 0xd
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*/
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#ifdef CONFIG_ARMV7_LPAE
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#define ARMV7_DCACHE_POLICY DCACHE_WRITEALLOC
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#else
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#define ARMV7_DCACHE_POLICY DCACHE_WRITEBACK & ~TTB_SECT_XN_MASK
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#endif
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void enable_caches(void)
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{
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/* Enable I cache if not enabled */
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if (!icache_status())
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icache_enable();
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dcache_enable();
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}
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void dram_bank_mmu_setup(int bank)
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{
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struct bd_info *bd = gd->bd;
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int i;
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u32 start = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
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u32 size = bd->bi_dram[bank].size >> MMU_SECTION_SHIFT;
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u32 end = start + size;
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debug("%s: bank: %d\n", __func__, bank);
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for (i = start; i < end; i++)
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set_section_dcache(i, ARMV7_DCACHE_POLICY);
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}
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