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d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
149 lines
3.6 KiB
C
149 lines
3.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Based on the iomux-v3.c from Linux kernel:
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* Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
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* Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
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* <armlinux@phytec.de>
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*
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* Copyright (C) 2004-2011 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/mach-imx/sys_proto.h>
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static void *base = (void *)IOMUXC_BASE_ADDR;
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/*
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* configures a single pad in the iomuxer
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*/
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void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
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{
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u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT;
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u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
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u32 sel_input_ofs =
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(pad & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT;
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u32 sel_input =
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(pad & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT;
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u32 pad_ctrl_ofs =
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(pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT;
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u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
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#if defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL)
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/* Check whether LVE bit needs to be set */
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if (pad_ctrl & PAD_CTL_LVE) {
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pad_ctrl &= ~PAD_CTL_LVE;
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pad_ctrl |= PAD_CTL_LVE_BIT;
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}
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#endif
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#ifdef CONFIG_IOMUX_LPSR
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u32 lpsr = (pad & MUX_MODE_LPSR) >> MUX_MODE_SHIFT;
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#ifdef CONFIG_MX7
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if (lpsr == IOMUX_CONFIG_LPSR) {
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base = (void *)IOMUXC_LPSR_BASE_ADDR;
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mux_mode &= ~IOMUX_CONFIG_LPSR;
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/* set daisy chain sel_input */
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if (sel_input_ofs)
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sel_input_ofs += IOMUX_LPSR_SEL_INPUT_OFS;
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}
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#else
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if (is_mx6ull() || is_mx6sll()) {
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if (lpsr == IOMUX_CONFIG_LPSR) {
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base = (void *)IOMUXC_SNVS_BASE_ADDR;
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mux_mode &= ~IOMUX_CONFIG_LPSR;
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}
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}
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#endif
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#endif
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if (is_mx7() || is_mx6ull() || is_mx6sll() || mux_ctrl_ofs)
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__raw_writel(mux_mode, base + mux_ctrl_ofs);
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if (sel_input_ofs)
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__raw_writel(sel_input, base + sel_input_ofs);
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#ifdef CONFIG_IOMUX_SHARE_CONF_REG
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if (!(pad_ctrl & NO_PAD_CTRL))
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__raw_writel((mux_mode << PAD_MUX_MODE_SHIFT) | pad_ctrl,
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base + pad_ctrl_ofs);
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#else
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if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
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__raw_writel(pad_ctrl, base + pad_ctrl_ofs);
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#if defined(CONFIG_MX6SLL)
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else if ((pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
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clrbits_le32(base + pad_ctrl_ofs, PAD_CTL_IPD_BIT);
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#endif
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#endif
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#ifdef CONFIG_IOMUX_LPSR
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if (lpsr == IOMUX_CONFIG_LPSR)
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base = (void *)IOMUXC_BASE_ADDR;
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#endif
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}
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/* configures a list of pads within declared with IOMUX_PADS macro */
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void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
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unsigned count)
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{
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iomux_v3_cfg_t const *p = pad_list;
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int stride;
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int i;
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#if defined(CONFIG_MX6QDL)
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stride = 2;
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if (!is_mx6dq() && !is_mx6dqp())
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p += 1;
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#else
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stride = 1;
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#endif
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for (i = 0; i < count; i++) {
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imx_iomux_v3_setup_pad(*p);
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p += stride;
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}
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}
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void imx_iomux_set_gpr_register(int group, int start_bit,
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int num_bits, int value)
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{
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int i = 0;
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u32 reg;
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reg = readl(base + group * 4);
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while (num_bits) {
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reg &= ~(1<<(start_bit + i));
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i++;
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num_bits--;
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}
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reg |= (value << start_bit);
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writel(reg, base + group * 4);
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}
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#ifdef CONFIG_IOMUX_SHARE_CONF_REG
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void imx_iomux_gpio_set_direction(unsigned int gpio,
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unsigned int direction)
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{
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u32 reg;
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/*
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* Only on Vybrid the input/output buffer enable flags
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* are part of the shared mux/conf register.
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*/
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reg = readl(base + (gpio << 2));
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if (direction)
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reg |= 0x2;
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else
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reg &= ~0x2;
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writel(reg, base + (gpio << 2));
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}
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void imx_iomux_gpio_get_function(unsigned int gpio, u32 *gpio_state)
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{
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*gpio_state = readl(base + (gpio << 2)) &
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((0X07 << PAD_MUX_MODE_SHIFT) | PAD_CTL_OBE_IBE_ENABLE);
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}
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#endif
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