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When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
92 lines
1.8 KiB
C
92 lines
1.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2011
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* Ilya Yanok, EmCraft Systems
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*/
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#include <cpu_func.h>
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#include <asm/cache.h>
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#include <linux/types.h>
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#include <common.h>
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#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
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void invalidate_dcache_all(void)
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{
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asm volatile("mcr p15, 0, %0, c7, c6, 0\n" : : "r"(0));
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}
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void flush_dcache_all(void)
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{
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asm volatile(
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"0:"
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"mrc p15, 0, r15, c7, c14, 3\n"
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"bne 0b\n"
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"mcr p15, 0, %0, c7, c10, 4\n"
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: : "r"(0) : "memory"
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);
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}
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void invalidate_dcache_range(unsigned long start, unsigned long stop)
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{
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if (!check_cache_range(start, stop))
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return;
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while (start < stop) {
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asm volatile("mcr p15, 0, %0, c7, c6, 1\n" : : "r"(start));
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start += CONFIG_SYS_CACHELINE_SIZE;
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}
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}
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void flush_dcache_range(unsigned long start, unsigned long stop)
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{
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if (!check_cache_range(start, stop))
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return;
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while (start < stop) {
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asm volatile("mcr p15, 0, %0, c7, c14, 1\n" : : "r"(start));
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start += CONFIG_SYS_CACHELINE_SIZE;
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}
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asm volatile("mcr p15, 0, %0, c7, c10, 4\n" : : "r"(0));
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}
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#else /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
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void invalidate_dcache_all(void)
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{
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}
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void flush_dcache_all(void)
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{
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}
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#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
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/*
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* Stub implementations for l2 cache operations
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*/
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__weak void l2_cache_disable(void) {}
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#if CONFIG_IS_ENABLED(SYS_THUMB_BUILD)
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__weak void invalidate_l2_cache(void) {}
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#endif
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#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
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/* Invalidate entire I-cache and branch predictor array */
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void invalidate_icache_all(void)
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{
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unsigned long i = 0;
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asm ("mcr p15, 0, %0, c7, c5, 0" : : "r" (i));
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}
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#else
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void invalidate_icache_all(void) {}
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#endif
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void enable_caches(void)
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{
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#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
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icache_enable();
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#endif
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#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
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dcache_enable();
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#endif
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}
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