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16ffcff028
The current spl_board_fixups API allows for modification of spl_image before the SPL jumps to it. This can be used to modify the DT for the next boot stage, however the current API only allows either the machine arch or the board to use it. This limits the utility of the API as there might be certain fixups that should be applied to all boards sharing the same machine architecture with others being board specific. For TI's K3 specifically, this prevents us from performing architecture level fixups since a lot of TI boards are already making use of the spl_board_fixups API. Therefore this patch splits the API into two to allow both board and the architecture specific fixups. The order is kept as arch then board to give board specific fixups the precedence. Reviewed-by: Dhruva Gole <d-gole@ti.com> Signed-off-by: Anshul Dalal <anshuld@ti.com> Tested-by: Wadim Egorov <w.egorov@phytec.de>
140 lines
3.1 KiB
C
140 lines
3.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2022 StarFive Technology Co., Ltd.
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* Author: Yanhong Wang<yanhong.wang@starfivetech.com>
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*/
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#include <asm/arch/eeprom.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/regs.h>
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#include <asm/arch/spl.h>
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#include <asm/io.h>
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#include <dt-bindings/clock/starfive,jh7110-crg.h>
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#include <fdt_support.h>
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#include <linux/libfdt.h>
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#include <log.h>
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#include <spl.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define JH7110_CLK_CPU_ROOT_OFFSET 0x0U
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#define JH7110_CLK_CPU_ROOT_SHIFT 24
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#define JH7110_CLK_CPU_ROOT_MASK GENMASK(29, 24)
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void spl_perform_board_fixups(struct spl_image_info *spl_image)
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{
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/* Update the memory size which read from eeprom or DT */
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if (spl_image->fdt_addr)
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fdt_fixup_memory(spl_image->fdt_addr, 0x40000000, gd->ram_size);
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}
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static void jh7110_jtag_init(void)
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{
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/* nTRST: GPIO36 */
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SYS_IOMUX_DOEN(36, HIGH);
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SYS_IOMUX_DIN(36, 4);
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/* TDI: GPIO61 */
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SYS_IOMUX_DOEN(61, HIGH);
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SYS_IOMUX_DIN(61, 19);
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/* TMS: GPIO63 */
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SYS_IOMUX_DOEN(63, HIGH);
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SYS_IOMUX_DIN(63, 20);
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/* TCK: GPIO60 */
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SYS_IOMUX_DOEN(60, HIGH);
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SYS_IOMUX_DIN(60, 29);
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/* TDO: GPIO44 */
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SYS_IOMUX_DOEN(44, 8);
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SYS_IOMUX_DOUT(44, 22);
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}
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int spl_board_init_f(void)
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{
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int ret;
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jh7110_jtag_init();
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ret = spl_dram_init();
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if (ret) {
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debug("JH7110 DRAM init failed: %d\n", ret);
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return ret;
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}
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return 0;
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}
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u32 spl_boot_device(void)
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{
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u32 mode;
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mode = in_le32(JH7110_BOOT_MODE_SELECT_REG)
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& JH7110_BOOT_MODE_SELECT_MASK;
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switch (mode) {
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case 0:
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return BOOT_DEVICE_SPI;
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case 1:
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return BOOT_DEVICE_MMC2;
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case 2:
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return BOOT_DEVICE_MMC1;
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case 3:
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return BOOT_DEVICE_UART;
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default:
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debug("Unsupported boot device 0x%x.\n", mode);
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return BOOT_DEVICE_NONE;
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}
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}
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void board_init_f(ulong dummy)
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{
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int ret;
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ret = spl_early_init();
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if (ret)
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panic("spl_early_init() failed: %d\n", ret);
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riscv_cpu_setup();
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preloader_console_init();
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/* Set the parent clock of cpu_root clock to pll0,
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* it must be initialized here
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*/
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clrsetbits_le32(JH7110_SYS_CRG + JH7110_CLK_CPU_ROOT_OFFSET,
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JH7110_CLK_CPU_ROOT_MASK,
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BIT(JH7110_CLK_CPU_ROOT_SHIFT));
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/* Set USB overcurrent overflow pin disable */
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SYS_IOMUX_DIN_DISABLED(2);
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ret = spl_board_init_f();
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if (ret) {
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debug("spl_board_init_f init failed: %d\n", ret);
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return;
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}
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}
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#if CONFIG_IS_ENABLED(LOAD_FIT)
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int board_fit_config_name_match(const char *name)
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{
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if (!strcmp(name, "starfive/jh7110-deepcomputing-fml13v01") &&
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!strncmp(get_product_id_from_eeprom(), "FML13V01", 8)) {
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return 0;
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} else if (!strcmp(name, "starfive/jh7110-milkv-mars") &&
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!strncmp(get_product_id_from_eeprom(), "MARS", 4)) {
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return 0;
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} else if (!strcmp(name, "starfive/jh7110-pine64-star64") &&
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!strncmp(get_product_id_from_eeprom(), "STAR64", 6)) {
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return 0;
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} else if (!strcmp(name, "starfive/jh7110-starfive-visionfive-2-v1.2a") &&
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!strncmp(get_product_id_from_eeprom(), "VF7110A", 7)) {
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return 0;
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} else if (!strcmp(name, "starfive/jh7110-starfive-visionfive-2-v1.3b") &&
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!strncmp(get_product_id_from_eeprom(), "VF7110B", 7)) {
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return 0;
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}
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return -EINVAL;
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}
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#endif
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