David Wu ef4cf5ae39 rockchip: clk: Add SARADC clock support for rk3288
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 8-bits width.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:29 +02:00
..
2017-06-01 07:03:01 -06:00
2017-06-01 07:03:01 -06:00