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cff451e03f
Add support for different RAM sizes and speed grades on the phyCORE-i.MX8MP. Add support for 1GB 1.5GHz, 1GB 2GHz, 4GB 1.5GHz, 4GB 2GHz and 8GB 2GHz RAM. The RAM size and speed grade is detected by the information stored in the EEPROM on the SoM. Co-developed-by: Benjamin Hahn <B.Hahn@phytec.de> Signed-off-by: Benjamin Hahn <B.Hahn@phytec.de> Co-developed-by: Yannic Moog <y.moog@phytec.de> Signed-off-by: Yannic Moog <y.moog@phytec.de> Co-developed-by: Yashwanth Varakala <y.varakala@phytec.de> Signed-off-by: Yashwanth Varakala <y.varakala@phytec.de> Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
30 lines
749 B
C
30 lines
749 B
C
/* SPDX-License-Identifier: GPL-2.0-or-later
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*
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* Copyright (C) 2020 PHYTEC Messtechnik GmbH
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* Author: Teresa Remmet <t.remmet@phytec.de>
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*/
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#ifndef __PHYCORE_IMX8MP_H
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#define __PHYCORE_IMX8MP_H
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#include <linux/sizes.h>
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#include <asm/arch/imx-regs.h>
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#define CFG_SYS_UBOOT_BASE \
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(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
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/* Link Definitions */
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#define CFG_SYS_INIT_RAM_ADDR 0x40000000
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#define CFG_SYS_INIT_RAM_SIZE SZ_512K
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#define CFG_SYS_SDRAM_BASE 0x40000000
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#define PHYS_SDRAM 0x40000000
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#define PHYS_SDRAM_SIZE (SZ_2G + SZ_1G) /* 3GB */
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#define PHYS_SDRAM_2 0x100000000
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#define PHYS_SDRAM_2_SIZE (SZ_4G + SZ_1G) /* 5GB */
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#endif /* __PHYCORE_IMX8MP_H */
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