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999c6baf79
These headers define the Tegra124 hardware. Add them to the usual place. Add Tegra124 chip ID/SKU ID definitions to common headers. There's no real HW change on Tegra124 for 90% of the toys, so it might make sense for a future patch to unify some of the content of these files in a common location. Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
27 lines
815 B
C
27 lines
815 B
C
/*
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* (C) Copyright 2013
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* NVIDIA Corporation <www.nvidia.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _TEGRA124_SYSCTR_H_
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#define _TEGRA124_SYSCTR_H_
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struct sysctr_ctlr {
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u32 cntcr; /* 0x00: SYSCTR0_CNTCR Counter Control */
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u32 cntsr; /* 0x04: SYSCTR0_CNTSR Counter Status */
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u32 cntcv0; /* 0x08: SYSCTR0_CNTCV0 Counter Count 31:00 */
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u32 cntcv1; /* 0x0C: SYSCTR0_CNTCV1 Counter Count 63:32 */
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u32 reserved1[4]; /* 0x10 - 0x1C */
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u32 cntfid0; /* 0x20: SYSCTR0_CNTFID0 Freq Table Entry */
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u32 cntfid1; /* 0x24: SYSCTR0_CNTFID1 Freq Table End */
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u32 reserved2[1002]; /* 0x28 - 0xFCC */
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u32 counterid[12]; /* 0xFD0 - 0xFxx CounterID regs, RO */
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};
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#define TSC_CNTCR_ENABLE (1 << 0) /* Enable */
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#define TSC_CNTCR_HDBG (1 << 1) /* Halt on debug */
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#endif /* _TEGRA124_SYSCTR_H_ */
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