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47edaea494
Add the new Atmel PIT timer driver, which supports the driver model and device tree. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
91 lines
1.9 KiB
C
91 lines
1.9 KiB
C
/*
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* Copyright (C) 2017 Microchip Corporation
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* Wenyou.Yang <wenyou.yang@microchip.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <timer.h>
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#include <asm/io.h>
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#define AT91_PIT_VALUE 0xfffff
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#define AT91_PIT_PITEN BIT(24) /* Timer Enabled */
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struct atmel_pit_regs {
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u32 mode;
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u32 status;
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u32 value;
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u32 value_image;
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};
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struct atmel_pit_platdata {
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struct atmel_pit_regs *regs;
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};
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static int atmel_pit_get_count(struct udevice *dev, u64 *count)
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{
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struct atmel_pit_platdata *plat = dev_get_platdata(dev);
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struct atmel_pit_regs *const regs = plat->regs;
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u32 val = readl(®s->value_image);
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*count = timer_conv_64(val);
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return 0;
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}
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static int atmel_pit_probe(struct udevice *dev)
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{
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struct atmel_pit_platdata *plat = dev_get_platdata(dev);
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struct atmel_pit_regs *const regs = plat->regs;
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struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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struct clk clk;
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ulong clk_rate;
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int ret;
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ret = clk_get_by_index(dev, 0, &clk);
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if (ret)
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return -EINVAL;
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clk_rate = clk_get_rate(&clk);
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if (!clk_rate)
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return -EINVAL;
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uc_priv->clock_rate = clk_rate / 16;
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writel(AT91_PIT_VALUE | AT91_PIT_PITEN, ®s->mode);
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return 0;
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}
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static int atmel_pit_ofdata_to_platdata(struct udevice *dev)
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{
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struct atmel_pit_platdata *plat = dev_get_platdata(dev);
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plat->regs = (struct atmel_pit_regs *)devfdt_get_addr_ptr(dev);
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return 0;
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}
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static const struct timer_ops atmel_pit_ops = {
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.get_count = atmel_pit_get_count,
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};
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static const struct udevice_id atmel_pit_ids[] = {
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{ .compatible = "atmel,at91sam9260-pit" },
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{ }
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};
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U_BOOT_DRIVER(atmel_pit) = {
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.name = "atmel_pit",
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.id = UCLASS_TIMER,
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.of_match = atmel_pit_ids,
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.ofdata_to_platdata = atmel_pit_ofdata_to_platdata,
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.platdata_auto_alloc_size = sizeof(struct atmel_pit_platdata),
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.probe = atmel_pit_probe,
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.ops = &atmel_pit_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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